WO2004019133A3 - Procede pour former une couche de masquage sur un substrat - Google Patents

Procede pour former une couche de masquage sur un substrat Download PDF

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Publication number
WO2004019133A3
WO2004019133A3 PCT/DE2003/002471 DE0302471W WO2004019133A3 WO 2004019133 A3 WO2004019133 A3 WO 2004019133A3 DE 0302471 W DE0302471 W DE 0302471W WO 2004019133 A3 WO2004019133 A3 WO 2004019133A3
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
layer
light source
structural element
masking
Prior art date
Application number
PCT/DE2003/002471
Other languages
German (de)
English (en)
Other versions
WO2004019133A2 (fr
Inventor
Peter Moll
Stefan Tegen
Original Assignee
Infineon Technologies Ag
Peter Moll
Stefan Tegen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Peter Moll, Stefan Tegen filed Critical Infineon Technologies Ag
Publication of WO2004019133A2 publication Critical patent/WO2004019133A2/fr
Publication of WO2004019133A3 publication Critical patent/WO2004019133A3/fr

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
    • G03F7/201—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image characterised by an oblique exposure; characterised by the use of plural sources; characterised by the rotation of the optical device; characterised by a relative movement of the optical device, the light source, the sensitive system or the mask
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Chemically Coating (AREA)

Abstract

La présente invention concerne un procédé pour former une couche de masquage sur un substrat (5) à l'aide d'un élément structurel (3, 62) qui présente au moins une paroi latérale (1) et est conçu pour assurer un masquage dans le cadre d'un processus physique ou chimique (100). Ledit élément structurel (3, 62) est en saillie ou en retrait par rapport au substrat (5). Ledit procédé consiste à préparer le substrat (5) avec une surface et l'élément structurel (3, 62), à déposer sur le substrat (5) une couche (20) d'un matériau qui peut se transformer chimiquement sous l'effet de lumière, par exemple du carbone amorphe, de façon à recouvrir sensiblement l'élément structurel (3, 62) avec le matériau, à installer une première source de lumière par rapport au substrat de façon qu'un faisceau de lumière (110) produit par cette source de lumière arrive à la surface du substrat (5) en formant un premier angle (α) différent de 90 degrés, à soumettre la couche (20) à une première exposition, au moyen de la source de lumière installée, de façon qu'une partie (21) de la couche reste non exposée dans une zone d'ombre de l'élément structurel (3, 62), sur la première paroi latérale (1) opposée à la source de lumière, à retirer la couche exposée (20), à l'exception de la zone d'ombre, de façon que la partie non exposée (21) de la couche (20) reste en place et serve de couche de masquage (10), puis à mettre ensuite en oeuvre le processus physique ou chimique (100).
PCT/DE2003/002471 2002-08-16 2003-07-22 Procede pour former une couche de masquage sur un substrat WO2004019133A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10237508.9 2002-08-16
DE10237508A DE10237508A1 (de) 2002-08-16 2002-08-16 Verfahren zum Bilden einer Maskierschicht auf einem Substrat

Publications (2)

Publication Number Publication Date
WO2004019133A2 WO2004019133A2 (fr) 2004-03-04
WO2004019133A3 true WO2004019133A3 (fr) 2004-10-07

Family

ID=31501774

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2003/002471 WO2004019133A2 (fr) 2002-08-16 2003-07-22 Procede pour former une couche de masquage sur un substrat

Country Status (3)

Country Link
DE (1) DE10237508A1 (fr)
TW (1) TWI230984B (fr)
WO (1) WO2004019133A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10355225B3 (de) * 2003-11-26 2005-03-31 Infineon Technologies Ag Herstellungsverfahren für einen Grabenkondensator mit einem Isolationskragen, der über einen vergrabenen Kontakt einseitig mit einem Substrat elektrisch verbunden ist, insbesondere für eine Halbleiterspeicherzelle

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4821094A (en) * 1985-11-08 1989-04-11 Lockheed Missiles & Space Company, Inc. Gate alignment procedure in fabricating semiconductor devices
US5153683A (en) * 1990-04-19 1992-10-06 Mitsubishi Denki Kabushiki Kaisha Field effect transistor
US6426253B1 (en) * 2000-05-23 2002-07-30 Infineon Technologies A G Method of forming a vertically oriented device in an integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4821094A (en) * 1985-11-08 1989-04-11 Lockheed Missiles & Space Company, Inc. Gate alignment procedure in fabricating semiconductor devices
US5153683A (en) * 1990-04-19 1992-10-06 Mitsubishi Denki Kabushiki Kaisha Field effect transistor
US6426253B1 (en) * 2000-05-23 2002-07-30 Infineon Technologies A G Method of forming a vertically oriented device in an integrated circuit

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"PROCESS FOR MAKING ASYMMETRIC FIELD-EFFECT TRANSISTORS", IBM TECHNICAL DISCLOSURE BULLETIN, IBM CORP. NEW YORK, US, vol. 32, no. 4A, 1 September 1989 (1989-09-01), pages 472 - 473, XP000039878, ISSN: 0018-8689 *
JACKMAN R B ET AL: "Laser projection patterning for the formation of thin film diamond microstructures", DIAMOND AND RELATED MATERIALS, ELSEVIER SCIENCE PUBLISHERS, AMSTERDAM, NL, vol. 5, no. 3-5, 1 April 1996 (1996-04-01), pages 317 - 320, XP004080648, ISSN: 0925-9635 *
NAKAJIMA K ET AL: "Pulsed laser ablation of graphite in O/sub 2/ atmosphere for preparation of diamond films and carbon nanotubes", DIAM. RELAT. MATER. (NETHERLANDS), DIAMOND AND RELATED MATERIALS, MARCH-JUNE 2002, ELSEVIER, NETHERLANDS, vol. 11, no. 3-6, June 2002 (2002-06-01), pages 953 - 956, XP002291322, ISSN: 0925-9635 *

Also Published As

Publication number Publication date
TW200403756A (en) 2004-03-01
WO2004019133A2 (fr) 2004-03-04
TWI230984B (en) 2005-04-11
DE10237508A1 (de) 2004-03-11

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