TWI229412B - Method for forming metal interconnect structures - Google Patents

Method for forming metal interconnect structures Download PDF

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TWI229412B
TWI229412B TW092106138A TW92106138A TWI229412B TW I229412 B TWI229412 B TW I229412B TW 092106138 A TW092106138 A TW 092106138A TW 92106138 A TW92106138 A TW 92106138A TW I229412 B TWI229412 B TW I229412B
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metal
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TW200428581A (en
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Jiun-Cheng Lin
Jen-Lin Huang
Jing-Hua Shie
Shau-Lin Shue
Mong-Song Liang
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Taiwan Semiconductor Mfg
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
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    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
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    • H01L21/76846—Layer combinations
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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Description

1229412 五、發明說明（1) 發明所屬之領域： 本發明係有關於一種内連線之製造方法，特別是有關 ;一種金屬内連線之結構及其製造方法以及 以增加内連線之可靠度。 卞守篮裝置 先前技術： 在極大型積體電路（ULSI )中，金屬化 、:：為一重要步驟，其中内連線扮演電性 中各個元件的角色，因此其深深影響元件之電特 ΐί:件功能之發揮。現今内連線製程中，由於銅金屬具 之内連5 3赳適用於深次微米之積體電路’所以成為矚目 :連線材料。然而’銅金屬擴散係數‘，與矽或二 氧化石夕接觸後會快速擴散 影燮。另一古二=進基材而造成70件電性之不良 β 2 .. ，通者内連線尺寸縮小化，電遷移性# μ 題也日趨嚴重。 心W I王的问 ^知技術之銅内連線製造方*中，會在 别形成擴散阻障層’例如鈦、 連二 属七《 β I Μ政不幸地’上述擴散阻障層材料蛊铜合 與金屬層間之介電層的附著性較差，：續^ =ί生剝•，導致内連線失效。因此，也有使= 2:二電層之附著性。同_，摻雜之銅金屬亦 銅原子擴散之特性。 興々八有防止
0503-8431TWF(Nl) ； TSMC2002-0338;spin.ptd 第6頁 1229412
—以下配合第1圖說明使用具摻雜的銅金屬之内連線結 構不意圖。其包含—基底剛、複數個交替堆疊之餘刻終 止層104、108及絕緣層1〇6、11〇以及嵌入於其中之金屬内 j線層114。基底100，例如一矽基底或其他半導體基底， /、上方可以形成任何所需的半導體元件，例如MOS電晶 體、電阻、邏輯元件#，不過此處為了簡化圖式，僅以平 整的基板100表不之。再者，一金屬接線層1〇2嵌入於 100 Φ 〇 * 叹置於基底100上方之触刻終止層104、108，其材質 為氮化矽或碳化矽。再者，絕緣層丨〇6、丨丨〇交替設置於 刻終止層m、1〇8中，用以作為金屬層間介；替又置、鍅 (lntermetal dielectric， IMD)層，其材質可為：電漿 氧化石夕、咼密度電漿所沈積的氧化矽（)、四乙 氧基石夕玻璃（TEOS oxide )或低介電常數之旋塗式玻璃、 氟化氧化矽（FSG )等。 經由一般微影蝕刻製程之後，可在交替堆疊之蝕刻終 止層104、108及絕緣層1〇6、11〇中形成一雙鑲嵌開口 πι。最後，金屬内連線層114設置於雙鑲嵌開口ln中並 與金屬接線層1 0 2電性連接。
一般而言，在設置金屬内連線層114之前，會先在雙 鑲嵌開口 111内表面順應性設置一擴散阻障層，其材質可 為鈦、鈕、氮化鈦、氮化钽等。其目的在於防止後續形成 銅金屬内連線時，銅原子擴散至絕緣層丨0 6、丨丨〇而降低内 連線之品質。此處係另一種做法，即金屬内連線層1 1 4之
1229412 五、發明說明（3) 材質係採用具摻雜之鋼金屬，如以 後，摻雜之原子會擴散至雙鑲嵌開口 述。其經由熱處理 1:4之界面，其作用如同上述之擴？1;:金：内連線層 外再設置一擴散阻障層。再者，具 丨早層，因此不需額 的絕緣層106、110形成摻雜金屬“二，鋼金屬會與含氧 於增加兩者之附著性。 曰Q未繪示）而有助 然而，儘管如此，對於由氮化矽 所構成之蝕刻終止層1 04、丨08而言，呈矽（不a乳）
^其形成摻雜金屬氧化層，導致附著性= , = f C 出㈣中A處之放大示意圖。：上；; 蝕刻終止層1〇4與金屬内連線層114之附著性不佳，而容 在兩者界面間出現孔洞115或是在實施研磨製程（例如， 化學機械研磨（Chemical mechanical p〇iishing，CMp) )期間發生剝離現象，嚴重影響内連線之品質以及元 可靠度。 、卞疋 美國專利第6, 365, 502號揭示一種具有附著促進層之 内連線材料，其利用鈷（Co )、釕（Ru )、或鉑（Pt )元 素摻雜於習知之擴散阻障層中以增加其與銅金屬層之附著 性並加強擴散阻障層之阻障能力。
另外，美國專利第6, 0 1 5, 749號揭示一種利用離子佈 植來改善銅與氮化鈦之間附著性之方法，其利用在金屬阻 I5早層上形成銅晶種層之後，實施一鍺（G e )離子佈植程 序，以在金屬阻障層與銅晶種層之間形成一銅鍺合金層來 作為附著層。
〇503-843lTWF(Nl) ； TSMC2002-0338;spin.ptd 第 8 頁
1229412 五、發明說明（4) 上述專利中係著重於金屬阻障層與銅金屬 而未對銅金屬層與蝕刻終止^ (由氮化矽或碳化矽所構成 圭的：題進行解決。由於内連線隨需求而 i;"響二間附著性的問 之道。円連線之“及疋件之可靠度’需尋求解決 發明内容： 方i發；之目的在於提供一種金屬内連線之 間形成-摻雜金屬氧化I，以增加蝕刻終止層 線之附著性而減少孔洞的發生，…善現行無阻連 (barrier-less )製程之可靠度。 干巧 根據上述之目的，本發明提供一 方法。首★’提供一基底並在其上形成至少一 及至少-絕緣層…，在姓刻終止層及絕緣 -金屬阻障層並接著氧化此金屬阻障層。#著及2形成 pn-si⑷去，除開口底部之氧化的金屬阻障層而露出基 屬晶種層。最後’…内填入= = 回火處理，以在開口與金屬層之間形成-4 其中’上述姓刻終止層可為一氮化石夕層或一碳化矽
1229412 五、發明說明（5) 層。金屬阻障層可尨# Λ 1Η00埃的範圍 氮化欽或氮化组且厚度在 及一:二推雜的金屬曰曰曰種層係、* — ##雜的銅層 ΐ，= 搀雜元素係m、錫或給。其 雜的銅層之厚卢在=種層厚度在40 0〜1 200埃的範圍且具摻 H 300埃的範圍。 所形成。上述金屬層係—銅金屬層並藉由電化學電鑛法 構。其包含的二本發明提供me迷線一 層、以及-摻雜：屬氧：；刻絕緣層、一金屬 設置於開口内以;^^一開口以露出基底表面。金屬層 口側壁與金屬層之間線。摻雜金屬氧化層係形成於開 層。' $蝕刻終止層可為-氮化矽層或-碳化矽 及-=層；= ”由-具摻雜的銅層 中，具摻雜的金屬曰稽2素係鎮、1呂、錯、錫或給。其 雜的銅層之厚度：5二:厚度在4〇°〜1 200埃的範圍且具摻 、序度在bO〜300埃的範圍。 所形2者上述金屬層係一銅金屬層並藉由電化學電鍍法 又很艨上述之 包含：一基底、一
tr、J 本發明提供 、 …， 裡千导體裝置， 内連線結構、至少一蝕刻終止層及至
再者， 所形成。 1229412 五、發明說明（6) $緣層、一金屬層、及一摻雜金屬氧化層。基底上形成 至夕一半導體元件且内連線結構，與半導體元件電性連 接其中’内連線結構包含：至少一蝕刻終止層及至少一 =緣層，依序設置於基底上且具有至少一開口以露出基底 表一金屬層，設置於開口内以作為一内連線；以及 摻雜金屬氧化層，形成於開口側壁與金屬層之間。 其中，上述蝕刻終止層可為一氮化矽層或一碳化矽層 且上述開口可為一單鑲嵌或雙鑲嵌開口。 再者，上述摻雜金屬氧化層之摻雜元素係鎂、鋁、 錄、錫或铪。 上述金屬層係一銅金屬層並藉由電化學電鍍法 為讓本發明之上述目的、特徵和優點能更明顯易懂 文特舉較佳實施例，並配合所附圖式，作詳細說明如 下· 實施方式： 、以下配合第3a到3e圖說明本發明實施例之内連線之 造方法，適用於半導體裝置。 、 首先，請參照第3a圖，首先，提供—基底2〇〇， 底或其他半導體基底，其上方可以形成任何所需 丰導體元件，例如MOS電晶體、電阻、邏輯元件等，、， 此處為了簡化圖式，僅以平整的基板2〇〇 明的敘述中，"基底"一詞係包括半導體晶y上已形成的系
0503-8431TWF(Nl) ； TSMC2002-0338;spin.ptd 1229412 五、發明說明（7) 件與覆蓋在晶圓上的各種塗層。再者，基底2〇〇更包含一 嵌入其中之接線層2 0 2 ’例如銅金屬接線層。 藉由習知之沉積技術，例如化學氣相沉積（chemical vapor deposition，CVD)，在基底2〇◦上方依序交替沉積 餘刻終止層2 0 4、2 0 8及絕緣層2 〇 6、2 1 0。另外，可選擇性 地在絕緣層210上在形成一抗反射層212，其材質可為氮氧 化矽，用以在後續進行微影製程時，避免光學干擾現象， 例如駐波效應（standing wave effect)。
餘刻終止層2 0 4、2 0 8分別提供於後續雙鑲嵌製程中定 義介層洞及溝槽之用，其材質可為氮化石夕或碳化石夕。 再者，絕緣層2 0 6、2 1 〇係用以作為金屬層間介電 (intermetal dielectric， IMD)層，其材質可為：電漿 氧化矽、低介電常數旋塗式玻璃（S0G )、四乙氧基石夕玻 璃（TEOS oxide)、填摻雜氧化石夕、氟石夕玻璃（fsg)、 磷矽玻璃（PSG )、高密度電漿所沈積的未摻雜矽玻璃 (HDP-USG)、高密度電漿所沈積的氧化矽（HDp-Si〇2)、 次壓化學氣相沈積法（S A C V D )所沈積的氧化石夕、以及以 臭氧-四乙氧基矽烷（〇3-TEOS )所沈積的氧化矽等。
接下來，請參照第3b圖，在抗反射層2 1 2上塗覆一光 阻層（未繪示），並藉由習知曝光顯影步驟在其中形成開 口 （未繪示）。接著，以具有開口之光阻層作為罩幕，並 藉由傳統之非等向性触刻，例如反應離子餘刻（r e a c t i v e ion etching，RIE )來蝕刻開口下方之抗反射層2i 2及交 替堆疊之蝕刻終止層204、208及絕緣層20 6、210，以形成
0503-8431TW(Nl) ； TSMC2002-0338;spin.ptd 第12頁 1229412 五、發明說明（8) 一鑲嵌開口，例如單鑲嵌開口或是經由兩次微影蝕刻步驟 所形成之雙鑲嵌開口，並露出接線層202表面。此處，本 貫施例係以雙鑲嵌開口 2 1 3作為範例，然而熟習此技藝之 人士可輕易了解到本發明並未受限於此。 藉由習知之沉積技術，例如CVD或物理氣相沉積 (Physical vapor deposition，PVD)，在抗反射層 212 上及鑲嵌開口 2 1 3内表面順應性形成一金屬阻障層2i 4，其 厚度約在1 0到1 〇 〇的埃範圍且材質可為鈦、钽、氮化鈦、 氮化组、鈦鶴合金、氮化鶴等。 接下來’請參照第3 c圖，進行本發明之關鍵步驟。完 成金屬阻障層214之後，對其實施一氧化程序，例如熱氧 化程序，以形成氧化的金屬阻障層2丨6。其目的將於本文 稍後說明。 接著，原位去除鑲嵌開口 2 1 3底部之氧化的金屬阻障 層2 1 6而露出接線層2 0 2表面，再在金屬阻障層2 1 6上順應 性沈積一層厚約600〜1 200埃（A )的具摻雜的金屬晶種層 2 2 2。在本實施例中，具摻雜的金屬晶種層2 2 2係由一具摻 雜的薄銅層218及一薄純銅層220所構成，而所摻雜元^係 鎂、鋁、錯、錫或铪。其中，具摻雜的薄銅層之厚度在 50〜300埃的範圍。此處，使用兩層之目的在於避免具摻雜 的金屬晶種層222之摻雜元素濃度過高而在後續製程中產 生漏電流。 ' 接下來，請參照第3 d圖，可藉由電化學電鍍沈積法 (electrochemical plating, ECP)在具摻雜的金屬晶種
0503-8431TW(Nl) ； TSMC2002-0338;spin.ptd 第13頁 1229412
層222上形成一金屬層224，例如銅金屬層，並使其填滿鑲 嵌開口213。隨後，對金屬層224實施一回火處理 (annealing )，使銅金屬層224得以達到穩定化。同時， 藉由此回火處理，使得具摻雜的薄銅層218中摻雜元素擴 散至氧化的金屬阻障層2 1 6並與其中的氧原子產生作用，、 而於鑲肷開口 2 1 3與金屬層2 2 4之間形成摻雜金屬氧化層 2 2 6。此摻雜金屬氧化層2 2 6之作用如同一擴散阻障層。在 本實施例中，回火處理的溫度在2〇〇。(：到4〇〇。(：的範圍且回 火時間在3 0到1 8 0 0秒的範圍。 最後，請參照第3e圖，藉由一研磨t程序，如化學機械 研磨法（CMP )，進行平坦化，並將鑲嵌開口 2 1 3以外多餘 的金屬層224、金屬晶種層220、摻雜金屬氧化層2ΐβ以及、 抗反射層212去除，而在鑲嵌開口213中形成餘留的金屬層 224a、餘留的金屬晶種層220a以及餘留的摻雜金屬氧化層 226a。其中，餘留的金屬層224a與餘留的金屬晶種層22〇a 係用以作為金屬内連線層228。如此一來，便完成本發明 之金屬内連線之製作。 同樣地，請參照第3e圖，其繪示出根據本發明實施例 之金屬内連線結構剖面示意圖。此結構包含：一基底 200、蝕刻終止層204、208、絕緣層206、210、一導電層 211、一摻雜金屬氧化層226a、及一金屬層22“。在本實 施例中，基底200可為一石夕基底或其他半導體基底，其上 方可以形成任何所需的半導體元件（未繪示），例如从的 電晶體、電阻、邏輯元件等。再者，基底2〇〇更包含一嵌
4 1229412 五、發明說明（10) 入其中之接線層202，例如銅金屬接線層。 基底200上設置有交替排置之餘刻終止層μα、208及 絕緣層206、210，且其中具有一雙鑲嵌開口 213而露出接 線層202表面。此處雖以雙鑲嵌開口作為範例，然而本發 明並未受限於此，此開口 2 1 3亦可為一單鑲嵌開口。 钱刻終止層2 0 4、2 0 8分別提供於後續雙鎮嵌製程中定 義介層洞及溝槽之用’其材質可為氮化石夕或碳化石夕。再 者，絕緣層2 0 6、2 1 0係用以作為金屬層間介電 (intermetal dielectric, IMD)層，其材質可為：電漿 氧化矽、低介電常數旋塗式玻璃（s〇G )、四乙氧基矽玻 璃（TEOS oxide)、碗摻雜氧化石夕、氟石夕玻璃（mg)、 磷矽玻璃（PSG )、高密度電漿所沈積的未摻雜矽玻璃 (HDP-USG)、高密度電漿所沈積的氧化矽（HDp-Si〇2)、 次壓化學氣^相沈積法（SACVD )所沈積的氧化矽、以及以 臭氧-四乙氧基矽烷（〇3 —TE0S )所沈積的氧化矽等。 一銅晶種層220a及藉由電化學電鍍沈積法（Ecp )形 成之銅金屬層224a係設置於鑲嵌開口 213内，以 内連線228。 _ 摻雜金屬氧化層226a係設置於鑲嵌開口 213與金屬内 連線228之間，其作用如一擴散阻障層以防止鋼原子之 散：再者’其中所摻雜之元素可為鎂、鋁、鍅、錫或铪、 元素。 接y來，請參照第4圖，其繪示出累積失效百分比（％ )與失政時間（hr )之關係曲線圖。其中，曲線b表示習
1229412 ! H. 五、發明說明（11) 一 用具摻雜的銅金屬層作為内連線且完全不使 二Γ表示根據本發明之方法使Ϊ 障層之情形。心ίί ϊ線配合同時使用氧化的金屬阻 於本；知技術延長兩個級數倍數以上。此乃由 程序中形成摻；：屬的=層：=金屬阻障層在回火 地阻擋銅原子二:減=孔洞的發生，同時也能有效 可靠度。子的擴放’進而提升内連線之品質以及元件之 雖然本發明已以較祛 限定本發明，任何熟習此項‘二者，：二然其並非用以 當視後附之申請專者本發明之保護範圍 _ 第16頁 〇5〇3-8431TW(Nl) ； TSMC2002-0338;spin.ptd 1229412 圖式簡單說明 第1圖係繪示出習知之使用具摻雜的銅金屬之内連線 結構示意圖。 第2圖係繪示出第1圖中A處之放大示意圖。 第3a到3e圖係繪示出根據本發明實施例之内連線之製 造方法。 第4圖係繪示出累積失效百分比（％ )與失效時間（hr )之關係曲線圖。 符號說明： 習知 1 0 0〜基底； 1 0 2〜金屬接線層 1 0 4、1 0 8〜蝕刻終止層； 1 0 6、11 0〜絕緣層； 11 4〜金屬内連線層 111〜鑲嵌開口； 1 1 5〜孔洞。 本發明 2 0 2〜接線層 Φ 2 0 0〜基底； 2 0 4、2 0 8〜#刻終止層； 2 0 6、2 1 0〜絕緣層； 2 1 2〜抗反射層； 213〜镶欲開口； 214〜金屬阻障層； 2 1 6〜氧化的金屬阻障層； 2 1 8〜具摻雜的薄銅層； 2 2 0〜薄純銅層； 2 2 0 a〜餘留的薄純銅層 222〜具摻雜的金屬晶種層；
〇503-8431TW(Nl) ： TSMC2002-0338;spin.ptd 第17頁 4 1229412 圖式簡單說明 224〜金屬層； 224a〜餘留的金屬層 226〜摻雜金屬氧化層； 226a〜餘留的摻雜金屬氧化層； 228〜内連線層。 # %
0503-8431TW(Nl) ： TSMC2002-0338;spin.ptd 第18頁

Claims (1)

1229412 "’"丨丨丨丨 六、申請專利範圍 種金屬内連線之製造方法 提供一基底； 巴括下列步驟·· 在該基底上形成至少一蝕刻終止芦 在該蝕刻終止層及該絕緣層中形^至 > 一絕緣層； 該基底表面； 7成至y 一開口以露出 在該開口側壁及底部形成— 氧化該金屬阻障層； 丨早層， 層 表面去除該開口底部之該氧化的金屬阻障層而露出該基底 在該氧化的金屬阻障層上形 八摻雜的金屬晶種 ^該開口内填人—金屬層以作為金屬内連線； 貫轭-回火處理’以在該開口與之 摻雜金屬氧化層。 屬尽之間形成一 法 2盆：：=利範圍第1項所述之金屬内連線之製造方 ，/、中a亥基底係一半導體基底。 法 3 ·如申.明專利範圍第j項所述之金屬内連線之製造方 ，其中該蝕刻終止層係一氮化矽層或一碳化矽層。 法 % 4·如申請專利範圍第1項所述之金屬内連線之製造方 ，其中該開口係一單鑲嵌或雙鑲嵌開口。 法 5·如申請專利範圍第1項所述之金屬内連線之製造方 ’其中該金屬.阻障層係鈦、钽、氮化鈦或氮化钽。 法 6 ·如申請專利範圍第5項所述之金屬内連線之製造方 ，其中該金屬阻障層之厚度在10〜1〇〇埃的範圍。 0503-8431TW(Nl) ； TSMC2002-0338;spin.ptd 第19頁 1229412 申請專利範圍 7甘=申凊專利範圍第丨項所述之金屬内連線 Lf:藉由物理氣相沉積法形成該具摻雜的金屬曰造方 ::去除該開口底部之該具摻雜的 ：曰:種層 的金屬阻障層。 徑層及該氧化 m請專利範圍第μ所述之金屬内 Li具摻雜的金屬晶種層係由-具摻雜的鋼二 / 、，s層所構成且摻雜元素係鎂、鋁、鍅、錫或铪。㈢~ 、9 ·如申印專利範圍第8項所述之金屬内連線之势1 法 >，其中該具摻雜的金屬晶種層厚度在400 ~ 1 20 0埃^^ 且該具摻雜的銅層之厚度在50〜300埃的範圍。 & 、10·如申請專利範圍第8項所述之金屬内連線之製造方 法，其中該金屬層係一銅金屬層並藉由電化學電鍍法所形 成0 1 1 ·如申請專利範圍第1項所述之金屬内連線之製造方 法’其中該回火處理之溫度在2 〇 〇 °C到4 0 0 °C的範圍。 1 2 · —種金屬内連線結構，包括： 一基底；
一餘刻終止層及一絕緣層，依序設置於該基底上且具 有至少一開口以露出該基底表面； 一金屬層，設置於該開口内以作為一内連線；以及 一換雜金屬氧化層，形成於該開口與該金屬層之間。 1 3 ·如申請專利範圍第1 2項所述之金屬内連線結構’ 其中該基底係一半導體基底。 1 4 ·如申請專利範圍第1 2項所述之金屬内連線結構，
0503-8431TWFCN1) ； TSMC2002-0338;spin.ptd 第20貢 4 1229412 六、申請專利範圍 其令該蝕刻終止層係一氮化矽層戒一碳化矽層。 1 5 ·如申請專利範圍第1 2項所述之金屬内連線結構， 其中該開口係一單鑲嵌開口。 1 6·如申請專利範圍第丨2項所述之金屬内連線結構， 其中4金屬層係一銅金屬層並藉由電化學電鍍法所形成。 1 7·如申請專利範圍第丨6項所述之金屬内連線結構， 其中該金屬層更包括一銅晶種層。 1 8 ·如申請專利範圍第丨2項所述之金屬内連線結構， 其中該摻雜金屬氧化層之摻雜元素係鎂、鋁、鍅、錫或 給。 19· 一種半導體裝置，包括： 一基底，該基底上形成至少^半導體元择；以及 一内連線結構，與該半導體元件電性連接，其中該内 連線結構包括： 至少一蝕刻終止層及至少/絕緣層，依序設置於該基 底上且具有至少一開口以露出該基底表面， 一金屬層，設置於該開口内以作為一内連線；以及 一摻雜金屬氧化層，形成於該開口側壁與該金屬層之 間。
20·如申請專利範圍第19項所述之半導體裝置，其中 該基底係一半導體基底。 2 1 ·如申請專利範圍第1 9項所述之半導體裝置，其中 該蝕刻終止層係一氮化矽層或〆碳化矽層。 22·如申請專利範圍第19項所述之半導體裝置，其中
0503-8431TW(Nl) ： TSMC2002-0338;spin.ptd 第 21 頁 1229412 六、+請專利範圍 ~" — --"" " 丨該開口係-單鑲嵌或雙鑲嵌之開口。 ^ 23·如申請專利範圍第ι9項所述之半導體裝置，其中 遠金屬層係一銅金屬層並藉由電化學電鍍法所形成。 ^ 24·如申凊專利範圍第23項戶斤述之半導體裝置，其中 4金屬層更包括一鋼晶種層。 2 5 ·如申請專利範圍第1 9項所述之半導體裝置，其中 該摻雜金屬氧化層之摻雜元素係錶、鋁、鍅、錫或铪。 2 6 · —種金屬内連線結構，包栝： 一基底； 一第一蝕刻終止層、一第〆絕緣層、一第二蝕刻終止 層及一第二絕緣層，依序設置於該基底上，且具有至少一 溝槽位於该第二钱刻終止層及該第一絕緣層中及一介層洞 位於該溝槽下方之該第一蝕刻終土層及該第一絕緣層中以 露出該基底表面； 一金屬層，設置於該溝槽及該介層洞内以作為一内連 線；以及 一摻雜金屬氧化層，形成於該溝槽及該介層洞之側壁 與該金屬層之間。 2 7·如申請專利範圍第26項所述之金屬内連線結構， 其中該基底係一半導體基底。 28·如申請專利範圍第26項所述之金屬内連線結構， 其中該蝕刻終止層係一氮化矽層或一碳化矽層。 2 9·如申請專利範圍第26項所述之金屬内連線結構， 其中該金屬層係一銅金屬層並藉由電化學電鍍法所形成。
4 1229412 六、申請專利範圍 30·如申請專利範圍第29項所述之金屬内連線結構， 其中該金屬層更包括一銅晶種層。 3 1 ·如申請專利範圍第2 6項所述之金屬内連線結構， 其中該摻雜金屬氧化層之摻雜元素係鎂、鋁、锆、錫或 铪。
0503-S43nW(Nl) ： TSMC2002-0338;spin.ptd 第 23 頁
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