1223498 玖、發明說朋 【發明所屬之技術領域】 本發明係關於振幅轉換電路，尤其是關於供轉換信號振 幅用的振幅轉換電路。 【先前技術】 -圖2 7所示係相關習知行動電話之影像顯示部分構造的 方塊圖。 在圖27中，此行動電話係具備有：屬於MOST(MOS電晶 體）型積體電路的控制用LSI71、屬於MOST型積體電路的 位準轉換器72、以及屬於TFT (薄膜電晶體）型積體電路的 液晶顯示裝置7 3。 控制用LS171係產生液晶顯示裝置73用的控制信號。 此控制信號的「Η」位準爲3 V，而「L」位準則爲0 V。控 制信號實際上產生多數個，但是在此爲求說明上的簡化， 便將控制信號設定爲一個。位準轉換器72係將來自控制用 L S I 7 1的控制信號之邏輯位準進行轉換，而產生內部控制 信號。此內部控制信號的「Η」位準爲7.5 V，而「L」位準 則爲0V。液晶顯示裝置73係依據來自位準轉換器72的內 控制信號而顯示出影像。 圖2 8所示係位準轉換器7 2構造的電路圖。在圖2 8中， 此位準轉換器72係包含有：Ρ通道MOS電晶體74,75、及Ν 通道MOS電晶體76,7 7。Ρ通道MOS電晶體7 4,7 5係分別 連接於電源電位 V C C ( 7.5 V )的節點 ν 7 1與輸出節點 Ν74，Ν75之間，該等的閘極則分別連接於輸出節點 5 312/發明說明書(補件)/92-〇5/奶〇438〇 1223498 N7 5，N74。N通道MOS電晶體7 6,7 7係分別連接於輸出節 點N74，N75與接地電位GND的節點之間，該等的閘極則 分別接收輸入信號VI，/VI。 現況乃將輸入信號VI，/VI分別設定爲「L」位準（0V)， 以及「H」位準（3V)，而輸入信號VO，/VO則分別設定爲「H」 位準（7.5 V)，以及「L」位準（0V)。此時，MOS電晶體74,77 將呈導通狀態，而MOS電晶體75，76則呈非導通狀態。 在此狀態下，若輸入信號VI從「L」位準（0V)提昇至「H」 位準（3V)，同時輸入信號/ VI從「H」位準（3V)下降至「L」 位準（0V)的話，首先N通道MOS電晶體76便將導通，並 降低輸出節點N74的電位。輸出節點N74的電位若較電源 電位VCC減掉P通道MOS電晶體75的臨限電壓的絕對値 後的電位値爲低的話，P通道MOS電晶體75便開始導通， 而輸出節點N75電位便將開始上升。若輸出節點N75的電 位開始上升的話，P通道MOS電晶體74之源極-閘極間的 電壓將變小，而P通道MOS電晶體74的導通電阻値則將 變高，使輸出節點N74的電位更加降低。所以，電路便將 正回饋（positive feedback)的進行動作，輸入信號V0，/V0 則將分別變成「L」位準（0V)與「Η」位準（7·5 V)，而完成 位準轉換動作。 再者，亦有將Ρ通道MOS電晶體74,7 5的閘極二者均連 接於一個輸出節點Ν74或Ν75的位準轉換器。此種位準轉 換器有如日本專利特開平1 1 - 1 4 5 8 2 1號公報中所揭示者。1223498 发明, invention said [Technical field to which the invention belongs] The present invention relates to an amplitude conversion circuit, and more particularly to an amplitude conversion circuit for converting the amplitude of a signal. [Prior art]-Fig. 27 is a block diagram showing the structure of a video display part of a related conventional mobile phone. In FIG. 27, this mobile phone is provided with a control LSI 71 which is a MOST (MOS transistor) integrated circuit, a level converter 72 which is a MOST integrated circuit, and a TFT (thin film transistor) type. Integrated circuit liquid crystal display device 73. The control LS171 series generates a control signal for the liquid crystal display device 73. The "Η" level of this control signal is 3 V, and the "L" bit criterion is 0 V. There are actually many control signals, but in order to simplify the explanation, the control signal is set to one. The level converter 72 converts the logic level of the control signal from the control L S I 7 1 to generate an internal control signal. The “Η” level of this internal control signal is 7.5 V, and the “L” level is 0V. The liquid crystal display device 73 displays an image based on an internal control signal from the level converter 72. FIG. 28 is a circuit diagram of the structure of the level converter 72. In FIG. 28, the level converter 72 includes: P-channel MOS transistors 74, 75, and N-channel MOS transistors 76, 77. The P-channel MOS transistors 7 4, 7 and 5 are respectively connected to the node ν 7 1 of the power supply potential VCC (7.5 V) and the output nodes N74 and N75, and the gates of these are respectively connected to the output node 5 312 / invention Instruction (Supplement) / 92-〇5 / Milk 0438 0223498 N7 5, N74. N-channel MOS transistors 7 6, 7 7 are respectively connected between the output nodes N74, N75 and the node of the ground potential GND. The gates of these channels respectively receive the input signals VI, / VI. The current situation is that the input signals VI, / VI are set to the "L" level (0V) and "H" level (3V), while the input signals VO, / VO are set to the "H" level (7.5 V ), And the "L" level (0V). At this time, the MOS transistors 74 and 77 will be in a conductive state, while the MOS transistors 75 and 76 will be in a non-conductive state. In this state, if the input signal VI rises from the "L" level (0V) to the "H" level (3V), and the input signal / VI falls from the "H" level (3V) to the "L" level If (0V), first the N-channel MOS transistor 76 will be turned on and the potential of the output node N74 will be reduced. If the potential of the output node N74 minus the absolute threshold value of the threshold voltage of the P-channel MOS transistor 75 is lower than the power supply potential VCC, the P-channel MOS transistor 75 will start conducting, and the potential of the output node N75 will Began to rise. If the potential of the output node N75 starts to rise, the voltage between the source and the gate of the P-channel MOS transistor 74 will become smaller, and the on-resistance 値 of the P-channel MOS transistor 74 will become higher, making the The potential is further reduced. Therefore, the circuit will perform positive feedback, and the input signal V0, / V0 will become the "L" level (0V) and "Η" level (7.5 V), respectively, and complete the level Conversion action. Furthermore, there are level converters in which both the gates of the P-channel MOS transistors 74 and 75 are connected to one output node N74 or N75. Such a level converter is disclosed in Japanese Patent Laid-Open No. 1 1-1 4 5 8 21.
如此的話，習知的位準轉換器72乃以配合輸入信號VI 6 312/發明說明書(補件)/92-05/92104380 1223498 從「L」位準（〇V)提昇至「h」位準（π)，而導通N通道 MOS電晶體76爲產生動作的提前。在爲導通n通道M〇s 電晶體76方面’便必須使N通道M〇S電晶體μ的臨限 電位在輸入信號V I的「η」位準（3 V )以下。 在一般的半導體LSI中，將電晶體的臨限電位設定在3V 下之事雖尙屬容易，但是對液晶顯示裝觼中所含的低溫多 晶矽T F T而言’則因爲臨限電壓的誤差較大，頗難將τ F τ 的臨限電壓設定在3 V以下。因此，如圖2 7所示，便將由 局耐壓Μ Ο S電晶體所構成的位準轉換器7 2，設置在控制 用L S I 7 1與液晶顯不裝置7 3之間，並執行信號的邏輯位準 轉換。 但是’若設計此種位準轉換器7 2的話，位準轉換器7 2 的成本將加計於系統成本上，導致系統成本上升。 【發明內容】 有鑒於斯，本發明的主要目的在於提供一種即便在輸入 信號的振幅電壓低於輸入電晶體的臨限電壓之情況下，仍 可正常進行動作的振幅轉換電路及採用其之半導體裝置。 本發明的振幅轉換電路係爲將其振幅屬於第1電壓的第 1信號，轉換爲其振幅高於第1電壓之屬於第2電壓的第2 信號，而具備有：第1導電形式第1與第2電晶體、第2導 電形式第3與第4電晶體；以及驅動電路。第1與第2電 晶體的第1電極均接收第2電壓，該等的第2電極則分別 連接於供輸出第2信號與其互補信號用的第1與第2輸出 節點上，該等的輸入電極則分別連接於第2與第1輸出節 7 312/發明說明書(補件)/92-05/921 (M3 80 1223498 點。第3與第4電晶體的第1電極係分別連接於第1與第 2輸出節點上。驅動電路係利用第1信號與其互補信號而 驅動著，並響應第1信號的互補信號前緣，將高於第1電 壓的第3電壓供應給第3電晶體的輸入電極與第2電極 間’俾導通第3電晶體，響應著第1信號之互補信號後緣 所對應的上述第1信號前緣，將第3電壓供應給第4電晶 體的輸入電極與第2電極之間，而導通第4電晶體。所以， 因爲將響應著第1信號之互補信號前緣、或第1信號前緣， 將高於第1電壓的第3電壓提供給第3或第4電晶體的輸 入電極與第2電極間，而導通第3或第4電晶體，因此即 便第1信號的振幅低於第3與第4電晶體的臨限電壓之情 況下，仍可正常的動作。 再者，本發明的另一振幅轉換電路，係爲將其振幅屬於 第1電壓的第1信號，轉換爲其振幅高於第1電壓之屬於 第2電壓的第2信號，而具備有：第〗導電形式第1與第2 電晶體、第2導電形式第3與第4電晶體；以及驅動電路。 第1與第2電晶體的第1電極均接收第2電壓，該等的第 2電極則分別連接於供輸出第2信號與其互補信號用的第1 與第2輸出節點上，該等的輸入電極則均連接於第2輸出 節點。第3與第4電晶體的第1電極係分別連接於第1與 第2輸出節點上。驅動電路係利用第1信號與其互補信號 而驅動著，並響應第1信號的互補信號前緣，將高於第1 電壓的第3電壓供應給第3電晶體的輸入電極與第2電極 間，俾導通第3電晶體，響應著第1信號之互補信號後緣 8 312/發明說明書(補件)/92-05/921043 80 1223498 所對應的上述第1信號前緣，將第3電壓供應給第4電晶 體的輸入電極與第2電極之間，而導通第4電晶體。所以， 因爲將響應著第1信號之互補信號前緣、或第1信號前緣， 將高於第1電壓的第3電壓提供給第3或第4電晶體的輸 入電極與第2電極間，而導通第3或第4電晶體，因此即 便第1信號的振幅低於第3與第4電晶體的臨限電壓之情 況下，仍可正常的動作。 【實施方式】 圖1爲顯示本發明一實施形態之行動電話影像顯示關聯 部分的構造的方塊圖。 在圖1中，此行動電話係具備有：屬於MOST型積體電路 的控制用LSI1、及屬於TFT型積體電路的液晶顯示裝置2 液晶顯示裝置2係含有：位準轉換器3與液晶顯示部4。 控制用L S11係輸出液晶顯示裝置2用的控制信號。此 控制信號的「Η」位準爲3 V，而「L」位準則爲〇 V。控制 信號實際上產生多數個，但是在此爲求說明上的簡化，便 將控制信號設定爲一個。位準轉換器3係將來自控制用 L S 11的控制信號之邏輯位準進行轉換，而產生內部控制信 號。此內部控制信號的「Η」位準爲7 · 5 V，而「L」位準則 爲0 V。液晶顯示裝置4係依據來自位準轉換器3的內控制 信號而顯示出影像。 圖2爲顯示位準轉換器3構造的電路圖。在圖2中，此 位準轉換器3係包含有·_Ρ型TFT5,6、Ν型TFT7〜14、電容 器15，16、及電阻元件17。P型TFT5,6係分別連接於電源 9 312/發明說明書(補件)/92-05/92104380 1223498 電位V C C ( 7 · 5 V )的節點N 1與輸出節點N 5，N 6之間，該等 的閘極則分別連接於輸出節點N6，N5。在輸出節點N5，N6 中所出現的信號分別形成此位準轉換器3的輸入信號 VO，/VO。N型TFT7連接於節點N5與N7之間，其閘極則 連接於節點N 1 1。N型T F T 8連接於節點N 6與N 8之間， 其閘極則連接於節點N 1 3。對節點n 7，N 8分別供應輸入信 號VI與其互補信號/VI。 電阻元件1 7與N型TF T9,1 〇係串聯連接於電源電位VCC 之節點N 1、與接地電位G N D之節點之間。n型T F T 9之閘 極係連接於其汲極（節點N 9)上，N型T F T 1 0之閘極連接於 其汲極上。N型TFT9,10係分別構成二極體元件，電阻元 件17與N型TFT9，10係構成定電位產生電路。若將電阻 元件1 7的電阻値設定爲充分大（譬如1 〇 〇 Μ Ω )，並將N型 T F Τ 9，1 0的導通電阻値設定爲充分小於電阻元件i 7電阻値 的話，節點N9的電位V9便將成爲V9 = 2VTN。其中，VTN 係指N型TFT的臨限電位。 N型TFT11係連接電源電位VCC之節點N1與節點Nil 之間，其閘極將接收節點N9的電位V9。N型TFT12係連 接於節點N 1 1與N 1 2之間，其閘極則連接於節點N 1 1上。 N型TFT 1 2係構成二極體元件。電容器1 5係連接於節點 Nil與N12之間。對節點N12提供信號/ VI。 N型TFT13係連接電源電位VCC之節點N1與節點N13 之間，其閘極將接收節點N 9的電位V 9。N型T F T 1 4係連 接於節點N 1 3與N 1 4之間，其閘極則連接於節點N 1 3上。 10 312/發明說明書(補件)/92-05/92104380 1223498 N型TFT 1 4係構成二極體元件。電容器1 6係連接於節點 N 1 3與N 1 4之間。對節點N 1 4提供輸入信號VI。 其次，針對此位準轉換器3的動作進行說明。現今若將 輸入信號V I，/ V I分別設定爲3 V、Ο V的話，N型T F T 1 1便 將藉由源極浮置動作，使節點 Nil的電位 V1 1成爲 V11=2VTN-VTN = VTN。此外，因爲連接於二極體的N型 TFT12之臨限電位將爲VTN，因此幾乎未從電源電位VCC 的節點N1對節點N12流入電流。因爲N型TFT7的閘極 電位爲V11=VTN，其源極電位爲3V，因此N型TFT7便 將呈非導通狀態。電容器1 5便被充電至臨限電壓V TN。 此外，如後述，因爲節點N 1 3的電位V 1 3將昇壓至V T N 以上，且節點N8將變爲0V，因此N型TFT 8便將被導通。 結果，輸出節點N6便將成爲輸入節點N8的電位（0V)，而 導通P型TFT5，並使輸出節點N5成爲電源電位VCC。藉 此，P型TFT6便將處於非導通狀態，在電源電位VCC之 節點N 1與輸入節點N8之間並未流通電流。 其次，若將輸入信號VI從3 V下降至0V，同時將輸入 信號/VI從0V上升至3 V的話，輸入信號/VI的電位變化 變將藉由電容耦合而經由電容器1 5傳輸給節點N 1 1，使節 點Nil的電位VII被昇壓。若將電容器15的電容量設定 爲充分大於節點Nil之寄生電容（未圖示）的電容量的話， 節點 Nil 的電位 VII 便將成爲 VII与VTN+ △ VI = VTN + 3V。其中，△ VI係指輸入信號VI，/VI的振幅， 爲3V。因爲N型TFT7的源極（節點N7)電位將變爲0V， 11 312/發明說明書(補件)/92-05/921043 80 因此N型TFT7的閘極-源極間電壓將爲vtn + 3 V，而導通 N型TFT7。結果，輸出節點N5的電位便將爲0V，而導通 P 型 TFT6 。 此外，輸入信號VI從3V至0V的電位變化，將利用電 容耦合而經由電容器1 6傳輸給節點N 1 3，而使節點N 1 3 的電位V13降壓。當輸入信號VI，/VI的變化週期屬於較短 的情況時，因爲在降壓前的節點N 1 3之電位V 1 3將成爲 V13=VTN + 3V，因此降壓時的節點N13之電位V13便將成 爲V13 = VTN + 3V-3V = VTN。當輸入信號VI，/VI的變化週期 屬於較長的情況時，因爲節點N 1 3之電位V 1 3將處於藉由 電容耦合而昇壓的電位狀態，因此將隨時間而降低。因此， 節點N13之電位V13僅降低較輸入信號VI，/VI變化週期 較短之情況時的値VTN爲低的部分，此情況下，N型TFT 1 3 將導通，而將節點N13的電位V13拉升至VTN。 如上述，因爲N型TFT8的閘極電位V13將變爲VTN， 而其源極（節點N8)電位將變爲3V。因此N型TFT8便處於 非導通狀態。結果，輸出節點N6的電位便將爲7.5 V，而 P型T F T 5則變爲非導通狀態。如此的話，輸出節點N 5，N 6 便將分別爲〇V、7.5 V，而形成執行從3 V變爲7 · 5 V的邏 輯位準轉換。 在本實施形態中，因爲響應著輸入信號VI的下降邊緣， 將N型TFT7的臨限電壓VTN中加計著輸入信號/VI之振 幅電壓（3 V )後的電壓V T N + 3 V，供應給N型T F T 7的閘極-源極間，因此即便輸入信號/VI的振幅電壓（3V)低於N型 12 312/發明說明書(補件)/92-05/92104380 1223498 TFT7的臨限電壓VTN之情況時，仍可使位準轉換器3正 常的產生動作。所以，如圖1所示，可將位準轉換器3與 ^ 液晶顯示部4形成一個液晶顯示裝置2 ( T F Τ型積體電路）。 ’ 所以，相較於需要個別設計位準轉換器5 2與液晶顯示裝^ 5 3的習知技術之下，可減少組件數量，並降低系統成本。 再者，雖在動作中途過度性的流通著電源電流，但是除 電阻元件17與Ν型TFT9，10之外，並未流通直流的電流。 因爲電阻元件1 7電阻値設定爲較大値，而僅流通.著微小電 流，因此位準轉換器3的消耗功率極小。 鲁 再者，在本實施形態中雖採用TFT5〜Μ，但是亦可取代 TFT而改爲採用MOS電晶體。此情況下，即便在輸入信號 VI，/VI的振幅小於MOS電晶體臨限電壓的情況下，仍可進 行動作。 再者，在本實施形態中雖採用屬於絕緣閘型場效電晶體 的TFT，但是當然亦可採用其他形式的場效電晶體。 以下，針對此實施形態的各種變化例進行說明。在圖3 φ 之位準轉換器20中，N型TFT 12，14的源極呈接地狀態。 在此變化例中，因爲N型TFT 12，14的電流將不致流入節 點Ν 1 2，N 1 4中，而流入接地電位GND的節點中，因此輸 入信號VI，/VI的驅動力便將變小。 在圖4的位準轉換器2 1中，對P型T F T 5，6的源極賦予 電源電位VCC(7.5V)，並對N型TFT11的汲極賦予不同於 電源電位V C C的正電源電位V C C ’，對電阻元件1 7的其中 一電極（未連接於節點N9上的電極）賦予不同於電源電位 13 312/發明說明書(補件)/92_05/92104380 1223498 vcc，vcc，的電源電位VCC”。在此變化例中， 隨電源電位 VCC節點中所產生的雜音 N9，N11，N13的電位V9，V11，V13產生變動。 在圖5的位準轉換器2 2中，電阻元件1 7係由 所構成。換句話說，P型TFT23係連接於電源‘ 節點N1與節點N9之間，其閘極則連接於接 的節點。由 TFT所構成的電阻元件之平均單 値，係大於由擴散層所構成的電阻元件之平均 阻値。所以，在此變化例中，可縮小電阻元件的 另外，由閘極接收電源電位V C C的N型T F T 阻元件1 7，亦可獲得相同的效果。 在圖6的位準轉換器24中，追加設置N型 N型TFT25係連接於節點N5與N7之間，其閘 節點N6。N型TFT26係連接於節點N6與N8 極則連接於節點N5。若輸入信號VI，/VI分別J 與「L」位準，且輸入信號VO，/VO分別呈「H」 位準的話，N型TFT25便將呈非導通狀態，同時 將導通，而使輸出節點N5，N6分別保持於「Η」 位準。若輸入信號VI，/VI分別呈「L」位準與 且輸入信號VO，/VO分別呈「L」位準與「Η」 N型TFT25便將呈導通狀態，同時N型TFT26 通狀態，而使輸出節點N5，N6分別保持於「L」 位準。 當輸入信號VI，/VI的變化週期屬於非常長的 312/發明說明書(補件)/92-05/92104380 譬如可防止 ，而使節點 ]P M TFT23 電位V C C之 地電位GND 位面積電阻 單位面積電 J佔有面積。 所構成的電 TFT2 5,26 ° 極則連接於 之間，其閘 i「Η」位準 位準與「L」 Ν 型 TFT26 位準與「L」 「Η」位準， 位準的話， 將處於非導 位準與「Η」 f情況時，節 14 1223498 點N 1 1，N 1 3的電位V 1 1，V 1 3均將變成N型T F T的臨限電 位VTN，輸出節點Ν5與Ν6的電位關係有反轉的可能性。 N型TFT2 5,26便屬於供防止發生此種節點N5與N6的電 位關係反轉現象者，而在無關節點N11，N13的電位 V11，V13的情況下，將節點N5，N6的電位予以固定。 圖7的位準轉換器2 7係屬於將圖6所示位準轉換器2 4 的N型T F T 2 5，2 6之源極，連接於接地電位G N D的節點上 者。在此變化例中，因爲N型TFT25,26的電流並未流入 輸入節點N 7，N 8中，而是流入接地電位G N D的節點中， 因此便可減小輸入信號VI，/VI的驅動力。 圖8的位準轉換器3 0係屬於將圖2所示位準轉換器3 的N型TFT7,8之源極，均連接於接地電位Gnd節點上者。 在此變化例中，因爲N型TFT?，8的電流並未流入輸入節 點N7，N8中，而是流入接地電位GND的節點中，因此便 可減小輸入信號VI，/VI的驅動力。 圖9的位準轉換器3 1係屬於將圖7所示位準轉換器2 7 的N型TFT7,8,25,26之源極，均連接於接地電位GND節 點上者。在此變化例中，因爲N型TFT7,8,25,2 6的電流並 未流入輸入節點N 7，N 8中，而是流入接地電位g N D的節 點中，因此便可減小輸入信號VI，/VI的驅動力。 圖1 0的位準轉換器3 2係屬於將圖2所示位準轉換器3 的P型TFT5,6之閘極，均連接於節點N5上者。P型TFT5,6 係構成電流鏡電路（current mirror circuit)。在P型TFT 5 與6中流通著同値的電流。當輸入信號v I，/ VI非別呈「l」 15 312/發明說明書(補件)/92-05/92104380 1223498 位準與「Η」位準，且N型T F Τ 7，8分別呈導通狀態與非導 通狀態之情況時，與TFT5,7中所流通電流相同値的電流， 亦將流入於P型T F T 6中，並執行差洞放大。輸出節點n 5，N 6 便分別呈「L」位準與「Η」位準。在此變化例中，亦可獲 得如同圖2之位準轉換器3相同的振幅轉換效果。 圖1 1的位準轉換器3 3係屬於將圖6所示位準轉換器24 的Ρ型T F Τ 5，6之閘極，均連接於節點Ν 5上者。在此變化 例中，亦可獲得如同圖6之位準轉換器2 4相同的振幅轉換 效果。 圖1 2的位準轉換器3 4係屬於將圖1 〇所示位準轉換器 32的Ν型TFT7,8之源極均呈接地狀態者。在此變化例中， 因爲N型TFT7,8中所流通的電流並未流入輸入節點N7，N8 中，而是流入接地電位G N D的節點中，因此便可減小輸入 信號VI，/VI的驅動力。 圖1 3的位準轉換器3 5係屬於將圖1 1所示位準轉換器 33的N型TFT7,8,2 5,2 6之源極均呈接地狀態者。在此變 化例中，因爲N型TFT7,8,2 5,2 6中所流通的電流並未流入 輸入節點N 7，N 8中，而是流入接地電位g N D的節點中， 因此便可減小輸入信號VI，/VI的驅動力。 在圖1 4的變化例中，含有電阻元件1 7與N型T F T 9，1 0 的定電位產生電路3 6，係對複數位準轉換器3 8，3 9，…共通 設置。在定電位產生電路36的輸出節點N9、與接地電位 GND的節點之間，連接著電位安定化用電容器37。雖在爲 使電阻元件1 7的電阻値增加方面，需要增加電阻元件i 7 16 312/發明說明書(補件)/92-05/92104380 1223498 的面積，但是在本變化例中，因爲對複數位準轉換器 3 8，3 9，…共通設置定電位產生電路3 6，因此可減小整體電 路的佔有面積。 圖1 5的位準轉換器40係在圖2的位準轉換器3中，追 加設置P型TFT41，42者。P型TFT41係連接於P型TFT5 的汲極與輸出節點N5之間，其閘極則連接於節點N 1 1上。 P型TFT42係連接於P型TFT6的汲極與輸出節點N6之 間，其閘極則連接於節點N 1 3上。若輸入信號/VI從0V上 升至3V的話，節點Nil的電位VII便將爲VTN + 3V，使P 型TFT4 1呈非導通狀態，同時使導通N型TFT7，而使輸 出節點N5的電位變爲0V。因爲此時的P型TFT41處於非 導通狀態，因此電流並未從電源電位V C C的節點N 1流入 輸出節點N5中，而使輸出節點N5的電位容易下降爲0V。 若輸入信號/ VI從3V下降至0V的話，節點Nil的電位VII 便將爲VTN，N型TFT7便將處於非導通狀態，同時p型 T F T 4 1將導通，使輸出節點n 5的電位變爲7.5 V。 再者’若輸入信號VI從〇V上升至3V的話，節點N1 3 的電位V13便將爲VTN + 3V，使P型TFT42呈非導通狀態， 同時使導通N型TFT8，而使輸出節點N6的電位變爲0V。 因爲此時的P型TFT42處於非導通狀態，因此電流並未從 電源電位V C C的節點N1流入輸出節點N6中，而使輸出 節點N6的電位容易下降爲0V。若輸入信號vi從3V下降 至0V的話’節點N13的電位V13便將爲VTN，N型TFT8 便將處於非導通狀態，同時P型TFT42將導通，使輸出節 17 312/發明說明書(補件)/92-05/92104380 1223498 點N 6的電位變爲7 · 5 v。在此變化例中，因爲輸出節點 N 5，N 6的電位較容易降低至Ο V，因此便可將輸入信號 V I，/ V I的振幅僅縮小此部份，而使輸入信號v I，/ V I的振幅 邊限變大。 圖16〜26的位準轉換器45〜55係分別在圖3〜圖13所示 位準轉換器20〜22,24,27,30〜35中追加p型TFT41，42者。 該等變化例亦可獲得如同圖1 5之位準轉換器4 0相同的效 果。 本次所揭示的實施形態全部均僅止於例示而已，不可認 爲係屬於限制。本發明的範圍並非上述說明，而是經申請 專利範圍所揭示者，舉凡在與申請專利範圍具均等涵義與 範疇內的所有變化均涵蓋在內。 【圖式簡單說明】 圖1爲本發明一實施形態之行動電話影像顯示所關聯部 分的構造方塊圖。 圖2爲圖1所示位準轉換器構造的電路圖。 圖3〜26分別爲本實施形態變化例的電路圖。 圖2 7爲習知行動電話影像顯示所關聯部分的構造方塊 圖。 圖28爲圖27所示位準轉換器構造的電路圖。 (元件符號說明）In this case, the conventional level converter 72 is raised from the "L" level (0V) to the "h" level in accordance with the input signal VI 6 312 / Invention Specification (Supplement) / 92-05 / 92104380 1223498 (Π), and turning on the N-channel MOS transistor 76 advances the action. In order to turn on the n-channel MOS transistor 76, it is necessary to make the threshold potential of the N-channel MOS transistor μ below the "η" level (3 V) of the input signal VI. In general semiconductor LSIs, it is easy to set the threshold potential of a transistor at 3V, but for low-temperature polycrystalline silicon TFTs included in liquid crystal display devices, it is because the threshold voltage has a large error. It is quite difficult to set the threshold voltage of τ F τ below 3 V. Therefore, as shown in FIG. 27, a level converter 72 composed of a local withstand voltage MOS transistor is placed between the control LSI 71 and the liquid crystal display device 73, and the signal is executed. Logic level conversion. However, if the level converter 72 is designed, the cost of the level converter 72 will be added to the system cost, which will cause the system cost to increase. SUMMARY OF THE INVENTION In view of this, the main object of the present invention is to provide an amplitude conversion circuit capable of operating normally even when the amplitude voltage of an input signal is lower than a threshold voltage of an input transistor, and a semiconductor using the same. Device. The amplitude conversion circuit of the present invention is to convert a first signal whose amplitude belongs to the first voltage to a second signal whose amplitude is higher than the first voltage and belongs to the second voltage, and includes: a first conductive form; A second transistor, third and fourth transistors of a second conductive form; and a driving circuit. The first electrodes of the first and second transistors both receive the second voltage, and the second electrodes of these are respectively connected to the first and second output nodes for outputting the second signal and its complementary signal, and the inputs of such The electrodes are connected to the second and first output sections 7 312 / Invention Manual (Supplement) / 92-05 / 921 (M3 80 1223498 points. The first electrode systems of the third and fourth transistors are respectively connected to the first And the second output node. The driving circuit is driven by the first signal and its complementary signal, and in response to the complementary signal leading edge of the first signal, supplies a third voltage higher than the first voltage to the input of the third transistor The third transistor is turned on between the electrode and the second electrode, and a third voltage is supplied to the input electrode of the fourth transistor and the second transistor in response to the first signal leading edge corresponding to the complementary signal trailing edge of the first signal. The fourth transistor is turned on between the electrodes. Therefore, because the complementary signal leading edge of the first signal or the leading edge of the first signal is supplied, a third voltage higher than the first voltage is supplied to the third or fourth voltage. The third or fourth transistor is turned on between the input electrode of the transistor and the second electrode. If the amplitude of the signal is lower than the threshold voltage of the third and fourth transistors, it can still operate normally. In addition, another amplitude conversion circuit of the present invention is the first one whose amplitude belongs to the first voltage. The signal is converted into a second signal belonging to the second voltage whose amplitude is higher than the first voltage, and includes: a first conductive form of the first and second transistors, a second conductive form of the third and fourth transistors; and Driving circuit. The first electrodes of the first and second transistors both receive the second voltage, and the second electrodes of these are respectively connected to the first and second output nodes for outputting the second signal and its complementary signal. The input electrodes are equal to the second output node. The first electrodes of the third and fourth transistors are respectively connected to the first and second output nodes. The driving circuit is driven by the first signal and its complementary signal. And in response to the complementary signal leading edge of the first signal, a third voltage higher than the first voltage is supplied between the input electrode and the second electrode of the third transistor, and the third transistor is turned on in response to the first signal Complementary signal trailing edge 8 312 / Invention specification (Supplement) / 92-05 / 921043 80 12234 The leading edge of the first signal corresponding to 98 supplies the third voltage between the input electrode of the fourth transistor and the second electrode, and turns on the fourth transistor. Therefore, it will respond to the complementary signal of the first signal The leading edge, or the leading edge of the first signal, supplies a third voltage higher than the first voltage between the input electrode of the third or fourth transistor and the second electrode, and turns on the third or fourth transistor. If the amplitude of the first signal is lower than the threshold voltages of the third and fourth transistors, normal operation is still possible. [Embodiment] FIG. 1 shows a structure of a mobile phone image display related portion according to an embodiment of the present invention. In FIG. 1, this mobile phone is provided with: a control LSI1 which is a MOST type integrated circuit, and a liquid crystal display device 2 which is a TFT type integrated circuit. The liquid crystal display device 2 includes a level converter. 3 与 LCDdisplay section4. The control L S11 series outputs a control signal for the liquid crystal display device 2. The "Η" level of this control signal is 3 V, and the "L" bit criterion is 0 V. There are actually many control signals, but for simplicity of explanation, the control signal is set to one. The level converter 3 converts the logic level of the control signal from the control L S 11 to generate an internal control signal. The "Η" level of this internal control signal is 7 · 5 V, and the "L" bit criterion is 0 V. The liquid crystal display device 4 displays an image based on an internal control signal from the level converter 3. FIG. 2 is a circuit diagram showing the structure of the level converter 3. As shown in FIG. In FIG. 2, the level converter 3 includes _P-type TFTs 5,6, N-type TFTs 7 to 14, capacitors 15, 16, and a resistive element 17. The P-type TFT5 and 6 are respectively connected to the power source 9 312 / Invention Specification (Supplement) / 92-05 / 92104380 1223498 between the node N 1 of the potential VCC (7.5 V) and the output nodes N 5, N 6. The equal gates are connected to the output nodes N6 and N5 respectively. The signals appearing at the output nodes N5, N6 form the input signals VO, / VO of the level converter 3, respectively. N-type TFT7 is connected between nodes N5 and N7, and its gate is connected to node N 1 1. N-type T F T 8 is connected between nodes N 6 and N 8, and its gate is connected to node N 1 3. The nodes n 7, N 8 are respectively supplied with the input signal VI and its complementary signal / VI. The resistance element 17 and the N-type TF T9, 10 are connected in series between the node N 1 of the power supply potential VCC and the node of the ground potential G N D. The gate of n-type T F T 9 is connected to its drain (node N 9), and the gate of N-type T F T 1 0 is connected to its drain. N-type TFTs 9 and 10 each constitute a diode element, and resistor elements 17 and N-type TFTs 9 and 10 each constitute a constant potential generating circuit. If the resistance 値 of the resistance element 17 is set to be sufficiently large (for example, 100 Ω Ω), and the on-resistance 値 of the N-type TF T 9,10 is set to be sufficiently smaller than the resistance of the resistance element i 7, the node N9 The potential V9 becomes V9 = 2VTN. Among them, VTN refers to the threshold potential of N-type TFT. The N-type TFT11 is connected between the node N1 and the node Nil of the power supply potential VCC, and its gate will receive the potential V9 of the node N9. The N-type TFT 12 is connected between the nodes N 1 1 and N 1 2, and its gate is connected to the node N 1 1. The N-type TFT 1 2 constitutes a diode element. Capacitor 15 is connected between nodes Nil and N12. Provide signal / VI to node N12. The N-type TFT 13 is connected between the node N1 and the node N13 of the power source potential VCC, and its gate will receive the potential V 9 of the node N 9. The N-type T F T 1 4 series is connected between the nodes N 1 3 and N 1 4, and its gate is connected to the node N 1 3. 10 312 / Invention Specification (Supplement) / 92-05 / 92104380 1223498 N-type TFT 1 4 series constitutes a diode element. Capacitor 16 is connected between nodes N 1 3 and N 1 4. An input signal VI is provided to the node N 1 4. Next, the operation of the level converter 3 will be described. At present, if the input signals V I, / V I are set to 3 V and 0 V, respectively, the N-type T F T 1 1 will cause the potential of the node Nil V1 1 to become V11 = 2VTN-VTN = VTN by floating the source. In addition, because the threshold potential of the N-type TFT12 connected to the diode will be VTN, almost no current flows from the node N1 of the power supply potential VCC to the node N12. Because the gate potential of the N-type TFT7 is V11 = VTN and its source potential is 3V, the N-type TFT7 will be non-conductive. The capacitor 15 is charged to a threshold voltage V TN. In addition, as described later, since the potential V 1 3 of the node N 1 3 will be boosted to V T N or more, and the node N 8 will become 0 V, the N-type TFT 8 will be turned on. As a result, the output node N6 becomes the potential (0V) of the input node N8, and the P-type TFT 5 is turned on, and the output node N5 becomes the power supply potential VCC. As a result, the P-type TFT 6 will be in a non-conducting state, and no current will flow between the node N 1 and the input node N 8 of the power supply potential VCC. Secondly, if the input signal VI is decreased from 3 V to 0 V and the input signal / VI is increased from 0 V to 3 V, the potential change of the input signal / VI will be transmitted to the node N through the capacitor 15 through capacitive coupling. 1 1. The potential VII of the node Nil is boosted. If the capacitance of the capacitor 15 is set to be sufficiently larger than the capacitance of the parasitic capacitance (not shown) of the node Nil, the potential VII of the node Nil will become VII and VTN + △ VI = VTN + 3V. Among them, ΔVI refers to the amplitude of the input signal VI, / VI, which is 3V. Because the potential of the source (node N7) of the N-type TFT7 will become 0V, 11 312 / Instruction Manual (Supplement) / 92-05 / 921043 80 Therefore, the gate-source voltage of the N-type TFT7 will be vtn + 3 V and turn on the N-type TFT7. As a result, the potential of the output node N5 will be 0V, and the P-type TFT6 is turned on. In addition, the potential change of the input signal VI from 3V to 0V will be transmitted to the node N 1 3 through the capacitor 16 through the capacitive coupling, and the potential V13 of the node N 1 3 will be stepped down. When the change period of the input signal VI, / VI is relatively short, because the potential V 1 3 of the node N 1 3 before step-down will become V13 = VTN + 3V, therefore the potential V13 of the node N13 during step-down This becomes V13 = VTN + 3V-3V = VTN. When the change period of the input signal VI, / VI is relatively long, since the potential V 1 3 of the node N 1 3 will be in a potential state boosted by capacitive coupling, it will decrease with time. Therefore, the potential V13 of the node N13 only decreases when the VTN of the input signal VI and the period of the VI change is short. In this case, the N-type TFT 1 3 will be turned on, and the potential V13 of the node N13 will be turned on. Pull up to VTN. As described above, because the gate potential V13 of the N-type TFT8 will become VTN, and the potential of the source (node N8) thereof will become 3V. Therefore, the N-type TFT8 is in a non-conductive state. As a result, the potential of the output node N6 will be 7.5 V, and the P-type T F T 5 becomes non-conducting. In this case, the output nodes N 5, N 6 will be 0V and 7.5 V, respectively, and a logic level conversion will be performed from 3 V to 7.5 V. In this embodiment, in response to the falling edge of the input signal VI, the threshold voltage VTN of the N-type TFT 7 is added to the voltage VTN + 3 V after adding the amplitude voltage (3 V) of the input signal / VI to N. Between gate and source of type TFT 7, so even if the amplitude voltage (3V) of the input signal / VI is lower than N-type 12 312 / Invention Manual (Supplement) / 92-05 / 92104380 1223498 the threshold voltage VTN of TFT7 In this case, the level converter 3 can still operate normally. Therefore, as shown in FIG. 1, the level converter 3 and the liquid crystal display portion 4 can be formed into a liquid crystal display device 2 (a TF integrated circuit). ′ Therefore, compared with the conventional technology that requires individually designing the level converter 5 2 and the liquid crystal display device 5 3, the number of components can be reduced and the system cost can be reduced. In addition, although a power supply current was excessively flowed during the operation, a direct current was not flowed except for the resistance element 17 and the N-type TFTs 9 and 10. Because the resistance of the resistance element 17 is set to a large value and only a small current flows, the power consumption of the level converter 3 is extremely small. Furthermore, although TFTs 5 to M are used in this embodiment, MOS transistors may be used instead of TFTs. In this case, even if the amplitude of the input signal VI, / VI is smaller than the threshold voltage of the MOS transistor, it can still operate. Furthermore, although a TFT belonging to an insulated gate field effect transistor is used in this embodiment, of course, other types of field effect transistor may be used. Hereinafter, various modifications of this embodiment will be described. In the level converter 20 of FIG. 3, the sources of the N-type TFTs 12, 14 are grounded. In this modification, since the current of the N-type TFTs 12, 14 will not flow into the nodes N 1 2 and N 1 4 and flow into the node of the ground potential GND, the driving force of the input signal VI, / VI will change. small. In the level converter 21 of FIG. 4, the source of the P-type TFTs 5, 6 is given a power supply potential VCC (7.5V), and the drain of the N-type TFT 11 is given a positive power supply potential VCC different from the power supply potential VCC. ', One of the electrodes of the resistive element 17 (the electrode not connected to the node N9) is given a power supply potential VCC different from the power supply potential 13 312 / Invention Specification (Supplement) / 92_05 / 92104380 1223498 vcc, vcc ". In this variation, the potentials V9, V11, and V13 of the noises N9, N11, and N13 generated in the power supply potential VCC node are changed. In the level converter 22 of FIG. 5, the resistance element 17 is caused by In other words, the P-type TFT23 is connected between the power source 'node N1 and node N9, and its gate is connected to the connected node. The average unitary resistance of the resistive element composed of TFT is larger than that of the diffusion layer. The average resistance of the constructed resistance element. Therefore, in this modified example, the N-type TFT resistance element 17 that can reduce the resistance element and receive the power supply potential VCC by the gate can also obtain the same effect. In FIG. 6 In the level converter 24, an N-type N-type TFT 2 is additionally provided. The 5 series is connected between the nodes N5 and N7, and its gate node N6. The N-type TFT26 is connected to the nodes N6 and N8 and is connected to the node N5. If the input signals VI, / VI are at the J and "L" levels, and If the input signals VO and / VO are at the "H" level, the N-type TFT 25 will be in a non-conducting state and will be conducting at the same time, so that the output nodes N5 and N6 are maintained at the "Η" level, respectively. If the input signals VI, / VI are at the "L" level and the input signals VO, / VO are at the "L" level and "Η", respectively, the N-type TFT25 will be turned on, and the N-type TFT26 will be turned on, and Keep output nodes N5 and N6 at the "L" level, respectively. When the input signal VI, the period of change of / VI belongs to a very long 312 / Invention Specification (Supplement) / 92-05 / 92104380 For example, it can be prevented to make the node] PM TFT23 potential VCC ground potential GND bit area resistance unit area electricity J occupies the area. The formed electric TFT2 is connected between the 5,26 ° poles, and its gate i "Η" level and "L" N-type TFT26 level and "L" "位" level, if the level, In the non-conducting level and the “Η” f condition, the potentials V 1 1 and V 1 3 of nodes 14 1223498 points N 1 1, N 1 3 will all become the threshold VTN of N-type TFT, and the output nodes N5 and N6 There is a possibility that the potential relationship of 反转 is reversed. N-type TFT2 5,26 are for preventing this kind of potential reversal phenomenon between nodes N5 and N6, and in the case of irrelevant nodes N11, N13 potential V11, V13, the potential of nodes N5, N6 is fixed . The level converter 2 7 of FIG. 7 belongs to a node in which the sources of the N-type T F T 2 5 and 2 6 of the level converter 2 4 shown in FIG. 6 are connected to the ground potential G N D. In this variation, since the current of the N-type TFTs 25 and 26 does not flow into the input nodes N 7, N 8, but flows into the node of the ground potential GND, the driving force of the input signal VI, / VI can be reduced. . The level converter 3 0 of FIG. 8 belongs to the source of the N-type TFTs 7 and 8 of the level converter 3 shown in FIG. 2, which are all connected to the ground potential Gnd node. In this variation, since the current of the N-type TFT ?, 8 does not flow into the input nodes N7, N8, but flows into the node of the ground potential GND, the driving force of the input signal VI, / VI can be reduced. The level converter 31 of FIG. 9 belongs to the source of the N-type TFTs 7, 8, 25, and 26 of the level converter 27 of FIG. 7, which are all connected to the ground potential GND node. In this variation, because the current of the N-type TFTs 7, 8, 25, and 26 does not flow into the input nodes N 7, N 8, but flows into the node of the ground potential g ND, the input signal VI can be reduced. The driving force of / VI. The level converter 3 2 in FIG. 10 belongs to the gates of the P-type TFTs 5 and 6 of the level converter 3 shown in FIG. 2, which are all connected to the node N5. The P-type TFTs 5 and 6 constitute a current mirror circuit. P-type TFTs 5 and 6 have the same current flowing through them. When the input signal v I, / VI is different, "l" 15 312 / Invention Specification (Supplement) / 92-05 / 92104380 1223498 level and "Η" level, and N-type TF Τ 7, 8 are turned on respectively In the case of the state and the non-conduction state, a current which is the same as the current flowing in the TFTs 5 and 7 will also flow into the P-type TFT 6 and perform differential hole amplification. The output nodes n 5, N 6 are respectively at the "L" level and the "Η" level. In this modification, the same amplitude conversion effect as the level converter 3 of Fig. 2 can also be obtained. The level converter 3 3 in FIG. 11 belongs to the gates of the P-type TFTs 5 and 6 of the level converter 24 shown in FIG. 6, which are all connected to the node N 5. In this modification, the same amplitude conversion effect as that of the level converter 24 of Fig. 6 can also be obtained. The level converter 34 of FIG. 12 belongs to those whose sources of the N-type TFTs 7, 8 of the level converter 32 shown in FIG. 10 are grounded. In this variation, since the current flowing in the N-type TFTs 7, 8 does not flow into the input nodes N7, N8, but flows into the node of the ground potential GND, the driving of the input signal VI, / VI can be reduced. force. The level converter 3 5 in FIG. 13 belongs to a state in which the sources of the N-type TFTs 7, 8, 2, 5, 26 of the level converter 33 shown in FIG. 11 are grounded. In this modification, since the current flowing through the N-type TFTs 7, 8, 2, 5, 26 does not flow into the input nodes N 7, N 8, but flows into the node of the ground potential g ND, it can be reduced. Driving force of small input signal VI, / VI. In the modified example of FIG. 14, the constant potential generating circuit 36 including the resistance element 17 and the N-type T F T 9, 10 is provided in common to the complex level converters 38, 39,.... A potential stabilization capacitor 37 is connected between the output node N9 of the constant potential generating circuit 36 and a node of the ground potential GND. In order to increase the resistance 的 of the resistance element 17, the area of the resistance element i 7 16 312 / Invention Specification (Supplement) / 92-05 / 92104380 1223498 needs to be increased. However, in this modification, the The quasi-converters 38, 39, ... are provided with the constant potential generating circuit 36 in common, so that the area occupied by the entire circuit can be reduced. The level converter 40 shown in Fig. 15 is the level converter 3 shown in Fig. 2, and P-type TFTs 41 and 42 are additionally provided. The P-type TFT41 is connected between the drain of the P-type TFT5 and the output node N5, and its gate is connected to the node N 1 1. The P-type TFT 42 is connected between the drain of the P-type TFT 6 and the output node N6, and the gate is connected to the node N 1 3. If the input signal / VI rises from 0V to 3V, the potential VII of the node Nil will be VTN + 3V, making the P-type TFT41 1 non-conducting, and turning on the N-type TFT7, so that the potential of the output node N5 becomes 0V. Since the P-type TFT 41 is in a non-conducting state at this time, the current does not flow from the node N 1 of the power supply potential V C C to the output node N5, and the potential of the output node N5 is easily reduced to 0V. If the input signal / VI drops from 3V to 0V, the potential VII of the node Nil will be VTN, the N-type TFT7 will be in a non-conducting state, and the p-type TFT 41 will be turned on, so that the potential of the output node n 5 becomes 7.5 V. Furthermore, if the input signal VI rises from 0V to 3V, the potential V13 of the node N1 3 will be VTN + 3V, making the P-type TFT42 non-conducting, and at the same time the N-type TFT8 will be turned on, and the output node N6 will The potential becomes 0V. Because the P-type TFT 42 is in a non-conducting state at this time, the current does not flow from the node N1 of the power supply potential V C C to the output node N6, and the potential of the output node N6 is easily reduced to 0V. If the input signal vi drops from 3V to 0V, the potential of the node N13 V13 will be VTN, the N-type TFT8 will be in a non-conducting state, and the P-type TFT42 will be on at the same time, so that the output section 17 312 / Invention Manual (Supplement) / 92-05 / 92104380 1223498 The potential of point N 6 becomes 7 · 5 v. In this variation, since the potentials of the output nodes N 5, N 6 are easily reduced to 0 V, the amplitude of the input signal VI, / VI can be reduced by only this part, and the input signal v I, / VI can be reduced. The amplitude margin becomes larger. The level converters 45 to 55 of Figs. 16 to 26 are those in which p-type TFTs 41 and 42 are added to the level converters 20 to 22, 24, 27, 30 to 35 shown in Figs. 3 to 13, respectively. These variations can also obtain the same effect as the level converter 40 of FIG. 15. All the embodiments disclosed this time are limited to illustrations, and cannot be considered as limiting. The scope of the present invention is not the above description, but is disclosed by the scope of the patent application, and all changes within the meaning and scope equivalent to the scope of the patent application are covered. [Brief Description of the Drawings] FIG. 1 is a block diagram showing a structure of a relevant portion of a mobile phone image display according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a level converter structure shown in FIG. 1. FIG. 3 to 26 are circuit diagrams of modified examples of this embodiment. Fig. 27 is a block diagram of a related part of a conventional mobile phone image display. FIG. 28 is a circuit diagram of a level converter structure shown in FIG. 27. (Description of component symbols)
1 控制用LSI 2 液晶顯示裝置 3 位準轉換器 18 312/發明說明書(補件)/92-05/921043 80 1223498 4 液晶顯不部 5,6 P 型 TFT 7〜1 4 N 型 TFT 1 5，1 6 電容器 17 電阻元件 20,2 1,22,24 位準轉換器 23 P 型 TFT 25、2 6 N 型 TFT 2 7,3 0,3 1，3 2,3 3,3 4 位準轉換器 36 定電位產生電路 3 7 電容器 40 位準轉換器 4 1,42 P 型 TFT 45 〜55 位準轉換器 5 3 液晶顯示裝 置 7 1 控制用LSI 72 位準轉換器 73 液晶顯示裝置 74,75 P通道MOS 電晶體 16,11 N通道MOS 電晶體 GND 接地電位 Nl、N5 〜N 9、N 1 1〜 N 1 4 節點 VCC 電源電位 VI，/VI 輸入信號 312/發明說明書(補件)/92-05/921043 80 1223498 vo，/vo 輸出信號 VTN 臨限電壓1 Control LSI 2 Liquid crystal display device 3 Level converter 18 312 / Instruction manual (Supplement) / 92-05 / 921043 80 1223498 4 Liquid crystal display section 5, 6 P-type TFT 7 ~ 1 4 N-type TFT 1 5 1 6 capacitor 17 resistance element 20,2 1,22,24 level converter 23 P type TFT 25, 2 6 N type TFT 2 7,3 0,3 1,3 2,3 3,3 4 level conversion 36 Constant potential generating circuit 3 7 Capacitor 40 level converter 4 1,42 P-type TFT 45 to 55 level converter 5 3 Liquid crystal display device 7 1 LSI for control 72 Level converter 73 Liquid crystal display device 74, 75 P-channel MOS transistor 16,11 N-channel MOS transistor GND Ground potential Nl, N5 to N 9, N 1 1 to N 1 4 node VCC power supply potential VI, / VI input signal 312 / Invention Specification (Supplement) / 92 -05/921043 80 1223498 vo, / vo output signal VTN threshold voltage
312/發明說明書(補件)/92-05/92104380 20312 / Invention Specification (Supplement) / 92-05 / 92104380 20