JP2004194154A

JP2004194154A - Amplitude conversion circuit

Info

Publication number: JP2004194154A
Application number: JP2002361811A
Authority: JP
Inventors: Yoichi Hida; 洋一飛田
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2002-12-13
Filing date: 2002-12-13
Publication date: 2004-07-08

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplitude conversion circuit reduced in consumption current especially for the amplitude conversion circuit converting the amplitude voltage of a signal. <P>SOLUTION: This level shifter 3 is provided with an N type TFT 25 which makes a current with a value corresponding to the potential (0V or 3V) of an input signal VI flow out from an output node N11, an N type TFT 26 which makes a current with a value corresponding to reference potential VR (=1.5V) flow out from an output node N12, a differential amplifier circuit consisting of TFTs 11 to 14 for amplifying a potential difference generated between the output nodes N11 and N12 in response to the fact that a control signal ϕ2 is brought to 7.5V of a power supply voltage VDD (=7.5V), and N type TFTs 15 and 16 for initializing the output nodes N11 and N12 to 0V in a period of time before activating the differential amplifier circuit. Since a through current is not caused to flow in an initial state and after an operation end of level shifting, only a small current consumption is required. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
この発明は振幅変換回路に関し、特に、信号の振幅電圧を変換する振幅変換回路に関する。
【０００２】
【従来の技術】
図７は、従来の１入力型レベルシフタ７０の構成を示す回路図である。図７において、このレベルシフタ７０は、ＮチャネルＭＯＳトランジスタ７１〜７３、キャパシタ７４およびインバータ７５を備える。ＮチャネルＭＯＳトランジスタ７１のドレインは入力信号ＶＩを受け、そのソースはノードＮ７１に接続され、そのゲートは制御信号φを受ける。ＮチャネルＭＯＳトランジスタ７２のドレインは参照電位ＶＲを受け、そのソースはノードＮ７１に接続され、そのゲートは制御信号／φを受ける。キャパシタ７４およびインバータ７５は、ノードＮ７１と出力ノードＮ７５の間に直列接続される。ＮチャネルＭＯＳトランジスタ７３は、インバータ７５に並列接続され、そのゲートは制御信号／φを受ける。入力信号ＶＩの「Ｈ」レベルは３Ｖであり、その「Ｌ」レベルは０Ｖである。参照電位ＶＲは、入力信号ＶＩの「Ｈ」レベルと「Ｌ」レベルの中間レベルすなわち１．５Ｖである。インバータ７５は、電源電位ＶＣＣ（＝７．５Ｖ）のラインと接地電位ＧＮＤ（＝０Ｖ）のラインとの間に直列接続されたＰチャネルＭＯＳトランジスタおよびＮチャネルＭＯＳトランジスタを含む周知のものである。
【０００３】
次に、このレベルシフタ７０の動作について説明する。初期状態では、制御信号φ，／φはそれぞれ「Ｌ」レベルおよび「Ｈ」レベルにされる。これにより、ＮチャネルＭＯＳトランジスタ７１が非導通になるとともにＮチャネルＭＯＳトランジスタ７２が導通し、ノードＮ７１が参照電位ＶＲにされる。また、ＮチャネルＭＯＳトランジスタ７３が導通し、インバータ７５の入力ノードＮ７４と出力ノードＮ７５が接続され、図８（ａ）に示すように、インバータ７５の入出力伝達特性曲線とＶｉｎ＝Ｖｏｕｔの直線の交点Ａでインバータ７５が動作し、ノードＮ７４，Ｎ７５の電位はＶａ＝ＶＣＣ／２となる。
【０００４】
ある時刻において、信号φ，／φがそれぞれ「Ｈ」レベルおよび「Ｌ」レベルにされると、ＮチャネルＭＯＳトランジスタ７２，７３が非導通にされるとともにＮチャネルＭＯＳトランジスタ７１が導通し、インバータ７５が活性化されるとともに入力信号ＶＩのレベルがノードＮ７１に伝達される。入力信号ＶＩが「Ｈ」レベル（３Ｖ）の場合は、ノードＮ７１の電位は１．５Ｖから３Ｖに変化する。この電位変化分はキャパシタ７４を介してノードＮ７４に伝達され、ノードＮ７４の電位がΔＶだけ上昇する。ここでΔＶは、ノードＮ７１の１．５Ｖから３Ｖへの電位変化に基づいてノードＮ７４に生じる電位変化である。
【０００５】
図８（ａ）に示したように、インバータ７５の入力電位ＶｉｎがΔＶだけ上昇すると、インバータ７５の出力電位ＶｏｕｔがＡ点から下降してＢ点で安定する。つまり、インバータ７５の出力電位Ｖｏｕｔは０Ｖになる。
【０００６】
入力信号ＶＩが「Ｌ」レベル（０Ｖ）の場合は、ノードＮ７１の電位は１．５Ｖから０Ｖに変化し、ノードＮ７５の電位がΔＶだけ低下する。この場合は、インバータ７５の出力電位ＶｏｕｔはＡ点から上昇してＣ点で安定する。つまり、インバータ７５の出力電位Ｖｏｕｔは７．５Ｖになる。したがって、振幅電圧が３Ｖの入力信号ＶＩは、振幅電圧が７．５Ｖの信号ＶＯに変換されたことになる。このようなレベルシフタ７０は、たとえば特許文献１に開示されている。
【０００７】
【特許文献１】
特公平２−３１５２３号公報
【０００８】
【発明が解決しようとする課題】
図８（ｂ）は、インバータ７５の入力電位Ｖｉｎと消費電流Ｉｃｃの関係を示す図である。図８（ｂ）において、インバータ７５の消費電流Ｉｃｃは、Ｖｉｎ＝Ｖｏｕｔ＝ＶＣＣ／２のときに最大になる。これは、Ｖｉｎ＝Ｖｏｕｔ＝ＶＣＣ／２の場合は、インバータ７５に含まれるＰチャネルＭＯＳトランジスタおよびＮチャネルＭＯＳトランジスタの両方が導通し、電源電位ＶＣＣのラインと接地電位ＧＮＤのラインとの間に貫通電流が流れるためである。しかるに従来のレベルシフタ７０では、初期状態においてインバータ７５をＶｉｎ＝Ｖｏｕｔ＝ＶＣＣ／２の条件で動作させていたので、消費電流が大きいという問題があった。
【０００９】
それゆえに、この発明の主たる目的は、消費電流が小さな振幅変換回路を提供することである。
【００１０】
【課題を解決するための手段】
この発明に係る振幅変換回路は、その一方のレベルが第１の電位であり、その他方のレベルが第１の電位よりも高い第２の電位である第１の信号を、その一方のレベルが第１の電位であり、その他方のレベルが第２の電位よりも高い第３の電位である第２の信号に変換する振幅変換回路であって、第１の出力ノードから第１の信号の電位に応じた値の電流を流出させる第１の放電回路と、第２の出力ノードから第１および第２の電位間の参照電位に応じた値の電流を流出させる第２の放電回路と、制御信号が活性化レベルにされたことに応じて活性化され、第１および第２の出力ノード間に生じた電位差を第３および第１の電位の差の電圧に増幅する差動増幅回路と、差動増幅回路が活性化される前の期間に第１および第２の出力ノードの各々を初期電位に設定する初期化回路とを備えたものである。
【００１１】
また、この発明に係る他の振幅変換回路は、その一方のレベルが第１の電位であり、その他方のレベルが第１の電位よりも高い第２の電位である第１の信号を、その一方のレベルが第１の電位であり、その他方のレベルが第２の電位よりも高い第３の電位である第２の信号に変換する振幅変換回路であって、第１の出力ノードから第１の信号の電位に応じた値の電流を流出させる放電回路と、制御信号が活性化レベルにされたことに応じて活性化され、第１の出力ノードの電位が第２の出力ノードの電位よりも低い場合は第１および第２の出力ノードの電位をそれぞれ第１および第３の電位にし、それ以外の場合は第１および第２の出力ノードの電位をそれぞれ第３および第１の電位にする差動増幅回路と、差動増幅回路が活性化される前の期間に第１および第２の出力ノードの各々を初期電位に設定する初期化回路とを備えたものである。
【００１２】
【発明の実施の形態】
［実施の形態１］
図１は、この発明の実施の形態１による携帯電話機の画像表示に関連する部分の構成を示すブロック図である。図１において、この携帯電話機は、ＭＯＳＴ（ＭＯＳトランジスタ）型集積回路である制御用ＬＳＩ１と、ＴＦＴ（薄膜トランジスタ）型集積回路である液晶表示装置２とを備え、液晶表示装置２はレベルシフタ３および液晶表示部４を含む。
【００１３】
制御用ＬＳＩ１は、主にＭＯＳトランジスタで構成され、液晶表示装置２用の制御信号を出力する。この制御信号の「Ｈ」レベルは３Ｖであり、その「Ｌ」レベルは０Ｖである。制御信号は実際には多数生成されるが、ここでは説明の簡単化のため制御信号を１つとする。レベルシフタ３は、ＴＦＴで構成され、制御用ＬＳＩ１からの制御信号の論理レベルを変換して内部制御信号を生成する。この内部制御信号の「Ｈ」レベルは７．５Ｖであり、その「Ｌ」レベルは０Ｖである。液晶表示部４は、主にＴＦＴで構成され、レベルシフタ３からの内部制御信号に従って画像を表示する。
【００１４】
レベルシフタ３が必要とされる理由は、ＴＦＴのしきい値電圧が制御用ＬＳＩ１の出力信号の振幅と同程度の電圧（３Ｖ程度）であるため、レベルシフタ３を設けないと液晶表示部４が安定に動作しないからである。制御用ＬＳＩ１の出力信号が接地電位ＧＮＤを基準電位とする正極性の信号である場合は、Ｎ型ＴＦＴのしきい値電圧ＶＴＮと制御用ＬＳＩ１の出力信号の振幅電圧との高低関係が問題になる。制御用ＬＳＩ１の出力信号が電源電位ＶＣＣを基準電位とする負極性の信号である場合は、Ｐ型ＴＦＴのしきい値電圧ＶＴＰと制御用ＳＬＳＩの出力信号の振幅電圧との高低関係が問題になる。制御用ＬＳＩ１の出力信号は、一般には正極性である。
【００１５】
レベルシフタには、互いに相補な２つの信号ＶＩ，／ＶＩが入力される２入力型と、１つの信号ＶＩが入力される１入力型がある。２入力型は、２つの入力信号ＶＩ，／ＶＩのみでレベルシフト動作が可能であるが、入力信号数が増大し、システムの小型化が困難になる。１入力型は、入力信号数が少なくシステムの小型化が容易であるが、入力信号ＶＩのみでは動作できず、レベルシフトされた制御信号φ，／φによって駆動される必要がある。上記の点を考慮し、実際の液晶表示装置では、１入力型レベルシフタを駆動するための信号φ，／φを２入力型レベルシフタで生成し、その他の信号ＶＯを１入力型レベルシフタで生成している。以下、この発明の特徴となる１入力型レベルシフタについて詳細に説明する。
【００１６】
図２は、レベルシフタ３の構成を示す回路図である。図２において、このレベルシフタ３は、Ｐ型ＴＦＴ１１，１２，２０、Ｎ型ＴＦＴ１３〜１６，２１〜２６，３１〜３６，４３〜４６、抵抗素子３０およびキャパシタ３７，４７を含む。Ｐ型ＴＦＴ１１，１２，２０の各々は−３Ｖ程度のしきい値電圧ＶＴＰを有し、Ｎ型ＴＦＴ１３〜１６，２１〜２６，３１〜３６，４３〜４６の各々は３Ｖ程度のしきい値電圧ＶＴＮを有する。
【００１７】
Ｐ型ＴＦＴ１１，１２のソースはともにノードＮ１０に接続され、それらのドレインはそれぞれ出力ノードＮ１１，Ｎ１２に接続され、それらのゲートはそれぞれ出力ノードＮ１２，Ｎ１１に接続される。Ｎ型ＴＦＴ１３，１４のドレインはそれぞれ出力ノードＮ１１，Ｎ１２に接続され、それらのソースはともに接地電位ＧＮＤのラインに接続され、それらのゲートはそれぞれ出力ノードＮ１２，Ｎ１１に接続される。制御信号φ２の「Ｈ」レベルは７．５Ｖであり、その「Ｌ」レベルは０Ｖである。ＴＦＴ１１〜１４は、制御信号φ２が７．５Ｖにされたことに応じて、出力ノードＮ１１，Ｎ１２間の電位差を７．５Ｖに増幅する正帰還型差動増幅回路を構成する。ノードＮ１１，Ｎ１２には、互いに相補な信号／ＶＯ，ＶＯがそれぞれ出力される。信号／ＶＯ，ＶＯの各々の「Ｈ」レベルは７．５Ｖであり、各々の「Ｌ」レベルは０Ｖである。
【００１８】
Ｎ型ＴＦＴ１５，１６はそれぞれ出力ノードＮ１１，Ｎ１２と接地電位ＧＮＤのラインとの間に接続され、それらのゲートはともに制御信号／φを受ける。制御信号／φの「Ｈ」レベルは７．５Ｖであり、その「Ｌ」レベルは０Ｖである。Ｎ型ＴＦＴ１５，１６は、制御信号／φが「Ｈ」レベルにされたことに応じて出力ノードＮ１１，Ｎ１２の電位を接地電位ＧＮＤに初期化する初期化回路を構成する。
【００１９】
抵抗素子３０およびＮ型ＴＦＴ３１，３２は、電源電位ＶＤＤのラインと接地電位ＧＮＤのラインとの間に直列接続される。Ｎ型ＴＦＴ３１，３２のゲートは、それぞれそれらのドレインに接続されている。Ｎ型ＴＦＴ３１，３２の各々は、ダイオード素子を構成する。抵抗素子３０の抵抗値はＮ型ＴＦＴ３１，３２の導通抵抗値に比べて十分高い値に設定されているので、抵抗素子３０とＮ型ＴＦＴ３１の間のノードＮ３０の電位は２ＶＴＮとなる。抵抗素子３０の抵抗値は十分高い値に設定されているので、抵抗素子３０およびＮ型ＴＦＴ３１，３２にはほとんど電流が流れない。
【００２０】
Ｎ型ＴＦＴ３３，３４，３６は、電源電位ＶＤＤのラインと接地電位ＧＮＤのラインとの間に直列接続される。Ｎ型ＴＦＴ３３のゲートは、ノードＮ３０の電位２ＶＴＮを受ける。Ｎ型ＴＦＴ３４のゲートは、そのドレイン（ノードＮ３３）に接続される。Ｎ型ＴＦＴ３４は、ダイオード素子を構成する。キャパシタ３７は、Ｎ型ＴＦＴ３４に並列接続される。Ｎ型ＴＦＴ３６のゲートは、制御信号／φを受け、そのソースはノードＮ３４に接続される。Ｎ型ＴＦＴ３５のドレインは入力信号ＶＩを受け、そのゲートは制御信号φ１を受ける。入力信号ＶＩの「Ｈ」レベルは３Ｖであり、その「Ｌ」レベルは０Ｖである。制御信号φ１の「Ｈ」レベルは７．５Ｖであり、その「Ｌ」レベルは０Ｖである。制御信号φ１は、制御信号／φと逆相の信号である。
【００２１】
制御信号／φ，φ１がそれぞれ「Ｈ」レベルおよび「Ｌ」レベルの期間は、Ｎ型ＴＦＴ３５が非導通になるとともにＮ型ＴＦＴ３６が導通し、ノードＮ３３，Ｎ３４はそれぞれＶＴＮ，０Ｖになる。Ｎ型ＴＦＴ３４は、導通状態と非導通状態の境界で動作しており、Ｎ型ＴＦＴ３４にはほとんど電流は流れない。キャパシタ３７は、ＶＴＮに充電される。制御信号／φ，φ１がそれぞれ「Ｌ」レベルおよび「Ｈ」レベルにされると、Ｎ型ＴＦＴ３６が非導通にされるとともにＮ型ＴＦＴ３５が導通し、入力信号ＶＩの電位（３Ｖまたは０Ｖ）がノードＮ３４に伝達される。入力信号ＶＩが３Ｖの場合は、キャパシタ３７を介してノードＮ３３の電位がＶＴＮ＋ΔＶに上昇する。ここでΔＶ≒３Ｖである。入力信号ＶＩが０Ｖの場合は、ノードＮ３３の電位はＶＴＮのまま変化しない。ノードＮ３３の電位は、Ｎ型ＴＦＴ２５のゲートに与えられる。
【００２２】
また、Ｎ型ＴＦＴ４３，４４，４６は、電源電位ＶＤＤのラインと接地電位ＧＮＤのラインとの間に直列接続される。Ｎ型ＴＦＴ４３のゲートは、ノードＮ３０の電位２ＶＴＮを受ける。Ｎ型ＴＦＴ４４のゲートは、そのドレイン（ノードＮ４３）に接続される。Ｎ型ＴＦＴ４４は、ダイオード素子を構成する。キャパシタ４７は、Ｎ型ＴＦＴ４４に並列接続される。Ｎ型ＴＦＴ４６のゲートは、制御信号／φを受ける。Ｎ型ＴＦＴ４５のドレインは参照電位ＶＲを受け、そのゲートは制御信号φ１を受ける。参照電位ＶＲは、入力信号ＶＩの「Ｈ」レベルと「Ｌ」レベルの中間レベルすなわち１．５Ｖである。
【００２３】
制御信号／φ，φ１がそれぞれ「Ｈ」レベルおよび「Ｌ」レベルの期間は、Ｎ型ＴＦＴ４５が非導通になるとともにＮ型ＴＦＴ４６が導通し、ノードＮ４３，Ｎ４４はそれぞれＶＴＮ，０Ｖになる。Ｎ型ＴＦＴ４４は、導通状態と非導通状態の境界で動作しており、Ｎ型ＴＦＴ４４にはほとんど電流は流れない。キャパシタ４７は、ＶＴＮに充電される。制御信号／φ，φ１がそれぞれ「Ｌ」レベルおよび「Ｈ」レベルにされると、Ｎ型ＴＦＴ４６が非導通にされるとともにＮ型ＴＦＴ４５が導通し、参照電位（１．５Ｖ）がノードＮ４４に伝達され、キャパシタ４７を介してノードＮ４３の電位がＶＴＮ＋ΔＶ／２に上昇する。ノードＮ４３の電位は、Ｎ型ＴＦＴ２６のゲートに与えられる。
【００２４】
Ｐ型ＴＦＴ２０のソースは電源電位ＶＤＤを受け、そのゲートは制御信号φ１を受け、そのドレインはノードＮ２０に接続される。Ｎ型ＴＦＴ２１，２２はともにノードＮ２０と接地電位ＧＮＤのラインとの間に接続され、それらのゲートはそれぞれ出力ノードＮ１２，Ｎ１１に接続される。Ｎ型ＴＦＴ２３，２５は出力ノードＮ１１と接地電位ＧＮＤのラインとの間に直列接続され、Ｎ型ＴＦＴ２４，２６は出力ノードＮ１２と接地電位ＧＮＤのラインとの間に直列接続される。Ｎ型ＴＦＴ２３，２４のゲートはともにノードＮ２０に接続され、Ｎ型ＴＦＴ２５，２６のゲートはそれぞれノードＮ３３，Ｎ４３に接続される。
【００２５】
制御信号φ１が「Ｌ」レベルの期間は、Ｐ型ＴＦＴ２０が導通してノードＮ２０が７．５Ｖに充電され、Ｎ型ＴＦＴ２３，２４が導通する。これにより、出力ノードＮ１１からＮ型ＴＦＴ２３，２５を介して接地電位ＧＮＤのラインに電流が流出するとともに、出力ノードＮ１２からＮ型ＴＦＴ２４，２６を介して接地電位ＧＮＤのラインに電流が流出する。Ｎ型ＴＦＴ２５，２６に流れる電流の大小関係により、ノードＮ１１，Ｎ１２の電位の高低関係が決まる。制御信号φ１が「Ｈ」レベルになると、Ｐ型ＴＦＴ２０が非導通になる。ＴＦＴ１１〜１４による差動増幅動作が行なわれて出力ノードＮ１１またはＮ１２が７．５Ｖにされると、Ｎ型ＴＦＴ２１または２２が導通してノードＮ２０が０Ｖになり、Ｎ型ＴＦＴ２３，２４が非導通になる。
【００２６】
図３は、このレベルシフタ３の動作を示すタイムチャートである。今、入力信号ＶＩは、「Ｈ」レベル（３Ｖ）にされているものとする。初期状態では、制御信号／φは７．５Ｖにされ、制御信号φ１，φ２はともに０Ｖにされている。これにより、Ｎ型ＴＦＴ１５，１６が導通し、出力ノードＮ１１，Ｎ１２がともに０Ｖに初期化される。また、Ｐ型ＴＦＴ２０が導通してノードＮ２０が７．５Ｖになり、Ｎ型ＴＦＴ２３，２４が導通する。また、Ｎ型ＴＦＴ３６，４６が導通してノードＮ３４，Ｎ４４が０Ｖにされ、ノードＮ３３，Ｎ４３がＶＴＮにされる。
【００２７】
ある時刻ｔ１において信号／φが「Ｌ」レベルに向けて下降し始めるとともに信号φ１が「Ｈ」レベルに向けて上昇し始める。時刻ｔ２において信号／φ，φ１がそれぞれ「Ｌ」レベルおよび「Ｈ」レベルに到達すると、Ｎ型ＴＦＴ３６，４６が非導通にされるとともにＮ型ＴＦＴ３５，４５が導通し、ノードＮ３３，Ｎ４３の電位がそれぞれＶＴＮ＋ΔＶ，ＶＴＮ＋ΔＶ／２になる。また、ＴＦＴ１５，１６，２０が非導通になる。
【００２８】
次いで時刻ｔ３において制御信号φ２が「Ｈ」レベルに向けて上昇し始めると、Ｐ型ＴＦＴ３，４の抵抗値が下降して出力ノードＮ１１，Ｎ１２の電位が上昇し始める。Ｎ型ＴＦＴ２５，２６のゲート電位はともにＶＴＮ以上になっているので、Ｎ型ＴＦＴ２５，２６の両方に電流が流れる。ところが、Ｎ型ＴＦＴ２５のゲート電位のほうがＮ型ＴＦＴ２６のゲート電位よりもΔＶ／２だけ高いので、Ｎ型ＴＦＴ２５に流れる電流がＮ型ＴＦＴ２６に流れる電流よりも大きくなり、出力ノードＮ１１の電位が出力ノードＮ１２の電位よりも低くなる。出力ノードＮ１１，Ｎ１２の電位差はＴＦＴ１１〜１４からなる差動増幅回路で増幅され、出力ノードＮ１１の電位が低下するとともに出力ノードＮ１２の電位が上昇し、時刻ｔ４において出力ノードＮ１１，Ｎ１２がそれぞれ０Ｖ，７．５Ｖになる。
【００２９】
また、出力ノードＮ１２の電位がＶＴＮを超えると、Ｎ型ＴＦＴ２１が導通してノードＮ２０が接地される。これにより、Ｎ型ＴＦＴ２３，２４が非導通になり、出力ノードＮ１２と接地電位ＧＮＤのラインとの間の電流経路が遮断され、ノードＮ１０と接地電位ＧＮＤのラインとの間の貫通電流がなくなって直流的な消費電流がなくなる。
【００３０】
次に、時刻ｔ５において制御信号φ２が７．５Ｖから０Ｖに立下げられると、出力ノードＮ１２の電荷がＰ型ＴＦＴ１２を介してノードＮ１０に放電される。信号φ２の電位が｜ＶＴＰ｜以下になるとＰ型ＴＦＴ１２が非導通になるので、出力ノードＮ１２の電位は一旦｜ＶＴＰ｜で停止する。
【００３１】
次いで時刻ｔ６において、信号／φが０Ｖから７．５Ｖに立上げられるとともに、信号φ１が７．５Ｖから０Ｖに立下げられる。これにより、Ｎ型ＴＦＴ１６が導通し、出力ノードＮ１２は接地される。また、Ｎ型ＴＦＴ３５，４５が非導通になるとともにＮ型ＴＦＴ３６，４６が導通し、ノードＮ３４，Ｎ４４が０Ｖになり、ノードＮ３３，Ｎ４３はＶＴＮになる。また、Ｐ型ＴＦＴ２０が導通し、ノードＮ２０が７．５Ｖに立上げられ、初期状態に戻る。
【００３２】
また、入力信号ＶＩが「Ｌ」レベル（０Ｖ）の場合は、図３で点線で示すように、信号φ１が「Ｈ」レベルに立上げられてもノードＮ３３の電位はＶＴＮのまま変化しない。一方、ノードＮ４３の電位は、信号φ１が「Ｈ」レベルに立上げられるとＶＴＮからＶＴＮ＋ΔＶ／２に上昇する。したがって、信号φ２が「Ｈ」レベルに立上げられると、ノードＮ１１の電位のほうがノードＮ１２の電位よりも高くなり、ＴＦＴ１１〜１４からなる差動増幅回路によってノードＮ１１，Ｎ１２がそれぞれ７，５Ｖ，０Ｖにされる。このようにして、振幅電圧が３Ｖの入力信号ＶＩが、振幅電圧が７．５Ｖの信号／ＶＯ，ＶＯに変換される。
【００３３】
この実施の形態１では、初期状態設定期間では、制御信号φ２が０Ｖにされているので、ノードＮ１０から接地電位ＧＮＤのラインに貫通電流は流れない。また、レベルシフト動作が終了すると、ＴＦＴ１１，１４または１２，１３およびＮ型ＴＦＴ２３，２４が非導通になり、ノードＮ１０から接地電位ＧＮＤのラインに貫通電流は流れない。したがって、消費電流が小さくて済む。
【００３４】
なお、この実施の形態１では、レベルシフタ３を主にＴＦＴで構成したが、レベルシフタ３をＴＦＴの代わりにＭＯＳトランジスタで構成してもよいことは言うまでもない。
【００３５】
また、Ｎ型ＴＦＴ１５，１６のソースを接地電位ＧＮＤのラインに接続したが、レベルシフタ３が正常に動作するのであれば、Ｎ型ＴＦＴ１５，１６のソースを接地電位ＧＮＤ以外の初期電位のラインに接続してもよい。
【００３６】
また、ＴＦＴ２０，３５，４５を同じ信号φ１で制御したが、ＴＦＴ２０，３５，４５を略同一位相の別々の信号で制御してもよい。
【００３７】
また、ＴＦＴ１５，１６，３６，４６を同じ信号／φで制御したが、ＴＦＴ１５，１６，３６，４６を略同一位相の別々の信号で制御してもよい。
【００３８】
また、抵抗素子３０の一方電極、Ｎ型ＴＦＴ３３，４３のドレインおよびＰ型ＴＦＴ２０のソースに同じ電源電位ＶＤＤを与えたが、レベルシフタ３が正常に動作するのであれば、それらに異なる電源電位を与えてもよい。
【００３９】
また、Ｎ型ＴＦＴ２１，２２のドレインに接地電位ＧＮＤを与えたが、Ｎ型ＴＦＴ２３，２４を非導通にすることができるのであれば、Ｎ型ＴＦＴ２１，２２のドレインに接地電位ＧＮＤ以外の電位を与えてもよい。
【００４０】
［実施の形態２］
図４は、この発明の実施の形態２によるレベルシフタ５０の構成を示す回路図である。図４を参照して、このレベルシフタ５０が図２のレベルシフタ３と異なる点は、Ｎ型ＴＦＴ１４がＮ型ＴＦＴ５１で置換され、Ｐ型ＴＦＴ２０およびＮ型ＴＦＴ２１〜２４，４５，４６が除去されている点である。
【００４１】
図２のレベルシフタ３では、Ｎ型ＴＦＴ１３の電流駆動能力とＮ型ＴＦＴ１４の電流駆動能力とは同じレベルに設定されているが、このレベルシフタ５０ではＮ型ＴＦＴ５１の電流駆動能力はＮ型ＴＦＴ１３の電流駆動能力よりも高いレベルに設定されている。Ｎ型ＴＦＴ５１の電流駆動能力をＮ型ＴＦＴ１３の電流駆動能力よりも高くする方法としては、Ｎ型ＴＦＴ５１のゲート幅（チャネル幅）をＮ型ＴＦＴ１３のゲート幅よりも長くする方法、Ｎ型ＴＦＴ５１のゲート長（チャネル長）をＮ型ＴＦＴ１３のゲート長よりも短くする方法などがある。
【００４２】
Ｎ型ＴＦＴ２５のドレインは出力ノードＮ１１に直接接続され、Ｎ型ＴＦＴ２６のドレインは出力ノードＮ１２に直接接続され、Ｎ型ＴＦＴ４０のソース（ノードＮ４４）は接地される。
【００４３】
入力信号ＶＩが３Ｖの場合は、信号φ１が「Ｌ」レベルから「Ｈ」レベルに立上げられたときにノードＮ３３の電位がＶＴＮからＶＴＮ＋ΔＶに立上げられてＮ型ＴＦＴ２５が導通する。一方、ノードＮ４３の電位はＶＴＮに固定されており、Ｎ型ＴＦＴ２６は非導通状態に固定されている。Ｎ型ＴＦＴ１３と２５の電流駆動能力の合計はＮ型ＴＦＴ５１の電流駆動能力よりも大きいので、信号φ２が「Ｌ」レベルから「Ｈ」レベルに立上げられると、ＴＦＴ１１〜１３，５１からなる差動増幅回路により、ノードＮ１１，Ｎ１２がそれぞれ０Ｖ，７．５Ｖにされる。
【００４４】
入力信号ＶＩが０Ｖの場合は、信号φ１が「Ｌ」レベルから「Ｈ」レベルに立上げられてもノードＮ３３の電位はＶＴＮのまま変化せず、Ｎ型ＴＦＴ２５が非導通状態のまま変化しない。Ｎ型ＴＦＴ５１の電流駆動能力はＴＦＴ１３の電流駆動能力よりも大きいので、信号φ２が「Ｌ」レベルから「Ｈ」レベルに立上げられると、ＴＦＴ１１〜１３，５１からなる差動増幅回路により、ノードＮ１１，Ｎ１２がそれぞれ７．５Ｖ，０Ｖにされる。
【００４５】
なお、入力信号ＶＩが３Ｖの場合はＴＦＴ１１，５１が非導通になるのでノードＮ１０から接地電位ＧＮＤのラインに貫通電流が流れず、入力信号ＶＩが０Ｖの場合はＴＦＴ１２，１３が非導通になるのでノードＮ１０から接地電位ＧＮＤのラインに貫通電流が流れない。したがって、ＴＦＴ２０〜２４は不要となる。また、Ｎ型ＴＦＴ２６，４３，４４およびキャパシタ４７を残してあるのは、ノードＮ１１とＮ１２の容量を等しくするためである。
【００４６】
この実施の形態２では、実施の形態１と同じ効果が得られる他、参照電位ＶＲを生成するための電位発生回路および参照電位ＶＲ用の配線が不要となり、消費電力の低減化およびレイアウト面積の縮小化が図られる。
【００４７】
［実施の形態３］
図５は、この発明の実施の形態３によるレベルシフタ５５の構成を示す回路図である。図５を参照して、このレベルシフタ５５が図２のレベルシフタ３と異なる点は、Ｐ型ＴＦＴ１１，１２，２０がＮ型ＴＦＴ５６〜６３で置換されている点である。したがって、このレベルシフタ５５では、Ｐ型ＴＦＴは１つも使用されていない。
【００４８】
Ｎ型ＴＦＴ５６のドレインは電源電位ＶＤＤを受け、そのソースはノードＮ２０に接続され、そのゲートは信号／φＢを受ける。信号／φＢは、信号φ１と逆相の信号であり、その「Ｈ」レベルはＶＤＤ＋ＶＴＮであり、その「Ｌ」レベルは０Ｖである。
【００４９】
Ｎ型ＴＦＴ５７，５８は、それぞれノードＮ１０と出力ノードＮ１１，Ｎ１２との間に接続される。Ｎ型ＴＦＴ５９，６０は、それぞれ電源電位ＶＤＤ（７．５Ｖ）のラインとＮ型ＴＦＴ５７，５８のゲート（ノードＮ５９，Ｎ６０）との間に接続され、それらのゲートはともに信号／φＢを受ける。Ｎ型ＴＦＴ６１は、ノードＮ５９，Ｎ６０間に接続され、そのゲートは信号／φＢを受ける。Ｎ型ＴＦＴ６２，６３のドレインはそれぞれノードＮ５９，Ｎ６０に接続され、それらのソースはそれぞれ出力ノードＮ１１，Ｎ１２に接続され、それらのゲートはそれぞれ出力ノードＮ１２，Ｎ１１に接続される。
【００５０】
次に、このレベルシフタ５５の動作について説明する。今、入力信号ＶＩは３Ｖにされているものとする。初期状態では、信号／φ，／φＢは「Ｈ」レベルにされ、信号φ２は「Ｌ」レベルにされる（図３参照）。これにより、Ｎ型ＴＦＴ５６が導通してノードＮ２０が「Ｈ」レベルになり、Ｎ型ＴＦＴ２３，２４が導通する。また、Ｎ型ＴＦＴ３６，４６が導通し、ノードＮ３３，Ｎ４３の電位がＶＴＮになる。また、Ｎ型ＴＦＴ１５，１６が導通してノードＮ１１，Ｎ１２が０Ｖになり、Ｎ型ＴＦＴ６２，６３が非導通になる。また、Ｎ型ＴＦＴ５９〜６１が導通してノードＮ５９，Ｎ６０が７．５Ｖになり、Ｎ型ＴＦＴ５７，５８が導通する。
【００５１】
次に、信号／φ，／φＢがともに「Ｌ」レベルに立下げられるとともに信号φ１が「Ｈ」レベルに立上げられると、Ｎ型ＴＦＴ１５，１６，３６，４６，５６，５９〜６１が非導通になるとともに、Ｎ型ＴＦＴ３５，４５が導通する。これにより、ノードＮ３３，Ｎ４３の電位はそれぞれＶＴＮ＋ΔＶ，ＶＴＮ＋ΔＶ／２になる。
【００５２】
次に、信号φ２が０Ｖから７．５Ｖに立上げられると（図３の時刻ｔ３）、Ｎ型ＴＦＴ５７，５８が導通しているので出力ノードＮ１１，Ｎ１２の電位が上昇する。このとき、出力ノードＮ１１からＮ型ＴＦＴ２３，２５を介して接地電位ＧＮＤのラインに流出する電流は、出力ノードＮ１２からＮ型ＴＦＴ２４，２６を介して接地電位ＧＮＤのラインに流出する電流よりも大きいので、出力ノードＮ１１の電位が出力ノードＮ１２の電位よりも低くなる。出力ノードＮ１１，Ｎ１２の電位差は、Ｎ型ＴＦＴ１３，１４，５７，５８，６２，６３からなる差動増幅回路によって増幅され、出力ノードＮ１１，Ｎ１２はそれぞれ０Ｖ，７．５Ｖになる。
【００５３】
また、入力信号ＶＩが０Ｖの場合は、Ｎ型ＴＦＴ３５，４５が導通したときにノードＮ３３，Ｎ４３の電位がそれぞれＶＴＮ，ＶＴＮ＋ΔＶ／２になり、信号φ２が７．５Ｖにされたとき出力ノードＮ１１から流出する電流が出力ノードＮ１２から流出する電流よりも小さくなる。このため、出力ノードＮ１１の電位が出力ノードＮ１２の電位よりも高くなり、出力ノードＮ１１，Ｎ１２はそれぞれ７．５Ｖ，０Ｖになる。他の構成および動作は、図２のレベルシフタ３と同じであるので、その説明は繰返さない。
【００５４】
この実施の形態３では、実施の形態１と同じ効果が得られる他、Ｐ型ＴＦＴを１つも使用しないので、アモルファスシリコン膜を用いた液晶表示装置のようにＮ型ＴＦＴしか使用できない装置にも搭載できる。また、製造工程の簡単化および製造コストの低減化を図ることができる。
【００５５】
なお、Ｎ型ＴＦＴ６２，６３のソースを出力ノードＮ１１，Ｎ１２に接続せずに接地電位ＧＮＤのラインに接続してもよい。
【００５６】
また、図６のレベルシフタ６５は、図５のレベルシフタ５５のＮ型ＴＦＴ１４をＮ型ＴＦＴ５１で置換し、Ｎ型ＴＦＴ２１〜２４，４５，４６，５６を除去したものである。この変更例は、実施の形態２と３を組合わせたものであり、実施の形態３と同じ効果が得られる他、参照電位ＶＲを生成するための電位発生回路および参照電位ＶＲ用の配線が不要となり、消費電力の低減化およびレイアウト面積の縮小化が図られる。
【００５７】
今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。
【００５８】
【発明の効果】
以上のように、この発明に係る振幅変換回路は、その一方のレベルが第１の電位であり、その他方のレベルが第１の電位よりも高い第２の電位である第１の信号を、その一方のレベルが第１の電位であり、その他方のレベルが第２の電位よりも高い第３の電位である第２の信号に変換するものである。この振幅変換回路では、第１の出力ノードから第１の信号の電位に応じた値の電流を流出させる第１の放電回路と、第２の出力ノードから第１および第２の電位間の参照電位に応じた値の電流を流出させる第２の放電回路と、制御信号が活性化レベルにされたことに応じて活性化され、第１および第２の出力ノード間に生じた電位差を第３および第１の電位の差の電圧に増幅する差動増幅回路と、差動増幅回路が活性化される前の期間に第１および第２の出力ノードの各々を初期電位に設定する初期化回路とが設けられる。したがって、初期状態設定期間に貫通電流は流れず、また、レベルシフト動作終了後に貫通電流は流れないので、消費電流が小さくて済む。
【００５９】
また、この発明に係る他の振幅変換回路は、その一方のレベルが第１の電位であり、その他方のレベルが第１の電位よりも高い第２の電位である第１の信号を、その一方のレベルが第１の電位であり、その他方のレベルが第２の電位よりも高い第３の電位である第２の信号に変換するものである。この振幅変換回路では、第１の出力ノードから第１の信号の電位に応じた値の電流を流出させる放電回路と、制御信号が活性化レベルにされたことに応じて活性化され、第１の出力ノードの電位が第２の出力ノードの電位よりも低い場合は第１および第２の出力ノードの電位をそれぞれ第１および第３の電位にし、それ以外の場合は第１および第２の出力ノードの電位をそれぞれ第３および第１の電位にする差動増幅回路と、差動増幅回路が活性化される前の期間に第１および第２の出力ノードの各々を初期電位に設定する初期化回路とが設けられる。したがって、初期状態設定期間に貫通電流は流れず、また、レベルシフト動作終了後に貫通電流は流れないので、消費電流が小さくて済む。
【図面の簡単な説明】
【図１】この発明の実施の形態１による携帯電話機の要部を示すブロック図である。
【図２】図１に示したレベルシフタの構成を示す回路図である。
【図３】図２に示したレベルシフタの動作を示すタイムチャートである。
【図４】この発明の実施の形態２によるレベルシフタの構成を示す回路図である。
【図５】この発明の実施の形態３によるレベルシフタの構成を示す回路図である。
【図６】実施の形態３の変更例を示す回路図である。
【図７】従来のレベルシフタの構成を示す回路図である。
【図８】図７に示したレベルシフタの動作を示す図である。
【符号の説明】
１制御用ＬＳＩ、２液晶表示装置、３，５０，５５，６５，７０レベルシフタ、４液晶表示部、１１，１２，２０Ｐ型ＴＦＴ、１３〜１６，２１〜２６，３１〜３６，４３〜４６，５６〜６３Ｎ型ＴＦＴ、３０抵抗素子、３７，４７，７４キャパシタ、７１〜７３ＮチャネルＭＯＳトランジスタ、７５インバータ。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an amplitude conversion circuit, and more particularly, to an amplitude conversion circuit that converts an amplitude voltage of a signal.
[0002]
[Prior art]
FIG. 7 is a circuit diagram showing a configuration of a conventional one-input type level shifter 70. 7, the level shifter 70 includes N-channel MOS transistors 71 to 73, a capacitor 74, and an inverter 75. N channel MOS transistor 71 has a drain receiving input signal VI, a source connected to node N71, and a gate receiving control signal φ. N channel MOS transistor 72 has its drain receiving reference potential VR, its source connected to node N71, and its gate receiving control signal / φ. Capacitor 74 and inverter 75 are connected in series between node N71 and output node N75. N-channel MOS transistor 73 is connected in parallel to inverter 75, and has a gate receiving control signal / φ. The “H” level of the input signal VI is 3V, and its “L” level is 0V. Reference potential VR is an intermediate level between “H” level and “L” level of input signal VI, that is, 1.5 V. Inverter 75 is a well-known inverter including a P-channel MOS transistor and an N-channel MOS transistor connected in series between a line of power supply potential VCC (= 7.5 V) and a line of ground potential GND (= 0 V).
[0003]
Next, the operation of the level shifter 70 will be described. In an initial state, control signals φ and / φ are set to “L” level and “H” level, respectively. Thereby, N-channel MOS transistor 71 is turned off and N-channel MOS transistor 72 is turned on, and node N71 is set to reference potential VR. Further, the N-channel MOS transistor 73 conducts, the input node N74 of the inverter 75 and the output node N75 are connected, and as shown in FIG. 8A, the input / output transfer characteristic curve of the inverter 75 and the straight line of Vin = Vout At the intersection A, the inverter 75 operates, and the potentials of the nodes N74 and N75 become Va = VCC / 2.
[0004]
At a certain time, when signals φ and / φ are set to “H” level and “L” level, N channel MOS transistors 72 and 73 are turned off, N channel MOS transistor 71 is turned on, and inverter 75 is turned on. Is activated, and the level of input signal VI is transmitted to node N71. When input signal VI is at “H” level (3 V), the potential of node N 71 changes from 1.5 V to 3 V. This potential change is transmitted to node N74 via capacitor 74, and the potential of node N74 increases by ΔV. Here, ΔV is a potential change generated at the node N74 based on a potential change at the node N71 from 1.5V to 3V.
[0005]
As shown in FIG. 8A, when the input potential Vin of the inverter 75 increases by ΔV, the output potential Vout of the inverter 75 decreases from the point A and stabilizes at the point B. That is, the output potential Vout of the inverter 75 becomes 0V.
[0006]
When the input signal VI is at the “L” level (0 V), the potential of the node N71 changes from 1.5 V to 0 V, and the potential of the node N75 decreases by ΔV. In this case, the output potential Vout of the inverter 75 rises from the point A and stabilizes at the point C. That is, the output potential Vout of the inverter 75 becomes 7.5V. Therefore, the input signal VI having the amplitude voltage of 3V is converted into the signal VO having the amplitude voltage of 7.5V. Such a level shifter 70 is disclosed in, for example, Patent Document 1.
[0007]
[Patent Document 1]
Japanese Patent Publication No. 2-31523
[0008]
[Problems to be solved by the invention]
FIG. 8B is a diagram illustrating a relationship between the input potential Vin of the inverter 75 and the current consumption Icc. In FIG. 8B, the consumption current Icc of the inverter 75 becomes maximum when Vin = Vout = VCC / 2. This is because when Vin = Vout = VCC / 2, both the P-channel MOS transistor and the N-channel MOS transistor included in the inverter 75 are turned on, so that the line between the power supply potential VCC line and the ground potential GND line penetrates. This is because current flows. However, in the conventional level shifter 70, since the inverter 75 is operated under the condition of Vin = Vout = VCC / 2 in the initial state, there is a problem that current consumption is large.
[0009]
Therefore, a main object of the present invention is to provide an amplitude conversion circuit with low current consumption.
[0010]
[Means for Solving the Problems]
An amplitude conversion circuit according to the present invention outputs a first signal whose one level is a first potential and the other level is a second potential higher than the first potential, An amplitude conversion circuit for converting a first signal to a second signal whose other level is a third potential higher than the second potential, wherein the amplitude conversion circuit converts the first signal from a first output node to a second signal. A first discharge circuit for causing a current having a value corresponding to the potential to flow, a second discharge circuit for allowing a current having a value corresponding to a reference potential between the first and second potentials to flow from a second output node, A differential amplifier circuit activated in response to the control signal attaining the activation level and amplifying a potential difference between the first and second output nodes to a voltage having a difference between the third and first potentials; , Each of the first and second output nodes during a period before the differential amplifier circuit is activated. The is that a initializing circuit for setting the initial potential.
[0011]
Further, another amplitude conversion circuit according to the present invention outputs a first signal whose one level is a first potential and whose other level is a second potential higher than the first potential. An amplitude conversion circuit for converting one level to a first potential and a second signal to a second level whose other level is a third potential higher than the second potential. A discharge circuit that causes a current having a value corresponding to the potential of the signal No. 1 to flow out; and a control circuit that is activated in response to the activation level being set to the activation level, so that the potential of the first output node becomes the potential of the second output node. If it is lower, the potentials of the first and second output nodes are set to the first and third potentials, respectively. Otherwise, the potentials of the first and second output nodes are set to the third and first potentials, respectively. And the differential amplifier before activation Each of the first and second output nodes are those with an initialization circuit which sets the initial potential during.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
[Embodiment 1]
FIG. 1 is a block diagram showing a configuration of a portion related to image display of a mobile phone according to Embodiment 1 of the present invention. In FIG. 1, this mobile phone includes a control LSI 1 which is a MOST (MOS transistor) type integrated circuit and a liquid crystal display device 2 which is a TFT (thin film transistor) type integrated circuit. The liquid crystal display device 2 includes a level shifter 3 and a liquid crystal display. The display unit 4 is included.
[0013]
The control LSI 1 is mainly composed of a MOS transistor and outputs a control signal for the liquid crystal display device 2. The "H" level of this control signal is 3V, and its "L" level is 0V. Although a large number of control signals are actually generated, one control signal is used here for simplification of the description. The level shifter 3 is configured by a TFT, and converts a logical level of a control signal from the control LSI 1 to generate an internal control signal. The "H" level of this internal control signal is 7.5V, and its "L" level is 0V. The liquid crystal display unit 4 is mainly composed of a TFT, and displays an image according to an internal control signal from the level shifter 3.
[0014]
The reason that the level shifter 3 is required is that the liquid crystal display unit 4 is stable unless the level shifter 3 is provided because the threshold voltage of the TFT is a voltage (about 3 V) substantially equal to the amplitude of the output signal of the control LSI 1. Does not work. When the output signal of the control LSI 1 is a positive signal with the ground potential GND as a reference potential, the level relationship between the threshold voltage VTN of the N-type TFT and the amplitude voltage of the output signal of the control LSI 1 becomes a problem. Become. When the output signal of the control LSI 1 is a signal of negative polarity with the power supply potential VCC as a reference potential, the height relationship between the threshold voltage VTP of the P-type TFT and the amplitude voltage of the output signal of the control LSI becomes a problem. Become. The output signal of the control LSI 1 generally has a positive polarity.
[0015]
The level shifter includes a two-input type in which two signals VI and / VI complementary to each other are input, and a one-input type in which one signal VI is input. The two-input type can perform a level shift operation only with two input signals VI and / VI, but the number of input signals increases, and it is difficult to reduce the size of the system. The one-input type has a small number of input signals and is easy to miniaturize the system, but cannot operate only with the input signal VI and needs to be driven by the level-shifted control signals φ and / φ. In consideration of the above points, in an actual liquid crystal display device, signals φ and / φ for driving a one-input type level shifter are generated by a two-input type level shifter, and other signals VO are generated by a one-input type level shifter. I have. Hereinafter, the one-input type level shifter which is a feature of the present invention will be described in detail.
[0016]
FIG. 2 is a circuit diagram showing a configuration of the level shifter 3. 2, the level shifter 3 includes P-type TFTs 11, 12, and 20, N-type TFTs 13 to 16, 21 to 26, 31 to 36, 43 to 46, a resistance element 30, and capacitors 37 and 47. Each of the P-type TFTs 11, 12, and 20 has a threshold voltage VTP of about -3V, and each of the N-type TFTs 13 to 16, 21 to 26, 31 to 36, 43 to 46 has a threshold voltage of about 3V. Has VTN.
[0017]
The sources of the P-type TFTs 11 and 12 are both connected to a node N10, their drains are connected to output nodes N11 and N12, respectively, and their gates are connected to output nodes N12 and N11, respectively. The drains of the N-type TFTs 13 and 14 are respectively connected to output nodes N11 and N12, their sources are both connected to the ground potential GND line, and their gates are connected to output nodes N12 and N11, respectively. The “H” level of control signal φ2 is 7.5V, and its “L” level is 0V. The TFTs 11 to 14 constitute a positive feedback differential amplifier circuit that amplifies the potential difference between the output nodes N11 and N12 to 7.5 V in response to the control signal φ2 being set to 7.5V. Complementary signals / VO and VO are output to nodes N11 and N12, respectively. The "H" level of each of signals / VO and VO is 7.5V, and each "L" level is 0V.
[0018]
N-type TFTs 15 and 16 are connected between output nodes N11 and N12 and a line of ground potential GND, respectively, and their gates both receive control signal / φ. The “H” level of control signal / φ is 7.5V, and its “L” level is 0V. The N-type TFTs 15 and 16 form an initialization circuit that initializes the potentials of the output nodes N11 and N12 to the ground potential GND in response to the control signal / φ being set to the “H” level.
[0019]
The resistance element 30 and the N-type TFTs 31 and 32 are connected in series between the line of the power supply potential VDD and the line of the ground potential GND. The gates of the N-type TFTs 31 and 32 are respectively connected to their drains. Each of the N-type TFTs 31 and 32 constitutes a diode element. Since the resistance value of resistance element 30 is set to a value sufficiently higher than the conduction resistance values of N-type TFTs 31 and 32, the potential of node N30 between resistance element 30 and N-type TFT 31 is 2 VTN. Since the resistance value of the resistance element 30 is set to a sufficiently high value, almost no current flows through the resistance element 30 and the N-type TFTs 31 and 32.
[0020]
The N-type TFTs 33, 34, 36 are connected in series between the line of the power supply potential VDD and the line of the ground potential GND. The gate of the N-type TFT 33 receives the potential 2VTN of the node N30. The gate of the N-type TFT 34 is connected to its drain (node N33). The N-type TFT 34 constitutes a diode element. The capacitor 37 is connected to the N-type TFT 34 in parallel. The gate of N-type TFT 36 receives control signal / φ, and its source is connected to node N34. The drain of N-type TFT 35 receives input signal VI, and its gate receives control signal φ1. The “H” level of the input signal VI is 3V, and its “L” level is 0V. The "H" level of control signal φ1 is 7.5V, and its "L" level is 0V. Control signal φ1 is a signal having a phase opposite to that of control signal / φ.
[0021]
While control signals / φ and φ1 are at “H” level and “L” level, respectively, N-type TFT 35 is non-conductive and N-type TFT 36 is conductive, and nodes N33 and N34 are at VTN and 0V, respectively. The N-type TFT 34 operates at the boundary between the conductive state and the non-conductive state, and almost no current flows through the N-type TFT 34. Capacitor 37 is charged to VTN. When the control signals / φ and φ1 are set to “L” level and “H” level, respectively, the N-type TFT 36 is turned off and the N-type TFT 35 is turned on, so that the potential (3 V or 0 V) of the input signal VI is changed. The signal is transmitted to node N34. When the input signal VI is 3V, the potential of the node N33 rises to VTN + ΔV via the capacitor 37. Here, ΔV ≒ 3V. When the input signal VI is 0 V, the potential of the node N33 remains unchanged at VTN. The potential of the node N33 is applied to the gate of the N-type TFT 25.
[0022]
The N-type TFTs 43, 44, and 46 are connected in series between the line of the power supply potential VDD and the line of the ground potential GND. The gate of the N-type TFT 43 receives the potential 2VTN of the node N30. The gate of the N-type TFT 44 is connected to its drain (node N43). The N-type TFT 44 constitutes a diode element. The capacitor 47 is connected to the N-type TFT 44 in parallel. The gate of N-type TFT 46 receives control signal / φ. The drain of N-type TFT 45 receives reference potential VR, and its gate receives control signal φ1. Reference potential VR is an intermediate level between “H” level and “L” level of input signal VI, that is, 1.5 V.
[0023]
While control signals / φ and φ1 are at “H” level and “L” level, respectively, N-type TFT 45 is non-conductive and N-type TFT 46 is conductive, and nodes N43 and N44 are at VTN and 0V, respectively. The N-type TFT 44 operates at the boundary between the conductive state and the non-conductive state, and almost no current flows through the N-type TFT 44. Capacitor 47 is charged to VTN. When control signals / φ and φ1 are set to “L” level and “H” level, respectively, N-type TFT 46 is turned off and N-type TFT 45 is turned on, so that the reference potential (1.5 V) is applied to node N44. The voltage is transmitted, and the potential of node N43 rises to VTN + ΔV / 2 via capacitor 47. The potential of the node N43 is applied to the gate of the N-type TFT 26.
[0024]
The source of P-type TFT 20 receives power supply potential VDD, its gate receives control signal φ1, and its drain is connected to node N20. N-type TFTs 21 and 22 are both connected between node N20 and a line of ground potential GND, and their gates are connected to output nodes N12 and N11, respectively. N-type TFTs 23 and 25 are connected in series between output node N11 and a line of ground potential GND, and N-type TFTs 24 and 26 are connected in series between output node N12 and a line of ground potential GND. The gates of N-type TFTs 23 and 24 are both connected to node N20, and the gates of N-type TFTs 25 and 26 are connected to nodes N33 and N43, respectively.
[0025]
While the control signal φ1 is at the “L” level, the P-type TFT 20 conducts, the node N20 is charged to 7.5 V, and the N-type TFTs 23 and 24 conduct. As a result, a current flows from the output node N11 to the ground potential GND line via the N-type TFTs 23 and 25, and a current flows from the output node N12 to the ground potential GND line via the N-type TFTs 24 and 26. The magnitude relationship between the currents flowing through the N-type TFTs 25 and 26 determines the magnitude relationship between the potentials of the nodes N11 and N12. When the control signal φ1 becomes “H” level, the P-type TFT 20 becomes non-conductive. When the differential amplification operation by the TFTs 11 to 14 is performed and the output node N11 or N12 is set to 7.5 V, the N-type TFT 21 or 22 becomes conductive, the node N20 becomes 0 V, and the N-type TFTs 23 and 24 become non-conductive. become.
[0026]
FIG. 3 is a time chart showing the operation of the level shifter 3. Now, it is assumed that the input signal VI is at the “H” level (3 V). In the initial state, the control signal / φ is set to 7.5V, and both the control signals φ1 and φ2 are set to 0V. As a result, the N-type TFTs 15 and 16 conduct, and the output nodes N11 and N12 are both initialized to 0V. Further, the P-type TFT 20 becomes conductive, the node N20 becomes 7.5V, and the N-type TFTs 23 and 24 become conductive. Further, the N-type TFTs 36 and 46 conduct, the nodes N34 and N44 are set to 0V, and the nodes N33 and N43 are set to VTN.
[0027]
At a certain time t1, signal / φ starts to decrease toward “L” level and signal φ1 starts to increase toward “H” level. When signals / φ and φ1 reach “L” level and “H” level, respectively, at time t2, N-type TFTs 36 and 46 are turned off and N-type TFTs 35 and 45 are turned on, and potentials of nodes N33 and N43 are set. Become VTN + ΔV and VTN + ΔV / 2, respectively. Further, the TFTs 15, 16, and 20 become non-conductive.
[0028]
Next, at time t3, when control signal φ2 starts to rise toward “H” level, the resistance values of P-type TFTs 3, 4 decrease, and the potentials of output nodes N11, N12 start increasing. Since the gate potentials of the N-type TFTs 25 and 26 are both equal to or higher than VTN, current flows through both the N-type TFTs 25 and 26. However, since the gate potential of the N-type TFT 25 is higher than the gate potential of the N-type TFT 26 by ΔV / 2, the current flowing through the N-type TFT 25 becomes larger than the current flowing through the N-type TFT 26, and the potential of the output node N11 is output. It becomes lower than the potential of the node N12. The potential difference between the output nodes N11 and N12 is amplified by the differential amplifier circuit including the TFTs 11 to 14, and the potential of the output node N12 increases while the potential of the output node N11 decreases. , 7.5V.
[0029]
When the potential of the output node N12 exceeds VTN, the N-type TFT 21 conducts and the node N20 is grounded. As a result, the N-type TFTs 23 and 24 are rendered non-conductive, the current path between the output node N12 and the ground potential GND line is cut off, and there is no through current between the node N10 and the ground potential GND line. DC current consumption is eliminated.
[0030]
Next, when the control signal φ2 falls from 7.5V to 0V at time t5, the charge at the output node N12 is discharged to the node N10 via the P-type TFT12. When the potential of the signal φ2 becomes equal to or less than | VTP |, the P-type TFT 12 becomes non-conductive, so that the potential of the output node N12 temporarily stops at | VTP |.
[0031]
Next, at time t6, signal / φ rises from 0V to 7.5V, and signal φ1 falls from 7.5V to 0V. As a result, the N-type TFT 16 conducts, and the output node N12 is grounded. Further, the N-type TFTs 35 and 45 become non-conductive and the N-type TFTs 36 and 46 become conductive, the nodes N34 and N44 become 0V, and the nodes N33 and N43 become VTN. Further, the P-type TFT 20 becomes conductive, the node N20 rises to 7.5 V, and returns to the initial state.
[0032]
When input signal VI is at "L" level (0 V), as shown by the dotted line in FIG. 3, even when signal φ1 rises to "H" level, the potential of node N33 remains at VTN. On the other hand, the potential of node N43 rises from VTN to VTN + ΔV / 2 when signal φ1 rises to “H” level. Therefore, when signal φ2 rises to the “H” level, the potential of node N11 becomes higher than the potential of node N12, and nodes N11 and N12 are set to 7.5V, It is set to 0V. Thus, the input signal VI having an amplitude voltage of 3 V is converted into signals / VO and VO having an amplitude voltage of 7.5 V.
[0033]
In the first embodiment, since the control signal φ2 is set to 0 V during the initial state setting period, no through current flows from the node N10 to the line of the ground potential GND. When the level shift operation is completed, the TFTs 11, 14 or 12, 13 and the N-type TFTs 23, 24 become non-conductive, and no through current flows from the node N10 to the line of the ground potential GND. Therefore, current consumption is small.
[0034]
In the first embodiment, the level shifter 3 is mainly composed of TFTs, but it goes without saying that the level shifter 3 may be composed of MOS transistors instead of TFTs.
[0035]
Further, the sources of the N-type TFTs 15 and 16 are connected to the line of the ground potential GND. However, if the level shifter 3 operates normally, the sources of the N-type TFTs 15 and 16 are connected to the line of the initial potential other than the ground potential GND. May be.
[0036]
Although the TFTs 20, 35, and 45 are controlled by the same signal φ1, the TFTs 20, 35, and 45 may be controlled by separate signals having substantially the same phase.
[0037]
Further, the TFTs 15, 16, 36, 46 are controlled by the same signal / φ, but the TFTs 15, 16, 36, 46 may be controlled by separate signals having substantially the same phase.
[0038]
The same power supply potential VDD is applied to one electrode of the resistance element 30, the drains of the N-type TFTs 33 and 43, and the source of the P-type TFT 20, but if the level shifter 3 operates normally, different power supply potentials are applied to them. You may.
[0039]
Although the ground potential GND is applied to the drains of the N-type TFTs 21 and 22, if the N-type TFTs 23 and 24 can be made non-conductive, a potential other than the ground potential GND is applied to the drains of the N-type TFTs 21 and 22. May be given.
[0040]
[Embodiment 2]
FIG. 4 is a circuit diagram showing a configuration of a level shifter 50 according to the second embodiment of the present invention. Referring to FIG. 4, this level shifter 50 is different from level shifter 3 in FIG. 2 in that N-type TFT 14 is replaced with N-type TFT 51, and P-type TFT 20 and N-type TFTs 21 to 24, 45, and 46 are removed. Is a point.
[0041]
In the level shifter 3 of FIG. 2, the current driving capability of the N-type TFT 13 and the current driving capability of the N-type TFT 14 are set to the same level. It is set to a level higher than the driving capability. As a method for making the current driving capability of the N-type TFT 51 higher than the current driving capability of the N-type TFT 13, a method of making the gate width (channel width) of the N-type TFT 51 longer than the gate width of the N-type TFT 13, There is a method of making the gate length (channel length) shorter than the gate length of the N-type TFT 13.
[0042]
The drain of the N-type TFT 25 is directly connected to the output node N11, the drain of the N-type TFT 26 is directly connected to the output node N12, and the source (node N44) of the N-type TFT 40 is grounded.
[0043]
When input signal VI is 3 V, when signal φ1 rises from “L” level to “H” level, the potential of node N33 rises from VTN to VTN + ΔV, and N-type TFT 25 conducts. On the other hand, the potential of the node N43 is fixed at VTN, and the N-type TFT 26 is fixed in a non-conductive state. Since the sum of the current driving capabilities of the N-type TFTs 13 and 25 is larger than the current driving capability of the N-type TFT 51, when the signal φ2 rises from the “L” level to the “H” level, the difference between the TFTs 11 to 13 and 51 is determined. The nodes N11 and N12 are set to 0V and 7.5V, respectively, by the dynamic amplifier circuit.
[0044]
When input signal VI is 0 V, even when signal φ1 rises from “L” level to “H” level, the potential of node N33 does not change as VTN, and N-type TFT 25 does not change while non-conductive state. . Since the current driving capability of the N-type TFT 51 is larger than the current driving capability of the TFT 13, when the signal φ2 rises from the “L” level to the “H” level, the node is controlled by the differential amplifier circuit composed of the TFTs 11 to 13 and 51. N11 and N12 are set to 7.5V and 0V, respectively.
[0045]
When the input signal VI is 3V, the TFTs 11 and 51 become non-conductive, so that no through current flows from the node N10 to the line of the ground potential GND. When the input signal VI is 0V, the TFTs 12 and 13 become non-conductive. Therefore, no through current flows from node N10 to the line of ground potential GND. Therefore, the TFTs 20 to 24 become unnecessary. The reason why the N-type TFTs 26, 43 and 44 and the capacitor 47 are left is to make the capacitances of the nodes N11 and N12 equal.
[0046]
In the second embodiment, the same effects as those of the first embodiment can be obtained, and a potential generation circuit for generating reference potential VR and a wiring for reference potential VR are not required, so that power consumption can be reduced and layout area can be reduced. Reduction is achieved.
[0047]
[Embodiment 3]
FIG. 5 is a circuit diagram showing a configuration of a level shifter 55 according to the third embodiment of the present invention. Referring to FIG. 5, level shifter 55 differs from level shifter 3 in FIG. 2 in that P-type TFTs 11, 12, and 20 are replaced with N-type TFTs 56 to 63. Therefore, in this level shifter 55, no P-type TFT is used.
[0048]
The drain of N-type TFT 56 receives power supply potential VDD, its source is connected to node N20, and its gate receives signal / φB. Signal / φB is a signal having a phase opposite to that of signal φ1, and its “H” level is VDD + VTN and its “L” level is 0V.
[0049]
N-type TFTs 57 and 58 are connected between node N10 and output nodes N11 and N12, respectively. N-type TFTs 59 and 60 are respectively connected between a line of power supply potential VDD (7.5 V) and gates of N-type TFTs 57 and 58 (nodes N59 and N60), and both of them receive signal / φB. N-type TFT 61 is connected between nodes N59 and N60, and its gate receives signal / φB. The drains of the N-type TFTs 62 and 63 are respectively connected to nodes N59 and N60, their sources are respectively connected to output nodes N11 and N12, and their gates are respectively connected to output nodes N12 and N11.
[0050]
Next, the operation of the level shifter 55 will be described. Now, it is assumed that the input signal VI is set to 3V. In the initial state, signals / φ and / φB are set to “H” level, and signal φ2 is set to “L” level (see FIG. 3). As a result, the N-type TFT 56 becomes conductive, the node N20 becomes “H” level, and the N-type TFTs 23 and 24 become conductive. Further, the N-type TFTs 36 and 46 conduct, and the potentials of the nodes N33 and N43 become VTN. Also, the N-type TFTs 15 and 16 become conductive, the nodes N11 and N12 become 0V, and the N-type TFTs 62 and 63 become non-conductive. Further, the N-type TFTs 59 to 61 conduct, the nodes N59 and N60 become 7.5 V, and the N-type TFTs 57 and 58 conduct.
[0051]
Next, when both signals / φ and / φB fall to “L” level and signal φ1 rises to “H” level, N-type TFTs 15, 16, 36, 46, 56, 59-61 are turned off. At the same time as conduction, the N-type TFTs 35 and 45 conduct. As a result, the potentials of the nodes N33 and N43 become VTN + ΔV and VTN + ΔV / 2, respectively.
[0052]
Next, when the signal φ2 rises from 0V to 7.5V (time t3 in FIG. 3), the potentials of the output nodes N11 and N12 rise because the N-type TFTs 57 and 58 are conducting. At this time, the current flowing from the output node N11 to the ground potential GND line via the N-type TFTs 23 and 25 is larger than the current flowing from the output node N12 to the ground potential GND line via the N-type TFTs 24 and 26. Therefore, the potential of output node N11 becomes lower than the potential of output node N12. The potential difference between the output nodes N11 and N12 is amplified by a differential amplifier circuit composed of N-type TFTs 13, 14, 57, 58, 62 and 63, and the output nodes N11 and N12 become 0V and 7.5V, respectively.
[0053]
When the input signal VI is 0V, the potentials of the nodes N33 and N43 become VTN and VTN + ΔV / 2 when the N-type TFTs 35 and 45 conduct, respectively, and the output node N11 when the signal φ2 becomes 7.5V. Is smaller than the current flowing from output node N12. Therefore, the potential of the output node N11 becomes higher than the potential of the output node N12, and the output nodes N11 and N12 become 7.5V and 0V, respectively. Other configurations and operations are the same as those of level shifter 3 of FIG. 2, and therefore, description thereof will not be repeated.
[0054]
In the third embodiment, the same effects as those of the first embodiment can be obtained. In addition, since no P-type TFT is used, a device that can use only an N-type TFT, such as a liquid crystal display device using an amorphous silicon film, can be used. Can be mounted. Further, the manufacturing process can be simplified and the manufacturing cost can be reduced.
[0055]
The sources of the N-type TFTs 62 and 63 may be connected to the ground potential GND line without connecting to the output nodes N11 and N12.
[0056]
The level shifter 65 of FIG. 6 is obtained by replacing the N-type TFT 14 of the level shifter 55 of FIG. 5 with an N-type TFT 51 and removing the N-type TFTs 21 to 24, 45, 46, and 56. This modified example is a combination of the second and third embodiments. The same effects as those of the third embodiment can be obtained. In addition, a potential generating circuit for generating reference potential VR and a wiring for reference potential VR are provided. This is unnecessary, and power consumption and layout area can be reduced.
[0057]
The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0058]
【The invention's effect】
As described above, in the amplitude conversion circuit according to the present invention, the first signal whose one level is the first potential and the other level is the second potential higher than the first potential, One level is a first potential, and the other level is converted to a second signal having a third potential higher than the second potential. In this amplitude conversion circuit, a first discharge circuit for causing a current having a value corresponding to the potential of the first signal to flow from the first output node, and a reference between the first and second potentials from the second output node. A second discharge circuit that causes a current having a value corresponding to the potential to flow out, and a third circuit that is activated in response to the control signal being set to the activation level and generates a potential difference between the first and second output nodes. And a differential amplifier circuit for amplifying to a voltage having a first potential difference, and an initialization circuit for setting each of the first and second output nodes to an initial potential during a period before the differential amplifier circuit is activated Are provided. Therefore, no through current flows during the initial state setting period, and no through current flows after the end of the level shift operation, so that the current consumption can be reduced.
[0059]
Further, another amplitude conversion circuit according to the present invention outputs a first signal whose one level is a first potential and whose other level is a second potential higher than the first potential. One level is a first potential, and the other level is converted into a second signal having a third potential higher than the second potential. In this amplitude conversion circuit, a discharge circuit that causes a current having a value corresponding to the potential of the first signal to flow out from the first output node, and a discharge circuit that is activated in response to a control signal being set to an activation level, Is lower than the potential of the second output node, the potentials of the first and second output nodes are set to the first and third potentials, respectively. Otherwise, the potentials of the first and second output nodes are different. A differential amplifier circuit for setting the potential of the output node to the third and first potentials, and setting each of the first and second output nodes to the initial potential during a period before the differential amplifier circuit is activated And an initialization circuit. Therefore, no through current flows during the initial state setting period, and no through current flows after the end of the level shift operation, so that the current consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a main part of a mobile phone according to Embodiment 1 of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a level shifter shown in FIG.
FIG. 3 is a time chart illustrating an operation of the level shifter illustrated in FIG. 2;
FIG. 4 is a circuit diagram showing a configuration of a level shifter according to a second embodiment of the present invention.
FIG. 5 is a circuit diagram showing a configuration of a level shifter according to a third embodiment of the present invention.
FIG. 6 is a circuit diagram showing a modification of the third embodiment.
FIG. 7 is a circuit diagram showing a configuration of a conventional level shifter.
FIG. 8 is a diagram showing an operation of the level shifter shown in FIG. 7;
[Explanation of symbols]
Reference Signs List 1 control LSI, 2 liquid crystal display device, 3, 50, 55, 65, 70 level shifter, 4 liquid crystal display unit, 11, 12, 20 P-type TFT, 13-16, 21-26, 31-36, 43-46 , 56 to 63 N-type TFT, 30 resistor, 37, 47, 74 capacitor, 71 to 73 N-channel MOS transistor, 75 inverter.

Claims

A first signal whose one level is a first potential and the other level is a second potential higher than the first potential; one level of which is the first potential; An amplitude conversion circuit for converting a second signal into a second signal whose other level is a third potential higher than the second potential,
A first discharge circuit that causes a current having a value corresponding to the potential of the first signal to flow from a first output node;
A second discharge circuit for causing a current having a value corresponding to a reference potential between the first and second potentials to flow out from a second output node;
A differential amplifier that is activated in response to the control signal attaining the activation level, and amplifies a potential difference generated between the first and second output nodes to a voltage having a difference between the third and first potentials. An amplitude conversion circuit comprising: a circuit; and an initialization circuit that sets each of the first and second output nodes to an initial potential during a period before the differential amplifier circuit is activated.

The first discharge circuit includes:
A first switching element that becomes non-conductive in response to at least one output node of the first and second output nodes exceeding a predetermined potential between the first and third potentials;
A first N-type transistor connected in series with the first switching element between the first output node and the first potential line, and a threshold potential of the first N-type transistor; A first potential generation circuit for applying a potential obtained by adding a potential according to a potential of the first signal to an input electrode of the first N-type transistor;
The second discharge circuit includes:
A second switching element that becomes nonconductive when at least one output node of the first and second output nodes exceeds a predetermined potential between the first and third potentials;
A second N-type transistor connected in series with the second switching element between the second output node and the first potential line, and a threshold potential of the second N-type transistor. 2. The amplitude conversion circuit according to claim 1, further comprising a second potential generation circuit that applies a potential obtained by adding a potential according to the reference potential to an input electrode of the second N-type transistor. 3.

The first potential generation circuit adds a threshold potential of the first N-type transistor and a potential according to a potential of the first signal during a period in which the differential amplifier circuit is activated. A potential is applied to an input electrode of the first N-type transistor, and during a period in which the differential amplifier circuit is not activated, the threshold potential of the first N-type transistor is set to the input of the first N-type transistor. Given to the electrodes,
The second potential generation circuit calculates a potential obtained by adding a threshold potential of the second N-type transistor and a potential according to the reference potential during a period in which the differential amplifier circuit is activated. And applying the threshold potential of the second N-type transistor to the input electrode of the second N-type transistor during a period when the differential amplifier circuit is not activated. An amplitude conversion circuit according to claim 2.

The inactivation level and the activation level of the control signal are the first and third potentials, respectively.
The differential amplifier circuit,
Their first electrodes both receive the control signal, their second electrodes are respectively connected to the first and second output nodes, and their input electrodes are respectively connected to the second and first output nodes. Are connected to the first and second output nodes, respectively, and the second electrodes are both connected to the first potential. And third and fourth N-type transistors whose input electrodes are connected to the second and first output nodes, respectively.
4. The amplitude conversion circuit according to claim 1, wherein said initial potential is said first potential.

The inactivation level and the activation level of the control signal are the first and third potentials, respectively.
The differential amplifier circuit,
A charging circuit for charging first and second nodes to the third potential during a period before the differential amplifier is activated;
Their first electrodes both receive the control signal, their second electrodes are respectively connected to the first and second output nodes, and their input electrodes are connected to the first and second nodes, respectively. Connected third and fourth N-type transistors,
Their first electrodes are respectively connected to the first and second nodes, their second electrodes are respectively connected to the first and second output nodes, and their input electrodes are each connected to the second And the fifth and sixth N-type transistors connected to the first output node, and their first electrodes are connected to the first and second output nodes, respectively, and their second electrodes are both A seventh and an eighth N-type transistor receiving the first potential and having their input electrodes connected to the second and first output nodes, respectively;
4. The amplitude conversion circuit according to claim 1, wherein said initial potential is said first potential.

The inactivation level and the activation level of the control signal are the first and third potentials, respectively.
The differential amplifier circuit,
A charging circuit for charging first and second nodes to the third potential during a period before the differential amplifier is activated;
Their first electrodes both receive the control signal, their second electrodes are respectively connected to the first and second output nodes, and their input electrodes are connected to the first and second nodes, respectively. Connected third and fourth N-type transistors,
Their first electrodes are respectively connected to the first and second nodes, their second electrodes both receive the first potential, and their input electrodes are respectively connected to the second and first outputs. Fifth and sixth N-type transistors connected to a node and their first electrodes are respectively connected to the first and second output nodes, and both of the second electrodes are connected to the first potential. And their input electrodes include seventh and eighth N-type transistors connected to the second and first output nodes, respectively.
4. The amplitude conversion circuit according to claim 1, wherein said initial potential is said first potential.

In the initialization circuit, one of the electrodes is connected to the first and second output nodes, and the other electrode receives the initial potential, and is turned off during a period in which the differential amplifier circuit is activated. The amplitude conversion circuit according to claim 1, further comprising third and fourth switching elements.

A first signal whose one level is a first potential and the other level is a second potential higher than the first potential; one level of which is the first potential; An amplitude conversion circuit for converting a second signal into a second signal whose other level is a third potential higher than the second potential,
A discharge circuit that causes a current having a value corresponding to the potential of the first signal to flow out of the first output node;
The control signal is activated in response to the activation level, and when the potential of the first output node is lower than the potential of the second output node, the potential of the first and second output nodes is reduced. A differential amplifier circuit for setting the potentials of the first and second output nodes to the third and first potentials, respectively; An amplitude conversion circuit, comprising: an initialization circuit that sets each of the first and second output nodes to an initial potential during a period before is activated.

The discharge circuit,
A first N-type transistor connected between the first output node and the first potential line; and a threshold potential of the first N-type transistor and a potential of the first signal. The amplitude conversion circuit according to claim 8, further comprising a potential generation circuit that provides a potential obtained by adding a corresponding potential to an input electrode of the first N-type transistor.

The potential generating circuit is configured to calculate a potential obtained by adding a threshold potential of the first N-type transistor and a potential corresponding to a potential of the first signal during a period in which the differential amplifier circuit is activated. A threshold voltage of the first N-type transistor is applied to an input electrode of the first N-type transistor during a period in which the differential amplifier circuit is not activated. An amplitude conversion circuit according to claim 9.

The inactivation level and the activation level of the control signal are the first and third potentials, respectively.
The differential amplifier circuit,
Their first electrodes both receive the control signal, their second electrodes are respectively connected to the first and second output nodes, and their input electrodes are respectively connected to the second and first output nodes. Are connected to the first and second output nodes, respectively, and the second electrodes are both connected to the first potential. And second and third N-type transistors whose input electrodes are connected to the second and first output nodes, respectively.
A current driving capability of the third N-type transistor is higher than a current driving capability of the second N-type transistor;
The amplitude conversion circuit according to claim 8, wherein the initial potential is the first potential.

The inactivation level and the activation level of the control signal are the first and third potentials, respectively.
The differential amplifier circuit,
A charging circuit for charging first and second nodes to the third potential during a period before the differential amplifier is activated;
Their first electrodes both receive the control signal, their second electrodes are respectively connected to the first and second output nodes, and their input electrodes are connected to the first and second nodes, respectively. Connected second and third N-type transistors,
Their first electrodes are respectively connected to the first and second nodes, their second electrodes are respectively connected to the first and second output nodes, and their input electrodes are each connected to the second And the fourth and fifth N-type transistors connected to the first output node, and their first electrodes are connected to the first and second output nodes, respectively, and their second electrodes are both A sixth and seventh N-type transistor receiving the first potential and having their input electrodes connected to the second and first output nodes, respectively;
The current drive capability of the seventh N-type transistor is higher than the current drive capability of the sixth N-type transistor,
The amplitude conversion circuit according to claim 8, wherein the initial potential is the first potential.

The inactivation level and the activation level of the control signal are the first and third potentials, respectively.
The differential amplifier circuit,
A charging circuit for charging first and second nodes to the third potential during a period before the differential amplifier is activated;
Their first electrodes both receive the control signal, their second electrodes are respectively connected to the first and second output nodes, and their input electrodes are connected to the first and second nodes, respectively. Connected second and third N-type transistors, their first electrodes are connected to the first and second nodes, respectively, and their second electrodes both receive the first potential; And fifth N-type transistors whose input electrodes are connected to the second and first output nodes, respectively, and their first electrodes are connected to the first and second output nodes, respectively. Their second electrodes both receive the first potential and their input electrodes include sixth and seventh N-type transistors connected to the second and first output nodes, respectively;
The current drive capability of the seventh N-type transistor is higher than the current drive capability of the sixth N-type transistor,
The amplitude conversion circuit according to claim 8, wherein the initial potential is the first potential.

In the initialization circuit, one of the electrodes is connected to the first and second output nodes, and the other electrode receives the initial potential, and is turned off during a period in which the differential amplifier circuit is activated. 14. The amplitude conversion circuit according to claim 8, further comprising a second and a third switching element.