JP2004186955A - Amplitude conversion circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplitude conversion circuit with a small consumption current. <P>SOLUTION: The level shifter 3 is provided with a p-type TFT 11 to make a current with a value corresponding to potential (0 V or 3 V) of an input signal VI corresponding to a state that a control signal ψ is set to 7.5 V to flow into an output node N13, a p-type TFT 12 to make a current with a value corresponding to reference potential VR(=1.5 V) corresponding to the state that the control signal ψ is set to 7.5 V to flow into an output node N14, a differential amplification circuit composed of TFTs 13-16 which amplify the potential difference generated between the output nodes N13, N14 to a power supply voltage VCC(=7.5 V), and n-type TFTs 17, 18 to initialize the output nodes N13, N14 to 0 V during the period that the control signal /ψ is 7.5 V. A through-current does not flow in the initial state and after the finish of level shift operations. As a result, only a small consumption current is required. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an amplitude conversion circuit, and more particularly, to an amplitude conversion circuit that converts an amplitude voltage of a signal.
[0002]
[Prior art]
FIG. 11 is a circuit diagram showing a configuration of a conventional one-input type level shifter 70. 11, the level shifter 70 includes N-channel MOS transistors 71 to 73, a capacitor 74, and an inverter 75. N channel MOS transistor 71 has a drain receiving input signal VI, a source connected to node N71, and a gate receiving control signal φ. N channel MOS transistor 72 has its drain receiving reference potential VR, its source connected to node N71, and its gate receiving control signal / φ. Capacitor 74 and inverter 75 are connected in series between node N71 and output node N75. N-channel MOS transistor 73 is connected in parallel to inverter 75, and has a gate receiving control signal / φ. The “H” level of the input signal VI is 3V, and its “L” level is 0V. Reference potential VR is an intermediate level between “H” level and “L” level of input signal VI, that is, 1.5 V. Inverter 75 is a well-known inverter including a P-channel MOS transistor and an N-channel MOS transistor connected in series between a line of power supply potential VCC (= 7.5 V) and a line of ground potential GND (= 0 V).
[0003]
Next, the operation of the level shifter 70 will be described. In an initial state, control signals φ and / φ are set to “L” level and “H” level, respectively. Thereby, N-channel MOS transistor 71 is turned off and N-channel MOS transistor 72 is turned on, and node N71 is set to reference potential VR. Also, the N-channel MOS transistor 73 conducts, the input node N74 of the inverter 75 and the output node N75 are connected, and as shown in FIG. 12A, the input / output transfer characteristic curve of the inverter 75 and the straight line of Vin = Vout At the intersection A, the inverter 75 operates, and the potentials of the nodes N74 and N75 become Va = VCC / 2.
[0004]
At a certain time, when signals φ and / φ are set to “H” level and “L” level, N channel MOS transistors 72 and 73 are turned off, N channel MOS transistor 71 is turned on, and inverter 75 is turned on. Is activated, and the level of input signal VI is transmitted to node N71. When input signal VI is at “H” level (3 V), the potential of node N 71 changes from 1.5 V to 3 V. This potential change is transmitted to node N74 via capacitor 74, and the potential of node N74 increases by ΔV. Here, ΔV is a potential change generated at the node N74 based on a potential change from 1.5V to 3V.
[0005]
As shown in FIG. 12A, when the input potential Vin of the inverter 75 increases by ΔV, the output potential Vout of the inverter 75 decreases from the point A and stabilizes at the point B. That is, the output potential Vout of the inverter 75 becomes 0V.
[0006]
When the input signal VI is at the “L” level (0 V), the potential of the node N71 changes from 1.5 V to 0 V, and the potential of the node N70 decreases by ΔV. In this case, the output potential Vout of the inverter 75 rises from the point A and stabilizes at the point C. That is, the output potential Vout of the inverter 75 becomes 7.5V. Therefore, the input signal VI having the amplitude voltage of 3V is converted into the signal VO having the amplitude voltage of 7.5V. Such a level shifter 70 is disclosed in, for example, Patent Document 1.
[0007]
[Patent Document 1]
Japanese Patent Publication No. 2-31523
[Problems to be solved by the invention]
FIG. 12B is a diagram illustrating a relationship between the input potential Vin of the inverter 75 and the consumption current Icc. In FIG. 12B, the current consumption Icc of the inverter 75 becomes maximum when Vin = Vout = VCC / 2. This is because when Vin = Vout = VCC / 2, both the P-channel MOS transistor and the N-channel MOS transistor included in the inverter 75 are turned on, so that the line between the power supply potential VCC line and the ground potential GND line penetrates. This is because current flows. However, in the conventional level shifter 70, since the inverter 75 is operated under the condition of Vin = Vout = VCC / 2 in the initial state, there is a problem that current consumption is large.
[0009]
Therefore, a main object of the present invention is to provide an amplitude conversion circuit with low current consumption.
[0010]
[Means for Solving the Problems]
In the amplitude conversion circuit according to the present invention, a first signal whose one level is a first potential and the other level is a second potential is a signal whose one level is a first potential, The other level is a third potential different from the second potential, and is converted into a second signal having an amplitude voltage larger than the amplitude voltage of the first signal. The amplitude conversion circuit includes a first transistor whose input electrode receives a first signal, and outputs a current having a value corresponding to the potential of the first signal in response to the control signal being set to an activation level. A second transistor whose input electrode receives a reference potential between the first and second potentials, and outputs a current having a value corresponding to the reference potential in response to the control signal being set to the activation level; It has first and second output nodes for receiving output currents of the first and second transistors, and converts a potential difference generated between the first and second output nodes into a voltage having a difference between the third and first potentials A differential amplifier circuit for amplifying, and an initialization circuit for setting each of the first and second output nodes to an initial potential before the control signal is set to the activation level.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
[Embodiment 1]
FIG. 1 is a block diagram showing a configuration of a portion related to image display of a mobile phone according to Embodiment 1 of the present invention. In FIG. 1, this mobile phone includes a control LSI 1 which is a MOST (MOS transistor) type integrated circuit and a liquid crystal display device 2 which is a TFT (thin film transistor) type integrated circuit. The liquid crystal display device 2 includes a level shifter 3 and a liquid crystal display. The display unit 4 is included.
[0012]
The control LSI 1 is mainly composed of a MOS transistor and outputs a control signal for the liquid crystal display device 2. The "H" level of this control signal is 3V, and its "L" level is 0V. Although a large number of control signals are actually generated, one control signal is used here for simplification of the description. The level shifter 3 is configured by a TFT, and converts a logical level of a control signal from the control LSI 1 to generate an internal control signal. The "H" level of this internal control signal is 7.5V, and its "L" level is 0V. The liquid crystal display unit 4 is mainly composed of a TFT, and displays an image according to an internal control signal from the level shifter 3.
[0013]
The reason that the level shifter 3 is required is that the liquid crystal display unit 4 is stable unless the level shifter 3 is provided because the threshold voltage of the TFT is a voltage (about 3 V) substantially equal to the amplitude of the output signal of the control LSI 1. Does not work. If the output signal of the control LSI 1 is a positive signal with the ground potential GND as a reference potential, the threshold voltage VTN of the N-type TFT and the amplitude of the output signal of the control LSI 1 become problems. If the output signal of the control LSI 1 is a signal of negative polarity with the power supply potential VCC as a reference potential, the threshold voltage VTP of the P-type TFT and the amplitude of the output signal of the control LSI become problematic. The output signal of the control LSI 1 generally has a positive polarity.
[0014]
The level shifter includes a two-input type in which two signals VI and / VI complementary to each other are input, and a one-input type in which one signal VI is input. The two-input type can perform a level shift operation only with two input signals VI and / VI, but the number of input signals increases, and it is difficult to reduce the size of the system. The one-input type has a small number of input signals and is easy to miniaturize the system, but cannot operate only with the input signal VI and needs to be driven by the level-shifted control signals φ and / φ. In consideration of the above points, in an actual liquid crystal display device, signals φ and / φ for driving a one-input type level shifter are generated by a two-input type level shifter, and other signals VO are generated by a one-input type level shifter. I have. Hereinafter, the one-input type level shifter which is a feature of the present invention will be described in detail.
[0015]
FIG. 2 is a circuit diagram showing a configuration of the level shifter 3. 2, the level shifter 3 includes P-type TFTs 11 to 14 and N-type TFTs 15 to 18. Each of the P-type TFTs 11 to 14 has a threshold voltage VTP of about -3V, and each of the N-type TFTs 15 to 18 has a threshold voltage VTN of about 3V. P-type TFTs 11 and 12 are connected between nodes N10 and N11 and N12, respectively, and have their gates receiving input signal VI and reference potential VR, respectively. Control signal φ is applied to node N10. The “H” level of control signal φ is 7.5 V, and its “L” level is 0 V. The “H” level of the input signal VI is 3V, and its “L” level is 0V. The reference potential VR is an intermediate level between the “H” level and the “L” level of the input signal VI, that is, 1.5 V.
[0016]
The sources of the P-type TFTs 13 and 14 are respectively connected to nodes N11 and N12, their drains are respectively connected to output nodes N13 and N14, and their gates are respectively connected to output nodes N14 and N13. The N-type TFTs 15 and 16 are connected between the output nodes N13 and N14 and the line of the ground potential GND, respectively, and their gates are connected to the output nodes N14 and N13, respectively. The TFTs 13 to 16 constitute a positive feedback differential amplifier circuit that amplifies a potential difference generated between the output nodes N13 and N14 to 7.5V. Complementary signals / VO and VO are output to nodes N13 and N14, respectively. Each "H" level of output signals / VO and VO is 7.5V, and each "L" level is 0V.
[0017]
N-type TFTs 17 and 18 are connected between output nodes N13 and N14 and a line of ground potential GND, respectively, and their gates both receive inverted signal / φ of control signal φ. The N-type TFTs 17 and 18 constitute an initialization circuit for initializing the potentials of the output nodes N13 and N14 to the ground potential GND.
[0018]
Next, the operation of the level shifter 3 will be described. Now, it is assumed that the input signal VI is at the “H” level (3 V). In the initial state, as shown in FIG. 3, the signal / φ is set to 7.5V and the signal φ is set to 0V. Since the signal / φ is set to 7.5 V, the N-type TFTs 17 and 18 conduct, and the output nodes N13 and N14 are both initialized to 0V. Therefore, the N-type TFTs 15 and 16 are in a non-conductive state. Since the signal φ is set to 0 V, the P-type TFTs 11 to 14 are turned off.
[0019]
At a certain time t1, the level of signal / φ starts to decrease and the level of signal φ starts to increase. In response, the N-type TFTs 17 and 18 begin to become non-conductive, and the P-type TFTs 11 to 14 and the N-type TFTs 15 and 16 begin to conduct.
[0020]
When the level of signal φ becomes higher than reference potential VR (= 1.5 V) by the absolute value | VTP | of the threshold voltage of P-type TFT 12, the source-gate voltage of P-type TFT 12 becomes P-type. Since the absolute value | VTP | of the threshold voltage of the TFT 12 is exceeded, the P-type TFT 12 starts to conduct. Further, when the level of the signal φ becomes higher than the level (3 V) of the input signal VI by the absolute value | VTP | of the threshold voltage of the P-type TFT 11, the source-gate voltage of the P-type TFT 11 becomes P Since the absolute value of the threshold voltage | VTP | of the type TFT 11 is exceeded, the P-type TFT 11 starts to conduct.
[0021]
Therefore, at times t1 to t2, all the TFTs 11 to 18 conduct. As a result, the potentials of both output nodes N13 and N14 start to rise. However, since the gate-source voltage of the P-type TFT 12 is 1.5 V lower than the gate-source voltage of the P-type TFT 11, the potential of the output node N14 is higher than the potential of the output node N13. The potential difference between the two output nodes N13 and N14 is amplified by a differential amplifier circuit including TFTs 13 to 16.
[0022]
As a result, at time t2, the level of signal / VO decreases toward 0V and the level of signal VO increases toward 7.5V, and finally TFTs 13 and 16 become non-conductive and TFTs 14 and 15 become conductive. , Signals / VO and VO become 0V and 7.5V, respectively. As a result, the input signal VI having the amplitude voltage of 3V is converted into the complementary signals / VO and VO having the amplitude voltage of 7.5V. Thereafter, at time t3, signals / φ and φ are set to 7.5 V and 0 V, respectively, and return to the initial state.
[0023]
When the input signal VI is at the “L” level (0 V), the operations of the TFTs 11, 13, 15, 17 and the TFTs 12, 14, 16, 18 are reversed, and the signals / VO, VO become 7.5 V, respectively. It becomes 0V.
[0024]
In the first embodiment, since control signal φ is set to the “L” level during the initial state setting period, no through current flows between node N10 and the ground potential GND line. Further, since the TFTs 13, 16 or 14, 15 become non-conductive after the level shift operation is completed, no through current flows between the node N10 and the line of the ground potential GND. Therefore, current consumption is small.
[0025]
In the first embodiment, the level shift circuit 3 is constituted by eight TFTs 11 to 18, but it is needless to say that the level shift circuit 3 can be constituted by eight MOS transistors.
[0026]
In the first embodiment, the sources of the N-type TFTs 17 and 18 are connected to the ground potential GND line. However, if the level shift circuit 3 operates normally, the sources of the N-type TFTs 17 and 18 are connected to the ground potential GND. May be connected to a line having an initial potential different from that of the line.
[0027]
Hereinafter, various modifications of the first embodiment will be described. The level shifter 20 in FIG. 4 is obtained by adding N-type TFTs 21 and 22 to the level shifter 3 in FIG. The N-type TFTs 21 and 22 are connected in parallel to the P-type TFTs 13 and 14, respectively, and their gates both receive a control signal / φ. In the level shifter 3 of FIG. 2, the nodes N11 and N12 are in a high impedance state in an initial state, and the potentials of the nodes N11 and N12 may become unstable. On the other hand, in the level shifter 20, in the initial state where the signal / φ is at the “H” level, the N-type TFTs 17, 18, 21 and 22 conduct, and the potentials of the nodes N11 and N12 are set to 0V. Therefore, in level shifter 20, the operation of differentially amplifying the minute potential difference between nodes N13 and N14 after signal / φ is set to the “L” level is performed stably, and the operation margin of the circuit is increased.
[0028]
The level shifter 25 shown in FIG. 5 is obtained by connecting the sources of the N-type TFTs 21 and 22 to the ground potential GND line in the level shifter 20 shown in FIG. Also in this modified example, the same effect as the level shifter 20 of FIG. 4 can be obtained.
[0029]
The level shifter 30 in FIG. 6 is obtained by removing the N-type TFTs 21 and 22 of the level shifter 20 in FIG. 4 and adding N-type TFTs 31 and 32. N-type TFTs 31 and 32 are connected in parallel to P-type TFTs 11 and 12, respectively, and their gates both receive signal / φ. Also in this modified example, the same effect as the level shifter 20 of FIG. 4 can be obtained.
[0030]
The level shifter 35 in FIG. 7 is obtained by removing the N-type TFTs 17 and 18 of the level shifter 20 in FIG. 4 and adding N-type TFTs 31 and 32. N-type TFTs 31 and 32 are connected in parallel to P-type TFTs 11 and 12, respectively, and their gates both receive signal / φ. Also in this modified example, the same effect as the level shifter 20 of FIG. 4 can be obtained.
[0031]
In the level shifters 3, 20, 25, and 30 of FIGS. 2 and 4 to 6, the output nodes N13 and N14 are grounded via the N-type TFTs 17 and 18 during the transition time from time t1 to t2 in FIG. The level rise of output nodes N13 and N14 is suppressed, and the rise of output signals / VO and VO is delayed. On the other hand, in the level shifter 35 of FIG. 7, the N-type TFTs 17 and 18 are removed, and conversely, when the signal φ rises, the levels of the output nodes N13 and N14 increase through the N-type TFTs 31 and 21; , Output signals / VO, VO rise faster.
[0032]
[Embodiment 2]
FIG. 8 is a circuit diagram showing a configuration of a level shifter 40 according to the second embodiment of the present invention. 8, the level shifter 40 is different from the level shifter 3 of FIG. 2 in that the N-type TFTs 17 and 18 are removed and P-type TFTs 41 and 42 are added, and the power supply potential VCC (7. 5V), and the signal φ is supplied to the sources (node N15) of the N-type TFTs 15 and 16 instead of the ground potential GND. P-type TFTs 41 and 42 are connected between node N10 and output nodes N13 and N14, respectively, and their gates both receive signal / φ.
[0033]
Next, the operation of the level shifter 40 will be described. Now, it is assumed that the input signal VI is at the “H” level (3 V). In the initial state, as shown in FIG. 9, the signal / φ is set to 0V and the signal φ is set to 7.5V. Since the signal / φ is set to 0V, the P-type TFTs 41 and 42 conduct, and both the output nodes N13 and N14 are initialized to 7.5V. Since the signal φ is set to 7.5 V, the gate-source voltage of the N-type TFTs 15 and 16 becomes 0 V, and the N-type TFTs 15 and 16 are turned off. The P-type TFTs 11 and 12 conduct and the nodes N11 and N12 are at 7.5V. Therefore, the gate-source voltage of the P-type TFTs 13 and 14 becomes 0 V, and the P-type TFTs 13 and 14 are turned off.
[0034]
At a certain time t1, the level of signal / φ starts to rise and the level of signal φ starts to fall. In response, the P-type TFTs 41 and 42 begin to become non-conductive, and the P-type TFTs 13 to 16 begin to conduct.
[0035]
When the level of signal φ becomes lower than power supply potential VCC (= 7.5 V) by the threshold voltage VTN of N-type TFTs 15 and 16, the gate-source voltage of N-type TFTs 15 and 16 becomes N-type TFT 15. , 16 exceed the threshold voltage VTN, the N-type TFTs 15, 16 begin to conduct. When the N-type TFTs 15 and 16 begin to conduct, the levels of the nodes N13 and N14 decrease, and the P-type TFTs 13 and 14 begin to conduct.
[0036]
Therefore, at times t1 to t2, all the TFTs 11 to 16, 41, and 42 conduct. As a result, the potentials of both the output nodes N13 and N14 start to decrease. However, since the gate-source voltage of the P-type TFT 12 is 1.5 V lower than the gate-source voltage of the P-type TFT 11, the potential of the output node N14 is higher than the potential of the output node N13. The potential difference between the two output nodes N13 and N14 is amplified by a differential amplifier circuit including TFTs 13 to 16.
[0037]
As a result, at time t2, the level of signal / VO decreases toward 0V and the level of signal VO increases toward 7.5V, and finally TFTs 13 and 16 become non-conductive and TFTs 14 and 15 become conductive. , Signals / VO and VO become 0V and 7.5V, respectively. As a result, the input signal VI having the amplitude voltage of 3V is converted into the complementary signals / VO and VO having the amplitude voltage of 7.5V. Thereafter, at time t3, signals / φ and φ are set to 7.5 V and 0 V, respectively, and return to the initial state.
[0038]
When the input signal VI is at the “L” level (0 V), the operations of the TFTs 11, 13, 15, 41 and the TFTs 12, 14, 16, 42 are reversed, and the signals / VO, VO become 7.5 V, respectively. It becomes 0V.
[0039]
In the second embodiment, since control signal φ is set to “H” level during the initial state setting period, no through current flows between the line of power supply potential VCC and node N10. After the level shift operation is completed, the TFTs 13, 16 or 14, 15 are turned off, so that no through current flows between the power supply potential VCC line and the node N10. Therefore, current consumption is small.
[0040]
The level shifter 45 in FIG. 10 is obtained by removing the P-type TFTs 41 and 42 of the level shifter 40 in FIG. 8 and adding P-type TFTs 46 and 47. P-type TFTs 46 and 47 are connected in parallel to N-type TFTs 15 and 16, respectively, and their gates both receive signal / φ. Also in this modified example, the same effect as the level shifter 40 of FIG. 8 can be obtained. Further, in the level shifter 40 of FIG. 8, since the output nodes N13 and N14 are connected to the line of the power supply potential VCC via the P-type TFTs 41 and 42 during the transition time from time t1 to time t2 in FIG. The decrease in the level of N14 is suppressed, and the fall of output signals / VO and VO is delayed. On the other hand, in the level shifter 45 of FIG. 10, the P-type TFTs 41 and 42 are removed, and conversely, when the signal φ decreases, the levels of the output nodes N13 and N14 decrease via the P-type TFTs 46 and 47, and the output signal / VO and VO fall faster.
[0041]
The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0042]
【The invention's effect】
As described above, in the amplitude conversion circuit according to the present invention, the first signal whose one level is the first potential and the other level is the second potential, and whose one level is the first potential, And the other level is a third potential different from the second potential, and is converted into a second signal having an amplitude voltage larger than the amplitude voltage of the first signal. In this amplitude conversion circuit, a first transistor whose input electrode receives a first signal and outputs a current having a value corresponding to the potential of the first signal in response to a control signal being set to an activation level; A second transistor whose input electrode receives a reference potential between the first and second potentials, and outputs a current having a value corresponding to the reference potential in response to the control signal being set to the activation level; It has first and second output nodes for receiving output currents of the first and second transistors. The potential difference generated between the first and second output nodes is reduced by the voltage of the difference between the third and first potentials. A differential amplifier circuit for amplifying and an initialization circuit for setting each of the first and second output nodes to an initial potential before the control signal is set to the activation level are provided. Therefore, no through current flows during the initial state setting period, and no through current flows after the end of the level shift operation, so that the current consumption can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a main part of a mobile phone according to Embodiment 1 of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a level shifter shown in FIG.
FIG. 3 is a time chart illustrating an operation of the level shifter illustrated in FIG. 2;
FIG. 4 is a circuit diagram showing a modification of the first embodiment;
FIG. 5 is a circuit diagram showing another modification of the first embodiment.
FIG. 6 is a circuit diagram showing still another modification of the first embodiment.
FIG. 7 is a circuit diagram showing still another modification of the first embodiment.
FIG. 8 is a circuit diagram showing a configuration of a level shifter according to a second embodiment of the present invention.
FIG. 9 is a time chart illustrating an operation of the level shifter illustrated in FIG. 8;
FIG. 10 is a circuit diagram showing a modification of the second embodiment.
FIG. 11 is a circuit diagram showing a configuration of a conventional level shifter.
FIG. 12 is a diagram illustrating an operation of the level shifter illustrated in FIG. 11;
[Explanation of symbols]
Reference Signs List 1 control LSI, 2 liquid crystal display device, 3, 20, 25, 30, 35, 40, 45, 70 level shifter, 4 liquid crystal display unit, 11 to 14, 41, 42, 46, 47 P-type TFT, 15 to 18 , 21, 22, 31, 32 N-type TFT, 71-73 N-channel MOS transistor, 74 capacitor, 75 inverter.

Claims (11)

A first signal whose one level is a first potential and the other level is a second potential is a first signal whose one level is the first potential and whose other level is the second potential. An amplitude conversion circuit that converts the signal into a second signal having a third potential different from that of the first signal and having a larger amplitude voltage than the amplitude voltage of the first signal,
A first transistor whose input electrode receives the first signal, and outputs a current having a value corresponding to the potential of the first signal in response to the control signal being set to an activation level;
A second transistor whose input electrode receives a reference potential between the first and second potentials, and outputs a current having a value corresponding to the reference potential in response to the control signal being set to an activation level;
There are first and second output nodes for receiving output currents of the first and second transistors, respectively, and a potential difference between the first and second output nodes is determined by comparing the potential difference between the third and first potentials. An amplitude conversion circuit, comprising: a differential amplifier circuit for amplifying to a difference voltage; and an initialization circuit for setting each of the first and second output nodes to an initial potential before the control signal is set to an activation level. . The inactivation level and the activation level of the control signal are the first and third potentials, respectively.
The first and second transistors are both of a first conductivity type, and their first electrodes both receive the control signal;
The differential amplifier circuit,
Their first electrodes are respectively connected to the second electrodes of the first and second transistors, and their second electrodes are respectively connected to the first and second output nodes, and their input electrodes Are connected to the second and first output nodes, respectively, and third and fourth transistors of a first conductivity type, and their first electrodes are connected to the first and second output nodes, respectively. And fifth and sixth transistors of the second conductivity type, both having their second electrodes receiving the first potential and having their input electrodes connected to the second and first output nodes, respectively. Including
The amplitude conversion circuit according to claim 1, wherein the initial potential is the first potential. The initialization circuit is configured so that one of the electrodes is connected to the first and second output nodes, the other electrode receives the first potential, and the control signal is set to an activation level. 3. The amplitude conversion circuit according to claim 2, further comprising first and second switching elements that become non-conductive accordingly. The initialization circuit further includes third and fourth switching elements connected in parallel to the third and fourth transistors, respectively, and becoming non-conductive in response to the control signal being set to an activation level. An amplitude conversion circuit according to claim 3. The initialization circuit further has one electrode thereof connected to the second electrode of each of the first and second transistors, the other electrode both receiving the first potential, and the control signal being activated. 4. The amplitude conversion circuit according to claim 3, further comprising third and fourth switching elements that become non-conductive in response to the transition to the activation level. 5. The initialization circuit further includes third and fourth switching elements which are connected in parallel to the first and second transistors, respectively, and become non-conductive in response to the control signal being set to an activation level. An amplitude conversion circuit according to claim 3. The initialization circuit includes:
First and second switching elements respectively connected in parallel to the first and second transistors and becoming non-conductive in response to the control signal being set to an activation level; and the third and fourth switching elements, respectively. 3. The amplitude conversion circuit according to claim 2, further comprising third and fourth switching elements that are connected in parallel to the transistor and become nonconductive when the control signal is set to an activation level. The inactivation level and the activation level of the control signal are the third and first potentials, respectively.
The first and second transistors are both of a first conductivity type, and their first electrodes both receive the third potential;
The differential amplifier circuit,
Their first electrodes are respectively connected to the second electrodes of the first and second transistors, and their second electrodes are respectively connected to the first and second output nodes, and their input electrodes Are connected to the second and first output nodes, respectively, and third and fourth transistors of a first conductivity type, and their first electrodes are connected to the first and second output nodes, respectively. A second conductive type fifth and sixth transistor having their second electrodes both receiving the control signal and having their input electrodes connected to the second and first output nodes, respectively.
The amplitude conversion circuit according to claim 1, wherein the initial potential is the third potential. In the initialization circuit, one of the electrodes receives the third potential, the other electrode is connected to the first and second output nodes, respectively, and the control signal is set to an activation level. The amplitude conversion circuit according to claim 8, further comprising first and second switching elements that become non-conductive in response to the first and second switching elements. The initialization circuit includes first and second switching elements connected in parallel to the fifth and sixth transistors, respectively, and becoming non-conductive in response to the control signal being set to an activation level. Item 10. An amplitude conversion circuit according to item 8. The amplitude conversion circuit according to any one of claims 1 to 10, wherein the reference potential is a potential substantially intermediate between the first and second potentials.

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