TW564527B - Hybrid interconnect substrate and method of manufacture thereof - Google Patents
Hybrid interconnect substrate and method of manufacture thereof Download PDFInfo
- Publication number
- TW564527B TW564527B TW091123873A TW91123873A TW564527B TW 564527 B TW564527 B TW 564527B TW 091123873 A TW091123873 A TW 091123873A TW 91123873 A TW91123873 A TW 91123873A TW 564527 B TW564527 B TW 564527B
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- forming
- scope
- patent application
- item
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0108—Transparent
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/016—Temporary inorganic, non-metallic carrier, e.g. for processing or transferring
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/061—Lamination of previously made multilayered subassemblies
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/107—Using laser light
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
Description
564527 五、發明說明(1) 1發明領域: 本發明係關於-種構裝基板與其形成方法,特別是— j具有高密度之複合多層内連線結構的構裝基板與其形成 方法。 〜2發明背景: 傳統用於覆晶封裴製程之基板包含增層結構(Buiid up Structur=與壓合結構(Laminate structure)。 =-圖顯示-覆晶封裝結構。如第一圖所示…高密度多 ,内連線結構1〇2形成於一基底材料(Base Materiai) 1〇〇 f。高密度多層^線結構102與基底材料1〇〇構成覆晶封 裴結構的基板。南密度多層内連線結構1〇2與一覆置的晶 片112藉由銲接凸塊110與銲墊1〇8的銲接結合以形成覆晶 封裝結構。多層内連線結構102包含—介電部份1〇4與一電 路部份106。多層内連線結構102具有多層介電層與電路層 ’而這些多層介電層與電路層係由増層或壓合的方式形成
覆晶封裝基板具有由一層接著一層直接形成於一基底 材料上而成之多層内連線結構者為增層基板。該結構係由 直接形成多層内連線結構於一載台/核心基板(Carrier Substrate/Core Substrate)上而成,此載台基板為一印
第4頁 (2) 564527 五 刷電 種增 精準 增層 台 寸 及 成 寸 亳 發明說明 路板 層基 的阻 基板 板的 更動 降低良 於栽台 ,目前 米。 基 的 。將多層 板結構具 抗控制與 之結構亦 兩面上。 而調整每 率等缺點 基板上, 所用載台 内連線 有精確 可直接 可同時 儘管如 次增層 。此外 增層基 基板的 結構 的增 將被 直接 此, 製程 ,由 板的 尺寸 直接形成於哉 層導線/間距//^板上,此 動元件植入等/度控制、 形成多層^ Ϊ ‘點。另外, 此種増芦式f線結構於一載 ,:1基板會因為基板尺 於多屏二造成增加製造成本 尺十連線結構係直接形i!ίΓ限於載台基板的尺 又J約為6 1 〇毫米X 6 1 0 级Η有4監於上述傳統基板結構與製程的缺赴 ‘ 4 -種新穎進步的基板結構與製程以券:因此有必咢 構與製程的缺點。而本發明正能符統基板結 ~3發明目的及概述: 連線目的為提供一種具有高密度之複合多肩
與高密^純’此複合基板係由分別形成之低密度遵 在度電路結構所構成,故具有高良率的優點。 本叙明之另一目的為提供一種具有高密度之複合多層 内連線結構的基板’此複合基板係由現有之積體電路或薄 膜電晶體液晶顯示器(TFT-LCD)製程技術並利用大尺
第5頁 564527 五、發明說明(3) 基板形成,故生產成本低的優點。 本發明之又一目的為提供一種具有高密度之複合多層 内連線結構的基板,此複合基板並具有精準的阻抗控制的 優點。 本發明之另一目的為提供一種具有高密度之複合多層 内連線結構的基板,此複合基板具有可直接將被動元件植 入的優點。 為 線結構 驟。首 於該操 分解介 構上。 複數個 複數個 黏性光 光分解 了達成 之基板 先提供 作基板 電層上 圖案化 銲墊。 導體結 分解介 介電層 上述之目 的形成方 的,本發明提供一 法,該基板的形成 透光操作基板並形成一黏 上。接著 。然後形 該黏性結 接著藉由 合該多層 電層並移 形成一多層 成一黏性結 合膜以暴露 知接結合該 内連線結構 除該操作基 内連線 合膜於 出該多 銲墊與 與該載 板。最 種具有 方法包 性光分 結構於 該多層 層内連 一載台 台基板 後在移 多層内$ 含以下士 解介電^ 該黏性3 内連線矣 線結構戈 基板上之 。分解驾 除該黏伯
上述有關發明的簡單說明及以下的詳細說 並非限制。其他不脫離本發 彳為靶 痛4人^ < 才月狎的寺效改蠻叆修餉 應匕3在的本發明的專利範圍 〆〆
564527 五、發明說明(4) 5〜4發明的詳細說明: 在此必須說明的是以下描述之製程步驟及結構並不包 含完整之製程。本發明可以藉各種製程方法來實施,在此 僅提及瞭解本發明所需之製程方法。 以下將根據本發明所附圖示做詳細的說明,請注意圖 示均為簡單的形式且未依照比例描繪,而尺寸均被誇大以 利於瞭解本發明。
參考第二A圖所示,顯示一具有 丞底材料(Base
Material) 20 2之操作基板(Handle Substrate) 200。4 作基板2 0 0包含一透光平板,特別是一石英基板或一玻璃 基板此石英基板或玻璃基板尺寸可大於6丨〇毫米χ 6丨0^ 米。紅作基板2 0 0的一較佳實例為用於薄膜電晶體液晶顯 不益(TFT-LCD)製程所用之破璃基板。基底材料2〇2具方 t占.性、,且以一具黏性之高分子材料或離形膜(Release 。離形膜為一般封裝製程所用之介電膜,用方
η ϊ迗至後續製程之過程中遭受外部環境所污_ 解甘^ t f料2〇 2能被例如紫外線與雷射光束照射分 解’並在被分解後能被移除。 接著參考第二β圖所示 ’顯示一多層内連線結構2 〇 4形
$ 7頁 564527 五、發明說明(5) 成於基底材料2 0 2上。多層内連線結構2 0 4包含一介電部份 2 0 6與一導電部份。多層内連線結構2 〇 4之導電部份包含銲 墊208、21 2與介層柱塞210。第二B圖所示之多層内連線結 構2 0 4為簡化的圖示。多層内連線結構2 0 4以薄膜電晶體液 晶顯示器製程所用之設備與製程形成,這些製程包含沈積 、微影與蝕刻製程。此外,被動元件可直接植入於多層内 連線結構2 04内。 參考第二C圖所示,顯示形成一結合膜(Bonding F i 1 m) 2 1 4於多層内連線結構2 0 4上,此結合膜2 1 4接著被 圖案化以暴露出銲墊2 1 2。結合膜2 1 4包含一具有黏性與附 著力之介電膜,可具有半固化(Semi-Cured)的特性。第 二C圖同時顯示一晶片載台基板2 1 6。此晶片載台基板2 1 6 包含一印刷電路板2 1 8,例如一低成本之類似球型陣列基 板(Ball Grid Array Like Substrate)。此晶片載台基 板21 6具有一包含銲墊22 2與介層柱塞22 0之電路。如第二C 圖所示,導體224形成於銲墊2 2 2上。而導體224包含銲膏 (Solder Paste)、表面鏟著金屬(Metal Surface Coating)或金屬凸塊(Metal Bump)。銲膏可用刮刀印 刷(Squeegee Printing)的方式形成,而表面鑛著余屬與 金屬凸塊可以電鍍的方式形成。結合膜2 1 4亦可形成於晶 片載台基板2 1 6上並·曝露出銲墊2 2 2而不形成於多層内連線 結構2 0 4上。
第8頁 五 發明說明(6) — 〜 一 ------ 21 2以及?合考《第^ 224^ ^ ^ 多層内連線結構204銲接結合。者力曰曰片載台基板2丨6與 =光束照射並分解。紫外線或雷= 才呆作基板2 0 0到達基底材料二=二5穿透可透光之 所需之熱(HeatDose)。 並楗供基底材料2〇2分解 少考弟^一 E圖所不,顯-收a , 2。2依序移除,而形成_ = = =2_基底材料 。分解的基底材料20 2係;剝‘曰口連線結構的複合基板 ίΠ3;Λν圖顯示將第二E圖所示複合基板與-半導體 20^Μ曰::!結果。,合基板與半導體晶片23 2藉由銲墊 〜而、处于人/塊230的銲接結合以及介電材料228的填充固 ^ 3形成覆晶封裝結構。介電材料228包含灌膠混合 (Molding Compound)或覆晶填充(Underfiu)物。 人本發明提供了一種具有高密度之多層内連線結構的複 。基板。利用微米/次微米積體電路製程與大尺寸石英/玻 离f板’南密度精細之電路先形成於石英/玻璃基板上, ^,再被轉移至一低成本之非增層基板上。由於使用成熟 穩疋之製程技術及大尺寸之操作基板,而非直接將精細電 路圖案增層形成於尺寸有限及低良率之核心基板(Core b s t r a t e)上’此多層内連線結構的複合基板之生產成 本低於傳統之增層基板。本發明同時藉由分別形成低密度
564527 五、發明說明(7) 基板與高密度電路結構,而非直接形成高密度電路結構於 核心基板上,可提高複合基板之良率,使其良率高於傳統 增層基板製程。利用高精準度與密度之多層内連線結構製 程技術以形成具有精細、準確寬度與厚度之線路及介電層 ,本發明可提供良好之阻抗控制。此外,將被動元件直接 植入多層内連線結構中可提升覆晶封裝結構較良好之電 性。另外,利用現有之積體電路或薄膜電晶體液晶顯示器 之製程設備、製程與導體、介電材料來形成多層内連線結 構可提供較穩定良好的性質。 上述有關發明的詳細說明僅為範例並非限制。其他不 脫離本發明之精神的等效改變或修飾均應包含在的本發明 的專利範圍之内。
第10頁 564527 圖式簡單說明 圖式的簡單說明: 為了能讓本發明上述之其他目的、特徵、和優點能更 明顯易懂,下文特舉一較佳實施例,並配合所附圖式,作 詳細說明如下: 第一圖顯示一覆晶封裝結構; 第二A圖顯示一具有一基底材料之操作基板; 第二B圖顯示一多層内連線結構形成於基底材料上的 結果; 第二C圖顯示形成一結合膜於多層内連線結構上,接 著被圖案化以暴露出銲墊的結果; 第二D圖顯示晶片載台基板與多層内連線結構銲接結 合的結果; 第二E圖顯示將操作基板與基底材料移除,形成一具 有多層内連線結構的複合基板的結果;及 第二F圖顯示將第二E圖所示複合基板與一半導體晶片 結合的結果。
第11頁 564527 圖式簡單說明 主要部分之代表符號: 1 0 0基底材料 1 0 2高密度多層内連線結構 1 0 4介電部份 1 0 6電路部份 1 0 8銲墊 1 1 0銲接凸塊 1 1 2晶片 2 0 0操作基板 2 0 2基底材料 2 0 4多層内連線結構 2 0 6介電部份 2 0 8銲墊 2 1 0介層柱塞 2 1 2銲墊 2 1 4結合膜 2 1 6晶片載台基板 2 1 8印刷電路板 2 2 0介層柱塞 2 2 2銲墊 2 2 4導體 2 28介電材料 2 3 0銲接凸塊
第12頁 564527 圖式簡單說明 2 3 2半導體晶片 1^1 第13頁
Claims (1)
- 564527 六、申請專利範圍 1 ·種具有多層内連線結構之基板的形成方法,該基板的 形成方法包含: 提供一透光操作基板(Handle Substrate); 形成一黏性光分解介電層於該操作基板上; 形成一多層内連線結構於該黏性光分解介電層上,該 多層内連線結構之表面具有複數個銲墊; 形成一黏性結合膜於該多層内連線結構上; 圖案化該黏性結合膜以暴露出該多層内連 之該複數個銲墊; 、!、、①構表面 提供一載台基板(Carrier Substrate),該載Α 板設有突出表面之複數個導體; σ基 藉由銲接分別結合該複數個銲墊與該載台基板上 ^ 複數個導體,以結合該多層内連線結構與該載台基板之该 分解該黏性光分解介電層; 土 ’ 移除該操作基板;及 移除該黏性光分解介電層。 2 ·如申請專利範圍第1項所述之基板的形成方法,其中 述之遠4呆作基板包含一石英基板。 3 ·如申請專利範圍第1項所述之基板的形成方法,其中上 述之該4呆作基板包含一玻璃基板。 4 ·如申請專利範圍第1項所述之基板的形成方法,其中上第14頁 564527 六、申請專利範圍 述之該黏性光分解介電層包含一離形膜。 5. 如申請專利範圍第1項所述之基板的形成方法,其中上 述之該多層内連線結構係以薄膜電晶體液晶顯示器(TFT-LCD)技術之沈積、微影與蝕刻製程形成。 6. 如申請專利範圍第1項所述之基板的形成方法,其中上 述之該黏性結合膜包含一半固化膜(Semi-Cured Film 7. 如申請專利範圍第1項所述之基板的形成方法,其中上 述之該載台基板包含一印刷電路板。 8. 如申請專利範圍第1項所述之基板的形成方法,其中上 述之該導體包含銲膏(Solder Paste)。 9. 如申請專利範圍第1項所述之基板的形成方法,其中上 述之該導體包含金屬凸塊(Metal Bump)。 1 0 .如申請專利範圍第1項所述之基板的形成方法,其中上 述之該導體包含表面鍵著金屬(Metal Surface Coating 1 1.如申請專利範圍第1項所述之基板的形成方法,其中上564527 六、申請專利範圍 述之該黏性光分解介電層係以紫外線分解。 1 2.如申請專利範圍第1項所述之基板的形成方法,其中上 述之該黏性光分解介電層係以雷射光束分解。 1 3 .如申請專利範圍第1項所述之基板的形成方法,其中上 述之該黏性光分解介電層係以蝕刻法移除。 1 4.如申請專利範圍第1項所述之基板的形成方法,其中上 述之該多層内連線結構中内嵌有至少一被動元件。 15. —種具有多層内連線結構之基板的形成方法,該基板 的形成方法包含: 提供一透光操作基板(Handle Substrate); 形成一黏性光分解介電層於該操作基板上; 形成一多層内連線結構於該黏性光分解介電層上,該 多層内連線結構之表面具有複數個銲墊; 提供一載台基板(Carrier Substrate),該載台基 板設有突出表面之複數個導體; 形成一圖案化之黏性結合膜於該載台基板表面,並暴 露出該載台基板表面之該複數個導體; 藉由銲接分別結合該複數個銲墊與該載台基板上之該 複數個導體,以結合該多層内連線結構與該載台基板; 分解該黏性光分解介電層;第16頁 564527 六、申請專利範圍 移除該操作基板;及 移除該黏性光分解介電層。 1 6 .如申請專利範圍第1 5項所述之基板的形成方法,其中 上述之該操作基板包含一石英基板。 1 7 .如申請專利範圍第1 5項所述之基板的形成方法,其中 上述之該操作基板包含一玻璃基板。 1 8 .如申請專利範圍第1 5項所述之基板的形成方法,其中 上述之該黏性光分解介電層包含一離形膜。 1 9 .如申請專利範圍第1 5項所述之基板的形成方法,其中 上述之該多層内連線結構係以薄膜電晶體液晶顯示器 (TFT-LCD)技術之沈積、微影與蝕刻製程形成。 2 0 .如申請專利範圍第1 5項所述之基板的形成方法,其中 上述之該黏性結合膜包含一半固化膜(Semi-Cured Film 2 1.如申請專利範圍第1 5項所述之基板的形成方法,其中 上述之該載台基板包含一印刷電路板。 2 2 .如申請專利範圍第1 5項所述之基板的形成方法,其中第17頁 564527 六、申請專利範圍 上述之該導體包含銲膏(Solder Paste)。 2 3 .如申請專利範圍第1 5項所述之基板的形成方法,其中 上述之該導體包含金屬凸塊(Metal Bump)。 2 4.如申請專利範圍第1 5項所述之基板的形成方法,其中 上述之該導體包含表面鑛著金屬(Metal Surface Coating) ° 2 5 .如申請專利範圍第1 5項所述之基板的形成方法,其中 上述之該黏性光分解介電層係以紫外線分解。 2 6 .如申請專利範圍第1 5項所述之基板的形成方法,其中 上述之該黏性光分解介電層係以雷射光束分解。 2 7 .如申請專利範圍第1 5項所述之基板的形成方法,其中 上述之該黏性光分解介電層係以蝕刻法移除。 2 8 .如申請專利範圍第1 5項所述之基板的形成方法,其中 上述之該多層内連線結構中内彼有至少一被動元件。第18頁
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW091123873A TW564527B (en) | 2002-10-17 | 2002-10-17 | Hybrid interconnect substrate and method of manufacture thereof |
US10/336,674 US6808643B2 (en) | 2002-10-17 | 2003-01-06 | Hybrid interconnect substrate and method of manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW091123873A TW564527B (en) | 2002-10-17 | 2002-10-17 | Hybrid interconnect substrate and method of manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
TW564527B true TW564527B (en) | 2003-12-01 |
Family
ID=32091999
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW091123873A TW564527B (en) | 2002-10-17 | 2002-10-17 | Hybrid interconnect substrate and method of manufacture thereof |
Country Status (2)
Country | Link |
---|---|
US (1) | US6808643B2 (zh) |
TW (1) | TW564527B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI562275B (en) * | 2014-11-27 | 2016-12-11 | Advance Process Integrate Technology Ltd | Process of forming waferless interposer |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4130158B2 (ja) * | 2003-06-09 | 2008-08-06 | 三洋電機株式会社 | 半導体装置の製造方法、半導体装置 |
TWI240390B (en) * | 2004-12-09 | 2005-09-21 | Phoenix Prec Technology Corp | Semiconductor package structure and method for fabricating the same |
TWI280081B (en) * | 2005-11-08 | 2007-04-21 | Phoenix Prec Technology Corp | Optical component integrated in semiconductor device |
TWI270327B (en) * | 2005-11-10 | 2007-01-01 | Phoenix Prec Technology Corp | Circuit board with optical component embedded therein |
US8779598B2 (en) * | 2011-06-28 | 2014-07-15 | Broadcom Corporation | Method and apparatuses for integrated circuit substrate manufacture |
DE102011116409B3 (de) * | 2011-10-19 | 2013-03-07 | Austriamicrosystems Ag | Verfahren zur Herstellung dünner Halbleiterbauelemente |
US9362143B2 (en) * | 2012-05-14 | 2016-06-07 | Micron Technology, Inc. | Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages |
US9768048B2 (en) | 2013-03-15 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on-package structure |
CN104051411B (zh) | 2013-03-15 | 2018-08-28 | 台湾积体电路制造股份有限公司 | 叠层封装结构 |
EP3373714B1 (en) * | 2017-03-08 | 2023-08-23 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Hybrid component carrier and method for manufacturing the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5480834A (en) * | 1993-12-13 | 1996-01-02 | Micron Communications, Inc. | Process of manufacturing an electrical bonding interconnect having a metal bond pad portion and having a conductive epoxy portion comprising an oxide reducing agent |
US6441473B1 (en) * | 1997-09-12 | 2002-08-27 | Agere Systems Guardian Corp. | Flip chip semiconductor device |
US6462423B1 (en) * | 2000-08-31 | 2002-10-08 | Micron Technology, Inc. | Flip-chip with matched lines and ground plane |
-
2002
- 2002-10-17 TW TW091123873A patent/TW564527B/zh not_active IP Right Cessation
-
2003
- 2003-01-06 US US10/336,674 patent/US6808643B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI562275B (en) * | 2014-11-27 | 2016-12-11 | Advance Process Integrate Technology Ltd | Process of forming waferless interposer |
Also Published As
Publication number | Publication date |
---|---|
US6808643B2 (en) | 2004-10-26 |
US20040074865A1 (en) | 2004-04-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Lau et al. | Fan-out wafer-level packaging for heterogeneous integration | |
TWI221664B (en) | Structure of chip package and process thereof | |
TW451368B (en) | Flip chip assembly of semiconductor IC chips | |
US5485038A (en) | Microelectronic circuit substrate structure including photoimageable epoxy dielectric layers | |
JP5152177B2 (ja) | 導電性バンプとその製造方法および電子部品実装構造体 | |
TW564527B (en) | Hybrid interconnect substrate and method of manufacture thereof | |
US8119449B2 (en) | Method of manufacturing an electronic part mounting structure | |
EP0613333A1 (en) | Mounting/connecting method of an electronic component with patterning electrodes | |
TW200834770A (en) | Electronic component mounting structure and method for manufacturing the same | |
KR20110120218A (ko) | 디바이스를 기판에 실장하는 방법과, 디바이스를 실장하는 기판의 구조 | |
TW200917395A (en) | Semiconductor device and manufacturing method thereof | |
KR20120082773A (ko) | 패턴형성 가능한 접착 조성물, 이를 이용한 반도체 패키지, 및 이의 제조방법 | |
KR20140070929A (ko) | 비 절연성 타입 접착수단과 이를 구비한 표시장치 | |
US20240105893A1 (en) | Substrate, backlight module, and display apparatus | |
KR20120084194A (ko) | 반도체 패키지 제조방법 및 반도체 패키지용 다이 | |
JP2009016377A (ja) | 多層配線板及び多層配線板製造方法 | |
JP2016171133A (ja) | フィルム状回路接続材料及び回路部材の接続構造体の製造方法 | |
CN117276454A (zh) | 一种微型发光芯片键合的方法及芯片键合件 | |
US10600761B2 (en) | Nanoscale interconnect array for stacked dies | |
JP2004079816A (ja) | チップ状電子部品の製造方法及びチップ状電子部品、並びにその製造に用いる疑似ウェーハの製造方法及び疑似ウェーハ、並びに実装構造 | |
CN1180461C (zh) | 复合高密度构装基板与其形成方法 | |
CN114567966B (zh) | 柔性可拉伸电路及其制造方法 | |
TWI305018B (en) | Semiconductor module and method for making same | |
WO2000021135A1 (fr) | Dispositif semi-conducteur et son procede de fabrication | |
US11735529B2 (en) | Side pad anchored by next adjacent via |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MK4A | Expiration of patent term of an invention patent |