552711 _______案號91115106_年月曰 修正_ 五、發明說明（1) 本發明「場效電晶體」旨在提供一可防止電晶體因為 電流或電壓輸入之錯誤而遭擊穿之場效電晶體結構，其主 要係將電晶體閘極接點區隔有一與源極電子流接點相聯結 之電晶體閘極封裝接點，以及另一高阻抗元件的封裝接點 ，並在電晶體閘極接點之高阻抗元件的封裝接點與其中一 電子流接點間聯結有一高阻抗元件，當場效電晶體在與實 際之應用電路相聯結而將電晶體閘極接點之高阻抗元件的 封裝接點與電晶體閘極封裝接點導通後，其高阻抗元件即 可形成一將電晶體閘極接點與電子流接點之間形成保護迴 路，藉以限制高負荷之電流由電子流接點之方向經由電晶 體閘極接點進入場效電晶體中，以防止場效電晶體内部之 薄層遭擊穿者。 如第一圖所示，其係為目前電子電路用於做為電源控 制元件或做為信號控制元件之場效電晶體（A )結構示意圖 ，其中，場效電晶體（A )為三端子元件，其端子之作用主 要係為一用以與實際應用電路中控制信號線路相聯結之電 晶體閘極接點（Ag)，以及分別配合與電子電路之電源線路 相聯結之源極電子流接點（A s )及沒極電子流接點（A d )，其 場效電晶體（A )即由電晶體閘極接點（Ag )之電壓狀態控制 源極電子流接點（As )與汲極電子流接點（Ad)間之通道，進 而達到控制電源或信號ΟΝ/OFF之功能；另外，其場效電晶 體（A )可以如第二圖所示，配合與測試迴路（B )相串接，用 以測試場效電晶體（A)之功能。 然而，由於其場效電晶體（A)主要係利用二氧化矽薄552711 _______ Case No. 91115106_ Revised Year of the Month _ V. Description of the Invention (1) The "Field Effect Transistor" of the present invention aims to provide a field effect transistor that can prevent breakdown of the transistor due to an incorrect current or voltage input. Crystal structure, which mainly separates the transistor gate contact with a transistor gate package contact that is connected to the source electron current contact and another high impedance component package contact. A high-impedance element is connected between the package contact of the high-impedance element of the pole contact and one of the electronic current contacts. When the field effect transistor is connected with the actual application circuit, the high-impedance element of the transistor gate contact is connected. After the package contact and the transistor gate package contact are turned on, the high-impedance component can form a protection circuit between the transistor gate contact and the electronic current contact, thereby limiting the high-load current from being connected by the electron. The point direction enters the field effect transistor through the transistor gate contact to prevent the thin layer inside the field effect transistor from being punctured. As shown in the first figure, it is a schematic diagram of the structure of a field effect transistor (A) in which an electronic circuit is currently used as a power control element or a signal control element, where the field effect transistor (A) is a three-terminal element The function of the terminal is mainly a transistor gate contact (Ag) for connection with the control signal line in the actual application circuit, and a source electron current contact for the connection with the power circuit of the electronic circuit respectively. (A s) and non-electrode current contact (A d), the field effect transistor (A) is controlled by the voltage state of the transistor gate contact (Ag). The channel between the pole electron current contacts (Ad), so as to control the power or signal ON / OFF function. In addition, the field effect transistor (A) can be matched with the test circuit (B) as shown in the second figure. Connected in series to test the function of the field effect transistor (A). However, since its field effect transistor (A) is mainly made of silicon dioxide,
552711 ~~---~~ 五、發明說明（2) 層具有提供元 晶體閘極接點 點（A d)間之絕 因為靜態電荷 化矽薄層崩潰 之無法發揮原 爰是，本 點區隔有一與 點，以及另一 封裝接點與其 抗元件，當場 晶體閘極接點 接點導通後， 裝接點與電子 電流由電子流 晶體中，以防 目的者。 本發明「 接點之高阻抗 微小之間隔配 效電晶體在實 封裝接點與電 制信號線路相 電晶體與控制552711 ~~ --- ~~ V. Description of the invention (2) The layer has to provide elementary crystal gate contacts (A d). It is absolutely impossible for the thin layer of silicon to collapse due to static charge. There is an AND point, and another package contact point and its anti-component. After the on-site crystal gate contact point is turned on, the mounting contact point and the electronic current flow in the electron flow crystal to prevent the target. According to the invention, the high impedance of the contacts and the small interval matching transistor are in effect. The contact between the package and the electrical signal line is the same.
# 一 —丨丄包丁流 ，專層之處理時，常 的電位差，而使二 路徑而使場效電晶 件高輸入阻抗特性的正 (Ag)與源極電子流接點 緣，但在進行二氧化石夕 之累積而建立跨於薄層 並建立經過薄層之導通 有之功能。 發明「場效電晶體」即藉由將電晶體閘極 源極電子流接點相聯結之電晶體閘極封I 咼阻抗元件的封裝接點，並在高阻抗元件、 中一電子流接點相聯結之線路中設有—古的 效電晶體在與實際之應用電路相聯結而將電 之高阻抗元件的封裝接點與電晶體閘極封I 其高阻抗元件即可形成一將高阻抗元件的封 流接點之間形成保護迴路，以限制高負荷< 接點之方向經由電晶體閘極接點進入場效^ 止場效電晶體内部之薄層遭擊穿，為其主要 場效電晶體」之另一目的係將其電晶體閘極 元件的封裝接點與電晶體閘極封裝接點以極 置’而可以B〇ndingPad方式連接，其係在場 際之應用電路相聯結，而需將高阻抗元件的 ”，極封裝接點導通並與應用電路中之控 聯結a夺’可直接由一跨線動作同時構成場效 4吕3虎線路之_ <聯結者。# 一 — 丨 Dingliu Bao, the constant potential difference during the processing of the monolayer, so that the two paths make the positive input (Ag) of the high-effect impedance of the field effect transistor and the source electron current contact edge, but the The accumulation of dioxide dioxide creates a function that spans the thin layer and establishes conduction through the thin layer. Invented the "field effect transistor", which is the package contact of the transistor gate sealed by the transistor gate source electron current contact, and the high-impedance element, the middle one electron current contact In the connected circuit, an ancient effect transistor is connected with the actual application circuit to connect the package contact of the electric high-impedance component with the transistor gate seal. The high-impedance component can form a high-impedance component. A protection loop is formed between the current-sealing contacts of the device to limit the direction of the high load < contact through the transistor gate contact into the field effect ^ stop the thin layer inside the field effect transistor is broken down, its main field The other purpose of the "effect transistor" is to connect the package contact of the transistor gate element and the package contact of the transistor gate with the pole pad, so that they can be connected by BondingPad. It is connected to the application circuit in the field. However, it is necessary to turn on the high-impedance components of the "package" contacts and connect them with the control circuit in the application circuit, which can directly constitute a field effect 4 and 3 tiger circuits by a cross-line action at the same time.
第5頁 552711 案號 91115106 曰 五、發明說明（3) 本發明「場效電晶體」，其整體場效電曰辦之其士力 構如第三圖所示，其中，場效電晶體（n在曰曰體之基本杀 ，其端子之作用主要係為一用以與實p庫用為二端子元件 ^信號線路相聯結之電晶體問極接點（lg)，以及 ^ 笔子電路中之電源相聯結之源極電子流接點 接點（5)，而其場效電晶體（1)即利用二氧化妙 有提供兀件高輸入阻抗特性的正面效應之薄層，用以盖= 電晶體閘極接點（1 g )與源極電子流接 :、 構成 (⑷間之絕緣，再由電晶體閘極接 :: 道，進而達到控制受控元件運作之s (d)間之通 隔有f 其場效電晶體（1)係將電晶體閘極接點（lg)區 元件的封/；一局阻抗元件的封褒接點（lgr)，並在高阻抗 中設有—f接點（lgr)與其中一電子流接點相聯結之線路 η-通路之^阻抗元件（ΐΓ)，圖式中之場效電晶體ΟΜ系為 的封裝接，式，所以其高阻抗元件（ΐΓ)係設於高阻抗元件 ，以在逸4_Ugr)與源極電子流接點（ls)相聯結之線路中 ’係分 ^亍彡琢效電晶體（1)之功’則試時’如第四圖所示 阻抗元77 Μ由場效電晶體〇)之電晶體閘極接點（1 g)中的高 回:^B)的封裝接點Ogr)與由電路開關SW3所構成之測試 體（1)内1串接，而可由構測試迴路（B)用以測試場效電晶 r )並部之回路是否正常，且在測試過程中高阻抗元件 不會影響測試電流之通過；當然，其整體測試作業 552711 --——^ 91115106, 五、發明說明（4) 亦可做高阻抗元件（1〇 路（B)以外另設有一 A “ 0 ，如圖所示，其可在測試迴 與高阻抗元件的封裝接C，SW2所構成之測試迴路（C) 測試高阻抗元件（丨r )之^ gr)，而可由測試迴路（C )用以 SW1所構成之測試迴1能’·抑曰或是，另夕卜由-電路開關 聯結，而可由測試迴路亩、垃閘極封裝接點（1 gm)相 之薄層功能之測試。 ）直接用以對場效電晶體（1 )内部 結，而如第=圖/所干六電日日體（1 )在與實際之應用電路相聯 件的封裝：二，二 其高阻抗元件（lr)即可阳體閘極封裝接點（Um)導通後， 極電子流接點（ls)(電子—將閘極接點…)與源 ::免實際應用控制電路 ♦由源極電子流接點（1y貝鼓^^接而產生之高負荷電 閘極接點（丨） /;,l接點）之方向經由電晶體 ⑴内部之薄 構，亦可隨場效電晶體 ，、整體场效電晶體（1)之架 同，圖式中之實施；：現之：通道或p-通道之形式不 通道之形式呈現時，1古係為本叙明之場效電晶體（〇以η-接點（lg)之高 二间阻抗兀件（lr)即設於電晶體閘極 點(1二…封裝接點(1以)與源極電子流接 随枋又从其場效電晶體（1)並將電晶體閘極接點η k古 抗兀件的封裝接點（1 ) Ί位接點（Ig)之同 極微小之間隔配晋 gr)與電日日體閘極封裝接點（lgm)以 之間…，以當場效電晶體⑴在與實際之應用 552711 _案號 91115106_年月日__ 五、發明說明（5) 電路相聯結，而需將電晶體閘極接點（1 r )之高阻抗元件接 點（1 gr )與源極電子流接點接點（1 gm )導通，以在與外部應 用電路中之控制信號線路相聯結時，即可直接由一跨線動 作同時構成場效電晶體與控制信號線路之聯結，可在整體 應用電路之建構過程中，大幅縮減場效電晶體組配所需之 工時、工序，進而提升其產能。 本發明「場效電晶體」措由在電晶體閘極接點之南阻 抗元件的封裝接點與其中一電子流接點之線路間設有一高 阻抗元件，當其場效電晶體在與實際之應用電路相聯結而 將高阻抗元件的封裝接點與電晶體閘極接點導通後，其高 阻抗元件即可形成一保護迴路，以限制高負荷之電壓或電 流由電子流接點之方向經由電晶體閘極接點進入場效電晶 體中，以防止場效電晶體内部之薄層遭擊穿，提供了另一 較佳可行之場效電晶體結構，爰依法提呈發明專利之申請Page 5 552711 Case No. 91115106 Five. Description of the invention (3) The "field effect transistor" of the present invention is shown in the third figure in the overall field effect transistor structure, of which the field effect transistor ( The basic function of n in the body is to use the terminals of a transistor to connect to the real p bank as a two-terminal element. The signal contact (lg) of the transistor is connected to the circuit of the pen. The source electron current contact point (5) connected to the power source, and its field effect transistor (1) is a thin layer that uses the dioxide to provide a positive effect of the high input impedance characteristics of the component to cover = The transistor gate contact (1 g) is connected to the source electrons, and constitutes (the insulation between the electrodes, and then the transistor gate is connected to the: channel, thereby achieving the interval between s (d) that controls the operation of the controlled component. There are f field-effect transistors (1) that seal the components of the transistor gate contact (lg) area of the transistor; the sealed contact (lgr) of a local impedance component, and are provided in high impedance— f contact (lgr) and one of the electronic current contacts are connected to the line η-path of the ^ impedance element (ΐΓ), the field effect transistor OM in the figure is It is packaged, so its high-impedance element (ΐΓ) is set on the high-impedance element, so that it can be used in the circuit that is connected to the source current contact (ls). (1) When the work is “tested,” as shown in the fourth figure, the impedance element 77 M is composed of field-effect transistor 0), the high return in the gate contact (1 g) of the transistor: ^ B) package contact Ogr) is connected in series with 1 in the test body (1) formed by the circuit switch SW3, and can be used to construct a test circuit (B) to test whether the circuit of the field effect transistor is normal and has high impedance during the test The component will not affect the passing of the test current; of course, the overall test operation 552711 ------ ^ 91115106, V. Description of the invention (4) It can also be used as a high-impedance component (other than 10 (B), there is an A "0 As shown in the figure, it can be connected to the high-impedance component package C and SW2 on the test back (C) to test the high-impedance component (丨 r), and can be used by the test circuit (C). The test composed of SW1 can return to “1” or “Yes”, or it is connected by a-circuit switch, and can be packaged by a test circuit and a gate. Point (1 gm) phase of the thin layer function test.) Directly used to field-effect transistor (1) internal junction, and as shown in the figure / dried Liudian solar body (1) in the actual application circuit Encapsulation of the associated parts: Second, the high-impedance component (lr) can be used to turn on the anode gate package contact (Um), and the pole electron current contact (ls) (electronics-connect the gate contact ...) with Source :: Application-free control circuit ♦ The direction of the high-load electric gate contact (丨) / ;, l contact generated by the source electron current contact (1y shell ^^ connection) passes through the transistor The thin structure can also follow the structure of the field effect transistor and the overall field effect transistor (1), and is implemented in the diagram; now: when the channel or p-channel is not in the form of a channel, it is ancient This is the field effect transistor (0 to η-contact (lg) of the two high-impedance element (lr) that is set at the gate of the transistor (1 2 ... package contact (1 to) and the source electron The current connection follows from its field effect transistor (1) and the transistor gate contact η k of the packaged contact (1) of the ancient resistive element is matched with the same minute interval of the bit contact (Ig). gr) and electric day Between the body gate package contact (lgm) and the field effect transistor 电, and the actual application 552711 _ case number 91115106_ year month day __ V. Description of the invention (5) The circuit is connected and requires When the high-impedance element contact (1 gr) of the transistor gate contact (1 r) and the source electron current contact (1 gm) are conducted, when connecting with the control signal line in the external application circuit It can directly form a connection between the field effect transistor and the control signal line by a cross-line action at the same time. During the construction of the overall application circuit, the man-hours and processes required for the field effect transistor assembly can be greatly reduced, thereby improving Its capacity. The field-effect transistor of the present invention is provided with a high-impedance element between the package contact of the south-resistance element of the transistor gate contact and one of the electronic current contacts. When the field-effect transistor is in contact with the actual After the application circuit is connected and the package contact of the high-impedance element is connected with the transistor gate contact, the high-impedance element can form a protection circuit to limit the direction of the high-load voltage or current from the electronic current contact. Enter the field effect transistor through the transistor gate contact to prevent breakdown of the thin layer inside the field effect transistor, and provide another better and feasible field effect transistor structure. The invention patent application was filed according to law
第8頁 552711 ___案號91115106_年月日_iMz__ 圖式簡單說明 第一圖係為一般習用場效電晶體之結構示意圖。 第二圖係為習用場效電晶體之測試狀態示意圖。 第三圖係為本發明之場效電晶體之結構示意圖。 第四圖係為本發明中場效電晶體之測試狀態示意圖。 (A) 場效電晶體 (Ad)汲極電子流接點 (Ag)電晶體閘極接點 (A s )源極電子流接點 (At)測試接點 (B) 、（C)、（D)測試回路 (1 ) 場效電晶體 (1 d)汲極電子流接點 (1 g)電晶體閘極接點 (lgr)高阻抗元件的封裝接點 (lgm)電晶體閘極封裝接點 (1 r )高阻抗元件 (1 s )源極電子流接點Page 8 552711 ___Case No. 91115106_year month_iMz__ Brief description of the diagram The first diagram is a schematic diagram of the structure of a conventional conventional field effect transistor. The second figure is a schematic diagram of the test state of a conventional field effect transistor. The third figure is a schematic diagram of the structure of a field effect transistor of the present invention. The fourth figure is a schematic diagram of a test state of a field effect transistor in the present invention. (A) Field effect transistor (Ad) Drain electron current contact (Ag) Transistor gate contact (A s) Source electron current contact (At) Test contact (B), (C), ( D) Test circuit (1) Field-effect transistor (1 d) Drain electron current contact (1 g) Transistor gate contact (lgr) Package contact (lgm) of high impedance element Transistor gate package Point (1 r) high impedance element (1 s) source electron current contact