JPS58158953A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPS58158953A
JPS58158953A JP4080982A JP4080982A JPS58158953A JP S58158953 A JPS58158953 A JP S58158953A JP 4080982 A JP4080982 A JP 4080982A JP 4080982 A JP4080982 A JP 4080982A JP S58158953 A JPS58158953 A JP S58158953A
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
electrodes
gate
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4080982A
Other languages
Japanese (ja)
Inventor
Koji Takebe
建部 光司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4080982A priority Critical patent/JPS58158953A/en
Publication of JPS58158953A publication Critical patent/JPS58158953A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To prevent the electrostatic damage of a semiconductor device by sealing the device with resin having electrical conductivity of the degree which does not affect the influence of the operation of the device. CONSTITUTION:Electrodes S, D are attached to N type source and drain layers 2 of a P type Si substrate 1, gate electrodes G1, G2 are formed on a gate oxidized film 3, and a P type layer 5 in an N type layer 4 is coupled to the electrodes S, G1. Carbon powder is mixed with epoxy resin to provide suitable conductivity in resin 6, and the resin 6 is used to seal. Parallel resistors R1, R2 are inserted to the protective diodes D1, D2 between the source and the gate, the resin can become the leakage pass of static electricity, and when the resistance between the electrodes is selected to approx. 5MOMEGA by regulating the mixed amount, the influence to the operation of an FET is reduced, and in case of high frequency FET, the leakage is approx. 1muA. According to this configuration, the static damage resistance for the FET can be improved.

Description

【発明の詳細な説明】 本発明は樹脂刺止半導体装置罠関し、王に絶縁ゲート電
界効果トランジスタ(MOSFET)の静電破壊防止技
術を対象とする。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resin-sealed semiconductor device trap, and is particularly directed to a technique for preventing electrostatic breakdown of an insulated gate field effect transistor (MOSFET).

高周波増幅用のMOSFETにおいては静電破壊防止用
の保膿ダイオードが同じ基板上に内蔵されているがそれ
にもかかわらずゲートの静電破壊が起り易い。特に高い
胸波数を使う双極形MO8FETでは保腰ダイオードの
静電容量が大きくインピーダンスのマツチングがとれな
いため遅れを生じることが多い。このため樹脂封止され
たMOSFETを導電性ケースに入れて静電気がチ々−
ジされないようにしているが、測定時や機器への組み込
み時に生じる静電破壊音防止することは困難であったう 本発明は上記した問題を解消するためになされたもので
、その目的は静電破壊耐量を大きくした信頼性のある樹
脂刺止半導体装置の提供にある。
Although MOSFETs for high frequency amplification have a built-in impurity diode for preventing electrostatic damage on the same substrate, electrostatic damage to the gate is still likely to occur. In particular, in the case of a bipolar MO8FET that uses a high chest frequency, delays often occur because the capacitance of the Kogoshi diode is large and impedance matching cannot be achieved. For this reason, static electricity is generated by placing a resin-sealed MOSFET in a conductive case.
However, it is difficult to prevent electrostatic breakdown noise that occurs during measurement or when installed into equipment.The present invention was made to solve the above-mentioned problems, and its purpose is to An object of the present invention is to provide a reliable resin-punched semiconductor device with increased electrical breakdown resistance.

以下本発明を実施例にそって具体的に説明する。The present invention will be specifically described below with reference to Examples.

第1図は本発明を高周波増幅用の双極形MO8FETに
適用した場合の一実施例を示す原理的構造断面図である
FIG. 1 is a sectional view showing the principle structure of an embodiment in which the present invention is applied to a bipolar MO8FET for high frequency amplification.

同図において、lは例えばP型Si牛導体基板、2はN
型拡散層でMOSFETのソース、ドレイン電極S、 
 Dが接続され、3はケート絶縁膜でこの上にゲート1
1極G、、G、が設けられる。4゜5はPN接合をつ(
るN型及びP型拡散層で、2つのP型拡散層5をソース
SとゲートG、にそれぞれ接続することによってゲート
保睦タイオードを構成する。なお第2ゲートG、の保睦
夕゛イオードは同図では省略されている。ソース、ドレ
イン及びゲートの各電&はAuワイヤ等を介して図示さ
れないリード端子に接続される。6は樹脂モールド体で
リード端子の一部は樹脂の外部に突出するようになる。
In the same figure, l is, for example, a P-type Si conductor board, and 2 is an N
Source and drain electrodes S of MOSFET in the type diffusion layer,
D is connected, and 3 is a gate insulating film on which gate 1 is connected.
One pole G, ,G, is provided. 4゜5 connects the PN junction (
A gate protection diode is constructed by connecting the two P-type diffusion layers 5 to the source S and the gate G, respectively. Note that the protection diode of the second gate G is omitted in the figure. The sources, drains, and gates are connected to lead terminals (not shown) via Au wires or the like. 6 is a resin molded body, and a part of the lead terminal comes to protrude outside the resin.

上記樹脂モールド体はエポキシ糸樹脂等の樹脂材料にカ
ーボン(C)粉床等を混入して適当な導電性をもたせた
ものを使用する。この導電性をもった樹脂はそれによる
リーク電流によって内部のMQSFETの動作が影響さ
れることな(、しかもそれが静電破壊防止に効果のある
導電率をもつものを選ぶものである。例えば、樹脂モー
ルド体で刺辻された電極間抵抗が5J’)程度であるこ
とが最ものぞましい。
The resin molded body is made of a resin material such as epoxy thread resin mixed with a bed of carbon (C) powder or the like to impart appropriate conductivity. This conductive resin is selected so that the operation of the internal MQSFET is not affected by the leakage current caused by it (and has a conductivity that is effective in preventing electrostatic damage. For example, It is most desirable that the resistance between the electrodes pierced by the resin molded body be about 5 J').

以上実施例で述べた本発明によれば、導電性を有する樹
脂モールド体で封止することにより、第2図に示すよう
にソース・ゲート掴の保−タイオードD、、I)、に並
列抵抗R,,R,が挿入されたと同じことになり、樹脂
モールド体が静電気のリークバスとなってMQSFET
に印加される電圧が低T″fる。例えば5MΩ程度では
MQSFETの動作に及ぼす影響は小さく、高周波MO
8FE′rの場合1〜μA程度しかリークしないうこの
ことから本発明によってMQSFETの静電破壊に対す
る耐性が向上し、しかもコスト的には全く変ることなく
工程管理上の効果が上る。
According to the present invention described in the above embodiments, by sealing with a conductive resin mold body, a parallel resistance is applied to the source/gate holding diode D, I) as shown in FIG. It is the same as if R,,R, were inserted, and the resin mold body becomes a static electricity leak bus and the MQSFET
For example, if the voltage applied to the
In the case of 8FE'r, since only about 1 to .mu.A leaks, the present invention improves the resistance of the MQSFET to electrostatic damage, and also improves process control effects without changing the cost at all.

本発明の説明にあたって双極形MO8FETを例に掲げ
たが、本発明はこれ以外のパワーMO8FET、高周波
増幅用バイポーラトランジスタ。
In explaining the present invention, a bipolar MO8FET was used as an example, but the present invention relates to power MO8FETs other than this, and bipolar transistors for high frequency amplification.

バイポーラ・MQSIC等にも同様に応用することがで
きる。
It can be similarly applied to bipolar/MQSIC, etc.

【図面の簡単な説明】[Brief explanation of drawings]

事 第1図は本発明による樹脂封止双極形MO8FETのI
IA理的構造を示す断面図、第2図は第1図で示したM
QSFETと等価の回路図である。 l・・・半導体基板、2・・・拡散層、3・・・ゲート
絶縁膜、4,5・・・拡散層、6・・・樹脂モールド体
Figure 1 shows the I of the resin-sealed bipolar MO8FET according to the present invention.
A sectional view showing the IA physical structure, Figure 2 is the M shown in Figure 1.
It is a circuit diagram equivalent to QSFET. 1... Semiconductor substrate, 2... Diffusion layer, 3... Gate insulating film, 4, 5... Diffusion layer, 6... Resin mold body.

Claims (1)

【特許請求の範囲】 1、樹脂モールド体により刺止された半導体装置におい
て、樹脂モールド体に導電性材料を使用し。 この導電性樹脂はそれによるリーク1m流により半導体
装置の動作が影響されることな(、かつ静電破壊防止の
効果がある導電1軍を!fることを%徴とする機脂刺止
半導体装徽。 2、上記半導体装置は絶縁ゲート電界効果トランジスタ
とそのゲート保麹ター4オートとを当むものである咎許
―求の範囲第1項に記載の樹脂刺止半導体装置。 3、上記導電性樹脂による電極間抵抗は5MΩ程度であ
る特許請求の範囲第2項に記載の樹脂刺止半導体装置。 。
[Claims] 1. In a semiconductor device stuck with a resin mold body, a conductive material is used for the resin mold body. This conductive resin is designed to prevent the operation of semiconductor devices from being affected by leakage of 1 meter flow (and to provide conductivity that is effective in preventing electrostatic damage). Mounting. 2. The resin-embedded semiconductor device according to item 1, wherein the semiconductor device is an insulated gate field effect transistor and its gate protector. The resin-stamped semiconductor device according to claim 2, wherein the inter-electrode resistance is about 5 MΩ.
JP4080982A 1982-03-17 1982-03-17 Resin-sealed semiconductor device Pending JPS58158953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4080982A JPS58158953A (en) 1982-03-17 1982-03-17 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4080982A JPS58158953A (en) 1982-03-17 1982-03-17 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS58158953A true JPS58158953A (en) 1983-09-21

Family

ID=12590964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4080982A Pending JPS58158953A (en) 1982-03-17 1982-03-17 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS58158953A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0265290A2 (en) * 1986-10-24 1988-04-27 Xerox Corporation Electrostatic discharge protection network for large area transducer arrays
FR2645680A1 (en) * 1989-04-07 1990-10-12 Thomson Microelectronics Sa Sg ENCAPSULATION OF ELECTRONIC MODULES AND METHOD OF MANUFACTURE

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0265290A2 (en) * 1986-10-24 1988-04-27 Xerox Corporation Electrostatic discharge protection network for large area transducer arrays
FR2645680A1 (en) * 1989-04-07 1990-10-12 Thomson Microelectronics Sa Sg ENCAPSULATION OF ELECTRONIC MODULES AND METHOD OF MANUFACTURE
US5041395A (en) * 1989-04-07 1991-08-20 Sgs-Thomson Microelectronics S.A. Method of encapsulating an integrated circuit using a punched metal grid attached to a perforated dielectric strip

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