TW494564B - Electrostatic discharge protection circuit - Google Patents

Abstract

A kind of electrostatic discharge (ESD) protection circuit, which is suitably used for the bonding pad of input/output circuit that tolerates high voltage, includes the following devices: the first switch, which is connected with the bonding pad and conducts to output electrostatic discharge current when the voltage value of bonding pad reaches a determined electric potential; the second switch, which is connected with the first reference level and is provided with a control electrode; the third switch, which is connected between the second switch and the second reference level; and an NMOS transistor disposed between the first reference level and the second reference level, in which the NMOS transistor is provided with a drain that is connected with the first reference level and is doped with another P-type impurity. When receiving the electrostatic discharge current, the PN junction voltage at the drain position of the NMOS transistor is broken down to release the electrostatic discharge current.

Description

4 ^ 4 ^ 04 V. Description of the invention (1) ---------- The present invention relates to an electrostatic discharge protection circuit. The detailed description is about-a kind of 3V / 5V resistant In the input / output circuit, an electrostatic discharge clamping circuit in which an impurity-doped electrostatic discharge clamping element is disposed between a power line and a ground line. ^ Electrostatic Discharge (ESD) is commonly used in the measurement, assembly, installation and use of integrated circuits. It may cause damage to integrated circuits and indirectly affect the function of electronic systems. However, 'The most common reason for the formation of ESD stress is the following three pepper types * (1) Human body model: human military standard model: US Military Standard 883 Method 30 15 · 6 (MIL-STD-883, Method 3015 · 6) The following defined model represents the ESD stress caused by the static electricity of the human body when it contacts the pins of the integrated circuit. (2) machine model ·· The static electricity of the machine contacts the integrated circuit The ESD stress caused by the pin is the measurement method defined by the current industry standard EIAJ-IC-121 method 20. (3) Charge device model: The integrated circuit with the charge has been subsequently In the process of contacting grounded conductive materials, an ESD pulse path is formed on the integrated circuit. Most of the ESD protection circuits mentioned are used to protect human body mode (HBM) or machine discharge mode ( mac Hine mode (MM) electrostatic discharge. Basically, the charge of this type of electrostatic discharge or MM _ comes from the outside of the integrated circuit (1C) and passes through a pin of the IC (pi η) enter the IC and then flow out I c through another pin. In order to prevent damage to the IC caused by this type of ESD ', the ESD protection circuit is laid out in I c

0503-6282TW; TSMC2001-0088; ROBERT.ptd page 4 494564 V. Description of the invention (2) ------- All are designed near the bonding pad, so that the ESD power is bypassed nearby. machine. Refer to Figure 丨, which shows a conventional protection circuit for high-voltage output / input circuits. As shown in U-three-volt / 5-volt-proof I / O circuit, the PMOS transistor Mpl of the output buffer 10 is set in a floating-type ~ well (not shown) in. In addition, the level of voltage output by the bonding pad 12 during normal operation is 0 to 5V. In order to prevent the 5 volts output by the bonding pad 12 from generating excessive stress on the NMOS of the stage output buffer 10, the NMOS part in the rear stage output buffer 10 is stacked with NMOS transistors such as ^ and "" Structure. The gate of the NMOS transistor Mnla is biased at Vdd (33V), and the gate of the NMOS transistor Mnlb is controlled by the output buffer 14 of the previous stage. In this way, when the external signal is between 0 and 5 volts, it can be ensured that the cross-over voltage of the gate oxide layers of the NMOS transistor M ^ ila and Mnlb will not be shifted by 3.3 volts to avoid being caused by galvanic stress. Reliability issues. In addition, the source of the Qs transistor Mnlb is connected to the input / output Vss power line, and the power line ν⑽ and the ground line

There is an inter-power ESD clamping element 16 between Vss, which contains a transistor core? And resistor R. Referring to Fig. 2, Fig. 2 is a cross-sectional view showing the output buffer 10 of the rear stage and the ESD clamping element 16 between the power sources in the first diagram. In order to protect the damage caused by the IMB / ESD event to Ic, the conventional technique is usually doped with a p-type impurity 18, such as the side (B), at the junction of the NMOS transistor Mnla near __12. The breakdown voltage of the PN junction here. Therefore, when the joint 塾 12 suddenly receives a large amount of electrostatic stress, the NMOS transistor and its pole will collapse in advance and release the electrostatic discharge current to ground.

4 ^ 4!) 64 V. Description of the invention (3) ^ To prevent the internal circuit from being damaged by electrostatic stress, which will cause reliability problems. On the other hand, the “method used in the above-mentioned conventional technology will increase the parasitic capacitance of the NMOS transistor Mn la”, which will cause a delay in the internal circuit of the output buffer of the subsequent stage and reduce the operating efficiency of the circuit elements. In order to solve the above problems, the main purpose of the present invention is to provide an electrostatic discharge protection circuit. In a 3 volt / 5 volt output / input circuit, an electrostatic discharge doped with p-type impurities is clamped to the element. It is arranged between the power supply line and the ground line, so that the internal circuit of the output buffer of the subsequent stage will not cause the circuit operation efficiency to deteriorate due to the parasitic capacitance effect caused by doping the P-type impurity. In order to achieve the above object, the present invention proposes an electrostatic discharge protection circuit) a bonding pad suitable for an output / input circuit withstanding high voltage, including the following components. The first is a first switch coupled to the bonding pad. When the voltage value of the bonding pad reaches a predetermined potential, it turns on and outputs an electrostatic discharge current. The second switch coupled to the first level has a control electrode. A third switch that is consumed between the second switch and the second level, and an NMOS transistor that is disposed between the first and second levels, has a drain that is connected to the first level, This anode is doped with another P-type impurity. When an electrostatic discharge current is received, the junction voltage at the drain of the NMOS transistor collapses to release the static electric current. Brief description of the drawings: In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible,

494564 V. Description of the invention (4) ^ Special mention of the invention-the preferred embodiment, and in conjunction with the attached drawings, detailed description as illustrated: Figure 1 shows the traditional ESD protection circuit. Figure 2 shows the first! In the figure, the post-stage output buffer 10 is a cross-sectional view of the ESD clamping element 6. ", Fig. 3 is a sectional view showing the electrostatic discharge Baoguman circuit according to the embodiment of the present invention. Fig. 4 is a sectional view showing the "back stage output buffer 2 0" and the electric ESD pushing element 26 in Fig. 3. . Inter-source symbol description: 10, 20 ~ back stage output buffer 1 2 '2 2 ~ bonding pad 14, 24 ~ front stage output buffer 16, 26 ~ power source ESD clamping element 18, 28 ~ P type impurities Mpl, Mpll ~ PMOS transistor Mnla, Mnlb, Mn2, Mnlla

Mnllb, Mnl2 to NMOS transistor R to resistor VDD to power line Vss to ground

0503-6282TW; TSMC2001-0088; ROBERT.ptd Page 7 494564 V. Description of the invention (5) " ------ 1 Example: Refer to FIG. 3, which shows a diagram according to an embodiment of the present invention. Regarding the static electricity, the electrical protection compliance circuit is applied to an output / input circuit that is subject to the South voltage. 3 volt / 5 volt tolerant output / input circuit as shown in Figure 3. The PM0S transistor Mpll of the rear output buffer 20 is set in a floating type well (not shown). In addition, the voltage level input by the bonding pad 22 during normal operation is 0 to 5V. In order to avoid that the 5 volts = voltage output by the bonding pad 22 exerts the same stress on the gate of the transistor in the output buffer 20 of the subsequent stage, the NM0s part in the output buffer 20 of the subsequent stage is closed. The triode core 113 and the core 1113 are stacked. Here, the gate of the transistor M < nlia is biased at Vdd (3.3V), and the gate of the NMOS transistor Mnllb is controlled by the high-level output buffer 24. Therefore, when the signal input to the bonding pad 22 is between 0 and 5 volts, it can be ensured that the cross-over voltage of the gate oxide layer of the NM0s transistor and the transistor Mnl lb will not exceed 3.3V, to avoid Reliability problems caused by high voltage stress. In addition, the source of the NMMOS transistor MnUb is connected to the ground line vss the power line, and there is an inter-power ESD clamping element 26 between the power line v⑽ and the ground line L, including NM〇s transistor core 12 and resistor R. Refer to Fig. 4, which is a cross-sectional view of Fig. 3, the output buffer 20 at the rear stage, and the ESD clamping element 26 between the power sources. To protect HMB / MM · ESD One thing that may cause damage to the IC and consider the operating speed of the internal output buffer 2 〇 The internal operating speed of the internal components' in the embodiment of the present invention between the power supply ESI) clamping element 26 NMOS transistor Mnl2 drain and p-type substrate ( p-Sub) junctions are doped with P-type impurities 28 'such as butterfly (B) to reduce the pN junctions here

494564 V. The breakdown voltage of invention description (6). Therefore, when the bonding pad 22 suddenly receives a large amount of electrostatic discharge current, a relatively high voltage will be coupled to the parasitic capacitance between the drain and gate of the PMOS transistors Mp 11 and Mpl2, and make the PMS current The crystals Mpl 1 and Mpl 2 are turned on. Therefore, a large amount of static discharge current received by the bonding pad 22 flows to the power supply line VDD through the PMOS transistors Mpll and Mpl2, respectively, and flows to the ESD clamping device 26 between the power supplies through the power supply line vDD. As described above, P-type impurities 28 have been doped below the junction between the drain of the NMOS transistor Mnl2 of the ESD clamp element 26 between the power sources and the P-substrate (P-Sub), so the breakdown voltage here is lower, so NMOS Under the conditions of ESD stress, the PN junction of the transistor Mη 1 2 can easily collapse the voltage and release the electrostatic discharge current to the ground point, so as to avoid the internal circuit from being damaged by electrostatic stress' and thus cause reliability problems. . According to the embodiment of the present invention, the 3 volt / 5 volt tolerant I / O circuit can effectively avoid the post-stage output buffer because the electrostatic discharge clamping element between the power line and the ground line is doped with P-type impurities. The internal circuit does not cause the circuit operation performance to deteriorate due to the additional parasitic capacitance effect caused by doping P-type impurities, and can effectively externalize the electrostatic discharge circuit generated by the human discharge mode ΗBM or the machine discharge mode, which improves the Reliability of the circuit. Mt 2 = The above is disclosed in the preferred embodiment, but it is not intended to limit it; any person skilled in the art will not depart from the scope of protection of the present invention as defined by the scope of the attached patent application.

Claims (1)

494564 6 Application patent scope 12: A kind of electrostatic discharge protection circuit, suitable for a joint, a first switch, coupled to the above-mentioned bonding pad, if the "m "" is turned on and output; Zhidian Yiqiaoguan has a control pole, which is coupled to the first level. The first and third switches are lightly connected between the second switch and the second level. The electric discharge clamp element # 'is coupled to In the above, between the current ΐ =; =? Level, when the above static is received, 2 of the above = please refer to the electrostatic discharge protection circuit described in item 1 of the patent scope, one switch, the second switch and the third switch are M0S Transistor. Straight to the middle, t 请 Please refer to the electrostatic discharge protection circuit described in the second item of the patent scope. Αφ4. The electrostatic discharge protection circuit described in item 3 of the patent application, wherein the second switch and the third switch are NMOS transistors. Basin 5 · The electrostatic discharge protection circuit as described in item 4 of the patent scope, ^ = The electrostatic discharge clamping element described above is a 0 05 transistor, which is coupled to the upper electrode and the upper electrode, and the above The drain of the electrostatic discharge device is additionally doped with P-type impurities. The other 6 · The electrostatic discharge protection circuit as described in item 5 of the scope of patent application, wherein the p-type impurity is boron (B) ion. 7. The electrostatic discharge protection circuit according to item 1 of the scope of patent application, wherein the first level is the level of the power line. ROBERT, ptd page 10 VI Application scope of patents 8 · As for the electrostatic discharge protection circuit described in the above-mentioned item No. 1 of the above-mentioned patent application, one of k must be at the ground level. 9 · According to the electrostatic discharge protection circuit described in item 1 of the patent application Fan Didi w douzhong Shangren enclosing, the above-mentioned bonding pads at the right ^ ^ value are higher than the high level output when the first level is above Signal potential input and output 1 type of electrostatic discharge protection circuit, suitable for bonding pads of high-voltage input and output circuits, including: i π ▼ 刖 Wishin, Gui Gui—Open 5 'connected to the above joint, when the above joint When the electric power is at a certain potential, it turns on and outputs the electrostatic discharge current;-ask the j switch, which is coupled to the first switch and the bonding pad, and the first sweat switch has a control electrode, which is coupled to the first position. A second switch coupled between the second switch and the second level; and an NMOS transistor coupled to the first switch and set between the first and second levels In the meantime, the NMOS transistor has a drain coupled to the first level, and the drain is additionally doped with a p-type impurity. When the NMOS transistor receives the electrostatic discharge current, the switch is closed. Voltage collapse at the PN junction of the transistor . 11 · The electrostatic discharge protection circuit according to item 丨 0 of the scope of the patent application, wherein the first switch, the second switch, and the third switch are MOS electric crystals. 1 2 · The electrostatic discharge protection circuit according to item 11 of the scope of patent application, wherein the first switch is a PMOS transistor. 1 3 · Electrostatic discharge protection as described in item 12 of the scope of patent application 0503-6282TW; TSMC2001-0088; ROBERT.ptd page 11 6. Scope of patent application, in which the second switch and the third switch are transistors. 14. Please refer to item 13 of the patent scope for electrostatic discharge guarantee, such as towels, where the p-type impurity is boron (B) ion. 1 5 · The electrostatic discharge protection power as described in item 1 Q of the scope of patent application, wherein the first level is the level of the power cord. 16 · The electrostatic discharge protection device as described in item 10 of the patent application range, wherein the second level is the ground level. 17. The electrostatic discharge protection potential s1 as described in item 10 of the scope of the patent application, the% value of the high level shovel that is output when it is set to normal operation is two above the first level. The Road to Dryness Road Road Road Road Road 0503-6282TW; TSMC2001-0088; ROBERT.ptd Page 12