425687 五、發明說明（1) 本發明係有關於一種輸出/入驅動電路，特別有關於 一種具有靜電保護及驅動功能之積體電路，藉由在—〇pen drain之輸出/入驅動電路中增加一pad-to-Vdd之放電路徑 以增強其靜電保護功能。 在靜電保護電路中，直接的放電路徑可以提升靜電保 護能力。一般來說，接合塾至Vdd(pad-to-Vdd)及接合塾 至Vss(pad-to-Vss)之放電路徑均由專用之靜電件 來建立。這些靜電保護元件可以是場效氧化 元件、薄膜氧化（thin oxide)元件或其他特殊元件。 另外’輸出/入驅動電路由於其面積大、驅動力 所以為了節省面積及減低輸出電容’除了將其做為驅^雷’ 路外’通常也用來做為靜電保護電路。圖〗顯示了常用之一 pul卜up & pul 1 down驅動電路1〇，用來保護内部電路12 不受靜電之襲擊’包括了電晶體〗3、14、阻抗r及—靜電 保護元件]5。電晶體13、14共同連接至一接合墊u，且且 另一端分別連接至vdd及vss。電晶體13及14在正常之ς 下分別提供兩個相反電流方向之路徑，同時也可以在接人 塾接文靜電襲擊時，將靜電分別導出至Vdd及Vss。: 圖1中之驅動電路10中，自然地具備了接合墊至 及接合塾至Vss(pad-to-Vss)之放電路徑。 T,'' !*tS3) =2顯示了一種open drain驅動電路“及其 電路21 1以保護内部電路12不受靜電之襲擊 保:蔓 圖1相同之元件使用相同之符號表示以方 - drain驅動電路22包括—電晶體25，其沒極連接至 4 2 56 87，. 五、發明說明¢2) 源極連接至V s s、而閘極則接收一輪入信號S。靜電保護電 路21則具有兩個場效氧化電晶體23、24，及一阻抗R。從 i 圖2中可以看出，由於open drain驅動電路22中僅使用一 個電晶體2 5提供電流路徑，所以在靜電襲擊時，驅動電路 2 2無法像圖1中之驅動電路1 〇直接提供了接合墊至 Vdd(pad-to-Vdd)之放電路徑，而僅具備接合塾至 Vss(pad-to-Vss)之放電路徑’造成其靜電保護能力不 足。因此’在使用open dra i η驅動電路時通常必需額外加 ' 入一靜電保護電路21'以建立完整之放電路徑。然而，靜I 電保護電路21之增加，會佔用較大之佈局面積並造成輸出1 電容加大的問題。 因此，為了能在open drai η驅動電路中建立接合墊至 Vdd(pad-to-Vdd)之放電路徑，也同時避免佈局面積及輸 出電容的增加’本發明提供了 一種具有靜電保護功能之驅 動器積體電路’包括：一基底，連接一第一電位；一驅動 電路’形成於基底上’至少包括一電晶體，形成於基底 上’上述電晶體之汲極區、源極區與閘極層分別連接至一 接合塾、第一電位及一輸入信號；一第一摻雜區，形成於 基底上’絕緣地設置於上述電晶體之没極區旁且連接至一 第三電位’第一摻雜區與電晶體之源極與汲極區具有同型 之#雜離子。 其中’更包括一第二摻雜區，形成於基底上，絕緣地 設置於電晶體源極區旁且連接至第三電位，第二摻雜區與 電晶體之源極與汲極區具有同型之摻雜離子，且第一摻雜425687 V. Description of the invention (1) The present invention relates to an output / input driving circuit, and in particular to an integrated circuit with electrostatic protection and driving functions. By adding to the output / input driving circuit of 〇pen drain A pad-to-Vdd discharge path to enhance its electrostatic protection. In electrostatic protection circuits, a direct discharge path can improve electrostatic protection. In general, the discharge paths from bonding 塾 to Vdd (pad-to-Vdd) and bonding 塾 to Vss (pad-to-Vss) are established by special electrostatic parts. These electrostatic protection elements can be field effect oxidation elements, thin oxide elements or other special elements. In addition, because of its large area and driving force, in order to save area and reduce output capacitance, the I / O driving circuit is also used as an electrostatic protection circuit in addition to using it as a driving circuit. The diagram shows one of the commonly used pul up & pul 1 down drive circuits 10, which are used to protect the internal circuit 12 from static electricity. 'Includes transistor. 3, 14, impedance r and-electrostatic protection element] 5 . The transistors 13, 14 are commonly connected to a bonding pad u, and the other ends are connected to vdd and vss, respectively. Transistors 13 and 14 respectively provide two paths with opposite current directions under normal conditions. At the same time, static electricity can also be exported to Vdd and Vss when they are exposed to static electricity. : The driving circuit 10 in FIG. 1 naturally includes a discharge path from a bonding pad to a bonding pad to a Vss (pad-to-Vss). T, ``! * TS3) = 2 shows an open drain driving circuit "and its circuit 21 1 to protect the internal circuit 12 from static electricity. Guarantee: the same components shown in Figure 1 use the same symbols to indicate square-drain The driving circuit 22 includes a transistor 25, whose terminals are connected to 4 2 56 87. V. Description of the invention ¢ 2) The source is connected to V ss, and the gate receives a round-in signal S. The electrostatic protection circuit 21 has Two field-effect oxidation transistors 23, 24, and an impedance R. As can be seen from FIG. 2, since only one transistor 25 is used in the open drain driving circuit 22 to provide a current path, during an electrostatic attack, the driving Circuit 2 2 cannot provide the discharge path from bonding pad to Vdd (pad-to-Vdd) directly like driving circuit 1 in FIG. 1, but only has the discharge path from bonding pad to Vss (pad-to-Vss). Its electrostatic protection capability is insufficient. Therefore, 'an electrostatic protection circuit 21' must usually be added when using an open dra i η drive circuit to establish a complete discharge path. However, the increase of the electrostatic protection circuit 21 will occupy more Large layout area and increased output 1 capacitance Therefore, in order to be able to establish a discharge path from the bonding pad to Vdd (pad-to-Vdd) in the open drai η drive circuit, and at the same time to avoid the increase in layout area and output capacitance, the present invention provides an electrostatic protection function A driver integrated circuit 'includes: a substrate connected to a first potential; a driving circuit' formed on the substrate 'includes at least one transistor formed on the substrate' the drain region, source region and gate of the transistor The layers are respectively connected to a bonding layer, a first potential and an input signal; a first doped region is formed on the substrate and is 'insulatedly arranged beside the electrode region of the transistor and connected to a third potential'. The doped region and the source and drain regions of the transistor have the same type of #hetero ions. Among them, a second doped region is formed on the substrate, and is located next to the source region of the transistor and is connected to the Three potentials, the second doped region and the source and drain regions of the transistor have the same type of doped ions, and the first doped
^ 2 56 87 *·ί _______ 五、發明說明（3) 區與第二摻雜區相連成一環形’而絕緣地設置於該驅動電 路四周。第一電位亦巧"以為Vbb或Vss，而第二及第三電位 分別為Vss及Vdd。 因此，由於在本發明提供之具有靜電保護功能之驅動 器積體電路中，在驅動電路四周增加一同型摻雜區，產生 一寄生電晶體，此電晶體提供一接合墊至Vdd(pad-to Vdd)之放電路徑，所以本發明同時達到了增強open drain 驅動電路之靜電保護能力及避免電路面積及輸出電容增加 之目的。 為讓本發明之上述目的、特徵及優點能更明顯易懂， 下文特舉較佳實施例’並配合所附圖式，作詳細說明如 下。 圖式簡單說明 圖1係pull-up & pull down驅動電路示意圖。 圖2係一傳統0pen drain 驅動電路及其靜電保護電路 之示意圖。 圖3A係本發明一實施例之部份佈局圖。 圖3B係圖3A中電路之等效電路圖。 圖4A係本發明另一實施例之部份佈局圖。 圖4B係圖4A中電路之等效電路圖。 符號說明 11〜接合墊； 1 2内部電路； 13〜pull up電晶體；^ 2 56 87 * · ί _______ V. Description of the invention (3) The region and the second doped region are connected in a ring shape 'and are arranged around the driving circuit in an insulated manner. The first potential is also known as Vbb or Vss, and the second and third potentials are Vss and Vdd, respectively. Therefore, in the driver integrated circuit with electrostatic protection function provided by the present invention, a homo-doped region is added around the driving circuit to generate a parasitic transistor. This transistor provides a bonding pad to Vdd (pad-to Vdd). ) Discharge path, so the invention simultaneously achieves the purpose of enhancing the electrostatic protection capability of the open drain driving circuit and avoiding the increase in circuit area and output capacitance. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following describes in detail the preferred embodiments' in conjunction with the accompanying drawings. Brief description of the diagram Figure 1 is a schematic diagram of a pull-up & pull down drive circuit. Figure 2 is a schematic diagram of a conventional 0pen drain driving circuit and its electrostatic protection circuit. FIG. 3A is a partial layout diagram of an embodiment of the present invention. FIG. 3B is an equivalent circuit diagram of the circuit in FIG. 3A. FIG. 4A is a partial layout diagram of another embodiment of the present invention. FIG. 4B is an equivalent circuit diagram of the circuit in FIG. 4A. Explanation of symbols 11 ~ bonding pads; 1 2 internal circuits; 13 ~ pull up transistors;
4256 87·, 五、發明說明（4) 1 4〜pu 1丨down電晶體； 23 ' 24〜場效氧化電晶體； 2 5 - open drain driver 酋曰祕 免aa體； 301、302、303 ' 304〜驅動電路 3 1〜汲極區 ’ 3 2〜源極區 3 3〜閘極層 3 4〜絕緣層 35-同型摻雜區； 36、41〜寄生電晶體。 實施_例 如圖&A所不，係本實施例之驅動電路在一基底上各元 件佈局之示意圖。實#例中之驅動電路包括四個驅動電 路單元301、302、^备..¾ 〇 4。由於每個驅動電路單元結構 ，同，此處僅以驅動電路單元3 〇 i為例做說明。驅動電路 單兀301中具有兩個共用汲極區之電晶體，包括一汲極區 31、源極區32、閘極層33、絕緣層34及一摻雜區35。其 中’源極區32及汲極區31為N+摻雜區，而摻雜區35與源極 區32及沒極區31為同型離子之摻雜區，即亦為N+摻雜區。 另外’此驅動電路所在之基底具有Vss之電位，汲極 區31係連接至接合墊ιι(圖未顯示）’源極區32係連接至 Vss ’閘極層33接收一輸入信號s而摻雜區35則連接至 Vdd。另外’兩個相鄰之驅動電路單元之源極區係被合併 的’即驅動電路單元301及驅動電路單元303之源極區被合 画 第7頁 4 2 56 87·· 五、發明說明（5) 併’驅動電路單元302及驅動電路單元3〇4之源極區亦被合 併。 圖3B係圖3A之等效電路30之電路圖。其中包括電晶體 25、寄生電晶體36及接合墊11 由於圖“中之電晶體在電 路上為並聯’所以圖3B中僅使用一個電晶體25來代表。另 外’由於摻雜區35與源極區32及汲極區31為同型離子之摻 雜區（N +摻雜區）’且摻雜區3 5係連接至v d d，所以在汲極 區31與Vdd之間存在一寄生電晶體36。當靜電襲擊時，電 流可從電晶體25流至Vss，或是從寄生電晶體36流至Vdd ^ 從圖3B中可以看出’使用圖3A所示意之結構製造之驅 動電路與圖2中傳統之ope n drain驅動電路最大之不同在 於沒有使用額外之靜電保護電路的情況下’增加了 一接合 墊至Vdd之放電路徑。因此，本實施之驅動電路在不增加 輸出電容及佈局面積之條件下，達成提高靜電保護能力之 目的。 圖4A係本實施例之驅動電路在一基底上佈局之示意 圖。圖4A中與圖3A中相同之元件係使用相同之符號。 在圖4A中’由於每個驅動電路單元3〇1、3()2、3(}3、 3 04之結構相同，此處僅以驅動電路單元3〇1為例做說明。 驅動電路單元301中具有兩個共用汲極區之電晶體，包括 一汲極區31、源極區32、閘極層33、絕緣層34及一摻雜區 35。其中，源極區32及汲極區31為^摻雜區，而摻雜區35 與源極區32及汲極區31為同型離子之摻雜區，即亦為N+摻 雜區。另外，此驅動電路所在之基底具有Vss之電位，汲4256 87 ·, V. Description of the invention (4) 1 4 ~ pu 1 丨 down transistor; 23 '24 ~ field effect oxidation transistor; 2 5-open drain driver Aa body; 301, 302, 303' 304 ~ driving circuit 3 1 ~ drain region '3 2 ~ source region 3 3 ~ gate layer 3 4 ~ insulating layer 35-isotype doped region; 36,41 ~ parasitic transistor. Implementation Example As shown in & A, it is a schematic diagram of the layout of the components of the driving circuit of this embodiment on a substrate. The driving circuit in the actual example includes four driving circuit units 301, 302, and ^ .. ¾ 04. Because of the structure of each driving circuit unit, the driving circuit unit 30i is used as an example for description here. The driving circuit 301 includes two transistors having a common drain region, including a drain region 31, a source region 32, a gate layer 33, an insulating layer 34, and a doped region 35. Among them, the 'source region 32 and the drain region 31 are N + doped regions, and the doped region 35 and the source region 32 and the non-electrode region 31 are doped regions of the same type of ions, that is, also N + doped regions. In addition, 'The substrate on which the driving circuit is located has a potential of Vss, and the drain region 31 is connected to the bonding pad (not shown)' the source region 32 is connected to Vss. Region 35 is connected to Vdd. In addition, the source regions of two adjacent driving circuit units are merged, that is, the source regions of driving circuit unit 301 and driving circuit unit 303 are grouped together. Page 7 4 2 56 87 ·· V. Description of the invention ( 5) The source regions of the driving circuit unit 302 and the driving circuit unit 304 are also merged. FIG. 3B is a circuit diagram of the equivalent circuit 30 of FIG. 3A. This includes transistor 25, parasitic transistor 36, and bonding pad 11. Because the transistor in the figure is “parallel in the circuit,” only one transistor 25 is used in FIG. 3B. In addition, because the doped region 35 and the source The region 32 and the drain region 31 are doped regions (N + doped regions) of the same type of ions, and the doped region 35 is connected to vdd, so a parasitic transistor 36 exists between the drain region 31 and Vdd. When static electricity strikes, the current can flow from the transistor 25 to Vss, or from the parasitic transistor 36 to Vdd. ^ From Figure 3B, it can be seen that 'the driving circuit manufactured using the structure shown in Figure 3A and the traditional Figure 2 The biggest difference between the ope n drain driving circuit is that the discharge path of a bonding pad to Vdd is added without the use of an additional electrostatic protection circuit. Therefore, the driving circuit of this implementation does not increase the output capacitance and layout area. To achieve the purpose of improving electrostatic protection. Figure 4A is a schematic diagram of the layout of the driving circuit of this embodiment on a substrate. The same components in Figure 4A as in Figure 3A use the same symbols. In Figure 4A, drive The circuit units 3101, 3 () 2, 3 (} 3, 304) have the same structure, and here only the driving circuit unit 301 is taken as an example. The driving circuit unit 301 has two shared drain regions. The transistor includes a drain region 31, a source region 32, a gate layer 33, an insulating layer 34, and a doped region 35. The source region 32 and the drain region 31 are doped regions, and doped. Region 35, source region 32, and drain region 31 are doped regions of the same type of ions, that is, also N + doped regions. In addition, the substrate on which the driving circuit is located has a potential of Vss.
4 256 87* 五、發明說明（6) 極區3 1係連接至接合墊1丨（圖未顯示），源極區3 2係連接至 V s s，閘極層3 3接收一輪入信號s，而摻雜區3 5則連接至 Vdd °此處與圖3 A最大之不同在於，摻雜區3 5係絕緣地設 置於電晶體之四周而成環形。 圖4B係圖4A之等效電路50之電路圖其中包括電晶體 25 '寄生電晶體36、41及接合墊11。由於圖4A中之電晶體 在電路上為並聯，所以圖中僅使用—個電晶體π來代 表。另外’由於摻雜區3 5與源極區3 2及汲極區31為同型離 子之摻雜區（N+摻雜區），且掺雜區35係連接至vdd，所以 在汲極區31與Vdd之間存在一寄生電晶體36。又源極區係 連接至Vss，所以在vdd與Vss之間亦存在一寄生電晶體 41 °當靜電襲擊時，電流可從電晶體25流至Vss，或是從 寄生電晶體36流至vss ’亦或經由寄生電晶體41間接地流 至Vdd或Vss。從圖4B中可以看出，使用圖4A所示意之結構 製造之驅動電路在沒有使用額外之靜電保護電路的情況 下’不僅較圖2中傳統之0pen drain驅動電路增加了接合 墊至Vdd之放電路徑，亦增加了一vdd至Vss之放電路徑。 因此’本實施之驅動電路亦在不增加輸出電容及佈局 面積之條件下’達成提高靜電保護能力之目的。 “合上述’本發明係在傳統open drain驅動電路之四 周增加一同型摻雜區，使Vd(J與接合墊或vdd與Vss之間產 生寄生電晶體’使接合墊遭受靜電襲擊時，電流可以由寄 生電晶體流至Vdd或Vss，進而增加了 open drain驅動電路 之靜電保護能力。此外，本發明之驅動電路特別適用於基4 256 87 * V. Description of the invention (6) The pole area 3 1 is connected to the bonding pad 1 丨 (not shown in the figure), the source area 3 2 is connected to V ss, and the gate layer 3 3 receives a round of incoming signal s. The doped region 35 is connected to Vdd °. The biggest difference between this and FIG. 3A is that the doped region 35 is arranged annularly around the transistor in an insulating manner. Fig. 4B is a circuit diagram of the equivalent circuit 50 of Fig. 4A, which includes transistors 25 ', parasitic transistors 36, 41, and bonding pads 11. Since the transistors in Figure 4A are connected in parallel on the circuit, only one transistor π is used in the figure to represent them. In addition, since the doped region 35, the source region 32, and the drain region 31 are doped regions (N + doped regions) of the same type of ions, and the doped region 35 is connected to vdd, so the drain region 31 and the There is a parasitic transistor 36 between Vdd. The source region is connected to Vss, so there is also a parasitic transistor 41 between vdd and Vss. When static electricity strikes, current can flow from transistor 25 to Vss, or from parasitic transistor 36 to vss. It may also flow to Vdd or Vss indirectly via the parasitic transistor 41. It can be seen from FIG. 4B that the driving circuit manufactured using the structure shown in FIG. 4A without using an additional electrostatic protection circuit not only increases the discharge from the bonding pad to Vdd than the conventional 0 pen drain driving circuit in FIG. 2 The path also adds a discharge path from vdd to Vss. Therefore, 'the driving circuit of this embodiment also achieves the purpose of improving the electrostatic protection ability without increasing the output capacitance and layout area'. "Together with the above," the present invention adds a homo-doped region around the traditional open drain driving circuit to make Vd (parasitic transistor between J and the bonding pad or vdd and Vss'). When the bonding pad is subjected to electrostatic attack, the current can be The parasitic transistor flows to Vdd or Vss, thereby increasing the electrostatic protection capability of the open drain driving circuit. In addition, the driving circuit of the present invention is particularly suitable for basic
第9頁 ^25687^ 五、發明說明（7) 底有特殊偏壓（Vbb)之產品。 本發明雖已以較佳實施例揭露如上5但其並非兩以限 制本發明。任何熟悉此技藝者，在不脫離本發明之精神和 範圍内，當可做些許之更動與潤飾。因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。Page 9 ^ 25687 ^ V. Description of the invention (7) Products with special bias (Vbb) at the bottom. Although the present invention has been disclosed above in the preferred embodiment, it is not two to limit the present invention. Anyone familiar with the art can make some changes and retouching without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.
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