JP3360192B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS (metal oxide semiconductor) with reduced standby current.
(DUT) semiconductor device having a capacitor. 2. Description of the Related Art Currently, for example, a capacitor is manufactured in a semiconductor device for the purpose of stabilizing a power supply.

In such a capacitor, the insulating film (dielectric film) between the electrode plates is formed as thin as possible in order to increase the capacitance. However, the thinner, the more leaky the insulating film becomes. Since the standby current increases, this problem must be solved.

[0003]

2. Description of the Related Art In general, it is accepted that thinning a dielectric film between electrodes in a capacitor naturally becomes leaky. Until now, it has been mainly required to seek a dielectric material having a high withstand voltage. I was eager.

[0004] Until now, there is no known effective technique for compensating an increase in standby current caused by a leaky dielectric film in a capacitor built in a semiconductor chip.

[0005]

As described above, the increase in standby current caused by a leaky dielectric film in a capacitor can be achieved by increasing the thickness of the dielectric film at the expense of capacity at present. There is no way to do it.

According to the present invention, the dielectric film between the electrode plates in the capacitor is made thinner to increase the capacitance, and furthermore, to prevent leakage current from flowing during standby.

[0007]

According to the present invention, it is a basic principle that both electrodes of a capacitor are set to the same potential during standby to prevent current from flowing.

From the above, in the semiconductor device according to the present invention, (1) a first power supply line, a second power supply line, and a
A first switch, a p-channel transistor, and a second switch.
N-channel transistor, which is a switch of
And the first terminal of the capacitor is connected to the first power supply line.
And the second terminal of the capacitor switches the first switch.
And a second terminal of the capacitor connected to the first power supply line
Is connected to a second power supply line via a second switch,
A first switch is turned on and a second switch is turned off when a standby signal is input to a gate of the inverter ; or (2) a first power supply line, a second power supply Wire and inverter
P-channel transistor and the first switch
An n-channel transistor as a second switch;
And a second end of the capacitance at a second power line.
And a first terminal of the capacitor is connected to a second switch.
Connected to the second power supply line via the
Terminal is connected to the first power supply line via the first switch.
And a standby signal is input to the gate of the inverter.
The second switch conducts and the first switch turns off.
Or characterized in that it is cross-sectional, or, in the (3) above (1) or (2), the first power supply line is high
Or the second power supply line is a lower power supply line , or (4) In the above (1) or (2) , the first power supply line is a power supply line of the low side and the second power supply line is it being a power supply line of the high side.

[0009]

[0010]

[0011]

[0012]

According to the above-mentioned means, since the potential of both plates of the capacitor becomes the same at the time of standby, no leak current flows even if the dielectric film is leaky, so that the increase of the standby current is suppressed. be able to.

[0013]

FIG. 1 is an explanatory view of a main part of a semiconductor device for explaining a first embodiment according to the present invention.

In the figures, (A) is a main part plane, (B) is an equivalent circuit, 1 is a Si semiconductor substrate, 2 is an n-well, 3 is an n-well, and 4 is an n ⁺⁺ -electrode contact region. 5 and 5 are p ⁺ -regions in the p-channel potential control transistor, and 6
Is an n ⁺ -region of the n-channel potential control transistor, 7 is a gate electrode common to the p-channel and n-channel potential control transistors, and 7A is an input terminal of the p-channel and n-channel potential control transistors. , 8 is a V _CC side wiring, 9 is a V _SS side wiring, 11 is an electrode serving as one electrode plate of a capacitor, 11A is an electrode contact window, 12 is a wiring, 12A is a wiring contact window, Q
1 denotes a p-channel transistor, Q2 denotes an n-channel transistor, C denotes a capacitor portion, and Q denotes a potential control transistor portion.

In the illustrated example, one electrode plate in the capacitor portion C is an electrode 11 and the other electrode plate is an n-well 2.
It has become. An insulating film, which is a dielectric film, is naturally interposed between them, but is omitted for the sake of simplicity, and many electrode contact windows represent those formed on the insulating film.

When an "H" level signal is input to the input terminal 7A, the transistor Q1 is turned off, the transistor Q2 is turned on, and the electrode 11, which is one of the plates of the capacitor, has the potential _Vcc. Since the n-well 2, which is the other electrode of the capacitor, has the potential of V _SS , the capacitor portion C functions as the capacitor.

However, when an "L" level signal is input to the input terminal 7A, the transistor Q1 is turned on, the transistor Q2 is turned off, and the electrode 11, which is one of the pole plates of the capacitor, is of course set to the _Vcc potential. it has been also because Na'iru n- well 2 and the other plate of the capacitor becomes V _CC potential, the capacitor portion C is not the original working capacitor bipolar plate is at the same potential.

Here, if the "L" level of the signal input to the input terminal 7A is taken as the standby signal of the semiconductor device,
Since the current does not flow through the capacitor portion C at the same time as the standby state, even if the dielectric film is thin, the leak current does not increase.

FIG. 2 is an explanatory view of a main part of a semiconductor device for explaining a second embodiment according to the present invention.

In the figure, (A) is a main part plane, (B) is an equivalent circuit, 21 is a Si semiconductor substrate, 22 is an n-well,
23 is an n-well, 24 is an n ⁺⁺ -electrode contact region,
25 is p ^{+ in the} p-channel potential control transistor.
, 26 is an n ⁺ -region of the n-channel potential control transistor, 27 is a gate electrode common to the p-channel and n-channel potential control transistors, and 27A is a p-channel and n-channel potential control transistor. Input terminal, 28 is a V _CC side wiring, 29 is a V _SS side wiring, 31 is an electrode serving as one of the plates of a capacitor, 32 is a wiring, 32 A is a wiring contact window, and Q 1 is p
A channel transistor, Q2 is an n-channel transistor, C is a capacitor portion, and Q is a potential control transistor portion.

In the illustrated example, one electrode plate in the capacitor portion C is an electrode 31 and the other electrode plate is an n-well 2.
It is 2. In the meantime, as in the first embodiment, an insulating film as a dielectric film is interposed, but is omitted for simplicity, and a number of electrode contact windows are formed in the insulating film. Is represented.

When an "L" level signal is input to the input terminal 27A, the transistor Q1 is turned on.
Transistor Q2 is turned off, the electrode 31 that is a one plate of the capacitor is V _CC potential, also because Na'iru n- well 22 and the other plate of the capacitor has a V _SS potential, the capacitor Portion C functions as a capacitor.

However, when an "H" level signal is input to the input terminal 7A, the transistor Q1 is turned off, the transistor Q2 is turned on, and the electrode 11, which is one of the plates of the capacitor, is set to the V _SS potential. In addition, since the n-well 2 serving as the other electrode plate of the capacitor is also at the _Vss potential, both electrode plates of the capacitor portion C have the same potential, and the capacitor does not perform its original function.

Here, if the "H" level of the signal input to the input terminal 7A is used as the standby signal of the semiconductor device,
Since the current does not flow through the capacitor portion C at the same time as the standby state, even if the dielectric film is thin, the leak current does not increase.

[0025]

Is In the semiconductor device according to the present invention, the
A first power line, a second power line, and a first
A p-channel transistor, which is a switch of
Switch n-channel transistor, capacitance one
And the first terminal of the capacitor is connected to the first power line
And a second terminal of the capacitor is connected through a first switch.
And the second terminal of the capacitor is connected to the first power line.
Connected to a second power supply line via a second switch;
Basically, the first switch is turned on and the second switch is turned off when a standby signal is input to the gate of the inverter .

By adopting the above configuration, the potential of both plates of the capacitor is the same at the time of standby, so that even if the dielectric film is leaky, no leak current flows, so that the increase of the standby current is suppressed. be able to.

[Brief description of the drawings]

FIG. 1 is a main part explanatory view showing a semiconductor device for explaining a first embodiment according to the present invention.

FIG. 2 is an explanatory view of a main part of a semiconductor device for explaining a second embodiment according to the present invention;

[Explanation of symbols]

Reference Signs List 1 Si semiconductor substrate 2 n-well 3 n-well 4 n ⁺⁺ -electrode contact region 5 p ⁺ -in p-channel potential control transistor
Region 6 n ⁺ − in n-channel potential control transistor
Region 7 Gate electrode common to each potential control transistor 7A Input terminal of each potential control transistor 8 _Vcc side wiring 9 _Vss side wiring 11 Electrode serving as one electrode plate of capacitor 11A Electrode contact window 12 Wiring 12A Wiring contact window Q1 P-channel transistor Q2 N-channel transistor C Capacitor part Q Potential control transistor part

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 21/8238 H01L 27/04 H01L 27/092

Claims (4)

(57) [Claims] 1. A first power supply line, a second power supply line, and an inverter
P-channel transistor which is the first switch constituting
Transistor and second switch , n-channel transistor
A first terminal of the capacitor is connected to the first power line, a second terminal of the capacitor is connected to the first power line via the first switch, and A second terminal of the capacitor is connected to a second power supply line via a second switch, and when a standby signal is input to the gate of the inverter.
The semiconductor device and the first switch is conductive and the second switch, characterized in that it is cut. 2. A first power supply line, a second power supply line, and an inverter.
P-channel transistor which is the first switch constituting
Transistor and second switch, n-channel transistor
A second terminal of the capacitor connected to the second power supply line,
A first terminal of the capacitor is connected to a second terminal via a second switch.
A first terminal connected to the source line and having a first terminal connected to the first line;
Connected to the first power supply line via a switch, and a standby signal is input to the gate of the inverter.
The second switch is turned on and the first switch is turned off.
A semiconductor device characterized in that: 3. The first power supply line is a high-side power supply line, and
The second power supply line of the semiconductor device according to claim 1 or 2, wherein the a power supply line of the low potential side. Wherein the first power supply line of the semiconductor device according to claim 1 or 2, wherein the and the second power supply line is a power supply line of the low potential side is a power supply line of the high side.