551020 A7551020 A7
經濟部智慧財產局員工消費合作社印製 五、發明說明（） 本發明係與電子產品有關，特別係關於一種印刷電 路板之焊墊結構。 在現今的電子製造工業中，晶粒直接裝載（Direct Chip Attach，DCA)以及晶片級封裝（chip以沉以‘明， 5 CSP)等技術被大量應用於製造印刷電路板（Printed Circuit Board，PCB)上。在印刷電路板上會設置焊墊 (bonding pads)，使覆晶裝載時，裸晶可與電路板電性 導接。焊墊的製作方法大多是利用照相顯影之方式，在 印刷電路板之防焊層上設置微孔，藉以暴露電路佈局的 10預定位置。並在被暴露的電路佈局的銅線上電鍍鎳-金 層，使其形成前述之焊塾。 在前述的照相顯影製程中，底片貼附於基板時，必 然會有對準的誤差產生，換言之，前述之微孔的位置， 會相對於原本預定的位置產生偏移。 15 先前技藝中解決前述微孔偏移的方法有二：其—為 防焊層定義法（solder mask define method)，另一為非防 焊層定義法（non_solder mask define method)。防烊層定 義法是在防焊層上開設孔徑較大的微孔，而非防焊層定 義法是加大電路佈局在對應於焊墊位置之銅導線的尺 20 寸。但此二種方法均具有缺點。 第一圖係顯示一基板80，其上具有一以非防焊層定 義法所製作之焊墊81。該基板80上設有預定之電路佈 -3- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背*之注意事項再填寫本頁} · 裝Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention () The invention relates to electronic products, and particularly to a pad structure for printed circuit boards. In today's electronics manufacturing industry, technologies such as Direct Chip Attach (DCA) and wafer-level packaging (chip to Shen Yiming, 5 CSP) are widely used in the manufacture of printed circuit boards (Printed Circuit Board, PCB). )on. Bonding pads are provided on the printed circuit board so that when the flip chip is loaded, the bare chip can be electrically connected to the circuit board. Most of the manufacturing methods of the solder pads use photographic development to set micro-holes in the solder mask layer of the printed circuit board to expose the predetermined position of the circuit layout. A nickel-gold layer is plated on the copper wire of the exposed circuit layout to form the aforementioned solder pad. In the aforementioned photographic development process, when a negative film is attached to a substrate, an alignment error must be generated. In other words, the position of the aforementioned microholes will be shifted from the original predetermined position. 15 In the prior art, there are two methods to solve the aforementioned microvia offset: it is the solder mask define method, and the other is the non_solder mask define method. The definition method of anti-rust layer is to create micro-holes with larger pores in the solder resist layer, while the definition method of non-solder layer is to increase the circuit layout by 20 inches of copper wire corresponding to the pad position. However, both methods have disadvantages. The first diagram shows a substrate 80 having a pad 81 made thereon by a non-solder mask definition method. The substrate 80 is provided with a predetermined circuit cloth. -3- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back * before filling this page}.
經濟部智慧財產局員工消費合作社印製 551020 A7 __B7_ 五、發明說明（） 局82，其在焊墊81的位置具有較大尺寸的銅導線，以 及一防焊層83覆蓋該電路佈局82之預定部位。該防焊 層83上開設有微孔84，令該電路佈局82之預定位置 暴露。該電路佈局82被暴露之部分電鑛有一錄-金層 5 85，藉以形成前述之焊墊81。圖中顯示了該微孔84偏 移一預定距離，因此，焊墊81係位於各該微孔84之一 側。 第二圖係顯示一覆晶90裝設於該基板80上，使凸 塊（solder bumps) 91連接該覆晶90與該基板80之焊墊 10 81。我們可以很輕易的瞭解，如果微孔84的偏移量較 大，則焊墊81的面積會減小。因此，凸塊91連接該覆 晶90與該基板80之能力亦隨之減小。所以，傳統的製 造法還是會使得所製造的電路板具有較高的不良率。 此外，電路佈局82在位於該焊墊81位置的尺寸加 15 大，會造成焊墊81的間距增加，如此，在相同的面積 中，覆晶90僅可具有較少數量之凸塊91，或者必須加 大覆晶90的尺寸。 再者，在裝設覆晶90後，微孔84内常會存積助焊 劑殘渣92，不易清除。 20 以防焊層法製造的電路板也會產生相同的問題，在 此容不詳述。 本發明之主要目的在於提供一種印刷電路板之焊墊 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱tt-背面之注意事項再填寫本頁) -丨裝Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 551020 A7 __B7_ V. Description of the invention () Bureau 82, which has a larger size copper wire at the position of the pad 81, and a solder mask 83 to cover the circuit layout 82 plan Parts. Micro-holes 84 are formed in the solder resist layer 83 to expose a predetermined position of the circuit layout 82. A part of the power ore exposed in the circuit layout 82 has a recording-gold layer 5 85 to form the aforementioned bonding pad 81. The figure shows that the micro-holes 84 are offset by a predetermined distance. Therefore, the pad 81 is located on one side of each of the micro-holes 84. The second figure shows that a flip chip 90 is mounted on the substrate 80 so that solder bumps 91 connect the solder pads 10 81 of the flip chip 90 and the substrate 80. We can easily understand that if the displacement of the micro-holes 84 is large, the area of the pads 81 will be reduced. Therefore, the ability of the bump 91 to connect the flip chip 90 and the substrate 80 is also reduced. Therefore, the traditional manufacturing method still makes the manufactured circuit board have a higher defect rate. In addition, the size of the circuit layout 82 at the position of the pad 81 is increased by 15, which will increase the pitch of the pad 81. In this way, the flip chip 90 can only have a small number of bumps 91 in the same area, or The size of the flip-chip 90 must be increased. Furthermore, after the flip-chip 90 is installed, flux residues 92 often accumulate in the micro-holes 84 and are difficult to remove. 20 The same problem arises with the circuit board manufactured by the solder mask method, which will not be described in detail here. The main purpose of the present invention is to provide a solder pad for a printed circuit board. -4- The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). (Please read the precautions on the back of tt- before filling this page. )-丨
551020 A7 五、發明說明（ 15 經濟部智慧財產局員工消費合作社印製 20 結構，其可解決前述之問題。 為達成前述之發明目的，本發明所提供之—種印刷 電路板之焊塾結構，包含有：一基板，具有-電路佈局， 其係由複數個導線所形成之迴路；一防焊層，設於該基 板上，覆蓋該電路佈局之預定部分，該防燁層上開設有 至少-個微孔’藉以使位於該微孔下方的導線被暴露， 以及至少-焊塾層設置於該微孔之側壁’並與位於該該 微孔下方被暴露的導線電性連接，以形成前述之焊塾。 以下兹舉-較佳實施例，配合圖示，對本發明作進 一步之說明，其中 第三圖係本發明—較佳實施例之剖面示意圖； 第四圖係本發明-較佳實_之剖面示意圖，顯示 一覆晶裝設於其上； 第五圖係製造本發明較佳實施例之流程圖，以及 第/、圖係另-種製造本發明較佳實施例之流程圖。請參閱第三圖所示，本發明—較佳實施例所提供之 印刷電路板之焊墊結構，包含有. 基板1〇係以夕功能環氧樹脂（multi-function ep°xyfesi_㈣㈣’其上設有-電路佈局20,豆 為由複數個銅導線所形成之㈣，以及一防焊層3〇, 覆蓋該電路佈局20之預定部分。該防焊層30亦為多功 能環氧樹㈣製成°本發明切刷電路板可為-單層印 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297 !1!1 一一 — I (請先閱諫背面·之注意事項再填寫本頁) ta·551020 A7 V. Description of the invention (15 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, a structure printed by 20, which can solve the aforementioned problems. In order to achieve the aforementioned object of the invention, a soldering structure of a printed circuit board provided by the present invention, It includes: a substrate with a -circuit layout, which is a circuit formed by a plurality of wires; a solder mask layer provided on the substrate, covering a predetermined portion of the circuit layout, and at least- Micro-holes 'so that the wires below the micro-holes are exposed, and at least-a solder layer is disposed on the side wall of the micro-holes' and is electrically connected to the wires exposed under the micro-holes to form the aforementioned Welding: The following is a preferred embodiment, accompanied by illustrations, to further illustrate the present invention, in which the third figure is a schematic cross-sectional view of the present invention-the preferred embodiment; the fourth figure is the present invention-the preferred embodiment_ A schematic cross-sectional view showing a flip chip mounted thereon; the fifth diagram is a flowchart for manufacturing a preferred embodiment of the present invention, and the fifth and third diagrams are another flowchart for manufacturing a preferred embodiment of the present invention. Please refer to the third figure. The pad structure of the printed circuit board provided by the present invention-the preferred embodiment includes: The substrate 10 is a multi-function ep ° xyfesi_㈣㈣'on which Yes-circuit layout 20, beans are made of copper wire, and a solder mask 30, covering a predetermined part of the circuit layout 20. The solder mask 30 is also made of multifunctional epoxy tree ° The cutting and brushing circuit board of the present invention can be-single-layer printed paper with a standard of China National Standards (CNS) A4 (210 X 297! 1! 1-1-I (please read the precautions on the back and fill in this page first) ) ta ·
經濟部智慧財產局員工消費合作社印製 551020 A7 __B7_ 五、發明說明（） 刷電路板，當然亦可為一多層印刷電路板。 該防焊層30在預定位置上設有複數個微孔31，藉 以暴露該電路佈局20之預定部分。第三圖中同樣顯示 該等微孔31因照相顯影製程而產生偏移，因此，該電 5 路佈局20被暴露的部分係位於各該微孔31的一側。 在該等微孔31的側壁以及該電路佈局20被暴露之 部份（有時亦會在位於該等微孔31下方被暴露的該基板 10上），分別設有一焊墊層40，其與該電路佈局20呈 電性連接之狀態。每一焊墊層40具有一内層41以及一 10 外層42。該内層41可為一銅箔層，貼附於該等微孔31 的側壁以及該電路佈局20被暴露之部份，有時亦會貼 附於位於該等微孔31下方被暴露的該基板10上（當該 等微孔31的偏移量過大，導致該基板10具有一部份會 暴露於該等微孔31之下方時），而該外層42可為鎳-金 15 層，貼附於該内層41上，如此，及形成前述之焊墊21。 本發明之優點在於： 1. 即使該等微孔31的位置偏離預定位置，只要該 電路佈局20至少具有一部份位於該微孔31中，藉以使 該焊墊層40可與該電路佈局20電性導通，即可完成本 20 發明所提供之焊墊21。如此，製作本發明之印刷電路 板，可使製程的良率大幅提高。 2. 本發明之焊墊21的位置即為該等微孔31的位 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------_裝--- (請先閱諫背面·之注意事項再填寫本頁) 551020 A7 B7_ 五、發明說明（） (請先閱tt-背面之注意事項再填寫本頁) 置，而不是位於該等微孔31下方之該電路佈局20被暴 露的部分。亦即，本發明之焊墊21的面積與該等微孔 31的尺寸有關，但與該等微孔31之偏移量無關。因此， 當將一覆晶70裝設於本發明之基板10上時，凸塊71 5 會與該焊墊層40的所有面積接合，如此，本發明之焊 墊21可提供穩固的狀態連結基板10與覆晶70。再者， 焊墊21内亦不會積存助焊劑的殘渣。 3·本發明之焊墊21結構並不需要如習用技術中增 加電路佈局20之銅導線的尺寸，也不需要加大微孔3 1 10 的尺寸。該銅導縣之尺寸可與該微孔31大約相等。因 此，在基板10上的焊墊21的間距可縮小。如此，該基 板10與該覆晶70的尺寸亦可對應縮小。 以下發明人提供二製程方法，藉以說明如何製作本 發明之焊墊： 15 方法一，請參閱第五圖所示·· 1. 預先準備基板10,其上具有電路佈局20以及防 焊層30覆蓋該電路佈局之預定部分。該防焊層30開設 有若干微孔31，藉以暴露該電路佈局20之預定部分。 經濟部智慧財產局員工消費合作社印製 2. 以化學鍍銅法在該防焊層30上設置一銅層41， 20 此銅層41除貼附於該防焊層30之表面外，還貼附於該 等微孔31的側壁與該電路佈局20位於該等微孔31下 方被暴露之部份，如前所述，當該等微孔31的偏移量 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 551020 A7 __B7_ 五、發明說明（） 較大時，該銅層41還會貼附於該基板10位於該等微孔 31下方被暴露的部分。 (請先閲tt-背面之注意事項再填寫本頁) 3.設置一罩層50覆蓋該等微孔31，之後並將該銅 層41暴露之部份移除。 5 4.移除該罩層50。 5·電鍍鎳-金層42於該銅層41上。如此即行成本 發明之焊墊21。 方法二，請參閱第六圖所示： 1. 預先準備基板10,其上具有電路佈局20以及防 10 焊層30覆蓋該電路佈局之預定部分。該防焊層30開設 有若干微孔31，藉以暴露該電路佈局20之預定部分。 2. 以化學鍍銅法在該防焊層30上設置一銅層41， 此銅層41除貼附於該防焊層30之表面外，還貼附於該 等微孔31的側壁與該電路佈局20位於該等微孔31下 15 方被暴露之部份，如前所述，當該等微孔31的偏移量 較大時，該銅層41還會貼附於該基板10位於該等微孔 31下方被暴露的部分。 經濟部智慧財產局員工消費合作社印製 3·設置一罩層60覆蓋該防焊層30,並將該罩層60 在對應於等微孔31之部份移除。 20 4·電鍍鎳-金層42於該銅層41位於該等微孔31中 被暴露之部份。 5·移除該罩層60以及該銅層41暴露之部份。如此 -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 551020 A7 _B7_ 五、發明說明（） 即完成本發明之焊墊21。 最後要提出說明的是，在前二製程中，該鎳-金層42 可以電鍍或是化學沉積法設置於該銅層41上。然而， 以化學沉積法所形成之鎳-金層42，其厚度較小，如須 5 得到厚度較大的外層42，可在化學鎳-金層上在電鍍一 金層，或市直接使用電鍍法設置該鎳-金層。 另外，發明所提供之印刷電路板之焊墊結構，是用 以經由該等焊墊21使該印刷電路板連接至其他電路， 其用途並非僅侷限於說明書中所描述的裝設覆晶用。 10 經濟部智慧財產局員工消費合作社印製 -9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 551020 A7 B7 五、發明說明（ 圖示之簡單說明： 第一圖係習知印刷電路板上之焊墊結構； 第二圖係顯示一覆精裝設於該習知印刷電路板上之 情形； 第三圖係本發明一較佳實施例之剖面示意圖； 第四圖係本發明一較佳實施例之剖面示意圖，顯示 一覆晶裝設於其上； 第五圖係製造本發明較佳實施例之流程圖，以及 -I — — — — — — — — — — - I I (請先閱讀背面之注意事項再填寫本頁) · 經濟部智慧財產局員工消費合作社印製 -10- 第六圖係另一種製造本發明較佳實施例之流程圖。 10 主要成分代表符號： 10基板 20電路佈局 21焊墊 3 0防焊層 31微孔 40焊墊層 41内層 42外層 50罩層 15 60罩層 70覆晶 71凸塊 80基板 81焊墊 82電路佈局 83防焊層 84微孔 8 5錄-金層 90覆晶 91凸塊 92助焊劑殘渣 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 551020 A7 __B7_ V. Description of the invention () Brush circuit board, of course, it can also be a multilayer printed circuit board. The solder resist layer 30 is provided with a plurality of micro holes 31 at predetermined positions, thereby exposing a predetermined portion of the circuit layout 20. The third figure also shows that the micro holes 31 are shifted due to the photographic development process. Therefore, the exposed portion of the electrical circuit layout 20 is located on one side of each of the micro holes 31. On the side walls of the micro holes 31 and the exposed part of the circuit layout 20 (sometimes also on the substrate 10 exposed under the micro holes 31), a pad layer 40 is provided, which The circuit layout 20 is electrically connected. Each pad layer 40 has an inner layer 41 and an outer layer 42. The inner layer 41 may be a copper foil layer attached to the side walls of the micro holes 31 and the exposed part of the circuit layout 20, and sometimes it is also attached to the substrate exposed under the micro holes 31 10 (when the offset of the micro-holes 31 is too large, so that a part of the substrate 10 will be exposed below the micro-holes 31), and the outer layer 42 may be a nickel-gold 15 layer, attached On the inner layer 41, the pads 21 are formed as described above. The advantages of the present invention are: 1. Even if the positions of the micro-holes 31 deviate from a predetermined position, as long as at least a part of the circuit layout 20 is located in the micro-holes 31, the bonding pad layer 40 can be connected to the circuit layout 20. Electrically conducting, the pad 21 provided by the present invention 20 can be completed. In this way, the production of the printed circuit board of the present invention can greatly improve the yield of the process. 2. The position of the bonding pad 21 of the present invention is the position of the micro-holes 31-6-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --------- ---_ install --- (please read the precautions on the back side and then fill out this page) 551020 A7 B7_ 5. Description of the invention () (please read the precautions on the back side before filling out this page) It is not the exposed part of the circuit layout 20 located under the micro-holes 31. That is, the area of the pad 21 of the present invention is related to the size of the micro-holes 31, but has nothing to do with the offset of the micro-holes 31. Therefore, when a flip chip 70 is mounted on the substrate 10 of the present invention, the bumps 71 5 will be bonded to all the areas of the pad layer 40. Thus, the pad 21 of the present invention can provide a stable state to connect the substrate 10 与 chip 70. In addition, no residue of flux is accumulated in the pads 21. 3. The structure of the bonding pad 21 of the present invention does not need to increase the size of the copper wires of the circuit layout 20 as in conventional technology, nor does it need to increase the size of the micro-holes 3 1 10. The size of the copper guide can be approximately equal to that of the micro-hole 31. Therefore, the pitch of the bonding pads 21 on the substrate 10 can be reduced. In this way, the sizes of the substrate 10 and the flip chip 70 can be reduced accordingly. The following inventors provide a two-process method to explain how to make the solder pad of the present invention: Method one, please refer to the fifth figure. 1. Prepare a substrate 10 in advance, which has a circuit layout 20 and a solder mask 30 covering it. A predetermined part of the circuit layout. The solder mask layer 30 is provided with a plurality of micro holes 31 to expose a predetermined portion of the circuit layout 20. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 2. A copper layer 41 is provided on the solder resist layer 30 by electroless copper plating. 20 The copper layer 41 is attached to the surface of the solder resist layer 30. The side wall attached to the micro-holes 31 and the exposed part of the circuit layout 20 below the micro-holes 31, as mentioned before, when the offset of the micro-holes 31 is in accordance with Chinese national standards ( CNS) A4 specification (210 X 297 mm) 551020 A7 __B7_ V. Description of the invention () When larger, the copper layer 41 will also be attached to the exposed portion of the substrate 10 below the micro holes 31. (Please read the precautions on the back of tt- before filling this page) 3. Set a cover layer 50 to cover the micro holes 31, and then remove the exposed part of the copper layer 41. 5 4. Remove the cover 50. 5. Plating a nickel-gold layer 42 on the copper layer 41. In this way, the bonding pad 21 of the invention is implemented. Method two, please refer to the sixth figure: 1. Prepare a substrate 10 in advance, which has a circuit layout 20 and a solder mask 30 covering a predetermined portion of the circuit layout. The solder mask layer 30 is provided with a plurality of micro holes 31 to expose a predetermined portion of the circuit layout 20. 2. A copper layer 41 is provided on the solder resist layer 30 by an electroless copper plating method. The copper layer 41 is attached to the surface of the solder resist layer 30, and is also attached to the side walls of the micro holes 31 and the The circuit layout 20 is located on the exposed part below the micro-holes 31. As mentioned above, when the micro-holes 31 have a large offset, the copper layer 41 will also be attached to the substrate 10. The exposed portions under the micro holes 31. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 3. Set up a cover layer 60 to cover the solder resist layer 30, and remove the cover layer 60 at the portion corresponding to the isopore 31. 20 4. An electroplated nickel-gold layer 42 is located in the copper layer 41 in the exposed portions of the micro holes 31. 5. Remove the exposed portions of the cover layer 60 and the copper layer 41. This -8- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 551020 A7 _B7_ V. Description of the invention () The pad 21 of the present invention is completed. Finally, it should be noted that in the first two processes, the nickel-gold layer 42 can be disposed on the copper layer 41 by electroplating or chemical deposition. However, the thickness of the nickel-gold layer 42 formed by the chemical deposition method is small. If a thicker outer layer 42 is required, a gold layer can be electroplated on the chemical nickel-gold layer, or electroplating can be used directly in the city. Method to set the nickel-gold layer. In addition, the solder pad structure of the printed circuit board provided by the invention is used to connect the printed circuit board to other circuits through the solder pads 21, and its use is not limited to the use of a flip chip as described in the specification. 10 Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -9 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 551020 A7 B7 V. Description of the invention The structure of a solder pad on a conventional printed circuit board. The second diagram is a case where a hardcover is mounted on the conventional printed circuit board. The third diagram is a schematic cross-sectional view of a preferred embodiment of the present invention. The fourth diagram is A schematic cross-sectional view of a preferred embodiment of the present invention, showing a flip chip mounted thereon; the fifth diagram is a flowchart of manufacturing the preferred embodiment of the present invention, and -I — — — — — — — — — — — II (Please read the notes on the back before filling out this page) · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-10- The sixth picture is another flowchart for manufacturing a preferred embodiment of the present invention. : 10 substrate 20 circuit layout 21 solder pad 3 0 solder mask 31 micro-hole 40 solder pad layer 41 inner layer 42 outer layer 50 cap layer 15 60 cap layer 70 flip chip 71 bump 80 substrate 81 solder pad 82 circuit layout 83 solder mask layer 84 Microwell 8 5 Records-Gold Flip chip bumps 90 91 92 Paper scale applies flux residues present China National Standard (CNS) A4 size (210 X 297 mm)