TWI435675B - Wiring board - Google Patents

Description

Wiring board

The present disclosure relates to a wiring board, and more particularly to a wiring board in which the size of the wiring board in the thickness direction can be miniaturized and the cost of the wiring board can be reduced.

Heretofore, a wiring board called a coreless board has been utilized as a wiring board which is miniaturized in the thickness direction. Compared with a build-up wiring board having a core board (a wiring board formed by a build-up structure on both sides of the core board), the coreless board (without the core board) has low strength, so that it is prone to warp song. The wiring board 200 shown in Fig. 1 can be utilized as a wiring board which can reduce the warpage of the coreless board.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view of a wiring board in a related art.

Referring to FIG. 1, a wiring board 200 in the related art has solder resist layers 201 and 215, pads 202, resin layers 203 and 211, vias 204, 208 and 212, wirings 205 and 209, a reinforced insulating layer 207, and The electronic component mounting pad 213.

The solder resist layer 201 has a through portion 218 for placing the solder pad 202 (the through portion 218 passes through the solder resist layer 201). The pad 202 has a connection surface 202A for arranging an external connection end 261. The bonding pad 202 is provided in the through portion 218 such that the connecting surface 202A of the bonding pad 202 and one surface 201A of the solder resist layer 201 become approximately flush with each other. The pad 202 is a solder pad electrically connected to a mounting board 260 (eg, a motherboard) via the external connection end 261. For example, a gold/nickel deposited layer having a gold layer and a nickel layer deposited in sequence may be used as the material of the pad 202.

The resin layer 203 is provided to cover most of the surface 201B of the solder resist layer 201 (the surface of the solder resist layer 201 on the side opposite to the surface 201A) and one surface 202B of the solder pad 202. The resin layer 203 has an opening 219 to expose a portion of the face 202B of the pad 202.

The via 204 is provided in the opening 219. The via 204 is integrally formed with the wiring 205 and has a connection to the lower end of the pad 202. This wiring 205 is provided on one surface 203A of the resin layer 203. The wiring 205 is connected to the upper end of the via 204. For example, copper can be used as the material of the via 204 and the wiring 205.

The reinforced resin layer 207 is provided on the face 203A of the resin layer 203 so as to cover most of the wiring 205. The reinforced resin layer 207 is provided by infiltrating a glass cloth into a resin. Therefore, the reinforced resin layer 207 has a thickness thicker than the other resin layers 203 and 211 (for example, has a thickness of 35 μm). The thickness of the reinforced resin layer 207 can be set to 50 μm to 100 μm. The reinforced resin layer 207 has an opening 221 to expose a portion of the wiring 205. The openings 221 are formed by laser beam processing.

The via 208 is provided in the opening 221. The via 208 is integrally formed with the wiring 209 and has a connection to the lower end of the wiring 205. This wiring 209 is provided on one surface 207A of the reinforced resin layer 207. The wiring 209 is connected to the upper end of the via 208. For example, copper can be used as the material of the via 208 and the wiring 209.

The resin layer 211 is provided on the face 207A of the reinforced resin layer 207 so as to cover most of the wiring 209. The resin layer 211 has an opening 223 to expose a portion of the wiring 209.

The via 212 is provided in the opening 223. The via 212 is integrally formed with the electronic component mounting pad 213 and has a connection to the lower end of the wiring 209. The electronic component mounting pad 213 is provided on one surface 211A of the resin layer 211. The electronic component mounting pad 213 has a connection surface 213A for mounting an electronic component 250 (eg, a semiconductor wafer, a wafer capacitor, etc.). For example, copper can be used as the material for the via 212 and the electronic component mounting pad 213.

The solder resist layer 215 has an opening 225 to expose the connection surface 213A. The solder resist layer 215 is provided to cover the surface 211A of the resin layer 211.

The wiring board 200 has the reinforced resin layer 207 provided by infiltrating the glass cloth of the reinforcing member into the resin, and thus the strength of the wiring board 200 is increased, and the resin layers 203 and 211 and the dielectric layers 204 and 208 can be reduced. And the warpage of the wiring board 200 caused by the difference in thermal expansion coefficient between 212 and 209 and 209. (For example, refer to Patent Document 1).

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2007-96260

However, the wiring board 200 in the related art is provided with the reinforced resin layer 207 having a thickness thicker than the resins 203, 211 (for example, the thickness of the reinforced resin layer 207 is 50 μm to 100 μm) in order to reduce the resin layers. 203 and 211, the warpage of the wiring board 200 caused by the difference in thermal expansion coefficients between the dielectric layers 204, 208 and 212 and the wirings 205 and 209, and thus the dimension of the wiring board 200 in the thickness direction thereof Big; this is a problem.

Therefore, the reinforced resin layer 207 provided by infiltrating the glass cloth into the resin is expensive, so there is a problem that the cost of the wiring board 200 is increased.

Further, in order to form the opening 221 in the reinforced resin layer 207, it takes time for the laser to pass through the glass cloth, and thus there is a problem that the manufacturing cost of the wiring board 200 is increased.

An exemplary embodiment of the present invention provides a wiring board in which the size of the wiring board in the thickness direction can be miniaturized, the warpage of the wiring board can be reduced, and the cost of the wiring board can be reduced.

According to an aspect of the present invention, a wiring board includes: a first insulating layer; an electronic component mounting pad having a connecting surface connecting an electronic component, wherein the electronic component mounting pad is provided on the first insulating layer a layer for exposing the connection surface; a via, passing through a portion of the first insulating layer relative to the mounting portion of the electronic component, the via having an end connected to the mounting pad of the electronic component; a first wiring, Provided on the first insulating layer and connected to one opposite end of the dielectric layer; a second insulating layer deposited on the first insulating layer; and a second wiring provided on the second insulating layer and electrically Connected to the first wiring, wherein a portion of the first insulating layer placed between the electronic component mounting pad and the first wiring has a thickness smaller than one of the second insulating layers is placed on the first wiring and the first The thickness of the portion between the two wirings.

According to another aspect of the present invention, a wiring board includes: a first insulating layer; an electronic component mounting pad having a connecting surface connecting an electronic component, wherein the electronic component mounting pad is provided in the first insulating a layer passing through a portion of the first insulating layer corresponding to the mounting pad of the electronic component, the via having an end connected to the mounting pad of the electronic component; a first wiring provided at the first An insulating layer is connected to the opposite end of the dielectric layer; a second insulating layer is deposited on the first insulating layer; and a second wiring is provided on the second insulating layer and electrically connected to the first a wiring, wherein a portion of the first insulating layer disposed between the electronic component mounting pad and the first wiring has a thickness smaller than a portion of the second insulating layer disposed between the first wiring and the second wiring thickness of.

According to the present invention, the thickness of the portion of the first insulating layer placed between the electronic component mounting pad and the first wiring (the first insulating layer does not need to ensure insulation between the electronic component mounting pad and the first wiring) a portion of the characteristic) is set to be smaller than a thickness of a portion of the second insulating layer placed between the first wiring and the second wiring (the need for the second insulating layer to ensure the gap between the first wiring and the second wiring) Part of the insulation properties). Therefore, the size of the wiring board in the thickness direction thereof can be miniaturized and the warpage of the wiring board can be reduced (the first wiring, the second wiring, the dielectric layers, and the thermal expansion between the first and second insulating layers) Warpage caused by coefficient difference).

The warpage of the wiring board can be reduced without using a reinforced resin layer provided by infiltrating the resin by an expensive glass cloth which is difficult to form an opening. Therefore, the cost of the wiring board (including its manufacturing cost) can be reduced.

At the time of manufacture, it is difficult to make the thickness of the portion of the first insulating layer placed between the electronic component mounting pad and the first wiring less than 5 μm. If the thickness of the portion of the first insulating layer placed between the electronic component mounting pad and the first wiring is greater than the thickness of the portion of the second insulating layer placed between the first wiring and the second wiring, The warpage of the wiring board cannot be sufficiently reduced.

According to the present invention, the size of the wiring board in the thickness direction thereof can be miniaturized, the warpage of the wiring board can be reduced, and the cost of the wiring board can be reduced.

Other features and advantages will be apparent from the description, appended claims and claims.

Referring now to the drawings, specific examples of the invention are shown.

(first specific example)

Figure 2 is a cross-sectional view showing a wiring board in accordance with an embodiment of the present invention.

Referring to FIG. 2, the wiring board 10 of the specific example is a coreless board and has an insulating layer 17 of a first insulating layer, an electronic component mounting pad 18, via layers 19, 24 and 28, and a wiring 22 of a first wiring. The insulating layers 23 and 27 of the second insulating layer, the wirings 25 and 29 of the second wiring, and a solder resist layer 31.

The insulating layer 17 is used to internally place the electronic component pads 18 on which the electronic components 11 are mounted and the dielectric layers 19 and the insulating layer on which the wirings 22 are disposed. One surface 17A of the insulating layer 17 (the surface on which the electronic component 11 is mounted) is approximately flush with the connection surface 18A of the electronic component mounting pads 18. The insulating layer 17 forms an opening 35 for passing through the portion of the insulating layer 17 relative to the electronic component mounting pads 18. The thickness of the portion of the insulating layer 17 between the wiring 22 provided on the surface 17B of the insulating layer 17 (the surface on the opposite side of the surface 17A of the insulating layer 17) T ₁ line is formed smaller than the insulating layer 23 to stand in the wire 22 and the thickness of the portion 25 of the wire T ₂ and is smaller than the insulating layer is placed 27 of a thickness to the wiring 25 and the portion 29 of the wires T ₃ of .

Therefore, the insulating layer 17 is placed between the wiring 22 provided on the surface 17B of the insulating layer 17 (the surface on the opposite side of the surface 17A of the insulating layer 17). thickness portion T ₁ of the line is formed smaller than the insulating layer is placed on the wire 22 and the thickness of the portion 25 of the wire T ₂ and is smaller than the insulating layer is placed 27 of the portion to the wiring 25 and the wiring 29 of the 23 of the Thickness T ₃ . Therefore, the size of the wiring board 10 in the thickness direction thereof can be miniaturized and the warpage of the wiring board 10 can be reduced (due to the interlayers 19, 24, and 28, the wirings 22, 25, and 29, and the like) Warpage caused by the difference in thermal expansion coefficient between layers 23 and 27). It is technically difficult to make the thickness T _{1 of} the insulating layer 17 smaller than 5 μm at the time of manufacture. If the thickness of the insulating layer 17 so that T ₁ is greater than the thickness of the insulating layer 23 and the thickness T ₂ of the insulating layer 27 of T _3, can not sufficiently reduce the warpage of the wiring board 10.

Since the electronic component mounting pad 18 and the wiring 22 are connected by the dielectric layer 19, if the thickness T _{1 of} the insulating layer 17 is reduced, the electrical characteristics of the wiring board 10 are hardly affected. If the wiring arranged on the face 17A of the insulating layer 17 is formed on the face 17A, short-circuiting from the wiring 22 formed on the face 17B of the insulating layer 17 is considered, and the electrical characteristics are considered. From a design point of view, it is difficult to reduce the thickness T _{1 of} the insulating layer 17. However, in the wiring board 10 of this specific example, only the electronic component mounting pads 18 are provided on the face 17A of the insulating layer 17 and are directly connected to the wiring 22 by the vias 19. The portion of the electronic component mounting pad 18 below. Therefore, it is not necessary to provide wiring arranged on the face 17A of the insulating layer 17 to connect the electronic component mounting pads 18 and the wiring 22. Therefore, in the wiring board 10 of this specific example, if the thickness T _{1 of} the insulating layer 17 is reduced, problems concerning short-circuit or electrical characteristics do not occur. Therefore, the thickness T _{1 of} the insulating layer 17 can be appropriately adjusted by adopting a method of counter warping.

Preferably, the electronic component mounting pad 18 and the wiring 22 connected to the other electronic component mounting pad 18 are formed in a state where the electronic component mounting pad 18 and the wiring 22 do not overlap each other when viewed from above. Due to such a structure, even if the thickness T _{1 of} the insulating layer 17 is reduced, the insulating property between the electronic component mounting pad 18 and the wiring 22 connected to the other electronic component mounting pad 18 can be ensured.

The warpage of the wiring board 10 can be reduced without providing the reinforced resin layer 207 (see FIG. 1) which is expensive and difficult to process in order to reduce the warpage of the wiring board 200 in the wiring board 200 of the related art. Therefore, the cost of the wiring board 10 (including its manufacturing cost) can be reduced. For example, a resin layer made of an insulating resin such as an epoxy resin or a polyimide resin can be used as the insulating layer 17.

The thicknesses T ₂ and T ₃ of the insulating layers 23 and 27 set to 25 μm, 30 μm, 35 μm, 40 μm, and 45 μm and the insulating layers set to 0 μm, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, and 35 μm will be discussed. The result of the warpage amount of the wiring board 10 of the thickness T ₁ of 17 was simulated. Table 1 shows the relationship between the thickness T _{1 of} the insulating layer 17 and the warpage of the wiring board. Fig. 13 is a graph showing the relationship between the thickness T _{1 of} the insulating layer 17 and the warpage of the wiring board.

The material of the wiring is copper and the insulating layer (insulating layers 17, 23, 27) is made of epoxy resin, and the thicknesses T ₂ and T ₃ of the insulating layers 23 and 27 are set to 25 μm, 30 μm, 35 μm, 40 μm. The simulation was carried out under the conditions of 45 μm and the thickness T ₁ of the insulating layer 17 set to 0 μm, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, and 35 μm.

In Table 1, the amount of warpage of the wiring board when there is no warpage is zero, and the concave warpage is represented by a negative number while the convex warpage is represented by a positive number. A thickness T _{1 of} 0 μm indicates a case where the insulating layer 17 is not provided (the electronic component mounting pad 18 is a part of the wiring 22).

From these results, it is recognized that if the allowable range of the warpage of the wiring board 10 is set to 200 μm or less (absolute value), it is necessary to select the thickness T _{1 of} the insulating layer 17 in the range of 5 μm to 20 μm. It is technically difficult to make the thickness T _{1 of} the insulating layer 17 smaller than 5 μm at the time of manufacture. If the thickness T _{1 of} the insulating layer 17 is made larger than 20 μm, the allowable range (200 μm) of the warpage of the wiring board 10 is exceeded.

However, in view of mounting the electronic component on the wiring board or mounting the wiring board on the mother board, the amount of warpage of the wiring board 10 is preferably less than or equal to 80 μm (absolute value). Therefore, it can be recognized that if the allowable range of warpage of the wiring board 10 is set to be less than or equal to 80 μm, it is necessary to select the thickness T _{1 of} the insulating layer 17 in the range of 5 μm to 15 μm.

Further, it is admitted that the thicknesses T ₂ and T _{3 of} the insulating layers 23 and 27 are preferably set to 25 μm to 45 μm. In addition to the warpage of the wiring board or the miniaturization of the thickness direction of the wiring board, the thicknesses T ₂ and T _{3 of} the insulating layers 23 and 27 are more preferably set to 30 μm to 40 μm in consideration of the insulating property.

Although the above-described simulation results of the warpage amount of the wiring board have been described, the actually manufactured wiring board also exhibits a warpage reducing effect corresponding to the simulation results.

Each of the electronic component mounting pads 18 has a connecting surface 18A for mounting (connecting) the electronic components 11. The electronic component mounting mat 18 is placed internally in the insulating layer 17 such that the connecting surface 18A and the face 17A of the insulating layer 17 become substantially flush with each other. For example, a gold/palladium having a gold layer (for example, 0.05 μm thick), a palladium layer (for example, 0.05 μm thick), and a nickel layer (for example, 5 μm thick) may be sequentially deposited from the joint face 18A. / Nickel deposited film is used as the electronic component mounting pad 18. In this case, the electronic component 11 is mounted on the gold layer.

The dielectric layer 19 is provided in the opening 35 formed in the insulating layer 17. The via 19 has an end connected to the electronic component mounting pad 18. The via 19 is integrally formed with the wiring 22 to electrically connect the electronic component mounting pad 18 and the wiring 22.

The wiring 22 is provided on the face 17B of the insulating layer 17 (the face of the insulating layer 17 on the opposite side of the face 17A). The wiring 22 is formed integrally with the dielectric layer 19. For example, the via 19 and the wiring 22 can be formed in accordance with a half-additive method. For example, copper can be used as the material of the dielectric layer 19 and the wiring 22.

The insulating layer 23 is provided on the face 17B of the insulating layer 17 so as to cover most of the wiring 22. The insulating layer 23 is used to internally place the dielectric layers 24 and the insulating layer forming the wiring 25. The insulating layer 23 has an opening 36 to expose a portion of the wiring 22. The opening 36 is provided to configure the via 24. The wiring 25 is disposed on one surface 23A of the insulating layer 23 (the surface on the side opposite to the side of the insulating layer 23 in contact with the insulating layer 17). Since it is necessary to ensure the insulating property between the wiring 22 and the wiring 25, the thickness T ₂ of the portion of the insulating layer 23 placed between the wiring 22 and the wiring 25 is formed to be larger than the thickness T _{1 of} the insulating layer 17. Specifically, the thickness T ₂ of the portion of the insulating layer 23 placed between the wiring 22 and the wiring 25 can be set to, for example, 25 μm to 45 μm. For example, a resin layer made of an insulating resin such as an epoxy resin or a polyimide resin can be used as the insulating layer 23.

The via 24 is provided in the opening 36 formed in the insulating layer 23. The via 24 has an end connected to the wiring 22. The via 24 is integrally formed with the wiring 25 provided on the face 23A of the insulating layer 23 to electrically connect the wiring 22 and the wiring 25.

The wiring 25 is provided on the face 23A of the insulating layer 23 (the face on the side opposite to the side of the insulating layer 23 in contact with the insulating layer 17). The wiring 25 is formed integrally with the via layer 24. For example, the via 24 and the wiring 25 can be formed in accordance with a half additive process. For example, copper can be used as the material of the dielectric layer 24 and the wiring 25.

The insulating layer 27 is provided on the face 23A of the insulating layer 23 so as to cover most of the wiring 25. The insulating layer 27 is used to internally place the dielectric layers 28 and the insulating layer forming the wiring 29. The insulating layer 27 has an opening 38 to expose a portion of the wiring 25. The opening 38 is provided to configure the via 28. The wiring 29 is disposed on one surface 27A of the insulating layer 27 (the surface on the side opposite to the side of the insulating layer 27 in contact with the insulating layer 23). Since it is necessary to ensure the insulating property between the wiring 25 and the wiring 29, the thickness T ₃ of the portion of the insulating layer 27 placed between the wiring 25 and the wiring 29 is formed to be larger than the thickness T _{1 of} the insulating layer 17. Specifically, the thickness T ₃ of the portion of the insulating layer 27 placed between the wiring 25 and the wiring 29 can be set to, for example, 25 μm to 45 μm. For example, a resin layer made of an insulating resin such as an epoxy resin or a polyimide resin can be used as the insulating layer 27.

The via 28 is provided in the opening 38 formed in the insulating layer 27. The via 28 has an end connected to the wiring 25. The via 28 is integrally formed with the wiring 29 provided on the face 27A of the insulating layer 27 to electrically connect the wiring 25 and the wiring 29.

The wiring 29 is provided on the face 27A of the insulating layer 27 (the face on the side opposite to the side of the insulating layer 27 in contact with the insulating layer 23). The wiring 29 is placed to face a portion of the wiring 25 via the insulating layer 27. The wiring 29 is formed integrally with the via layer 28. The wiring 29 has a pad portion 41 for arranging an external connection terminal 14 (for example, a solder ball). The pad portion 41 is a portion that is electrically connected to the mounting plate 13 of a motherboard or the like via the external connection terminal 14. The wiring 29 is formed integrally with the via layer 28. For example, the via 28 and the wiring 29 can be formed in accordance with a half additive process. For example, copper can be used as the material of the via 28 and the wiring 29.

In the drawing, it is shown that only the pad portion 41 is provided on the face 27A of the insulating layer 27; however, other portions of the wiring 29 are actually formed on the face 27A of the insulating layer 27 (the wiring 29) A portion other than the pad portion 41). Furthermore, the diameter of the electronic component mounting pad 18 is, for example, in the range of 50 to 150 μm, whereas the diameter of the pad portion 41 for the external connection end is, for example, in the range of 200 to 1000 μm. Therefore, it is shown in the drawing that, when viewed from above, one pad portion 41 and the wiring 25 connected to the other pad portion 41 do not overlap each other; however, when viewed from above, a pad portion 41 is connected to The wirings 25 of the other pad portion 41 are actually partially overlapped with each other. Due to this fact, it is impossible to make the thickness T _{3 of} the insulating layer 27 small in order to ensure insulation between the wiring 29 (including the pad portion 41 formed on the face 27A of the insulating layer 27) and the wiring 25. characteristic.

The solder resist layer 31 is provided on the face 27A of the insulating layer 27 so as to cover a portion of the wiring 29 other than the pad portion 41. The solder resist layer 31 has an opening 31A to expose the pad portions 41.

According to the wiring board of the specific example, the insulating layer 17 is placed between the electronic component mounting pad 18 and the wiring 22 (the insulating layer 17 does not need to ensure insulation between the electronic component mounting pad 18 and the wiring 22). The thickness T ₁ of the characteristic portion is set to be smaller than a portion of the insulating layer 23 placed between the wiring 22 and the wiring 25 (the portion of the insulating layer required to ensure the insulating property between the wiring 22 and the wiring 25) The thickness T _{2 is} set to be smaller than a portion of the insulating layer 27 placed between the wiring 25 and the wiring 29 (which are opposite to each other with the insulating layer 27 therebetween) (the need for the insulating layer ensures the wiring 25 and the The thickness T ₃ of the portion of the insulating property between the wirings 29). Therefore, the size of the wiring board 10 in the thickness direction thereof can be miniaturized and the warpage of the wiring board 10 can be reduced.

The warpage of the wiring board 10 can be reduced without using the reinforced resin layer 207 (see Fig. 1) provided by infiltrating the expensive glass cloth which is difficult to form an opening into the resin, so that the cost of the wiring board 10 can be reduced. (including its manufacturing costs).

Fig. 3A is a cross-sectional view showing a wiring board according to a first modified embodiment of the specific example of the present invention. In Fig. 3A, components identical to the wiring board 10 shown in Fig. 2 are denoted by the same reference numerals.

Referring to FIG. 3A, in addition to providing an insulating layer 51 in place of the insulating layer 17 provided in the wiring board 10 of this specific example, a wiring board 50 of the first modified embodiment of this specific example is identical to the wiring. Board 10.

The insulating layer 51 is disposed except for the portion of the insulating layer 17 provided in the wiring board 10 placed on the connecting surface 18A to the one surface 18B of the electronic component mounting pad 18 (on the opposite side of the connecting surface 18A). The insulating layer 17 is formed like this. One face 51A of the insulating layer 51 is approximately flush with the face 18B of the electronic component mounting pad 18. A wiring 22 and an insulating layer 23 are provided on one surface 51B of the insulating layer 51 (the surface of the insulating layer 51 placed on the opposite side of the surface 51A).

The above wiring board 50 can provide advantages similar to those of the foregoing wiring board 10.

Fig. 3B is a cross-sectional view showing a wiring board according to a second modified embodiment of the specific example of the present invention. In Fig. 3B, components identical to the wiring board 50 shown in Fig. 3A are denoted by the same reference numerals.

Referring to FIG. 3B, in addition to further providing a solder resist layer 56 in the configuration of the wiring board 50 of the first modified embodiment of the specific example, a wiring board 55 of the second modified embodiment of the specific example is identical to the Wiring board 50.

The solder resist layer 56 is provided on one surface 51A of an insulating layer 51. The solder mask 56 has an opening 56A for receiving the electronic component mounting pad 18. The solder mask 56 exposes the connection faces 18A of the electronic component mounting pads 18. The thickness of the solder mask 56 is formed to be approximately equal to the thickness of the electronic component mounting pad 18. A resin layer made of an epoxy resin, a polyimide resin, an acrylic resin or the like can be used as the solder resist layer 56. In the wiring board 55, the insulating layer 51 and the solder resist layer 56 correspond to the first insulating layer as described in the patent application.

A photoresist layer 56 having an opening 56A may be formed in place of the steps shown in FIGS. 4 and 5 to be described later, instead of forming a photoresist film 62 for electroplating and then forming electronic components in the openings 56A. The mounting pad 18 and then the steps shown in FIGS. 7 to 12 to be described later are carried out in a state where the solder resist layer 56 is left to manufacture the above-described wiring board 55.

4 to 12 are views showing a manufacturing procedure of a wiring board according to this specific example of the present invention. In FIGS. 4 to 12, components identical to the wiring board 10 of this specific example are denoted by the same component symbols.

A method of manufacturing the wiring board 10 of this specific example will be described with reference to Figs. First, in the step shown in Fig. 4, a photoresist film 62 for electroplating having an opening 62A is formed on one surface 61A of a substrate 61 having conductivity. At this time, the openings 62A are formed to expose portions of the face 61A of the substrate 61 corresponding to the formation regions of the electronic component mounting pads 18. Specifically, the photoresist film 62 having the openings 62A is formed, for example, by applying a photoresist and then exposing and developing the photoresist. For example, a metal plate (for example, a copper plate), a metal foil (for example, copper foil), or the like can be used as the substrate 61.

Next, in the step shown in FIG. 5, an electronic component mounting pad 18 is formed on a portion of the substrate 61 exposed to the openings 62A. Specifically, a gold/palladium/nickel deposition film is used as the electronic component mounting pad 18, for example, on the face 61A of the substrate 61 by electrolytic plating using the substrate 61 as a feed layer. A gold layer (e.g., 0.05 μm thick), a palladium layer (e.g., 0.05 μm thick), and a nickel layer (e.g., 5 μm thick) are sequentially deposited, thereby forming the electronic component mounting pads 18. As the electronic component mounting pads 18, a gold/palladium/nickel/copper deposition film may be used instead of the gold/palladium/nickel deposition film.

Next, in the step shown in FIG. 6, the photoresist film 62 shown in FIG. 5 is removed. Next, in the step shown in FIG. 7, an insulating layer 17 having openings 35 is formed, each opening 35 exposing a portion of the electronic component mounting pad 18. For example, a resin layer made of an insulating resin such as an epoxy resin or a polyimide resin can be used as the insulating layer 17. For example, the insulating layer can be formed by depositing a resin film made of an epoxy resin, a polyimide resin, or the like. For example, the openings 35 can be formed by laser beam processing.

The thickness T of the portion of the insulating layer 17 between the wiring 22 provided on the surface 17B of the insulating layer 17 (the surface on the opposite side of the surface 17A of the insulating layer 17) is provided. ₁ is smaller than a line formed of the insulating layer 23 is placed in the thickness of the wiring portion 25 of the wiring ₂₂₂ and T are placed less than one insulating layer 27 of the wiring 25 in the thickness of the wiring portion 29 of T _3.

Therefore, the insulating layer 17 is placed between the wiring 22 provided on the surface 17B of the insulating layer 17 (the surface on the opposite side of the surface 17A of the insulating layer 17). thickness portion T ₁ of the line is formed smaller than the insulating layer is placed on the wire 22 and the thickness of the portion 25 of the wire T ₂ and is smaller than the insulating layer is placed 27 of the portion to the wiring 25 and the wiring 29 of the 23 of the Thickness T ₃ . Therefore, the size of the wiring board 10 in the thickness direction thereof can be miniaturized and the warpage of the wiring board 10 can be reduced (due to the interlayers 19, 24, and 28, the wirings 22, 25, and 29, and the insulating layers 23) And the warpage caused by the difference in thermal expansion coefficient between 27). It is technically difficult to make the thickness T _{1 of} the insulating layer 17 smaller than 5 μm at the time of manufacture. If the thickness of the insulating layer 17 so that T ₁ is greater than the thickness of the insulating layer 23 and the thickness T ₂ of the insulating layer 27 of T _3, can not sufficiently reduce the warpage of the wiring board 10.

Since the electronic component mounting pad 18 and the wiring 22 are connected by the dielectric layer 19, if the thickness T _{1 of} the insulating layer 17 is reduced, the electrical characteristics of the wiring board 10 are hardly affected. If the wiring arranged on the face 17A of the insulating layer 17 is formed on the face 17A, short-circuiting from the wiring 22 formed on the face 17B of the insulating layer 17 is considered, and the electrical characteristics are considered. From a design point of view, it is difficult to reduce the thickness T _{1 of} the insulating layer 17. However, in the wiring board 10 of this specific example, only the electronic component mounting pads 18 are provided on the face 17A of the insulating layer 17 and are directly connected to the wiring 22 by the vias 19. The portion of the electronic component mounting pad 18 below. Therefore, it is not necessary to provide wiring arranged on the face 17A of the insulating layer 17 to connect the electronic component mounting pads 18 and the wiring 22. Therefore, in the wiring board 10 of this specific example, if the thickness T _{1 of} the insulating layer 17 is reduced, problems concerning short-circuit or electrical characteristics do not occur. Therefore, the thickness T _{1 of} the insulating layer 17 can be appropriately adjusted by adopting a method of counter warping.

The warpage of the wiring board 10 can be reduced without providing the reinforced resin layer 207 (see FIG. 1) which is expensive and difficult to process in order to reduce the warpage of the wiring board 200 in the wiring board 200 of the related art. Therefore, the cost of the wiring board 10 (including its manufacturing cost) can be reduced.

If the allowable range of the warpage of the wiring board 10 is set to be less than or equal to 80 μm, it is necessary to select the thickness T _{1 of} the insulating layer 17 in the range of 5 μm to 15 μm. It is technically difficult to make the thickness T _{1 of} the insulating layer 17 smaller than 5 μm at the time of manufacture. If the thickness T _{1 of} the insulating layer 17 is made larger than 15 μm, the allowable range (80 μm) of the warpage of the wiring board 10 is exceeded.

Next, in the step shown in FIG. 8, the dielectric layers 19 and the wirings 22 are simultaneously formed. For example, the dielectric layers 19 and the wiring 22 are formed in accordance with a half-addition method. Specifically, a sub-layer (for example, a copper layer) is formed in accordance with an electrolytic plating method so as to cover the upper side of the structure shown in FIG. 7 and then on the seed layer (not shown) corresponding to the formation of the wiring 22. A photoresist film (not shown) having an opening (not shown) is formed in a portion of the region. Next, a plating film (eg, a copper plating film) is grown on the portion of the seed layer exposed to the openings by electrolytic plating using the seed layer as a feed layer and then removed. The photoresist film, and then the seed layer not covered by the plating film, is removed, thereby simultaneously forming the dielectric layer 19 and the wiring 22.

Next, in the step shown in FIG. 9, the insulating layer 23 having the openings 36, the vias 24, and the wiring 25 are sequentially formed in accordance with a technique similar to the steps described in the previous FIGS. 7 and 8. For example, a resin layer made of an insulating resin such as an epoxy resin or a polyimide resin can be used as the insulating layer 23. The thickness T ₂ of the portion of the insulating layer 23 placed between the wiring 22 and the wiring 25 is formed to be larger than the thickness T _{1 of} the insulating layer 17. In particular, the thickness T _{2 of} the insulating layer 23 can be set to, for example, 25 μm to 45 μm. For example, copper can be used as the material of the dielectric layer 24 and the wiring 25.

Next, in the step shown in FIG. 10, the insulating layer 27 having the openings 38, the vias 28, and the wiring 29 are sequentially formed in accordance with a technique similar to the steps described in the previous FIGS. 7 and 8. For example, a resin layer made of an insulating resin such as an epoxy resin or a polyimide resin can be used as the insulating layer 27. The thickness T ₃ of the portion of the insulating layer 27 placed between the wiring 25 and the wiring 29 is formed to be larger than the thickness T _{1 of} the insulating layer 17. Specifically, the thickness T _{3 of} the insulating layer 27 can be set to, for example, 25 μm to 45 μm. For example, copper can be used as the material of the via 28 and the wiring 29.

Next, in the step shown in Fig. 11, a solder resist layer 31 having an opening 31A is formed on one surface 27A of the insulating layer 27 so as to cover the wiring 29 other than the pad portion 41. The openings 31A are formed to expose the pad portions 41.

Next, in the step shown in Fig. 12, the substrate 61 shown in Fig. 11 is removed. Thus, the wiring board 10 is manufactured. In Fig. 12, the wiring board 10 shown in Fig. 2 is vertically turned upside down for the manufacturing processes.

While the invention has been described with respect to the preferred embodiments of the present invention, it is understood that the invention is not limited to the specific embodiments and various modifications and changes can be made without departing from the spirit and scope of the invention.

For example, the wiring boards 10, 50, and 55 may be used as a PGA (Pin Grid Array) having pins connected to the pad portions 41 and an external connection using the pad portions 41. LGA (substrate grid array) and a BGA (spherical grid array).

The invention is applicable to a coreless board.

10. . . Wiring board

11. . . Electronic component

13. . . Mounting plate

14. . . External connection

17. . . Insulation

17A. . . surface

17B. . . surface

18. . . Electronic component mounting mat

18A. . . Connection surface

18B. . . surface

19. . . Interlayer

twenty two. . . wiring

twenty three. . . Insulation

23A. . . surface

twenty four. . . Interlayer

25. . . wiring

27. . . Insulation

27A. . . surface

28. . . Interlayer

29. . . wiring

31. . . Solder mask

31A. . . Opening

35. . . Opening

36. . . Opening

38. . . Opening

41. . . Solder pad

50. . . Wiring board

51. . . Insulation

51A. . . surface

51B. . . surface

55. . . Wiring board

56. . . Solder mask

56A. . . Opening

61. . . Substrate

61A. . . surface

62. . . Photoresist film

62A. . . Opening

200. . . Wiring board

201. . . Solder mask

201A. . . surface

201B. . . surface

202. . . Solder pad

202A. . . Connection surface

202B. . . surface

203. . . Resin layer

203A. . . surface

204. . . Interlayer

205. . . wiring

207. . . Reinforced insulation

207A. . . surface

208. . . Interlayer

209. . . wiring

211. . . Resin layer

211A. . . surface

212. . . Interlayer

213. . . Electronic component mounting mat

213A. . . Connection surface

215. . . Solder mask

218. . . Penetration

219. . . Opening

221. . . Opening

223. . . Opening

225. . . Opening

250. . . Electronic component

260. . . Mounting plate

261. . . External connection

T ₁ . . . thickness

T ₂ . . . thickness

T ₃ . . . thickness

In the drawings,

Figure 1 is a cross-sectional view of a wiring board in a related art;

Figure 2 is a cross-sectional view of a wiring board in accordance with one embodiment of the present invention;

Figure 3A is a cross-sectional view showing a wiring board according to a first modified embodiment of the specific example of the present invention;

Figure 3B is a cross-sectional view showing a wiring board according to a second modified embodiment of the specific example of the present invention;

Figure 4 is a view showing a manufacturing procedure of a wiring board according to this specific example of the present invention (first);

Figure 5 is a diagram (second) showing a manufacturing procedure of a wiring board according to this specific example of the present invention;

Figure 6 is a view showing a manufacturing procedure of a wiring board according to this specific example of the present invention (third);

Figure 7 is a view showing a manufacturing procedure of a wiring board according to this specific example of the present invention (fourth);

Figure 8 is a view showing a manufacturing procedure of a wiring board according to this specific example of the present invention (fifth);

Figure 9 is a view showing a manufacturing procedure of a wiring board according to this specific example of the present invention (sixth);

Figure 10 is a view showing a manufacturing procedure of a wiring board according to this specific example of the present invention (seventh);

Figure 11 is a view showing the manufacturing procedure of the wiring board according to this specific example of the present invention (eighth);

Figure 12 is a diagram (ninth) showing a manufacturing procedure of a wiring board according to this specific example of the present invention;

Figure 13 is a graph showing the relationship between the thickness of the insulating layer and the warpage of the wiring board.

10. . . Wiring board

11. . . Electronic component

13. . . Mounting plate

14. . . External connection

17. . . Insulation

17A. . . surface

17B. . . surface

18. . . Electronic component mounting mat

18A. . . Connection surface

19. . . Interlayer

twenty two. . . wiring

twenty three. . . Insulation

23A. . . surface

twenty four. . . Interlayer

25. . . wiring

27. . . Insulation

27A. . . surface

28. . . Interlayer

29. . . wiring

31. . . Solder mask

31A. . . Opening

35. . . Opening

36. . . Opening

38. . . Opening

41. . . Solder pad

T ₁ , T ₂ , T ₃ . . . thickness

Claims (8)

A wiring board comprising a plurality of insulating layers and a wiring layer, comprising: a first insulating layer including a surface as a surface of the wiring board and a back surface thereof; and an electronic component mounting pad having a connection surface connecting the electronic components The connection surface is buried in the first insulating layer so as to be exposed on the surface of the first insulating layer, and the back surface and the side surface are in direct contact with the first insulating layer; the interlayer is connected to the first insulating layer The back surface is provided with an opening exposing the back surface of the electronic component mounting pad, and is disposed in the opening in such a manner as to pass through the portion of the first insulating layer facing the electronic component mounting pad, and one end thereof and the electron a back surface of the component mounting pad is directly connected; a first wiring is disposed on a back surface of the first insulating layer and connected to an opposite end of the dielectric layer; a second insulating layer is deposited on the first insulating layer; and a second wiring, Provided on the second insulating layer and electrically connected to the first wiring, wherein a thickness of a portion of the first insulating layer disposed between the electronic component mounting pad and the first wiring is smaller than the second The thickness of the edge layer is disposed between the portion of the second wiring in the first wiring. The wiring board of claim 1, wherein a thickness of the portion of the first insulating layer between the electronic component mounting pad and the first wiring is 5 μm to 20 μm. The wiring board of claim 1 or 2, wherein the first insulating layer is a resin layer. The wiring board of claim 1 or 2, wherein a portion of the second insulating layer placed between the first wiring and the second wiring has a thickness of 25 μm to 45 μm. A wiring board comprising a plurality of insulating layers and a wiring layer, comprising: a first insulating layer including a surface as a surface of the wiring board and a back surface thereof; and an electronic component mounting pad having a connection surface connecting the electronic components The connection surface is disposed on the first insulating layer in a manner exposed on the surface of the first insulating layer, and the back surface thereof is in direct contact with the first insulating layer; the interlayer is on the back surface of the first insulating layer Providing an opening exposing a back surface of the mounting pad of the electronic component, and disposing a portion of the first insulating layer opposite to the mounting portion of the electronic component in the opening, and mounting one end thereof with the electronic component a back surface of the pad is directly connected; a first wiring is disposed on a back surface of the first insulating layer and connected to an opposite end of the dielectric layer; a second insulating layer is deposited on the first insulating layer; and a second wiring is provided on The second insulating layer is electrically connected to the first wiring, wherein a thickness of the portion of the first insulating layer disposed between the electronic component mounting pad and the first wiring is smaller than the second insulating layer Thickness of the first wiring disposed between a portion of the second wiring. The wiring board of claim 5, wherein the first insulating layer The thickness of the portion placed between the electronic component mounting pad and the first wiring is 5 μm to 20 μm. The wiring board of claim 5 or 6, wherein the first insulating layer is a resin layer. The wiring board of claim 5 or 6, wherein a thickness of a portion of the second insulating layer placed between the first wiring and the second wiring is 25 μm to 45 μm.