JP2009111358A - Wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board whose size in the thickness direction of the wiring board can be made small, and whose cost can be reduced, in the wiring board. <P>SOLUTION: The thickness T<SB>1</SB>of the portion, which is placed between an electronic component mounting pad 18 and wiring 22, of an insulating layer 17 (insulating layer in which the electronic component mounting pads 18 are placed) is set to be smaller than the thickness T<SB>2</SB>of the portion, which is placed between the wiring 22 and wiring 25, of an insulating layer 23. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring board, and more particularly to a wiring board capable of reducing the size in the thickness direction of the wiring board and reducing the cost.

  2. Description of the Related Art Conventionally, there is a wiring board called a coreless board as a wiring board having a reduced size in the thickness direction. Since the coreless substrate does not have a core substrate, warping occurs because the strength is low compared to a buildup wiring substrate with a core substrate (a wiring substrate in which buildup structures are formed on both sides of the core substrate). Cheap. A wiring board 200 as shown in FIG. 1 can reduce the warpage of the coreless board.

  FIG. 1 is a cross-sectional view of a conventional wiring board.

  Referring to FIG. 1, a conventional wiring board 200 includes solder resist layers 201 and 215, pads 202, resin layers 203 and 211, vias 204, 208 and 212, wirings 205 and 209, and reinforcing insulation. A layer 207 and an electronic component mounting pad 213 are provided.

  The solder resist layer 201 has a through portion 218 for disposing the pad 202. The pad 202 has a connection surface 202A on which the external connection terminal 261 is disposed. The pad 202 is provided in the penetrating portion 218 so that the connection surface 202A of the pad 202 and the surface 201A of the solder resist layer 201 are substantially flush with each other. The pad 202 is a pad that is electrically connected to a mounting substrate 260 (for example, a mother board) via the external connection terminal 261. As a material of the pad 202, for example, an Au / Ni laminated film in which an Au layer and a Ni layer are sequentially laminated can be used.

  The resin layer 203 is provided so as to cover the surface 201B of the solder resist layer 201 (the surface of the solder resist layer 201 opposite to the surface 201A) and most of the surface 202B of the pad 202. The resin layer 203 has an opening 219 that exposes a part of the surface 202B of the pad 202.

  The via 204 is provided in the opening 219. The via 204 is configured integrally with the wiring 205, and its lower end is connected to the pad 202. The wiring 205 is provided on the surface 203 </ b> A of the resin layer 203. The wiring 205 is connected to the upper end of the via 204. As a material of the via 204 and the wiring 205, for example, Cu can be used.

  The reinforcing resin layer 207 is provided on the surface 203 </ b> A of the resin layer 203 so as to cover most of the wiring 205. The reinforcing resin layer 207 is configured such that a glass cloth, which is a reinforcing member, is impregnated with a resin. Therefore, the reinforcing resin layer 207 is thicker than the other resin layers 203 and 211 (for example, 35 μm). The thickness of the reinforcing resin layer 207 can be, for example, 50 μm to 100 μm. The reinforcing resin layer 207 has an opening 221 that exposes a part of the wiring 205. The opening 221 is formed by laser processing, for example.

  The via 208 is provided in the opening 221. The via 208 is configured integrally with the wiring 209, and its lower end is connected to the wiring 205. The wiring 209 is provided on the surface 207 </ b> A of the reinforcing resin layer 207. The wiring 209 is connected to the upper end of the via 208. As a material of the via 208 and the wiring 209, for example, Cu can be used.

  The resin layer 211 is provided on the surface 207A of the reinforcing resin layer 207 so as to cover most of the wiring 209. The resin layer 211 has an opening 223 that exposes a part of the wiring 209.

  The via 212 is provided in the opening 223. The via 212 is formed integrally with the electronic component mounting pad 213, and its lower end is connected to the wiring 209. The electronic component mounting pad 213 is provided on the surface 211 </ b> A of the resin layer 211. The electronic component mounting pad 213 has a connection surface 213A on which an electronic component 250 (for example, a semiconductor chip or a chip capacitor) is mounted. As a material of the via 212 and the electronic component mounting pad 213, for example, Cu can be used.

  The solder resist layer 215 has an opening 225 that exposes the connecting portion 213A. The solder resist layer 215 is provided so as to cover the surface 211A of the resin layer 211.

Since the wiring board 200 having the above-described configuration includes the reinforcing resin layer 207 obtained by impregnating a glass cloth serving as a reinforcing member with a resin, the strength is improved, and the resin layers 203 and 211 and the via 204 are improved. , 208, 212 and wirings 205, 209 can reduce the warpage of the wiring board 200 caused by the difference in thermal expansion coefficient (see, for example, Patent Document 1).
JP 2007-96260 A

  However, in the conventional wiring board 200, the reinforcing resin layer 207 (thickness is, for example, 50 μm to 100 μm) thicker than the resin layers 203 and 211 is provided, so that the resin layers 203 and 211 and the via 204 are formed. , 208, 212 and wirings 205, 209, the warpage of the wiring board 200 caused by the difference in thermal expansion coefficient is reduced, and thus there is a problem that the size in the thickness direction of the wiring board 200 increases.

  Further, the reinforcing resin layer 207 in which the glass cloth is impregnated with the resin is expensive, and there is a problem that the cost of the wiring board 200 increases.

  Further, when the opening 221 is formed in the reinforcing resin layer 207, it takes time for the laser to penetrate the glass cloth, so that there is a problem that the manufacturing cost of the wiring board 200 increases.

  Therefore, the present invention has been made in view of the above-described problems, and provides a wiring board capable of reducing the warping of the wiring board by reducing the size in the thickness direction of the wiring board and reducing the cost. For the purpose.

  According to one aspect of the present invention, the first insulating layer has a connection surface to which an electronic component is connected, and is provided on one surface side of the first insulating layer so that the connection surface is exposed. The electronic component mounting pad is provided so as to pass through the first insulating layer at a portion facing the electronic component mounting pad, and one end thereof is connected to the electronic component mounting pad. A via, a first wiring provided on the other surface side of the first insulating layer, connected to the other end of the via, and laminated on the other surface side of the first insulating layer A wiring board comprising: a second insulating layer; and a second wiring provided in the second insulating layer and electrically connected to the first wiring, wherein the electronic component mounting pad And the thickness of the first insulating layer in the portion disposed between the first wiring and the first wiring Wiring board, characterized in that less than the thickness of the second insulating layer disposed portion is provided between the second wiring.

  According to the present invention, a portion of the first insulating layer (between the electronic component mounting pad and the first wiring is secured between the electronic component mounting pad and the first wiring). The thickness of the first insulating layer of the unnecessary portion is set to the thickness of the second insulating layer of the portion disposed between the first wiring and the second wiring (the first wiring and the second wiring). The thickness of the wiring board is reduced by making it thinner than the insulating layer that is necessary to ensure insulation between the wiring and the warping of the wiring board (first wiring, second wiring). Wiring and warpage due to a difference in thermal expansion coefficient between the via and the first and second insulating layers can be reduced.

  In addition, since it is possible to reduce the warping of the wiring board without using a reinforcing resin layer in which a resin is impregnated with an expensive glass cloth which is difficult to form an opening, the cost of the wiring board (the manufacturing cost is also reduced). Including) can be reduced.

  Note that it is difficult in manufacturing to make the thickness of the first insulating layer in the portion disposed between the electronic component mounting pad and the first wiring thinner than 5 μm. In addition, the thickness of the first insulating layer in the portion disposed between the electronic component mounting pad and the first wiring is set to the thickness of the portion disposed between the first wiring and the second wiring. When the thickness is greater than the thickness of the insulating layer 2, the warp of the wiring board cannot be sufficiently reduced.

  According to the present invention, it is possible to reduce the size of the wiring board in the thickness direction and reduce the warping of the wiring board, and to reduce the cost of the wiring board.

  Next, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 2 is a cross-sectional view of the wiring board according to the embodiment of the present invention.

  Referring to FIG. 2, the wiring substrate 10 of the present embodiment is a coreless substrate, and includes an insulating layer 17 that is a first insulating layer, an electronic component mounting pad 18, vias 19, 24, and 28, A wiring 22 as a first wiring, insulating layers 23 and 27 as a second insulating layer, wirings 25 and 29 as a second wiring, and a solder resist layer 31 are provided.

The insulating layer 17 is an insulating layer for providing an electronic component mounting pad 18 and a via 19 on which the electronic component 11 is mounted and for disposing the wiring 22. The surface 17A of the insulating layer 17 (the surface on which the electronic component 11 is mounted) is substantially flush with the connection surface 18A of the electronic component mounting pad 18. The insulating layer 17 has an opening 35 formed so as to penetrate the portion of the insulating layer 17 facing the electronic component mounting pad 18. The thickness T of the insulating layer 17 in the portion disposed between the electronic component mounting pad 18 and the wiring 22 provided on the surface 17B of the insulating layer 17 (the surface located on the opposite side of the surface 17A of the insulating layer 17). ₁ is the thickness T _{2 of} the portion of the insulating layer 23 disposed between the wiring 22 and the wiring 25 and the thickness T _{3 of} the portion of the insulating layer 27 disposed between the wiring 25 and the wiring 29. It is configured to be thin.

In this way, the insulating layer 17 in a portion disposed between the electronic component mounting pad 18 and the wiring 22 provided on the surface 17B of the insulating layer 17 (the surface located on the opposite side of the surface 17A of the insulating layer 17). thickness T ₁ is the thickness of the insulating layer 27 of the portion located between the thickness T ₂ of the insulating layer 23 of the arrangement _portion, and the wiring 25 and the wiring 29 between the wiring 22 and the wiring 25 By configuring the wiring board 10 to be thinner than the thickness T _3, the size in the thickness direction of the wiring board 10 is reduced and the warping of the wiring board 10 (vias 19, 24, 28 and wirings 22, 25, 29 and insulating layers 23, 27). (Warp due to the difference in thermal expansion coefficient between the two) can be reduced. Incidentally, it is thinner than 5μm thickness T ₁ of the insulating layer 17 is a manufacturing technically difficult insulating layer 17. In addition, when the thickness _{T 1} of the insulating layer 17 was thicker than the thickness _T 2, _{T 3} of the insulating layer 23 and 27, it is impossible to sufficiently reduce the warp of the wiring substrate 10.

Incidentally, between the electronic component mounting pad 18 and the wiring 22 to be connected directly via 19, there is little effect on the electrical properties of even when the thickness T ₁ wiring board 10 of the insulating layer 17. Temporarily, when the wiring routed on the surface 17A is formed on the surface 17A of the insulating layer 17, it is designed to prevent a short circuit with the wiring 22 formed on the surface 17B of the insulating layer 17 and to take into consideration electric characteristics. Due to the above problem, it is difficult to reduce the thickness T ₁ of the insulating layer 17. However, in the wiring substrate 10 of the present embodiment, only the electronic component mounting pad 18 is provided on the surface 17A of the insulating layer 17, and the electronic component mounting pad 18 is connected to the electronic component mounting pad by the via 19. 18 is directly connected to a portion of the wiring 22 arranged immediately below. Therefore, it is not necessary to provide a wiring routed around the surface 17A of the insulating layer 17 for connecting the electronic component mounting pad 18 and the wiring 22. Therefore, in the wiring board 10 of this embodiment, even when the thickness T ₁ of the insulating layer 17 issues a short circuit or electrical properties do not occur. Thus, for warp measures, it can be suitably adjusting the thickness T ₁ of the insulating layer 17.

If reduced thickness T ₁ of the insulating layer 17, in a plan view, forming an electronic component mounting pad 18, so that the other electronic component mounting pad 18 and connected to another wiring 22 do not overlap Good. Thereby, the insulation between the electronic component mounting pad 18 and the other wiring 22 connected to the other electronic component mounting pad 18 can be ensured.

In FIG. 2, only the pad portion 41 is provided on the surface 27 </ b> A of the insulating layer 27, but actually, another wiring 29 is formed on the surface 27 </ b> A of the insulating layer 27. The diameter of the electronic component mounting pad 18 is as small as 50 μm to 150 μm, whereas the diameter of the pad portion 41 for external connection terminals is as large as 200 μm to 1000 μm. In FIG. 2, when the pad portion 41 and the wiring 25 connected to the other pad portion 41 are viewed in plan, the pad portion 41 and the wiring 25 connected to the other pad portion 41 are illustrated so as not to overlap each other. However, in actuality, when viewed in plan, the pad portion 41 and the wiring 25 connected to the other pad portion 41 always overlap. For these reasons, in order to ensure insulation between the wiring 29 and the pad portion 41 formed on the surface 27A of the insulating layer 27 and the wiring 25, the thickness T _{3 of the} insulating layer 27 as in the insulating layer 17 described above. if it is not possible to thin (i.e., by reducing the thickness T ₃ of the insulating layer 27 as the insulating layer 17, it is not possible to reduce the absolute value of warpage of the wiring board 10 .)

  Further, in order to reduce the warp of the conventional wiring substrate 200, the warp of the wiring substrate 10 can be reduced without providing the expensive and difficult-to-process reinforcing resin layer 207 (see FIG. 1). Since it becomes possible to reduce, the cost (a manufacturing cost is also included) of the wiring board 10 can be reduced. As the insulating layer 17, for example, a resin layer made of an insulating resin such as an epoxy resin or a polyimide resin can be used.

FIG. 3 is a diagram showing the amount of warping of the wiring board when the thickness T ₁ of the insulating layer and the thicknesses T ₂ and T ₃ of the insulating layer are changed by simulation. FIG. It is the figure which graphed the simulation result. 3 and FIG. 4, when a negative amount of warpage occurs in the wiring board, the central part of the wiring board 10 shown in FIG. 2 is located below the outer peripheral part of the wiring board 10. 3 and 4, when a positive amount of warpage occurs in the wiring board, the central portion of the wiring board 10 shown in FIG. 2 is located above the outer peripheral portion of the wiring board 10. The thickness T ₁ of the insulating layer 17 shown in FIG. 3 and is 0 .mu.m, if not provided with an insulating layer 17 shows (part of the wiring 22 may function as an electronic component mounting pad 18).

Here, with reference to FIG. 3 and FIG. 4, the amount of warping of the wiring board when the thickness T ₁ of the insulating layer and the thicknesses T ₂ and T _{3 of} the insulating layer obtained by the simulation are changed will be described. To do. In the simulation for obtaining the results shown in FIGS. 3 and 4, an epoxy resin is used as the insulating layers 17, 23, 27, the electronic component mounting pad 18, the vias 19, 24, 28, and the wirings 22, 25, Cu was used as 29 material.

The wiring board 10 can function as a product when the absolute value of the warpage amount is 200 μm or less. Therefore, as shown in FIG. 4, if the functioning of the wiring substrate 10 as a product, the thickness _{T 1} of the provided on the wiring substrate 10 insulating layer 17, for example, may be to 5Myuemu～20myuemu. However, the amount of warpage of the wiring board 10 is preferably 80 μm or less in absolute value, from the viewpoint of the mounting property of the electronic component 11 on the wiring board 10 and the mounting property of the wiring board 10 on the motherboard. That is, the thickness _{T 1} of the insulating layer 17 provided on the wiring substrate 10, for example, 5Myuemu～15myuemu are preferred.

Further, in consideration of thickness and warpage of the wiring board 10, the thickness _T 2, _{T 3} of the insulating layer 23 and 27, for example, it can be 25Myuemu～45myuemu. Furthermore, when the insulating properties of the insulating layers 23 and 27 are taken into account, the thickness of the insulating layers 23 and 27 is preferably 30 μm to 40 μm, for example.

  In addition, when the prototype of the wiring board 10 was actually produced, the curvature suppression result according to the simulation result was obtained.

  The electronic component mounting pad 18 has a connection surface 18A on which the electronic component 11 is mounted (connected). The electronic component mounting pad 18 is provided in the insulating layer 17 so that the connection surface 18A and the surface 17A of the insulating layer 17 are substantially flush with each other. As the electronic component mounting pad 18, for example, an Au layer (for example, thickness 0.05 μm), a Pd layer (for example, thickness 0.05 μm), and a Ni layer (for example, thickness 5 μm) from the connection surface 18A side. And Au / Pd / Ni laminated film sequentially laminated. In this case, the electronic component 11 is mounted on the Au layer.

  The via 19 is provided in the opening 35 formed in the insulating layer 17. One end of the via 19 is connected to the electronic component mounting pad 18. The via 19 is configured integrally with the wiring 22, and electrically connects the electronic component mounting pad 18 and the wiring 22.

  The wiring 22 is provided on the surface 17B of the insulating layer 17 (the surface of the insulating layer 17 located on the opposite side of the surface 17A). The wiring 22 is configured integrally with the via 19. The via 19 and the wiring 22 can be formed by, for example, a semi-additive method. As a material of the via 19 and the wiring 22, for example, Cu can be used.

The insulating layer 23 is provided on the surface 17B of the insulating layer 17 so as to cover most of the wiring 22. The insulating layer 23 is an insulating layer for providing the via 24 and forming the wiring 25. The insulating layer 23 has an opening 36 that exposes a part of the wiring 22. The opening 36 is for arranging the via 24. A wiring 25 is provided on the surface 23A of the insulating layer 23 (the surface of the insulating layer 23 opposite to the side in contact with the insulating layer 17). The thickness T ₂ of the insulating layer 23 in the portion disposed between the wiring 22 and the wiring 25 needs to ensure insulation between the wirings 22 and 25, and therefore is larger than the thickness T ₁ of the insulating layer 17. It is configured to be thick. Specifically, the thickness _{T 2} of the insulating layer 23 of the portion located between the wiring 22 and the wiring 25 may be, for example, a 25Myuemu～45myuemu. As the insulating layer 23, for example, a resin layer made of an insulating resin such as an epoxy resin or a polyimide resin can be used.

  The via 24 is provided in the opening 36 formed in the insulating layer 23. One end of the via 24 is connected to the wiring 22. The via 24 is configured integrally with the wiring 25 provided on the surface 23 </ b> A of the insulating layer 23. The via 24 electrically connects the wiring 22 and the wiring 25.

  The wiring 25 is provided on the surface 23A of the insulating layer 23 (the surface of the insulating layer 23 opposite to the surface in contact with the insulating layer 17). The wiring 25 is configured integrally with the via 24. The via 24 and the wiring 25 can be formed by, for example, a semi-additive method. As a material for the via 24 and the wiring 25, for example, Cu can be used.

The insulating layer 27 is provided on the surface 23 </ b> A of the insulating layer 23 so as to cover most of the wiring 25. The insulating layer 27 is an insulating layer for providing the vias 28 and forming the wirings 29. The insulating layer 27 has an opening 38 that exposes a part of the wiring 25. The opening 38 is for arranging the via 28. A wiring 29 is disposed on the surface 27A of the insulating layer 27 (the surface of the insulating layer 27 opposite to the side in contact with the insulating layer 23). The thickness T ₃ of the insulating layer 27 in the portion arranged between the wiring 25 and the wiring 29 needs to ensure the insulation between the wirings 25 and 29, and therefore is larger than the thickness T ₁ of the insulating layer 17. It is configured to be thick. Specifically, the thickness _{T 3} of the insulating layer 27 of the portion disposed between the wiring 25 and the wiring 29, for example, be a 25Myuemu～45myuemu. As the insulating layer 27, for example, a resin layer made of an insulating resin such as an epoxy resin or a polyimide resin can be used.

  The via 28 is provided in the opening 38 formed in the insulating layer 27. One end of the via 28 is connected to the wiring 25. The via 28 is configured integrally with the wiring 29 provided on the surface 27 </ b> A of the insulating layer 27. The via 28 electrically connects the wiring 25 and the wiring 29.

  The wiring 29 is provided on the surface 27A of the insulating layer 27 (the surface of the insulating layer 27 opposite to the surface in contact with the insulating layer 23). The wiring 29 is disposed so as to face a part of the wiring 25 with the insulating layer 27 interposed therebetween. The wiring 29 is configured integrally with the via 28. The wiring 29 has a pad portion 41 on which the external connection terminals 14 (for example, solder balls) are disposed. The pad portion 41 is a portion that is electrically connected to the mounting substrate 13 such as a mother board via the external connection terminal 14. The wiring 29 is configured integrally with the via 28. The via 28 and the wiring 29 can be formed by, for example, a semi-additive method. As a material of the via 28 and the wiring 29, for example, Cu can be used.

  The solder resist layer 31 is provided on the surface 27A of the insulating layer 27 so as to cover the portion of the wiring 29 excluding the pad portion 41. The solder resist layer 31 has an opening 31 </ b> A that exposes the pad portion 41.

According to the wiring board of the present embodiment, a portion of the insulating layer 17 (between the electronic component mounting pad 18 and the wiring 22 is ensured between the electronic component mounting pad 18 and the wiring 22). The thickness T ₁ of the portion of the insulating layer 17 that does not need to be used is set to the portion of the insulating layer 23 (the portion that needs to ensure insulation between the wires 22 and 25) disposed between the wiring 22 and the wiring 25. A thickness T ₂ of the insulating layer) and a portion of the insulating layer 27 (between the wirings 25 and 29) disposed between the wirings 25 and 29 disposed so as to face each other through the one insulating layer 27. by thinner than T ₃ of the necessary portions of the insulating layer) of a thickness direction size of the wiring board 10 can be reduced warpage of the wiring substrate 10 is miniaturized.

  In addition, since it is possible to reduce warping of the wiring substrate 10 without using a reinforcing resin layer 207 (see FIG. 1) in which a glass cloth in which an opening is difficult to form is impregnated with a resin, wiring can be reduced. The cost (including the manufacturing cost) of the substrate 10 can be reduced.

  FIG. 5 is a cross-sectional view of a wiring board according to a first modification of the embodiment of the present invention. 5, the same components as those of the wiring board 10 shown in FIG.

  Referring to FIG. 5, the wiring board 50 of the first modification of the present embodiment is the wiring board except that an insulating layer 51 is provided instead of the insulating layer 17 provided on the wiring board 10 of the present embodiment. 10 is configured in the same manner.

  The insulating layer 51 is a portion of the insulating layer 17 provided on the wiring board 10 that is disposed between the connection surface 18A and the surface 18B of the electronic component mounting pad 18 located on the opposite side of the connection surface 18A. The configuration is the same as that of the insulating layer 17 except that the insulating layer 17 is omitted. The surface 51A of the insulating layer 51 is substantially flush with the connection surface 18B of the electronic component mounting pad 18. On the surface 51B of the insulating layer 51 (the surface of the insulating layer 51 disposed on the opposite side of the surface 51A), the wiring 22 and the insulating layer 23 are provided.

  The wiring board 50 having such a configuration can obtain the same effects as those of the wiring board 10 described above.

  FIG. 6 is a cross-sectional view of a wiring board according to a second modification of the embodiment of the present invention. 6, the same components as those of the wiring board 50 shown in FIG.

  Referring to FIG. 6, the wiring board 55 of the second modification example of the present embodiment is the same as the wiring board 50 of the first modification example of the present embodiment except that a solder resist layer 56 is further provided. The configuration is the same as that of the substrate 50.

  The solder resist layer 56 is provided on the surface 51 </ b> A of the insulating layer 51. The solder resist layer 56 has an opening 56A in which the electronic component mounting pad 18 is accommodated. The solder resist layer 56 exposes the connection surface 18A of the electronic component mounting pad 18. The thickness of the solder resist layer 56 is configured to be substantially equal to the thickness of the electronic component mounting pad 18. As the solder resist layer 56, a resin layer made of epoxy resin, polyimide resin, acrylic resin, or the like can be used. In the wiring board 55, the insulating layer 51 and the solder resist layer 56 correspond to the first insulating layer recited in the claims.

  The wiring substrate 55 configured as described above forms a solder resist layer 56 having an opening 56A instead of the resist film 62 for plating in the steps shown in FIGS. The electronic component mounting pad 18 is formed on 56A, and thereafter, the solder resist layer 56 is left, and the same process as that shown in FIGS.

  7-15 is a figure which shows the manufacturing process of the wiring board based on Embodiment of this invention. 7 to 15, the same components as those of the wiring board 10 of the present embodiment are denoted by the same reference numerals.

  With reference to FIGS. 7-15, the manufacturing method of the wiring board 10 of this Embodiment is demonstrated. First, in the step shown in FIG. 7, a resist film 62 for plating having an opening 62A is formed on the surface 61A of the support 61 having conductivity. At this time, the opening 62 </ b> A is formed so as to expose the surface 61 </ b> A of the support 61 corresponding to the formation region of the electronic component mounting pad 18. Specifically, the resist film 62 having the opening 62A is formed by, for example, applying a photosensitive resist, and then exposing and developing the photosensitive resist. As the support 61, for example, a metal plate (for example, a Cu plate), a metal foil (for example, a Cu foil), or the like can be used.

  Next, in the step shown in FIG. 8, the electronic component mounting pad 18 is formed on the portion of the support 61 exposed at the opening 62A. Specifically, when an Au / Pd / Ni laminated film is used as the electronic component mounting pad 18, for example, an Au layer (on the surface 61A of the support 61 is formed by electrolytic plating using the support 61 as a power feeding layer). For example, the electronic component mounting pad 18 is formed by sequentially laminating a 0.05 μm thickness), a Pd layer (for example, a thickness of 0.05 μm), and a Ni layer (for example, a thickness of 5 μm).

  Instead of the Au / Pd / Ni laminated film, an Au / Pd / Ni / Cu laminated film formed by plating may be used as the electronic component mounting pad 18.

  Next, in the step shown in FIG. 9, the resist film 62 shown in FIG. 8 is removed. Next, in the step shown in FIG. 10, the insulating layer 17 having the opening 35 exposing a part of the electronic component mounting pad 18 is formed. As the insulating layer 17, for example, a resin layer made of an insulating resin such as an epoxy resin or a polyimide resin can be used. The insulating layer 17 can be formed by laminating an epoxy resin film or a polyimide resin film, for example. The opening 35 can be formed by, for example, a laser processing method.

The thickness T of the insulating layer 17 in the portion disposed between the electronic component mounting pad 18 and the wiring 22 provided on the surface 17B of the insulating layer 17 (the surface located on the opposite side of the surface 17A of the insulating layer 17). ₁ is the thickness T _{2 of} the portion of the insulating layer 23 disposed between the wiring 22 and the wiring 25 and the thickness T _{3 of} the portion of the insulating layer 27 disposed between the wiring 25 and the wiring 29. It is configured to be thin.

In this way, the insulating layer 17 in a portion disposed between the electronic component mounting pad 18 and the wiring 22 provided on the surface 17B of the insulating layer 17 (the surface located on the opposite side of the surface 17A of the insulating layer 17). thickness T ₁ is the thickness of the insulating layer 27 of the portion located between the thickness T ₂ of the insulating layer 23 of the arrangement _portion, and the wiring 25 and the wiring 29 between the wiring 22 and the wiring 25 By configuring the wiring board 10 to be thinner than the thickness T _3, the size in the thickness direction of the wiring board 10 is reduced and the warping of the wiring board 10 (vias 19, 24, 28 and wirings 22, 25, 29 and insulating layers 23, 27). (Warp due to the difference in thermal expansion coefficient between the two) can be reduced. Incidentally, it is thinner than 5μm thickness T ₁ of the insulating layer 17 is a manufacturing technically difficult insulating layer 17. In addition, when the thickness _{T 1} of the insulating layer 17 was thicker than the thickness _T 2, _{T 3} of the insulating layer 23 and 27, it is impossible to sufficiently reduce the warp of the wiring substrate 10.

Incidentally, between the electronic component mounting pad 18 and the wiring 22 to be connected directly via 19, there is little effect on the electrical properties of even when the thickness T ₁ wiring board 10 of the insulating layer 17. Temporarily, when the wiring routed on the surface 17A is formed on the surface 17A of the insulating layer 17, it is designed to prevent a short circuit with the wiring 22 formed on the surface 17B of the insulating layer 17 and to take into consideration electric characteristics. Due to the above problem, it is difficult to reduce the thickness T ₁ of the insulating layer 17. However, in the wiring substrate 10 of the present embodiment, only the electronic component mounting pad 18 is provided on the surface 17A of the insulating layer 17, and the electronic component mounting pad 18 is connected to the electronic component mounting pad by the via 19. 18 is directly connected to a portion of the wiring 22 arranged immediately below. Therefore, it is not necessary to provide a wiring routed around the surface 17A of the insulating layer 17 for connecting the electronic component mounting pad 18 and the wiring 22. Therefore, in the wiring board 10 of this embodiment, even when the thickness T ₁ of the insulating layer 17 issues a short circuit or electrical properties do not occur. Thus, for warp measures, it can be suitably adjusting the thickness T ₁ of the insulating layer 17.

  Further, in order to reduce the warp of the conventional wiring substrate 200, the warp of the wiring substrate 10 can be reduced without providing the expensive and difficult-to-process reinforcing resin layer 207 (see FIG. 1). Since it becomes possible to reduce, the cost (a manufacturing cost is also included) of the wiring board 10 can be reduced.

When the allowable range of warpage of the wiring board 10 is 80 μm or less, the thickness T ₁ of the insulating layer 17 can be appropriately selected within a range of 5 μm to 15 μm. Incidentally, it is thinner than 5μm thickness T ₁ of the insulating layer 17 is a manufacturing technically difficult insulating layer 17. Also, when the thickness T ₁ of the insulating layer 17 thicker than 15 [mu] m, exceeds 80μm are preferred tolerance of warp of the wiring substrate 10.

  Next, in the step shown in FIG. 11, the via 19 and the wiring 22 are formed simultaneously. The via 19 and the wiring 22 are formed by, for example, a semi-additive method. Specifically, a seed layer (for example, a Cu layer) is formed by electroless plating so as to cover the upper surface side of the structure shown in FIG. 10, and then the wiring 22 is formed on the seed layer (not shown). A resist film (not shown) having an opening (not shown) in a portion corresponding to the formation region is formed. Next, a plating film (for example, Cu plating film) is deposited and grown on the seed layer exposed in the opening by an electrolytic plating method using the seed layer as a power feeding layer, and then the resist film is removed, By removing the portion of the seed layer not covered with the plating film, the via 19 and the wiring 22 are formed simultaneously.

Next, in the process shown in FIG. 12, the insulating layer 23 having the opening 36, the via 24, and the wiring 25 are sequentially formed by the same method as the process shown in FIGS. As the insulating layer 23, for example, a resin layer made of an insulating resin such as an epoxy resin or a polyimide resin can be used. Further, the thickness T ₂ of the portion of the insulating layer 23 disposed between the wiring 22 and the wiring 25 is configured to be thicker than the thickness T ₁ of the insulating layer 17. Specifically, the thickness _{T 2} of the insulating layer 23 may be, for example, a 25Myuemu～45myuemu. As a material for the via 24 and the wiring 25, for example, Cu can be used.

Next, in the step shown in FIG. 13, the insulating layer 27 having the opening 38, the via 28, and the wiring 29 are sequentially formed by the same method as the steps shown in FIGS. 10 and 11 described above. As the insulating layer 27, for example, a resin layer made of an insulating resin such as an epoxy resin or a polyimide resin can be used. Further, the thickness T ₃ of the portion of the insulating layer 27 disposed between the wiring 25 and the wiring 29 is configured to be thicker than the thickness T ₁ of the insulating layer 17. Specifically, the thickness _{T 3} of the insulating layer 27, for example, be a 25Myuemu～45myuemu. As a material of the via 28 and the wiring 29, for example, Cu can be used.

  Next, in a step shown in FIG. 14, a solder resist layer 31 having an opening 31A is formed on the surface 27A of the insulating layer 27 so as to cover the portion of the wiring 29 excluding the pad portion 41. The opening 31A is formed so as to expose the pad portion 41.

  Next, in the step shown in FIG. 15, the support 61 shown in FIG. 14 is removed. Thereby, the wiring board 10 is manufactured. In FIG. 15, the wiring substrate 10 shown in FIG. 2 is shown upside down in the manufacturing process.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

  For example, the wiring boards 10, 50, 55 described above are not only a BGA (Ball Grid Array) but also a PGA (Pin Grid Array) in which pins are joined to the pad portion 41, or a LAG having the pad portion 41 itself as an external connection terminal. It can also be used as a (Land Grid Array).

  The present invention can be applied to a coreless substrate.

It is sectional drawing of the conventional wiring board. It is sectional drawing of the wiring board which concerns on embodiment of this invention. Is a diagram showing the amount of warpage of the wiring substrate when by changing the thickness T _2, T ₃ of the thickness T ₁ and the insulating layer of the insulating layer by simulation. FIG. 4 is a graph showing the simulation result shown in FIG. 3. It is sectional drawing of the wiring board which concerns on the 1st modification of embodiment of this invention. It is sectional drawing of the wiring board which concerns on the 2nd modification of embodiment of this invention. It is FIG. (The 1) which shows the manufacturing process of the wiring board which concerns on embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the wiring board which concerns on embodiment of this invention. It is FIG. (The 3) which shows the manufacturing process of the wiring board which concerns on embodiment of this invention. It is FIG. (4) which shows the manufacturing process of the wiring board which concerns on embodiment of this invention. It is FIG. (5) which shows the manufacturing process of the wiring board which concerns on embodiment of this invention. It is FIG. (6) which shows the manufacturing process of the wiring board which concerns on embodiment of this invention. It is FIG. (7) which shows the manufacturing process of the wiring board which concerns on embodiment of this invention. It is FIG. (The 8) which shows the manufacturing process of the wiring board which concerns on embodiment of this invention. It is FIG. (9) which shows the manufacturing process of the wiring board which concerns on embodiment of this invention.

Explanation of symbols

10, 50, 55 Wiring board 11 Electronic component 13 Mounting board 14 External connection terminal 17, 23, 27, 51 Insulating layer 17A, 17B, 18B, 23A, 27A, 51A, 51B, 61A Surface 18 Electronic component mounting pad 18A Connection surface 19,24,28 via 22,25,29 wiring 31,56 solder resist layer 31A, 35,36,38,56A, 62A opening 41 pad portion 61 support 62 resist film T _{1, T} 2, _{T 3} thickness The

Claims (4)

An electronic component mounting pad provided on one surface side of the first insulating layer such that the first insulating layer has a connection surface to which an electronic component is connected, and the connection surface is exposed; A via that is provided so as to penetrate the first insulating layer at a portion facing the electronic component mounting pad, and has one end connected to the electronic component mounting pad; and the first insulating layer A first wiring connected to the other end of the via, a second insulating layer stacked on the other surface of the first insulating layer, and the first wiring A wiring board comprising: a second wiring provided in the two insulating layers and electrically connected to the first wiring;
The thickness of the first insulating layer in the portion disposed between the electronic component mounting pad and the first wiring is disposed between the first wiring and the second wiring. A wiring board having a thickness smaller than that of the second insulating layer.   The wiring board according to claim 1, wherein a thickness of the first insulating layer in a portion disposed between the electronic component mounting pad and the first wiring is 5 μm to 20 μm.   3. The wiring board according to claim 1, wherein the first insulating layer is a resin layer.   4. The wiring board according to claim 1, wherein a thickness of the second insulating layer is 25 μm to 45 μm. 5.

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