TW544735B - Semiconductor device having a high-dielectric gate insulation film and fabrication process thereof - Google Patents
Semiconductor device having a high-dielectric gate insulation film and fabrication process thereof Download PDFInfo
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- TW544735B TW544735B TW091106211A TW91106211A TW544735B TW 544735 B TW544735 B TW 544735B TW 091106211 A TW091106211 A TW 091106211A TW 91106211 A TW91106211 A TW 91106211A TW 544735 B TW544735 B TW 544735B
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- oxygen
- silicon
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims description 79
- 230000008569 process Effects 0.000 title claims description 57
- 238000009413 insulation Methods 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 41
- 239000001301 oxygen Substances 0.000 claims abstract description 41
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 40
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 100
- 229910052710 silicon Inorganic materials 0.000 claims description 92
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 82
- 239000010703 silicon Substances 0.000 claims description 73
- 125000004429 atom Chemical group 0.000 claims description 47
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 34
- 239000004575 stone Substances 0.000 claims description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 23
- 239000007789 gas Substances 0.000 claims description 23
- 239000002052 molecular layer Substances 0.000 claims description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 23
- 229910044991 metal oxide Inorganic materials 0.000 claims description 13
- 150000004706 metal oxides Chemical class 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 9
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 7
- OYEHPCDNVJXUIW-UHFFFAOYSA-N plutonium atom Chemical compound [Pu] OYEHPCDNVJXUIW-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 229910052778 Plutonium Inorganic materials 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 239000008267 milk Substances 0.000 claims description 5
- 210000004080 milk Anatomy 0.000 claims description 5
- 235000013336 milk Nutrition 0.000 claims description 5
- 229910052735 hafnium Inorganic materials 0.000 claims description 4
- -1 hafnium nitride Chemical class 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 2
- 229910052712 strontium Inorganic materials 0.000 claims description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 229910052747 lanthanoid Inorganic materials 0.000 claims 1
- 150000002602 lanthanoids Chemical class 0.000 claims 1
- 238000001179 sorption measurement Methods 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- 229910052726 zirconium Inorganic materials 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract description 4
- 239000012212 insulator Substances 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 191
- 239000010408 film Substances 0.000 description 105
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
- 239000000377 silicon dioxide Substances 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- 230000004888 barrier function Effects 0.000 description 8
- 125000001309 chloro group Chemical group Cl* 0.000 description 8
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 8
- 229910021332 silicide Inorganic materials 0.000 description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 7
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 6
- NIHNNTQXNPWCJQ-UHFFFAOYSA-N fluorene Chemical compound C1=CC=C2CC3=CC=CC=C3C2=C1 NIHNNTQXNPWCJQ-UHFFFAOYSA-N 0.000 description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 5
- 229910052801 chlorine Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 5
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 5
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
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- 238000010438 heat treatment Methods 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical compound [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 description 3
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- 229910052693 Europium Inorganic materials 0.000 description 3
- 229910052776 Thorium Inorganic materials 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- OGPBJKLSAFTDLK-UHFFFAOYSA-N europium atom Chemical group [Eu] OGPBJKLSAFTDLK-UHFFFAOYSA-N 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 229910052914 metal silicate Inorganic materials 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 239000005049 silicon tetrachloride Substances 0.000 description 3
- KPZGRMZPZLOPBS-UHFFFAOYSA-N 1,3-dichloro-2,2-bis(chloromethyl)propane Chemical compound ClCC(CCl)(CCl)CCl KPZGRMZPZLOPBS-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 229910052769 Ytterbium Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
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- 238000009792 diffusion process Methods 0.000 description 2
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- 125000003983 fluorenyl group Chemical group C1(=CC=CC=2C3=CC=CC=C3CC12)* 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical group [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
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- 229910052682 stishovite Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- WEQHQGJDZLDFID-UHFFFAOYSA-J thorium(iv) chloride Chemical compound Cl[Th](Cl)(Cl)Cl WEQHQGJDZLDFID-UHFFFAOYSA-J 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 206010021143 Hypoxia Diseases 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910052770 Uranium Inorganic materials 0.000 description 1
- QOCJITIEZIWNLJ-UHFFFAOYSA-M [OH-].[O-2].[Eu+3] Chemical compound [OH-].[O-2].[Eu+3] QOCJITIEZIWNLJ-UHFFFAOYSA-M 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
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- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 150000003891 oxalate salts Chemical class 0.000 description 1
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
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- 229910052704 radon Inorganic materials 0.000 description 1
- SYUHGPGVQRZVTB-UHFFFAOYSA-N radon atom Chemical compound [Rn] SYUHGPGVQRZVTB-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 description 1
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- ZCUFMDLYAMJYST-UHFFFAOYSA-N thorium dioxide Chemical compound O=[Th]=O ZCUFMDLYAMJYST-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/308—Oxynitrides
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
- C23C16/45529—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations specially adapted for making a layer stack of alternating different compositions or gradient compositions
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- C—CHEMISTRY; METALLURGY
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
- C23C16/45531—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations specially adapted for making ternary or higher compositions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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Abstract
Description
544735 五、發明説明 本紙張尺度適财關家鮮(CNS) M規格⑽MW公楚) A7 B7 相關申請案之交 本案係基於曰本優先申請案第2〇〇卜〇97128號,申請曰 2001年3月29日,以及第2〇〇2-77〇55號申請日2〇〇2年3月^ 日,一案係向日本專利局提出申請,其全體内容以引用方 式併入此處。 發明背景 1·發明範疇 概略而言本發明係有關半導體元件,特別係有關具有 金屬氧化物或金屬矽酸鹽製成之高κ介電薄膜之半導體元 件及其製造方法。 2 _相關技藝說明 因半導體積體電路元件如CM〇s LSI為於超高速操作 所需,該兀件係、由具有極短閘長度 < 電場效應㉟電晶體 (MOSFET)組成。為了達成超高速操作,對之微縮 化進行密集研究。 "MOSFET微縮化時,也要求將閘絕緣膜減薄。例如以 氧化物相當厚度表示,要求減薄閘絕緣膜之薄膜厚度至約 2 · 5奈米或以下。 習知具有絕佳茂漏特性及小界面階密度之石夕氧化物 用於MOSFET之閘絕緣膜。但習知砂氧化物製成之問絕緣 膜有下述問題,隨著閘絕緣膜實體厚度的變薄,直接穿透 ㈣電流增高。任何小於前述數值之薄膜厚度由於直接穿 透位障電流將引發閘漏電流之最大問題。若閘漏電流增 局’則於閘關閉期間’實質漏電流保持流動而造成例如操 4 (請先閱讀背面之注意事項再填寫本頁)544735 V. Description of the invention The paper size is suitable for wealth management (CNS) M specification (MW public) A7 B7 The related application is based on the Japanese priority application No. 200b 097128, and the application date is 2001 On March 29, and the application date of 2000-77705, March ^ 2002, a case was filed with the Japan Patent Office, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to semiconductor devices, and more particularly, to semiconductor devices having high-k dielectric films made of metal oxides or metal silicates, and methods of making the same. 2 _Related technical description Because semiconductor integrated circuit elements such as CMOS LSI are required for ultra-high-speed operation, this element is composed of an extremely short gate length < electric field effect transistor (MOSFET). In order to achieve ultra-high-speed operation, intensive research has been conducted on its miniaturization. " When the MOSFET is miniaturized, it is also required to thin the gate insulating film. For example, it is expressed by the oxide equivalent thickness, and it is required to reduce the film thickness of the gate insulating film to about 2.5 nm or less. It is known that Shi Xi oxide with excellent leakage characteristics and small interface step density is used as the gate insulating film of MOSFET. However, the conventional insulating film made of sand oxide has the following problems. As the physical thickness of the gate insulating film becomes thinner, the direct plutonium current increases. Any film thickness smaller than the aforementioned value will cause the biggest problem of gate leakage current due to direct penetration of the barrier current. If the gate leakage current increases, the actual leakage current will keep flowing during the gate closing period, which will cause, for example, operation 4 (Please read the precautions on the back before filling this page)
)44735 A7 ^----------------B7 五、發明説明(2 ) 作異常以及耗電量增高等問題。 為了解決該等問題,曾經研究使用高K介電薄膜例如 金屬氧化物及金屬矽酸鹽。本發明中,高κ介電薄膜用來 私示具有比介電常數為10或以上之介電薄膜。 但於採用金屬氧化物或金屬矽酸鹽之高Κ介電間絕緣 膜,出現MOSFET操作不穩定問題,M〇SFET操作不穩定 原因為摻雜於閘極之硼滲透至高κ介電閘絕緣膜,製程使 用之氣體中之氫氣攻擊高κ介電閘絕緣膜等現象。又當形 成含有高Κ介電閘絕緣膜之閘結構於矽基板表面時,於矽 基板與高Κ介電閘絕緣膜間之界面、或於高尺介電閘絕緣膜 與多晶矽閘極間之界面可能發生反應例如金屬矽化物生成 反應。 習知對高Κ介電閘絕緣膜之研究主要係就抑制直接穿 透位障電流做研究,而未曾徹底進行有關元件特性安定性 研究。 例如JP,2001-267566揭示一種閘絕緣層,該層係藉所 謂之單原子層沉積(原子層C V D)方法沉積第一氮化矽分子 層於矽基板表面上組成;一高κ介電層如氧化锆層,係藉 重複形成氧原子層及鍅原子層於氮化矽分子層上形成,氧 原子層及錯原子層個別係藉原子層CVD方法製成;以及一 第二氮化矽分子層,該層係藉原子層CVD方法形成於高κ ”包層上。此外,相關技術也揭示一閘絕緣層,其係由藉 所謂之單原子層沉積(原子層CVD)方法於矽基板表面形成 的第一二氧化矽分子層組成;一高κ介電層如氧化鍅層形 本紙張尺度朝巾關家標準(CNS) Μ規格⑵⑽297公爱) 裳----- (請先閱讀背面之注意事^再填寫本頁} .訂丨 544735 A7 '^-----一 —__B7^_ 五、發明説明~' -- 成於鼠化石夕分子層上,該層係經由重複形成氧原子層及錯 原=層(各自係藉原子層CVD方法形成)形成;以及一第二 氧化矽刀子層,其係藉原子層CVD方法形成於高κ介電 層上。 例士鈾述;I電閘絕緣膜具有小型氧化物相當厚度,當 施加至具有閘長度為01微米或以下之超高速半導體裝置 時,可有效抑制經由直接穿透位障效應引起的間漏電流。 仁、、Ό構中第一及第二氮化矽分子層垂直夾置高K介電 薄膜,由於矽與氮間之價數差異,矽基板表面無法均一且 凡全地被氮原子所覆蓋,反而無可避免地出現懸垂鍵。若 懸垂鍵出現於閘絕緣膜,特別於與矽基板表面(作為通道區) 界面的閘絕緣膜,則半導體元件之臨限值特性受到載子陷 解專改變。 於前述先前技藝之例,其中高κ介電薄膜係由一對二 氧化矽分子層垂直夾置,它方面,並無懸垂鍵形成於矽基 板與閘絕緣膜間之界面。但因閘絕緣膜不存在有氮原子 層出現一個問題,多晶石夕閘極的·摻雜劑經由閘絕緣膜 展開至秒基板’半導體元件之臨限值特性改變。此外於此 種缺乏氮原子層之高κ介電閘絕緣膜,出現高κ介電膜之氧 亂容易藉擴散而到達矽基板,造成通道區之載子移動能力 低劣之問通。此外也造成金屬元素如錯由閘絕緣膜擴散至 石夕基板之問題。如此到達矽基板之金屬元素引發例如金屬 矽化物形成反應。 如此習知高κ介電閘絕緣膜有下列問題,包括於石夕基 本紙張尺度適财_家標準(CNS) Α4規格(2Κ)Χ297Μ) 6 —---------·裝丨: (請先閲讀背面之注意事項再填寫本頁) 、τ 544735 五、發明説明(4 ) (請先閲讀背面之注意事項再填寫本頁) 板=高〖介電閘絕緣關之界面形成懸垂鍵之問題,以及 雜質几素經由高K介電閘絕緣膜滲透問題。又氧氣及金屬 凡素擴散問題也未能解決。如此即使於半導體元件使用高 〖介電閘絕緣膜製造時仍然無法達成高K介電閘絕緣膜預 期的優異效果。 如此本發明之概略目的係提供—㈣财用之半導 體凡件,其中可消除前述問題。 本I月之3及更為特異性目的係提供一種具有高K 7電閘絕緣膜之半㈣元件及其製造方法,其巾删穿透問 題、以及由於元件製造時使用的氣體含有的還原氣氛如氯 氣造成的元件特性改變問題可成功地加以解決,以及直中 可成魏抑制高K介電閘絕緣膜與石夕基板間之反應,以及 抑制咼K介電閘絕緣膜與閘極間之反應。 本毛月之另一目的係提供一種半導體元件,包含: 一形成於矽晶體層之通道區, 、一形成於通道區之閘絕緣膜,含有一氧化矽層其係形 成於石夕晶體層上,-形成於氧化石夕層上之第一氮化石夕層, 一形成於第一氮化矽層上之介電金屬氧化物層,以及一形 成於介電金屬氧化物層上之第二氮化矽層,以及 一閘極其係形成於閘絕緣膜上。 本务月之另目的係提供一種半導體元件,包含: 一矽基板, 形成於矽基板上之閘絕緣膜;以及) 44735 A7 ^ ---------------- B7 V. Description of the Invention (2) Problems such as abnormal operation and high power consumption. To solve these problems, high-K dielectric films such as metal oxides and metal silicates have been studied. In the present invention, a high-k dielectric film is used to privately display a dielectric film having a specific dielectric constant of 10 or more. However, in the case of high-K dielectric interlayer films using metal oxides or metal silicates, the problem of unstable MOSFET operation occurs. The reason for the unstable operation of MOSFETs is that the gate-doped boron penetrates into the high-κ dielectric gate insulating film. , Hydrogen in the gas used in the process attacks the high-κ dielectric gate insulation film and other phenomena. When a gate structure containing a high-K dielectric gate insulating film is formed on the surface of the silicon substrate, at the interface between the silicon substrate and the high-K dielectric gate insulating film, or between the high-k dielectric gate insulating film and the polycrystalline silicon gate. Interface reactions may occur, such as metal silicide formation reactions. The research on the high-k dielectric gate insulation film has been mainly conducted on the suppression of the direct penetrating barrier current, but has not thoroughly studied the stability of the device characteristics. For example, JP, 2001-267566 discloses a gate insulating layer, which is formed by depositing a first silicon nitride molecular layer on the surface of a silicon substrate by a so-called monoatomic layer deposition (atomic layer CVD) method; a high-k dielectric layer such as The zirconia layer is formed on the silicon nitride molecular layer by repeatedly forming an oxygen atom layer and a hafnium atom layer, and the oxygen atom layer and the interatomic layer are individually formed by an atomic layer CVD method; and a second silicon nitride molecular layer This layer is formed on a high κ ”cladding layer by the atomic layer CVD method. In addition, the related art also discloses a gate insulating layer formed on the surface of a silicon substrate by the so-called monoatomic layer deposition (atomic layer CVD) method. Composed of the first silicon dioxide molecular layer; a high-k dielectric layer such as yttrium oxide; the paper size is toward the family standard (CNS) M specification ⑵⑽297 public love) ----- (Please read the back Attention ^ Fill in this page again}. Order 丨 544735 A7 '^ ----- 一 —__ B7 ^ _ V. Description of the invention ~'-It is formed on the molecular layer of rat fossil, which is formed by repeated formation of oxygen atoms Layer and source = layers (each formed by an atomic layer CVD method); and The silicon oxide knife layer is formed on the high-k dielectric layer by the atomic layer CVD method. For example, the uranium is described; the I-gate insulation film has a small oxide equivalent thickness, and when applied to a substrate with a gate length of 01 microns or less In high-speed semiconductor devices, it is possible to effectively suppress the indirect leakage current caused by the direct penetration barrier effect. The first and second silicon nitride molecular layers in the silicon, silicon, and silicon structures are sandwiched by high-K dielectric thin films. The valence difference between the two, the surface of the silicon substrate can not be uniformly and completely covered by nitrogen atoms, but inevitably appear dangling bonds. If the dangling bonds appear in the gate insulation film, especially with the surface of the silicon substrate (as a channel area) The gate insulation film at the interface changes the threshold characteristics of the semiconductor element by carrier breakdown. In the example of the previous technique, the high-k dielectric film is vertically sandwiched by a pair of silicon dioxide molecular layers. There is no dangling bond formed at the interface between the silicon substrate and the gate insulating film. However, a problem arises because the gate insulating film does not have a nitrogen atomic layer. The threshold characteristic of the second substrate 'semiconductor device changes. In addition, in this kind of high κ dielectric gate insulation film that lacks a nitrogen atom layer, the oxygen chaos of the high κ dielectric film easily reaches the silicon substrate by diffusion, causing the channel area. The problem of poor carrier mobility is caused. In addition, it also causes the problem of metal elements from diffusing from the gate insulating film to the Shixi substrate. The metal elements that reach the silicon substrate cause, for example, metal silicide formation reactions. Such a high-k dielectric The gate insulation film has the following problems, including the basic paper size of Shi Xi_Family Standard (CNS) Α4 size (2K) × 297M) 6 ----------- · installation 丨 (Please read the Note for this page, please fill in this page), τ 544735 V. Description of the invention (4) (Please read the notes on the back before filling this page) Board = High [Problem of forming dangling bonds at the interface of the dielectric gate insulation barrier, and the number of impurities The problem of infiltration through the high-K dielectric gate insulation film. In addition, the diffusion of oxygen and metals has not been resolved. Thus, even when the semiconductor element is manufactured using a high dielectric gate insulating film, the excellent effects expected from a high-K dielectric gate insulating film cannot be achieved. Thus, the general purpose of the present invention is to provide semiconductor devices for financial purposes, in which the aforementioned problems can be eliminated. The third and more specific purposes of this month are to provide a half-knife element with a high-K 7 gate insulation film and a method for manufacturing the same. The problem of penetration is eliminated, and the reducing atmosphere contained in the gas used in the manufacture of the element, such as The problem of changing element characteristics caused by chlorine gas can be successfully solved, as well as inhibiting the reaction between the high-K dielectric gate insulating film and the Shixi substrate, and the reaction between the 咼 K dielectric gate insulating film and the gate. . Another objective of the present month is to provide a semiconductor device including: a channel region formed in a silicon crystal layer, and a gate insulating film formed in the channel region, containing a silicon oxide layer formed on a stone evening crystal layer -A first nitride stone layer formed on the oxide stone layer, a dielectric metal oxide layer formed on the first silicon nitride layer, and a second nitrogen layer formed on the dielectric metal oxide layer A silicon layer and a gate are formed on the gate insulating film. Another objective of this month is to provide a semiconductor device including: a silicon substrate, a gate insulating film formed on the silicon substrate; and
544735 五、發明説明( a成於閑絕緣膜上 、之閉極’其中該開絕緣膜包含: 弟、%緣肤,其包含一由氧原子s 各個氧原子係&—子組成之乳原子層, 之石夕原子層,各個石夕原子係與氧原 =、、且成 子鍵結;以及-=:咖_子層之”、 係與氮原子層之氮原子鍵結/―石夕原子層’各個石夕原子 第一、%緣膜,其包含一由氧原子組成之氧 各個氧原子係與第二石夕原子層之石夕原子鍵結;—由全屬曰原 子組成之金屬原子層,各個金屬原子係與氧原子層之氧々 ^結;以氧原子組成之氧原子層,各個氧原子係與= 訂 之2子鍵結;以及於最頂部’-由氧原子組成 原之:=,各個氧原子係與金屬原子層之—個金屬 > -第三絕緣膜’其包含一由矽原子組成之矽原子層, 該層覆蓋最頂上氧原子層’各個石夕原子層係於最頂氧科 層之-個氧原子鍵結;以及—由氮原子組成之氮原子層, 各個氮原子係與覆蓋最頂上氧原子層及梦原子層,一㈣ 原子鍵結。 本發明之另-目的係提供—種製造半導體 法,包含: 製程’其中氣㈣供給切基板表面,讓石夕基板 表面吸收單一分子厚度的矽分子, ⑻-製程’其中含氧氣體供給石夕基板表面,該表面於 本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公釐) 544735 A7 B7 五、發明説明(6 ) _ 製程(A)後吸收矽原子,因此被吸附的矽分子經氧化,而於 石夕基板表面產生氧化石夕分子層, (C) 一製程,其中氣相矽供給矽基板表面,該表面於製 程(B)後係由氧化矽分子層覆蓋,因此矽分子被吸收成單分 子厚度, (D) —製程,其中含氮氣體供給矽基板表面,該表面於 製程(C)之後吸附矽分子,讓吸附的矽分子於矽基板表面上 形成氮化矽分子層, (E) —製程,其中含氧氣體以及含金屬元素氣體交替供 給矽基板表面,該表面於製程(D)之後由氮化矽分子層所覆 蓋,因而形成介電金屬氧化物膜, (F) —製程’其中氣相矽供給基板表面,該表面於製程 (E)之後需由介電金屬氧化物膜覆蓋,因此矽分子被吸附成 單分子厚度而形成矽分子層,以及 (G) ‘程’其中含氮氣體供給基板表面,該表面於製 私(F)之後係由矽分子層覆蓋,因此被吸附的矽分子於矽基 板表面上形成氮化石夕分子層。 本發明之特色及優點陳述於後文說明,部分由說明及 附圖將顯然自明,或可根據說明中提供的教示而由本發明 之實務習得。 本發明之目的及其它特色及優點可經由一種半導體 元件及其製法實現與達成,該元件及該方法特別以完整、 清晰、具體且確切的術語於說明書中陳述俾讓熟諳技藝人 士可實施本發明。 本紙張尺度適用中國國家標準(CNS) A4規格(210><297公爱) 9 (請先閲讀背面之注意事項再填寫本頁)544735 V. Description of the invention (a formed on the closed insulating film, the closed electrode 'wherein the open insulating film contains: younger brother,% margin skin, which contains a milk atom composed of oxygen atoms s each oxygen atom system &-child Layer, the Shixi atomic layer, each Shixi atomic system is bonded to the oxygen source, and-=: Ca_sublayer ", is bonded to the nitrogen atom of the nitrogen atomic layer /-Shixi atom The first and% edge film of each Shixi atom, which contains an oxygen composed of oxygen atoms, and each oxygen atom system is bonded to the Shixi atom of the second Shixi atomic layer;-a metal atom composed of all the atoms Layer, each metal atom system and the oxygen atom layer oxygen bond; the oxygen atom layer composed of oxygen atoms, each oxygen atom system and = 2 sub-bonds; and at the top '-composed of oxygen atoms : =, One metal of each oxygen atom system and metal atom layer> -The third insulating film 'comprises a silicon atom layer composed of silicon atoms, and this layer covers each of the topmost oxygen atom layers' -An oxygen atom bond to the topmost oxygen family; and-a nitrogen source consisting of nitrogen atoms Layer, each nitrogen atom system and the topmost oxygen atom layer and the dream atom layer are bonded to each other. Another object of the present invention is to provide a method for manufacturing a semiconductor, including: a process in which gas radon is supplied to the surface of a cutting substrate, Let the surface of the Shixi substrate absorb silicon molecules of a single molecular thickness, in which the oxygen-containing gas is supplied to the surface of the Shixi substrate, and this surface applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 544735 A7 B7 on this paper scale V. Description of the invention (6) _ After the process (A) absorbs silicon atoms, the adsorbed silicon molecules are oxidized, and a stone oxide molecular layer is generated on the surface of the stone substrate. (C) A process in which gas phase silicon is supplied. The surface of the silicon substrate is covered by a layer of silicon oxide molecules after the process (B), so the silicon molecules are absorbed to a single molecular thickness, (D) —the process, in which a nitrogen-containing gas is supplied to the surface of the silicon substrate, and the surface is in the process ( C) The silicon molecules are then adsorbed, so that the adsorbed silicon molecules form a silicon nitride molecular layer on the surface of the silicon substrate. (E) — the process in which oxygen-containing gas and metal element-containing gas are alternately supplied The surface of the silicon substrate, which is covered by a silicon nitride molecular layer after the process (D), thereby forming a dielectric metal oxide film. (F)-Process' wherein the gas phase silicon is supplied to the surface of the substrate, and the surface is on the process (E) ) Later, it needs to be covered by a dielectric metal oxide film, so silicon molecules are adsorbed to a single molecular thickness to form a silicon molecular layer, and (G) 'process' where a nitrogen-containing gas is supplied to the surface of the substrate, and this surface is used for manufacturing (F) It is then covered by a silicon molecular layer, so the adsorbed silicon molecules form a nitride stone molecular layer on the surface of the silicon substrate. The features and advantages of the present invention are described in the following description, and part of the description and the drawings will be self-explanatory, or may be It is learned from the practice of the present invention according to the teaching provided in the description. The objects and other features and advantages of the present invention can be achieved and achieved through a semiconductor element and a method for manufacturing the same, which are particularly complete, clear, specific, and exact terms It is stated in the description that a person skilled in the art can implement the present invention. This paper size applies to China National Standard (CNS) A4 specifications (210 > < 297 public love) 9 (Please read the precautions on the back before filling in this page)
544735 A7 ____B7 五、發明説明(7 ) "~ 星A之簡單說明 第1A圖-第ij圖為略圖_示根據本發明之第一具體每 施例,半導體元件之製造方法; 第2圖為略圖顯示由第u圖之結構製造之試樣結構,該 樣本係用於閘漏電流之測量; 第3圖為略圖顯示閘漏電流特性,此處第圖之氮原子 層未形成於第2圖之試樣; 第4圖為略圖顯示閘漏電流特性,此處第1;圖之氮原子 層形成於第2圖之試樣; 第5 A - 5 G圖為略圖顯示根據本發明之第二具體實施 例’半導體元件之製造方法;以及 第6圖為略圖顯示根據本發明之第三具體實施例, CMOS半導體裝置之結構。 說明 後文將參照附圖說明本發明之具體實施例。 第1A至1J圖顯示本發明之第一具體實施例,矽基板^ 上之高K介電閘絕緣膜之製造方法。 ’雖然純介電閘絕緣膜於後文說明中係藉原子層沉積方 法製成,但例如也可藉MBE方法等製成高κ介電閘絕緣膜。 mία圖,移除石夕基表面之天然氧化物膜而暴 露出基板表面之矽原子後,H2〇(水蒸氣)典型係於3〇〇它基 板溫度供給,於第1B圖之製程中,水分子被吸附至石夕基板 1表面。4結果石夕基板丨表面由單一原子厚度氧原子層〇1^所 均-覆蓋。該種情況下,氧原子層0L1之各個氧原子之一 本紙張尺度適用中國國家標準(CNS) A4規格(210χ297公嫠) 10 裝 訂 ----^^-線· C請先閱讀背面之注意事項再填寫本頁} 個鍵係鍵料基板之㈣子,而氧原子之另—個鍵係鍵結 風原子。結果於梦基板1表面上形成有-個分子厚度之二氧 化石夕層^二氧化石夕分子層表面2係由0H覆蓋。雖然氧原子 層队厫格而言並非—個原子厚度,9G%或以上氧原子鍵社 =基板表面之對料原子,故實質上可將其視為單原子層 厚度。 。其次’於第lc®之製程’四氯切氣體供給基板溫度 400 C之第1B圖結構表面,四氯化矽分子吸附。該種情況 下’氧原子層〇Ll表面之基於〇H之氫原子與四氯化石夕分子 反應且以氯化氫形式被移除’結果矽基板表面以單—原子 厚度由石夕原子層SL 1均—覆蓋。藉此方式製造切原子# SL 1之兩個㈣子鍵與氧原子層叫之兩個氧原子鍵社, 石夕原子之另外兩鍵係與兩個氯原子鍵結。雖然嚴格而言石夕 原子層SL i可能並非單原子厚度,但9〇%或以上矽原子與 -氧原子層OL,之氧原子鍵結,其隨後被視為單原子層 十八人於第1D圖之製程,氨氣於基板溫度4001:供給 第ic圖結構表面’然後單原子厚度之氮原子層叫係經由α 以氮原子歸梦原子層各個㈣子的氯原子形成。該種情 ^下,先刖鍵結矽原子層SL !之矽原子的氯原子係以氯化 氫形式被移除。以此種方式形成的各個氮原子係以兩個未 鍵結矽原子之鍵而與氫原子鍵結。經由第1〇圖之製程,單 原子厚度氮切層3形成於單原子厚度二氧切分子層^ 上。雖«格而言氮原子層NLi並非單—原子厚度,但卯曰% 五、發明説明(9 ) 或以上氮原子鍵結硬原子層SL i之對應㈣子,實質上可 被視為单原子厚度層。 、、 。其次於第1E®之製程’四氯切氣體供給基板溫度 4〇〇C之第1D圖結構表面,四氯化矽分子被均勻吸附。該 種情況下,與氮原子層叫之氮原子鍵結的氯原子係以氯 化氫形式被移除。結果,氮原子層NLi表面由單原子厚度 的矽原子層SL2均勻覆蓋。如此,形成的矽原子層乩2中一 個石夕原子的兩個鍵個別與氮原子層的—個氮原子鍵結。氮 化矽分子層之矽原子的剩餘兩個鍵個別與一個氯原子鍵 結。雖然嚴格言之,石夕原子層SL2並非單原子厚度,但90% 或以上矽原子係與氮原子層NL1之對應氮原子鍵結,其實 質上可視為單元之厚度層。 其次於第1F圖之製程,水蒸氣(私〇)於基板溫度4〇〇它 供給第1E圖之結構表面。然後與矽原子層SL〗之矽原子鍵 結的氯原子係以氯化氫形式被移除,形成氧原子層〇“, 其中氧原子係與矽原子層St之矽原子鍵結。氧原子層 之氧原子以及矽原子層SL2之矽原子可被視為組成二氧化 矽單分子層,也可被視為組成高K介電膜之一部分,容後 洋述。各個氫原子係與氧原子層〇L2的一個氧原子鍵結而 形成0H鹼。雖然嚴格而言氧原子層ο。並非單原子厚度, 但因90%或以上氧原子係與矽原子層sl之矽原子鍵結,其 貫夤上可視為早原子厚度層。 於第1G圖之製程中,四氯化铪氣體供給第巧圖結構表 面,四氯化铪分子被均勻吸附於氧原子層〇L2。該種情況 544735 A7 ----------B7 _ 五、發明説明(10 ) 下,於乳原子層〇L2表面形成0H鹼之氫原子與四氯化給分 子反應,H氯化氫形式被移除。結果氧原子層沉2由單 原子層厚度的給原子層HL1均勾覆蓋。如此形成的給原子 層HLl之一個铪原子的兩個鍵結係與氧原子層〇L2的兩個 氧原子鍵結,另外兩個鍵個別鍵結一個氯原子。雖然嚴袼 言之铪原子層非單原子厚度,但因9〇%或以上铪原子 層之铪原子係與氧原子層〇“之對應氧原子鍵結,故可 貫質考慮铪原子層1^1^為單原子厚度。 其次於第1H圖之製程,水蒸氣(h2〇)供給基板溫度4〇〇 C之第1G圖結構表面。結果鍵結铪原子層铪原子之氯 原子以氯化氫形式被移除,形成氧原子層〇1^,氧原子層 係由氧原子鍵結铪原子層Η。之铪原子組成。氧原子層〇l3 之氧原子係與铪原子層铪原子形成一個二氧化铪單 分子層。此外,一個氫原子鍵結氧原子層〇L3之各個氧原 子而形成OH鹼。又氧原子層ο。中,90%或以上氧原子鍵 結铪原子層HL之對應铪原子,其可實質視為組成單原子 厚度層。 又第1G圖及第1H圖製程可於第π圖製程重複任意次 數,因此組成氧原子層OL3及铪原子層Hl2之二氧化铪層4 形成於二氧化铪單分子層上,氧原子層〇L4進一步形成於 铪原子層HL2上。雖然氧原子層〇l3及铪原子層HL2嚴格而 言並非單原子厚度,但可實質視為單原子厚度層。 又一第1J圖之製程中,四氯化矽氣體及氨氣逐一供給 第Π圖結構,矽原子層SL3及氮原子層NL2組成的氮化矽單 * ............... 丨丨 本紙張尺度翻巾關家鮮(CNS) A4規格(21GX297公董) -~13~"544735 A7 ____B7 V. Description of the invention (7) " ~ A brief description of star A Figure 1A-Figure ij is a schematic diagram _ shows a method of manufacturing a semiconductor element according to the first specific embodiment of the present invention; Figure 2 is The sketch shows a sample structure made from the structure in Figure u, which is used to measure the leakage current. Figure 3 shows the characteristics of the leakage current in the thumbnail. The nitrogen atomic layer in Figure 2 is not formed in Figure 2. Fig. 4 is a schematic diagram showing the characteristics of the gate leakage current. Here, Fig. 1 is a sample in which the nitrogen atom layer is formed in Fig. 2. Figs. 5 A-5 G are schematic diagrams showing a second example according to the present invention. DETAILED DESCRIPTION A method of manufacturing a semiconductor device; and FIG. 6 is a schematic view showing a structure of a CMOS semiconductor device according to a third embodiment of the present invention. Description Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. Figures 1A to 1J show a first embodiment of the present invention, a method for manufacturing a high-K dielectric gate insulating film on a silicon substrate ^. Although a pure dielectric gate insulating film is made by an atomic layer deposition method in the following description, for example, a high-k dielectric gate insulating film may be made by the MBE method or the like. mία diagram, after removing the natural oxide film on the surface of Shi Xiji to expose the silicon atoms on the substrate surface, H2O (water vapor) is typically supplied at 300 substrate temperature. In the process of FIG. 1B, water Molecules are adsorbed on the surface of the Shi Xi substrate 1. 4 Results The surface of the Shixi substrate was uniformly-covered by a single-atom-thick oxygen atom layer. In this case, one of the oxygen atoms of the oxygen atomic layer 0L1. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210x297 cm) 10 Binding ---- ^^-line · C Please read the note on the back first Please fill in this page again} The bond of the bond system substrate and the other of the oxygen atom—the bond bond wind atom. As a result, on the surface of the dream substrate 1, a molecular oxide oxidized oxidized layer of ^ 2 oxidized oxidized molecular layer surface 2 was covered with 0H. Although the oxygen atomic layer is not an atomic thickness, 9G% or more oxygen atomic bond = the pair of atoms on the substrate surface, so it can be regarded as the thickness of the monoatomic layer. . Secondly, on the surface of the structure shown in FIG. 1B of the tetrachloro-cut gas supply substrate temperature 400 C in the process of lc®, silicon tetrachloride molecules are adsorbed. In this case, 'the hydrogen atom based on 0H on the surface of the oxygen atom layer 0Ll reacts with the tetrachloride stone molecule and is removed in the form of hydrogen chloride'. As a result, the surface of the silicon substrate has a single-atomic thickness from the stone layer atom SL1. -cover. In this way, the two bond bonds of the cut atom # SL 1 and the oxygen atom layer are called two oxygen atom bond society, and the other two bonds of Shi Xi atom are bonded with two chlorine atoms. Although strictly speaking, the Shi Xi atomic layer SL i may not be a single atom thickness, but 90% or more of the silicon atoms are bonded to the oxygen atoms of the-oxygen atom layer OL, which is subsequently regarded as a single atomic layer. In the process of 1D map, ammonia gas at the substrate temperature of 4001: supplied to the structure surface of the ic map, and then the single-atom-thickness nitrogen layer is formed by the chlorine atoms that are attributed to the various atoms of the dream atom layer through α. In this case, the chlorine atom of the silicon atom of the silicon atom layer SL! Which is first bonded is removed as hydrogen chloride. Each of the nitrogen atoms formed in this manner is bonded to a hydrogen atom with two unbonded silicon atoms. Through the process of FIG. 10, the single-atom-thickness nitrogen cut layer 3 is formed on the single-atom-thickness dioxon molecular layer ^. Although «the nitrogen atomic layer NLi is not mono-atomic in thickness, it is said to be%. 5. The description of the invention (9) or above The corresponding atom of nitrogen atom bonded to the hard atomic layer SL i can be regarded as a single atom in essence. Thick layer. ,,. Secondly, the silicon tetrachloride molecules are uniformly adsorbed on the surface of the structure shown in FIG. 1D of the 1C process of tetrachloro gas supply substrate temperature 400C. In this case, a chlorine atom bonded to a nitrogen atom called a nitrogen atom layer is removed as hydrogen chloride. As a result, the surface of the nitrogen atom layer NLi is uniformly covered by the silicon atom layer SL2 having a single atom thickness. In this way, the two bonds of one stone atom in the formed silicon atomic layer 乩 2 are individually bonded to one nitrogen atom of the nitrogen atomic layer. The remaining two bonds of the silicon atom in the silicon nitride molecular layer are each bonded to a chlorine atom. Although strictly speaking, the Shixi Atomic Layer SL2 is not a single-atom thickness, but 90% or more of the silicon atom system and the corresponding nitrogen atom of the nitrogen atom layer NL1 are bonded, which can actually be regarded as a thickness layer of the unit. Secondly, in the process of FIG. 1F, water vapor (private) is supplied to the structure surface of FIG. 1E at a substrate temperature of 400. Then the chlorine atom bonded to the silicon atom of the silicon atom layer SL is removed in the form of hydrogen chloride to form an oxygen atom layer 0 ", wherein the oxygen atom system is bonded to the silicon atom of the silicon atom layer St. The oxygen of the oxygen atom layer The atoms and silicon atoms of the silicon atom layer SL2 can be regarded as constituting a silicon dioxide monomolecular layer or a part of a high-K dielectric film, which will be described later. Each hydrogen atom system and oxygen atom layer 〇L2 An oxygen atom is bonded to form a 0H base. Although strictly speaking, the oxygen atom layer is not a single-atom thickness, but because 90% or more of the oxygen atom system is bonded to the silicon atom of the silicon atom layer sl, it can be seen from above. It is an early atomic thickness layer. In the process of FIG. 1G, thorium tetrachloride gas is supplied to the surface of the structure of the graph, and thorium tetrachloride molecules are uniformly adsorbed on the oxygen atom layer OL2. In this case 544735 A7 ---- ------ B7 _ 5. In the description of the invention (10), the hydrogen atom forming a 0H base on the surface of the milk atom layer OL2 reacts with the tetrachloride donor molecule, and the hydrogen hydrogen chloride form is removed. As a result, the oxygen atom layer is deposited. 2 is covered by a single atomic layer thickness of the donor atomic layer HL1. The two bonds of one plutonium atom in the sub-layer HL1 are bonded to two oxygen atoms in the oxygen atom layer 0L2, and the other two bonds are individually bonded to one chlorine atom. Although strictly speaking, the plutonium atomic layer has a non-monoatomic thickness. However, since 90% or more of the fluorene atomic system of the fluorene atomic layer is bonded to the corresponding oxygen atom of the oxygen atomic layer 0, the fluorene atomic layer 1 ^ 1 ^ can be considered as a single atom thickness. Secondly, in the process of FIG. 1H, water vapor (h2O) is supplied to the structure surface of FIG. 1G according to the substrate temperature of 400 ° C. As a result, the chlorine atoms of the 铪 atomic layer of the 铪 atomic layer were removed in the form of hydrogen chloride, forming an oxygen atom layer 〇1 ^, which was bonded to the 铪 atomic layer Η by the oxygen atom.铪 of atomic composition. The oxygen atomic layer of the oxygen atom layer 103 forms a monolayer of europium dioxide with the europium atom of the europium layer. In addition, one hydrogen atom binds each oxygen atom of the oxygen atom layer OL3 to form an OH base. And oxygen atom layer ο. Among them, 90% or more of the oxygen atoms are bonded to the corresponding plutonium atoms of the plutonium atomic layer HL, which can be substantially regarded as constituting a single-atom thick layer. The processes of Figures 1G and 1H can be repeated any number of times in the process of Figure π. Therefore, the hafnium dioxide layer 4 that constitutes the oxygen atom layer OL3 and the hafnium atom layer Hl2 is formed on the hafnium dioxide monolayer and the oxygen atom layer. L4 is further formed on the rhenium atomic layer HL2. Although the oxygen atomic layer 103 and the europium atomic layer HL2 are not strictly single-atom-thick, they can be considered substantially as single-atom-thickness layers. In the process of FIG. 1J, silicon tetrachloride gas and ammonia gas are supplied one by one to the structure of FIG. Π. The silicon nitride layer composed of the silicon atomic layer SL3 and the nitrogen atomic layer NL2 * .......... ..... 丨 丨 This paper is a standard size paper towel (CNS) A4 (21GX297)-~ 13 ~ "
.....裝..... (請先閲讀背面之注意事項再填窝本頁) 、τ· --線丨 544735 A7 -------__ 五、發明説明(11 ) 原子層5形成於氧原子層01^上。雖然矽原子層81^及氮原 子層NL2嚴格而言並非單元之厚度層,但類似先前各原子 層〇Ll至〇“可實質被視為單原子厚度層。 第1A圖至第ij圖之製程進行之原子層〇Li測量至原子 層NL2之厚度為丨至15奈米,製造高尺介電閘絕緣膜,於其 上方形成閘極如多晶石夕閘極。 % 第1A圖至第1J圖之製程中,特別第1A圖之中,此 處碎基板表面由氧原子層0Ll所直接均勾覆鍵或 界面階形成於界面,形成高品質二氧化石夕單|$層2。如 此,當半導體元件操作,通道區以高速運送載子時,載子 不會被懸垂鍵及界面|捕捉,因此半導體元件之臨限值特 性及漏電流特性不會歲化。 又因第1D圖之製程中,氮化石夕單分子層3形成於二氧 化矽單分子層2上’當於第1G圖至第II圖之製程,二氧化 铪形成於此氮化矽層3上時,可有效抑制二氧化铪層之铪及 氧展開石夕基板。進-步使用此種結構,因氮化石夕單分子層 之氮原子層係以氧原子層0Ll及石夕原子層%而與石夕基^ 表面分開,故可防止因氮原子之固定電荷造成半導體元件 之臨限值特性起伏波動。 同理,本具體實施例中’含氮化石夕分子層之氮原子芦 NL2形成於二氧化給層上’因此可有效抑祕原子及氧 子々由二氧化铪層展開至多晶石夕間極。此外,也可有效抑制 硼荨摻雜劑由多晶石夕閘極展開至發基板。 於具有第1J圖所示結構之高κ介電閘絕緣膜,重要地 本紙張尺度適用中國國家標準(CNS) Α4規格(210Χ297公楚) 14..... Packing ..... (Please read the precautions on the back before filling in this page), τ · --line 丨 544735 A7 -------__ V. Description of the invention (11) Atom The layer 5 is formed on the oxygen atom layer 01 ^. Although the silicon atomic layer 81 ^ and the nitrogen atomic layer NL2 are not strictly the thickness layer of the unit, they are similar to the previous atomic layers 0L1 to 0 "and can be regarded as the single-atom-thickness layer substantially. The processes of Figs. 1A to ij The atomic layer OLi measured to the thickness of the atomic layer NL2 is from 15 to 15 nanometers, and a high-scale dielectric gate insulating film is manufactured, and a gate electrode such as a polycrystalline silicon gate is formed thereon.% Figure 1A to 1J In the process of the drawing, especially in FIG. 1A, here the surface of the broken substrate is directly bonded to the interface by the oxygen atom layer 0Ll, or the interface step is formed at the interface to form a high-quality dioxide dioxide single layer | $ 2. So, When the semiconductor device is operated and carriers are transported at a high speed in the channel region, the carriers will not be captured by the dangling bonds and the interface |. Therefore, the threshold characteristics and leakage current characteristics of the semiconductor device will not age. Also because of the manufacturing process of Figure 1D In the process, nitride monolithic layer 3 is formed on silicon dioxide monomolecular layer 2. When the hafnium dioxide is formed on this silicon nitride layer 3 in the process of FIG. 1G to FIG. II, the The hafnium oxide layer and the oxygen-developed Shixi substrate. Further use of this structure Because the nitrogen atom layer of the nitride monolayer is separated from the surface of the stone base with the oxygen atom layer 0Ll and the stone base atom%, it can prevent the threshold characteristics of the semiconductor device due to the fixed charge of the nitrogen atom. In the same way, in this specific embodiment, 'the nitrogen atom NL2 of the nitrogen-containing molecular layer is formed on the dioxide supply layer', so it can effectively suppress the secretion of atoms and oxygen atoms from the hafnium dioxide layer to the polycrystalline stone. Evening poles. In addition, it can also effectively inhibit the dopant dopant from spreading from polycrystalline silicon gates to the hair substrate. For high κ dielectric gate insulating films with the structure shown in Figure 1J, it is important to use this paper size China National Standard (CNS) Α4 Specification (210 × 297)
裝---- (請先閲讀背面之注意事項再填寫本頁) 訂— -線丨 544735 五、發明説明(l2 由一乳化給層積層組成的高κ介電膜係由氧原子層〇 〇l4所失置。因而各㈣原子鍵結四個氧原子,^維 铪原子於四價態’防止因還原而造成氧缺乏。 、’ 本具體實施例中,提供一層氧原子層〇Li以及— 原子層SLl。但可提供多層氧原子層及多層石夕原子層。曰同 理,可提供多層氮原子層叫及多層石夕原子層sl2。作若罝 有低介電常數的二氧化石夕層厚度於二氧化給下方增加,則 ί攀 使用,有高K介電常數之二氧化給的效果降低。因此二氧 化石夕薄膜厚度的增加有極限。 至於高κ介電薄膜之替代材料’可考慮二氧化鍅。但 二氧化錯於半導體製程使料溫度範圍料產生麻田散鐵 型«遷。因此理由故,較好使用二氧化給,二氧化給於 訂 較咼溫產生相變遷。 •進-步,高Κ介電薄膜之其它材料包括Sr、Ba、丁卜 Ti Y Lr及金屬系元素之氧化物及石夕酸鹽。 ♦ 一第2圖顯示一種試樣結構,其中多晶矽層6係設置作為 以前述方式形成的高K介電閘絕緣膜上的電極。 第3圖及第4圖測量第2圖所示試樣之漏電流特性結 果。但第3圖所示結果表示第1J圖之氮原子層队及队被 刪除之例。以第4圖案例為例,氮原子層NLi及NL2係於第 1D圖及第^圖之製程中藉㈣。c之氨氣加熱製程形成,氧 原子層及氮原子層係形成為總厚度變成約為i奈米。任一種 情況下氧化铪層 < 總薄膜厚度為3奈米。=氧化铪層形 成後於700 C進行快速加熱處理3〇秒,然後於59〇。〔形成 本紙張尺度適用中國國豕標準(CNS) Α4規格(21〇\297公酱) 544735 A7 _ B7 五、發明説明(13 ) 多晶矽電極,然後於1000X:進行加熱處理5秒俾用於摻雜劑 的活化加熱處理。第3圖及第4圖中,不同曲線表示不同塊 試樣結果。 參照第3圖,漏電流密度jg於外加電壓+1伏特係於〇 β 至55安培厘米之範圍:、它方面,參照第4圖,於外加電壓 + 1伏特,漏電流密度/|係%0.84至7.88xl〇-5安培厘米·2之範 圍,该漏電流比較y 圖顯著減少。又以第4圖為例,以氧 化物當量厚度表示^^厚度係於1.77至1.84奈米之範圍。 藉此方式,根據本發明,經由以氧原子層覆蓋矽基板 表面,以及進一步藉氮原子層覆蓋高κ介電常數層之上方 及下方,可顯著改善高Κ介電閘絕緣層之漏電流特性。 [弟 '一具體貫施例] 第5Α至5G圖顯示本發明之第二具體實施例之半導體 元件10之製造方法。 參照第5Α圖,於具有表面方向性(1〇〇)ip型矽基板11 上,藉熱氧化處理形成熱氧化層lla,進一步藉CVD於熱氧 化膜11a上形成氮化矽膜111}。 此外,於第5A圖之製程,藉乾蝕刻圖樣化氮化矽膜Ub 而形成對應隔離區的開口,以及使用氮化矽膜丨lb作為光 罩,對熱氧化膜lla施加乾蝕刻圖樣化而形成暴露出石> 基板 11之另一開口。此外,使用氮化矽膜丨lb作為光罩,形成具 有傾斜側壁的隔離槽11A及UB,對應於藉濕蝕刻暴露矽基 板11形成的開口。 其次於第5B圖之製程,熱氧化施加至第5 A圖結構,附 本紙張尺度適用中國國家標準75) A4規格⑵〇χ297公釐 —-16 - -Installation ---- (Please read the precautions on the back before filling this page) Order --- line 丨 544735 V. Description of the invention (l2 A high-k dielectric film composed of an emulsified layer is composed of an oxygen atom layer. 〇〇 l4 is misplaced. Therefore, each fluorene atom is bonded to four oxygen atoms, and the dimensional fluorene atom is in a tetravalent state to prevent oxygen deficiency due to reduction. In this embodiment, a layer of oxygen atoms is provided, and Li and- Atomic layer SL1. However, it can provide multiple oxygen atom layers and multiple stone atom layers. In the same way, it can provide multiple nitrogen atom layers called multilayer stone layer atom layers sl2. It can be used as a silicon dioxide with low dielectric constant. If the thickness of the layer is increased below the oxide, then the effect of the oxide with a high K dielectric constant will be reduced. Therefore, there is a limit to the increase in the thickness of the SiO2 film. As for the alternative material of the high-k dielectric film ' It is possible to consider thorium dioxide. However, it is wrong that the semiconductor process causes the material temperature range of the Mata scattered iron type to be shifted. Therefore, it is better to use the titanic oxide to give a phase transition at a higher thorium temperature. Further, high-k dielectric films Other materials include Sr, Ba, Tib L, Ti Y Lr, and oxides of metal elements and oxalates. ♦ Figure 2 shows a sample structure in which the polycrystalline silicon layer 6 is set as the high K formed in the aforementioned manner. Electrodes on the dielectric barrier insulation film. Figures 3 and 4 measure the leakage current characteristics of the sample shown in Figure 2. However, the results shown in Figure 3 indicate that the nitrogen atomic team and team in Figure 1J have been deleted. Take the 4th pattern example as an example, the nitrogen atom layers NLi and NL2 are borrowed from the process of Figures 1D and ^. The ammonia gas heating process of c is formed, and the oxygen atom layer and nitrogen atom layer are formed as The total thickness becomes approximately 1 nanometer. In either case, the hafnium oxide layer < the total film thickness is 3 nanometers. = After the hafnium oxide layer is formed, a rapid heat treatment is performed at 700 C for 30 seconds, and then 59 °. This paper size applies the Chinese National Standard (CNS) A4 specification (21〇 \ 297 male sauce) 544735 A7 _ B7 V. Description of the invention (13) Polycrystalline silicon electrode, and then heat treatment at 1000X: 5 seconds, used for dopants Activation heat treatment. In Figures 3 and 4, different curves indicate different blocks. Sample results: Refer to Figure 3, the leakage current density jg at the applied voltage +1 volts is in the range of 0 β to 55 amp centimeters: For other aspects, refer to Figure 4, at the applied voltage + 1 volt, the leakage current density / | In the range of 0.84 to 7.88xl0-5 amp cm · 2, the leakage current is significantly reduced compared to the y graph. Taking the fourth graph as an example, the oxide equivalent thickness is shown ^^ The thickness is 1.77 to 1.84 nm In this way, according to the present invention, by covering the surface of the silicon substrate with an oxygen atom layer, and further covering the upper and lower layers of the high-k dielectric constant layer by the nitrogen atom layer, the high-K dielectric gate insulating layer can be significantly improved. Leakage current characteristics. [First embodiment] FIGS. 5A to 5G show a method of manufacturing a semiconductor device 10 according to a second embodiment of the present invention. Referring to FIG. 5A, a thermal oxidation layer 11a is formed on the silicon substrate 11 having surface directivity (100) ip type by thermal oxidation treatment, and a silicon nitride film 111 is further formed on the thermal oxidation film 11a by CVD. In addition, in the process of FIG. 5A, the silicon nitride film Ub is patterned by dry etching to form an opening corresponding to the isolation region, and the silicon nitride film lb is used as a photomask to apply a dry etching pattern to the thermal oxide film 11a. Another opening of the substrate 11 is formed. In addition, a silicon nitride film lb is used as a photomask to form the isolation grooves 11A and UB having inclined sidewalls, corresponding to the opening formed by exposing the silicon substrate 11 by wet etching. Secondly, in the process of Figure 5B, thermal oxidation is applied to the structure of Figure 5A. The size of the attached paper applies to the Chinese national standard 75) A4 specification ⑵〇χ297mm —-16--
.....裝----- (請先閲讀背面之注意事項再填寫本頁) 訂— 544735 A7 __B7 五、發明説明(14 ) 圖中被刪除之線性氧化物膜係形成於隔離槽丨丨A及1之 側壁及底部。然後隔離槽11A及11B以CVD-二氧化石夕膜填 補。然後CVD-Si〇2薄膜、其下方之氮化矽膜llb、及其下 方之熱氧化物膜Ua接地,藉CMP方法去除,形成填補隔離 槽11A及11B之二氧化矽隔離區11(:及110。 又於第5B圖之製程,矽基板1丨表面暴露出,矽基板表 面藉保護性氧化。然後經保護性氧化表面藉氫氟酸處理去 除’而暴露出新鮮碎基板表面。 其次於第5C圖之製程,進行前文說明之第丨八圖至第u 圖之製程至矽基板11表面,形成閘絕緣膜12,該層結構係 如第1J圖所示。 其次於弟5 D圖之製程,多晶石夕層13沉積於閘絕緣膜12 上,結果獲得第2圖之相同結構。 然後於第5E圖之製程,多晶石夕膜13及閘絕緣膜12經圖 樣化,形成多晶矽閘極13A、13B及13C。 於第5E圖之製程,使用多晶矽閘極13A至13C作為光 罩,植入η型雜質,因此於矽基板11内側形成LDD展開區。 特別LDD展開區14Α形成於閘極13Α兩面上,LDD展開區 HB形成於閘極13Β兩面上,以及LDD展開區14C形成於閘 極13C兩面上。 於第5Ε圖之製程,侧壁絕緣膜形成於閘極13 A、13Β 及13C個別之側壁上。使用閘極13A、13B及13C之侧壁薄 膜作為光罩,進行離子植入,因此展開區15A、15B及15C 形成於LDD展開區14A、14B及14C外側。 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 17 --------------·裝------------------訂--------------·線. (請先閲讀背面之注意事項再填寫本頁) 544735 五 Λ發明説明(i5) 又於第5F圖之製程,例如矽化始之低電阻石夕化金屬層 13a至13c及15a至15c係藉自我對準矽化物層方法,形成於 閘極13A至13C之展開區15A至15C表面上。 最後,於第5G圖之製程,氮化矽薄膜16係藉cVD而形 成於第5F圖結構上,故閘極13八至13(::經覆蓋,層絕緣膜17 進一步形成於氮化矽膜16上。 然後,層絕緣膜17藉CMP方法變平坦,形成接觸孔, 接觸孔暴露展開區15A至15C,接觸插塞ι8Α至18C形成於 接觸孔,故分別接觸展開區15八至15〇。 如刖述,本發明之半導體元件包括藉第5C圖製程形成 的高κ介電閘絕緣膜作為閘絕緣膜12,實現〇 ι微米或以下 勺短的閘長度達成1至數奈米之閘絕緣膜。實體薄膜厚 度,抑制直接穿透位障效應造成的閘漏電流。 又本卷明之半導體元件包括氧原子層於閘絕緣膜i 2 直接接财基板11部分,其組成通道區,達成穩定臨限值 特性,而於基板與閘絕緣膜間的界面未形成懸垂鍵及界面 階。 又使用本發明之半導體元件,因高W電膜係由氮原 子層所夾置,高K介電膜之金屬元素及氧未展開至石夕基板 叫多晶㈣㈤3A至13c,結果獲得絕佳臨限值特性。進 -步’來自多晶矽閘極的摻雜劑雜質經由閘絕緣㈣展開 至石夕基板也受到壓抑,而可抑制臨限值特性的起伏波動。 此外,本具體實施例中,因氮原子層係藉氧原子層 石夕原子層而與石夕基板層隔開,故可抑制因氮原子之固定 及 電 本紙張尺度適财國时鮮(⑽A4^..... install ----- (Please read the precautions on the back before filling this page) Order — 544735 A7 __B7 V. Description of the invention (14) The linear oxide film deleted in the figure is formed in the isolation groove丨 丨 A and 1 side wall and bottom. The isolation trenches 11A and 11B are then filled with a CVD-stone dioxide film. Then, the CVD-SiO2 film, the silicon nitride film 11b below it, and the thermal oxide film Ua below it are grounded and removed by the CMP method to form a silicon dioxide isolation region 11 (: and 110. In the process of FIG. 5B, the surface of the silicon substrate 1 is exposed, and the surface of the silicon substrate is subjected to protective oxidation. Then the protective oxidized surface is removed by hydrofluoric acid treatment to expose the surface of the freshly broken substrate. In the process of FIG. 5C, the processes described in the eighth to eighth diagrams described above to the surface of the silicon substrate 11 are formed to form a gate insulating film 12, and the layer structure is as shown in FIG. 1J. Next is the process of FIG. 5D The polycrystalline stone layer 13 is deposited on the gate insulating film 12, and the same structure as shown in FIG. 2 is obtained. Then, in the process of FIG. 5E, the polycrystalline silicon film 13 and the gate insulating film 12 are patterned to form a polycrystalline silicon gate. 13A, 13B, and 13C. In the process of FIG. 5E, polysilicon gates 13A to 13C are used as photomasks to implant n-type impurities, so LDD expansion regions are formed inside the silicon substrate 11. In particular, LDD expansion regions 14A are formed at the gates. On both sides of the pole 13A, the LDD expansion region HB is formed on the gate 13 On both sides, and the LDD expansion region 14C is formed on both sides of the gate electrode 13C. In the process of FIG. 5E, a sidewall insulating film is formed on each of the gate electrodes 13 A, 13B, and 13C. Gates 13A, 13B, and 13C are used. The side wall film is used as a photomask for ion implantation, so the expanded regions 15A, 15B, and 15C are formed outside the LDD expanded regions 14A, 14B, and 14C. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 17 -------------- · Install --------------------- Order -------------- · Wire. (Please read the notes on the back before filling in this page) 544735 Five Λ invention description (i5) and the process in Figure 5F, such as low-resistance petrified metal layers 13a to 13c and 15a to 15c from silicidation It is formed on the surface of the developed regions 15A to 15C of the gates 13A to 13C by the self-aligned silicide layer method. Finally, in the process of FIG. 5G, the silicon nitride film 16 is formed on the structure of FIG. 5F by cVD. Therefore, the gate electrodes 13 to 13 (:: are covered, and the layer insulating film 17 is further formed on the silicon nitride film 16. Then, the layer insulating film 17 is flattened by the CMP method to form a contact hole, and the contact hole is exposed and unfolded. 15A to 15C, contact plugs 8A to 18C are formed in the contact holes, so they contact the developed regions 15 to 15 respectively. As described, the semiconductor device of the present invention includes a high-κ dielectric gate insulating film formed by the process of FIG. 5C As the gate insulation film 12, a gate insulation film with a short gate length of 1 μm or less and a thickness of 1 to several nanometers is realized. The thickness of the solid film can suppress the gate leakage current caused by the barrier effect. The semiconductor element of this document includes an oxygen atom layer on the gate insulating film i 2 directly connected to the 11th part of the substrate, which constitutes a channel region to achieve stable threshold characteristics, and no dangling bond is formed at the interface between the substrate and the gate insulating film. Interface level. The semiconductor element of the present invention is also used, because the high-W electrical film is sandwiched by a layer of nitrogen atoms, and the metal elements and oxygen of the high-K dielectric film are not spread to the Shi Xi substrate called polycrystalline silicon 3A to 13c, and the result is excellent. Limit characteristics. Further, the dopant impurities from the polycrystalline silicon gate are expanded to the Shixi substrate through the gate insulator, and the fluctuation of the threshold characteristics can be suppressed. In addition, in this specific embodiment, since the nitrogen atom layer is separated from the stone substrate layer by the oxygen atom layer and the stone layer, it can be suppressed due to the fixation of the nitrogen atom and the size of the paper. ^
---------·裝…: (請先閲讀背面之注意事項再填寫本頁) .、可| r線丨 18 544735 A7 B7 五、發明説明(16 ) 荷造成臨限值特性的起伏波動。 又於本具體實施例中,因高K介電層係由氧原子層所 夾置,故高K介電層金屬元素如鍅及铪之價數穩定,而可 防止如相對介電常數下降等問題。 [第三具體實施例] 第6圖顯示本發明之第三具體實施例之CMOS半導體 元件20之結構。 參照第6圖,CMOS半導體元件20包括一隔離區22,其 將P型矽基板21劃分為p通道MOS區20A及η通道MOS區 20Β。於ρ通道MOS區20Α,形成η型井20W。 於ρ通道MOS區20Α,形成具有第1J圖所示相同層結構 的高Κ介電閘絕緣膜23 A,對應於通道區,以及於閘絕緣膜 23 A上形成硼摻雜的多晶矽閘極24A。此外,於多晶矽閘極 24 A上藉自我對準矽化物層方法形成矽化金屬層25A。又於 多晶矽閘極24A兩面上形成側壁薄膜。 於ρ通道MOS區20A,藉硼離子植入井20W,形成對應 閘極24A壁面之各邊的ρ型LDD區26Lp,進一步於側壁絕緣 膜外側形成P+型展開區26p。又於p+型展開區表面形成石夕 化金屬低電阻層27p。 同理,於η通道MOS區20B,形成具有第1J圖的相同層 結構之高Κ介電閘絕緣膜23Β,其係對應通道區;以及砷或 磷摻雜之多晶矽閘極24Β形成於閘絕緣膜23Β上。又於多晶 矽閘極24Β上藉自我對準矽化物製程形成矽化金屬層 25Β。又於多晶矽閘極25Β兩面上形成側壁薄膜。 19 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公釐) 544735 A7 ____B7_ 五、發明説明(Π ) 於η通道MOS區20B,對應閘極24B壁面兩面,藉離子 植入石申或鱗而形成η型LDD區26Ln,進一步於側壁絕緣膜 外側形成n+型展開區26η。又於n+型展開區26n表面上形成 矽化金屬低電阻層27η。 使用此種結構之CMOS裝置,經由使用第υ圖所示高尺 介電閘絕緣膜,p通道MOS電晶體及n通道M〇s電晶體個別 形成〇· 1微米或以下的極短閘長度。因此當減少閘絕緣膜之 氧化物相當薄膜厚度時,可形成一至數奈米實體薄膜厚度 的絕緣膜23A及23B,而可避免因穿透位障電流造成閘漏電 流的增加。 於第ij圖結構之高κ介電閘絕緣膜,因氮原子層NLi 及NL2係於薄膜形成,故可有效抑制氧及金屬元素如铪及 鍅經由閘絕緣膜23A及23B展開。又因高品質二氧化矽分子 層係形成於接觸矽通道區部分,故可避免於矽基板與閘絕 緣膜間的界面形成懸垂鍵以及形成界面階,而可達成穩定 臨限值特性。又因氮原子層NLi係與矽基板表面分開形 成’故也可避免因氮原子之固定電荷造成臨限值特性的起 伏波動。 特別使用第6圖之CMOS半導體元件,於使用摻雜成為 P型的多晶矽閘極24B之p通道MOS電晶體,硼由多晶矽閘 極24A展開至矽基板21係藉由形成氮原子層NLl及NLjip 制’而可避免通道區的摻雜造成臨限值特性的起伏波動。 又本毛明並非限於此等具體貫施例,可未丨孛離本發明 之範圍做出多種變化與修改。 本紙張尺度適用中國國家標準(CNS) A4規格(21〇><297公董) 20 裝 訂 線· (請先閲讀背面之注意事項再填寫本頁) 544735 A7 B7 五、發明説明(i8) 元件標號對照 1…梦基板 3…氮化石夕層 10··.半導體元件 11 a·.·熱氧化物膜 11A,11B··.隔離槽 12…閘絕緣膜 13a-c···矽化金屬層 14A-C··丄DD展開區 15A-C...展開區 17.. .層絕緣膜 20.. .CMOS半導體元件 206.. .11.道以〇8區 21···ρ型矽基板 23 Α·B · ·.南K介電閘絕緣膜 25 A-B. · ·石夕化金屬層 26Lp...p型 LDD區 26Ρ·.·ρ+型展開區 2----氧化碎層 6 · · ·多晶層 11·._ρ型矽基板 11 b · · ·氮化碎膜 lie,11D·.·二氧化矽隔 13.. .多晶層 13 A - C...多晶碎間極 15a_c…矽化金屬層 16…氮化石夕膜 18A-C···接觸插塞 20Α···ρ 通道 MOS 區 20W".n型井 22.. .隔離區 2 4 A - B…多晶秒問極 26Ln._.n型 LDD區 26η··.n+型展開區 27p···石夕化金屬低電阻層--------- · Installation: (Please read the precautions on the back before filling out this page)., You can | r line 丨 18 544735 A7 B7 V. Description of invention (16) Threshold characteristics caused by load Ups and downs. Also in this specific embodiment, since the high-K dielectric layer is sandwiched by an oxygen atom layer, the valences of the metal elements such as ytterbium and ytterbium in the high-K dielectric layer are stable, which can prevent, for example, a decrease in relative dielectric constant, etc. problem. [Third Specific Embodiment] Fig. 6 shows a structure of a CMOS semiconductor element 20 according to a third specific embodiment of the present invention. Referring to FIG. 6, the CMOS semiconductor element 20 includes an isolation region 22, which divides the P-type silicon substrate 21 into a p-channel MOS region 20A and an n-channel MOS region 20B. An n-well 20W is formed in the p-channel MOS region 20A. In the p-channel MOS region 20A, a high-K dielectric gate insulating film 23 A having the same layer structure as shown in FIG. 1J is formed, corresponding to the channel region, and a boron-doped polycrystalline silicon gate electrode 24A is formed on the gate insulating film 23 A. . In addition, a silicide metal layer 25A is formed on the polysilicon gate 24 A by a self-aligned silicide layer method. Side wall films are formed on both sides of the polysilicon gate 24A. In the p-channel MOS region 20A, boron ions are implanted into the well 20W to form p-type LDD regions 26Lp corresponding to the sides of the wall surface of the gate 24A. Further, a P + -type expansion region 26p is formed outside the sidewall insulating film. A low-resistance metal layer 27p is formed on the surface of the p + -type development region. Similarly, in the n-channel MOS region 20B, a high-K dielectric gate insulating film 23B having the same layer structure as in FIG. 1J is formed, which corresponds to the channel region; and an arsenic or phosphorus-doped polycrystalline silicon gate 24B is formed in the gate insulation. On film 23B. A self-aligned silicide process is used to form a silicide metal layer 25B on the polysilicon gate 24B. Side wall films are formed on both sides of the polysilicon gate 25B. 19 (Please read the notes on the back before filling this page) This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 544735 A7 ____B7_ V. Description of the invention (Π) is located in the n-channel MOS area 20B, corresponding to the gate On both sides of the pole 24B wall surface, an n-type LDD region 26Ln is formed by ion implantation of stone or scale, and an n + -type expanded region 26η is further formed on the outside of the sidewall insulation film. A low-resistance metal layer 27n is formed on the surface of the n + -type development region 26n. With this structure of the CMOS device, a p-channel MOS transistor and an n-channel MOS transistor are individually formed to have extremely short gate lengths of 0.1 micrometers or less by using the high-scale dielectric gate insulating film shown in Fig. Υ. Therefore, when the oxide of the gate insulating film is reduced to a film thickness, the insulating films 23A and 23B with a thickness of one to several nanometers can be formed, and the increase of the gate leakage current due to the barrier current can be avoided. In the high κ dielectric gate insulation film of the structure shown in FIG. Ij, since the nitrogen atom layers NLi and NL2 are formed on a thin film, oxygen and metal elements such as thorium and thorium can be effectively suppressed from spreading through the gate insulation films 23A and 23B. And because the high-quality silicon dioxide molecular layer system is formed in the contact silicon channel region, it can avoid the formation of dangling bonds and interface steps at the interface between the silicon substrate and the gate insulation film, and can achieve stable threshold characteristics. Since the nitrogen atom layer NLi is formed separately from the surface of the silicon substrate, it is also possible to avoid fluctuations in threshold characteristics due to the fixed charge of nitrogen atoms. In particular, the CMOS semiconductor device shown in FIG. 6 is used. In the p-channel MOS transistor doped with a polycrystalline silicon gate 24B that is P-type, boron is expanded from the polycrystalline silicon gate 24A to the silicon substrate 21 by forming nitrogen atom layers NL1 and NLjip. It can avoid the fluctuation of the threshold characteristics caused by the doping of the channel region. In addition, the present invention is not limited to these specific embodiments, and various changes and modifications can be made without departing from the scope of the present invention. This paper size applies the Chinese National Standard (CNS) A4 specification (21〇 > < 297). 20 Gutter · (Please read the precautions on the back before filling this page) 544735 A7 B7 V. Invention Description (i8) Element reference number 1 ... Dream substrate 3 ... Nitride layer 10 ... Semiconductor element 11 a ... Thermal oxide film 11A, 11B ... Isolation trench 12 ... Gate insulating film 13a-c ... Silicon metal layer 14A-C ·· DD development area 15A-C ... development area 17... Layer insulation film 20... CMOS semiconductor element 206......... 23 Α · B ··· South K dielectric gate insulation film 25 AB ··· Shixihua metal layer 26Lp ... p-type LDD region 26P ··· ρ + -type expansion region 2 ---- oxidized fragmentation layer 6 ··· Polycrystalline layer 11 · ._ρ-type silicon substrate 11 b ··· Nitride chip lie, 11D ··· Silicon dioxide barrier 13 .. .Polycrystalline layer 13 A-C ... Polycrystalline layer Electrode 15a_c ... silicided metal layer 16 ... nitride nitride film 18A-C ... contact plug 20A ... ρ channel MOS region 20W " .n-type well 22 ... isolation region 2 4 A-B ... polycrystalline seconds Interrogator 26Ln ._. N-type LDD region 26η ·· .n + -type expansion region 27p ··· Shi Xihua Metal Low Current Floor
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KR101030068B1 (en) * | 2002-07-08 | 2011-04-19 | 니치아 카가쿠 고교 가부시키가이샤 | Method of Manufacturing Nitride Semiconductor Device and Nitride Semiconductor Device |
-
2002
- 2002-03-19 JP JP2002077055A patent/JP3792589B2/en not_active Expired - Lifetime
- 2002-03-27 KR KR1020020016641A patent/KR100757645B1/en active IP Right Grant
- 2002-03-28 TW TW091106211A patent/TW544735B/en not_active IP Right Cessation
- 2002-03-29 CN CNB021218447A patent/CN1206736C/en not_active Expired - Lifetime
- 2002-03-29 US US10/109,001 patent/US6894369B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100757645B1 (en) * | 2001-03-29 | 2007-09-10 | 후지쯔 가부시끼가이샤 | Semiconductor device and complementary semiconductor device |
TWI460863B (en) * | 2008-06-27 | 2014-11-11 | Semiconductor Energy Lab | Thin film transistor |
Also Published As
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JP3792589B2 (en) | 2006-07-05 |
KR100757645B1 (en) | 2007-09-10 |
US20020146916A1 (en) | 2002-10-10 |
JP2002359370A (en) | 2002-12-13 |
KR20020077126A (en) | 2002-10-11 |
US6894369B2 (en) | 2005-05-17 |
CN1206736C (en) | 2005-06-15 |
CN1384549A (en) | 2002-12-11 |
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