JP3513018B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOSFET whose gate insulating film is thinned and a method for manufacturing the same.

[0002]

2. Description of the Related Art As a gate insulating film thickness of a fine transistor having a design dimension of 0.1 μm or less, 3 nm or less is required. In this thickness region, the conventional thermal oxide film cannot be used because of a large leak current. Therefore, Ta ₂ O
It has been proposed to apply a high dielectric film such as ₅ to a gate insulating film.

However, when a high dielectric film such as Ta ₂ O ₅ is used for the gate insulating film of the MOSFET, the underlayer (S
(between the i surface and the Ta ₂ O ₅ film) has a non-negligible thickness of S
Since it is necessary to form an iO ₂ layer or a silicon nitride film (SiN) layer, there is a problem that the effective oxide film thickness (T _eff ) of the gate insulating film cannot be reduced.

The reason for forming the SiO ₂ layer on the Si surface is as follows.
This is to form a good interface with few interface states. In addition, a silicon nitride film (SiN) layer is often formed on it. The reason is that Si is Ta ₂ O ₅
In order to prevent diffusion into the film, Ta ₂ O ₅ and Si
This is to prevent O ₂ from reacting.

[0005]

As described above, even if a Ta ₂ O ₅ film is used as a part of the gate insulating film and the effective oxide film thickness of the gate insulating film is reduced, a good interface level is obtained. There is a problem that it is necessary to form a SiO ₂ layer in order to obtain the interface, and the effective oxide film thickness cannot be reduced.

An object of the present invention is to use a high-dielectric or ferroelectric film as a part of the gate insulating film of a MOSFET and to reduce the leak current while reducing the effective oxide film thickness of the gate insulating film. It is to provide a semiconductor device to be obtained and a method for manufacturing the same.

[0007]

[Configuration] The present invention is configured as follows to achieve the above object. (1) The semiconductor device according to the present invention (claim 1) is (11)
1) A semiconductor device including a MOSFET formed on a silicon substrate, wherein a gate insulating film of the MOSFET has a single-layer Si—O bonding layer in which silicon atoms and oxygen atoms on the outermost surface of the silicon substrate are bonded. And this Si-O
It is characterized in that it is formed on the coupling layer and includes an insulating layer made of a high dielectric material or a ferroelectric material.

Preferred embodiments of the present invention are shown below.

The gate length of the MOSFET is 0.85 μ
m or less, the silicon oxide film equivalent effective film thickness of the gate insulating film is 2.6 nm or less, and the Si concentration in the insulating layer is less than 0.1 atom%. In addition, more preferably,
The Si concentration in the insulating layer is less than 0.001 atom%.

The insulating layer is directly formed on the Si-O bonding layer. (2) A method of manufacturing a semiconductor device according to the present invention (claim 3) comprises the steps of forming a dummy gate in a predetermined region on a (111) silicon substrate of the first conductivity type, and using the dummy gate as a mask. Introducing a second conductivity type impurity into the surface of the silicon substrate to form source / drain regions; forming an interlayer insulating film on the silicon substrate so as to cover the dummy gate; and forming the interlayer insulating film. Of exposing the dummy gate while flattening the surface thereof, forming a groove by selectively removing the dummy gate, and exposing the outermost surface of the silicon substrate on the bottom surface of the groove. A step of forming a single-layer Si-O bonding layer in which silicon atoms and oxygen atoms are bonded, and a step of forming an insulating layer made of a high dielectric material or a ferroelectric material on the Si-O bonding layer. And a step of burying and forming a gate electrode in the groove portion.

Preferred embodiments of the present invention are shown below.

After the insulating layer is formed, all processes are
It is performed at a temperature of 00 ° C or lower.

After the step of forming the dummy gate, silicide is formed in a self-aligned manner on the silicon substrate in the region to be the source / drain region.

The formation of the Si--O bond layer includes a step of removing a natural oxide film and a chemically formed oxide film on the surface of the silicon substrate on the bottom surface of the recess, and radical oxygen is applied to the silicon substrate. Irradiating.

The formation of the Si--O bond layer is performed by removing a natural oxide film or a chemically formed oxide film on the surface of the silicon substrate on the bottom surface of the recess and about 1 nm on the silicon substrate on the bottom surface of the recess. Forming a SiO ₂ film of
Irradiating the surface of the SiO ₂ film with nitrogen radicals at 600 ° C. or lower to nitride the surface of the SiO ₂ film.

[Operation] The present invention has the following operations and effects due to the above configuration.

Since oxygen is bonded to the silicon atoms on the (111) plane of silicon with good controllability, a good interface with a small interface state can be obtained even with a single-layer Si-O bonding layer. be able to. Therefore, the effective oxide film thickness of the gate insulating film can be reduced.

Further, according to the semiconductor manufacturing method of the present invention, since the gate electrode is formed after forming the source / drain regions, it is possible to use a metal electrode material such as Al for the gate electrode.

Since silicide (such as CoSi ₂ ) has a lattice constant close to that of silicon crystal, it is easy to grow epitaxially. However, CoSi ₂
Since CoSi and Co ₂ Si having different lattice constants grow, it is difficult to form a single crystal on the (100) plane of silicon and becomes polycrystalline.

For the (100) plane, the (11
In the 1) plane, since a large number of Si bonds are supplied, a silicide single crystal is likely to grow from the initial stage of growth. Therefore,
It is easy to form a uniform and low-resistance silicide film.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a sectional view showing the schematic arrangement of a semiconductor device according to the first embodiment of the present invention. In the semiconductor device of the present invention, the metal gate electrode 15 is formed in the region sandwiched by the source / drain regions 11 on the (111) silicon substrate 10 with the gate insulating film 20 interposed therebetween.

The feature of the present invention is that the gate insulating film 2 is formed.
0 is a single-layer Si—O bonding layer 12 formed by bonding oxygen to silicon atoms on the outermost surface of the (111) silicon substrate 10, a silicon nitride film (Si—N) 13, and a high dielectric film layer. (Ta ₂ O ₅ etc.) 14 is a laminated film.

As shown in FIG. 2, S of the (111) plane orientation is
Since the bonds of silicon atoms are regularly arranged on the surface of the i substrate 10, the Si—O bond layer 11 can be formed with good controllability. Therefore, the SiO ₂ layer can be made as thin as possible while maintaining a good interface with few interface states.

Next, the manufacturing process of the MOSFET to which the present invention is applied will be described with reference to the process sectional views of FIGS.

First, as shown in FIG.
1) A groove having a depth of about 200 nm is formed in an element isolation region on the surface of the semiconductor silicon substrate 10 having a plane orientation. Then, after the inner wall of the trench is thinly oxidized, for example, a TEOS-based oxide film is embedded and formed to form trench isolation (STI: Shal).
An element isolation insulating film 31 for low trench isolation is formed. Further, after performing ion implantation for forming wells and channels, a thermal oxide film 32 having a thickness of about 6 nm is formed on the surface of the substrate 10.

Next, as shown in FIG. 3B, as a dummy gate material, both a polysilicon film 33 ₁ and a silicon nitride film 33 ₂ are successively laminated by about 150 nm by LPCVD.

Next, as shown in FIG. 3C, a resist pattern (not shown) is formed in a gate formation planned region by photolithography or EB drawing, and silicon nitride other than the gate formation planned region is formed by RIE. The film 33 ₂ and the polysilicon film 33 ₁ are removed by etching to form a dummy gate 33. Then, the resist pattern is removed.

Next, as shown in FIG. 4D, an oxide film 35 having a thickness of about 6 nm is formed on the surface of the polysilicon film 33 ₁ by thermal oxidation. Next, as shown in FIG. 4E, ion implantation is performed using the dummy gate 33 as a mask to form an n ⁻ diffusion layer 36. The injection conditions are, for example, A
s, 15 keV, 3 × 10 ¹⁴ cm ⁻² . In the case of forming a CMOS, the n-type impurity and p
Type impurities.

Next, as shown in FIG. 4F, a sidewall insulating film 37 is formed on the side surface of the dummy gate 33 by depositing a silicon nitride film of about 70 nm and then performing RIE on the entire surface. Next, as shown in FIG. 5G, ion implantation is performed using the dummy gate 33 and the sidewall insulating film 37 as a mask, so that the n ⁺ diffusion layer in which the n-type impurity is doped at a higher concentration than the n ⁻ diffusion layer 36 is formed. 38 is formed. The implantation conditions are, for example, As, 45 keV, 3 × 10 ¹⁵ cm ^-2 . When forming a CMOS, n is formed by lithography.
Type impurities and p-type impurities are separated. Source /
The activation annealing of the drain diffusion layer may be performed each time immediately after the implantation, or may be performed once after the completion of all the ion implantations.

Then, as shown in FIG.
TEOS-based oxide film 39 ₁ is 350 nm over the entire surface by VD
Deposit to a degree. Then, as shown in FIG.
The interlayer insulating film 39 is formed by planarizing the surface of the TEOS oxide film 39 ₁ by the P method. At this time,
Sidewall insulating film 37 made of silicon nitride film 33 ₂ and the silicon nitride film becomes a stopper CMP, a dummy gate 33 is exposed. Then, as shown in FIG.
Etching using hot phosphoric acid is performed to selectively remove the silicon nitride film 33 ₂ of the dummy gate 33. At this time, the upper portion of the silicon nitride film of the side wall insulating film 37 is also etched, so that the height of the side wall insulating film 37 becomes slightly low.

Next, as shown in FIG. 6 (k), CDE
Removal of the polysilicon film 33 ₁ of the dummy gate by law,
By sequentially removing the silicon oxide films 32 and 35 by wet etching using HF, the trench 40 is formed in the gate formation planned region.

Next, a gate insulating film and a gate electrode are formed. Since the source / drain has already been formed (including activation) and there is basically no high temperature process of 600 ° C. or higher after this, a Ta ₂ O ₅ film or (Ba,
A high dielectric film such as Sr) TiO ₃ or a ferroelectric film can be used.

A metal material can be used for the gate electrode. When a high dielectric film or a ferroelectric film is used as the gate insulating film, it is necessary to select a gate electrode material according to the used gate insulating film. TiN, Al, W, R
u etc. can be used. Further, it is desirable to form TiN, WN or the like as a barrier metal between the gate insulating film and the gate electrode material.

Here, a Ta ₂ O ₅ film is used as the gate insulating film,
The case where aluminum / TiN is used for the gate electrode will be described.

As shown in FIG. 6 (l), (111) Si exposed in the groove 40 is formed by using hydrofluoric acid diluted once or a mixed solution of hydrofluoric acid and ammonium fluoride or anhydrous hydrofluoric acid.
The native oxide film or the chemically formed oxide film on the surface of the substrate 10 is removed. Then, the surface of the Si substrate 10 is irradiated with oxygen radicals to form a single-layer (film thickness of about 0.2 to 0.3 nm) Si—O bonding layer 12. Then, subsequently, the SiN layer 13 is 1.0 nm thick by using ammonia, silane, or the like.
About a thickness (0.6 nm equivalent to an oxide film) is deposited and formed. Further, a Ta ₂ O ₅ film 14 is formed to a thickness of about 1 nm (oxide film equivalent film thickness) by the whole surface CVD method. By doing so, the total film thickness of the gate insulating film becomes 2 nm (oxide film equivalent film thickness) or less.

As another method for forming the gate insulating film, first, a SiO ₂ film having a thickness of about 1 nm is formed, and the surface thereof is nitrided by nitrogen radicals at a low temperature (600 ° C. or lower) (N
₂ Plasma nitriding). When the SiN layer has a thickness of about 0.7 nm, the SiO ₂ layer has a thickness of about 0.3 nm,
Almost 1 monolayer Si-O bonding layer is realized. Then, a Ta ₂ O ₅ film 14 having a thickness of 1 nm is formed thereon by the CVD method.
If it is formed to a thickness (oxide film equivalent thickness), the gate insulating film thickness becomes 2 nm (oxide film equivalent film thickness) or less.

In any case, Si having a (111) plane orientation is used.
When using a substrate, the layer controllability is improved, and
It is easy to realize monolayer.

Next, a barrier metal T is used as a gate electrode.
iN41 and aluminum 42 ₁ are 10 nm and 2 respectively
Deposit about 50 nm. Then, as shown in FIG. 7 (m), the gate electrode 42 is formed by planarizing the surface of the aluminum 42 ₁ by the CMP method.

After that, the interlayer insulating film 43 made of plasma TEOS is subjected to CV in the same manner as in a normal LSI manufacturing process.
After forming by D, a contact hole is formed and an upper wiring 44 made of aluminum is formed.

As described above, according to the present invention, it is possible to form an extremely thin gate insulating film with good controllability, and it is possible to realize high performance of the transistor.

Although the silicon nitride film is interposed between the Si—O bond layer and the Ta ₂ O ₅ layer in the above-described embodiment, the silicon nitride film is omitted and the silicon nitride film is formed on the Si—O bond layer. It is also possible to directly form the Ta ₂ O ₅ layer.

[0043] In general, after the formation of the Ta ₂ O ₅ film, Ta ₂ O
_{5 In} order to remove impurities such as C in the film and replenish deficient oxygen, annealing is usually performed. In this annealing step, a silicon nitride film is formed in order to prevent silicon atoms in the silicon substrate from diffusing into Ta ₂ O ₅ .

However, by appropriately selecting the annealing temperature, the diffusion of silicon atoms can be suppressed and the silicon nitride film is not required. This will be described below.

FIG. 8 shows TiN / Ta ₂ O ₅ / NO film / S
Characteristic diagram (J. Electrochem, Soc. Vol.143.No.
3, P977 (1996)). (A) in the figure is 0.5 Torr
Sample annealed in oxygen atmosphere for 10 minutes,
In the figure, (b) shows 0.3 Torr after the above-mentioned annealing treatment.
FIG. 3 is a characteristic diagram of a leak current of a sample annealed at 400 ° C. for 10 minutes in the oxygen plasma of FIG.

It can be seen that the sample that has been subjected to the plasma annealing treatment has a suppressed leakage current and a high effect of modifying the Ta ₂ O ₅ film. Further, it has been confirmed that, when high temperature annealing exceeding 650 ° C. is performed on both samples, silicon atoms diffuse into the Ta ₂ O ₅ film and the leak current increases.

Therefore, the process after the Ta ₂ O ₅ film formation is 6
If it is performed at a temperature of 00 ° C. or lower and the annealing conditions are optimized, the leak current of the Ta ₂ O ₅ film can be suppressed. Therefore, since the diffusion of silicon atoms into the Ta ₂ O ₅ film is suppressed, the silicon nitride film becomes unnecessary.

Furthermore, FIG. 9 shows the result of SIMS analysis of the Si concentration in the Ta ₂ O ₅ film. Figure 9
Sample A shown in (a) is annealed at 700 degrees for 10 minutes in an oxygen atmosphere, and sample B shown in FIG. 9 (b) is annealed in oxygen plasma for 5 minutes.

The Si concentration in the Ta ₂ O ₅ film of Sample A is about 0.1 atom%, while the Si concentration of Sample B is 0.001% or less (below the detection limit).

As shown in FIG. 8, the leak currents of sample A and sample B differ by about three orders of magnitude, so that the annealing conditions of sample A are obviously not applicable. Therefore, the Si concentration in the Ta ₂ O ₅ film is 0.1 at
It is essential to make it less than om%.

Further, in order to reduce the short channel effect, realize a high driving force, reduce the variation of the threshold value, and improve the cutoff characteristic (improvement of S-factor), the gate insulating film must be thin. I have to. In the case of a MOSFET having a gate length of 0.085 μm or less, the thickness of the gate insulating film is 2.6 nm (oxide film equivalent effective film thickness).
Unless below, sufficient performance cannot be realized.

Therefore, in a MOSFET having a gate length of 0.085 μm or less, the thickness of the gate insulating film is 2.6 n.
It is required that the film thickness be less than m (effective film thickness equivalent to the oxide film) and that the Si concentration in the Ta ₂ O ₅ film be 0.1 atom% or less.

[Second Embodiment] FIGS. 10 to 12 are sectional views of a MOSFET manufacturing process for explaining the second embodiment of the present invention. The same components as those in FIGS. 3 to 7 are designated by the same reference numerals, and the description thereof will be omitted.

First, the structure shown in FIG.
In comparison with the structure shown in (c), a silicon nitride film of 70 nm
The sidewall insulating film 37 is formed on the side surface of the dummy gate 33 by depositing the same degree and performing RIE on the entire surface.

Then, as shown in FIG.
11) Single crystal silicon is epitaxially grown on the source / drain regions of the silicon substrate 10 to form elevated source / drain regions. In detail,
For example, the Si surface is exposed by a wet treatment with HF,
After the H ₂ annealing, source by epitaxial growth /
Raise the drain by about 50 nm.

Thereafter, the elevated source / drain regions are doped by ion implantation, and the n ⁺ diffusion layer 81 is formed by solid phase diffusion. The injection conditions are, for example, A
s, 45 keV, 3 × 10 ¹⁵ cm ⁻² . When forming a CMOS, it is necessary to separate n-type impurities and p-type impurities by lithography.

Then, Co is deposited on the entire surface and annealed to lift the elevated source /
The drain and Co are reacted to form cobalt silicide (CoSi ₂ ) 82. In addition to cobalt silicide, it is possible to form metal silicide such as NiSi ₂ , PtSi, and Pd ₂ Si. (11
1) On the Si surface having the plane orientation, these silicides are likely to be a single crystal, and a uniform and low resistance film can be formed.

Then, as shown in FIG.
A TEOS-based oxide film 39 ₁ is deposited on the entire surface by CVD by 350 n
Deposit about m. Then, as shown in FIG.
The surface of the TEOS-based oxide film 39 ₁ is planarized by CMP method to form an interlayer insulating film 39. At this time, the silicon nitride film 33 ₂ and the sidewall insulating film 37 serve as a CMP stopper.

Then, as shown in FIG. 11 (e), etching is performed using hot phosphoric acid to form the dummy gate 3
3 silicon nitride film 33 ₂ is selectively removed. At this time, the upper portion of the silicon nitride film of the side wall insulating film 37 is also etched, so that the height of the side wall insulating film 37 becomes slightly low.

Then, as shown in FIG. 11 (f), the CD
Method E removal of the polysilicon film 33 ₁ of the dummy gate by, by removing the silicon oxide film 32 and 35 by performing wet etching with HF, to form a groove 40 in the gate forming region. Then, as shown in FIG. 12G, the Si—O coupling layer 12, the SiN layer 13, and the Ta layer are formed by using the same method as the forming method described in the first embodiment.
_{A 2} O ₅ film 14, TiN 41 and aluminum 42 ₁ are formed. Then, as shown in FIG. 12 (h), to flatten the surface of the aluminum 42 ₁ by using the CMP method to form the gate electrode 42.

Thereafter, as in the normal LSI manufacturing process, as shown in FIG. 12 (i), an interlayer insulating film 43 made of plasma TEOS is formed by CVD, contact holes are then formed, and an upper layer wiring made of aluminum is formed. Four
4 is formed.

As described above, according to the present invention, an extremely thin gate insulating film can be formed with good controllability, and furthermore, high quality metal silicide can be formed on the source / drain with good controllability. Therefore, high performance of the transistor can be realized.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the gate electrode is formed by using the damascene process, but it can be formed by using the normal MOSFET manufacturing process.

In the above embodiment, Ta is used as the insulating layer.
_{Although the 2} O ₅ film is used, it is also possible to use other high dielectric materials or ferroelectric materials.

In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

[0066]

As described above, according to the present invention, S
By using a single-layer Si—O bonding layer instead of the iO ₂ layer, the effective oxide film thickness of the gate insulating film is reduced,
It is possible to suppress the leak current.

[Brief description of drawings]

FIG. 1 is a sectional view showing a schematic configuration of a semiconductor device according to a first embodiment.

FIG. 2 is a process sectional view showing a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 4 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 5 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 6 is a process sectional view showing a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 7 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

FIG. 8 is a characteristic diagram showing an annealing temperature dependency of a leak current in a laminated structure of TiN / Ta ₂ O ₅ / NO film / Si substrate.

FIG. 9 is a characteristic diagram showing Si concentration in a Ta ₂ O ₅ film.

FIG. 10 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment.

FIG. 11 is a process cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment.

FIG. 12 is a process cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment.

[Explanation of symbols]

10 ... (111) Silicon substrate 11 ... Source / drain region 12 ... Si—O coupling layer 13 ... SiN film 14 ... Ta ₂ O ₅ film 15 ... Metal gate electrode 31 ... Element isolation insulating film 32 ... Thermal oxide film 33 ... Dummy Gate 33 ₁ ... Polysilicon film 33 ₂ ... Silicon nitride film 35 ... Oxide film 36 ... N ^- diffusion layer 37 ... Side wall insulating film 38 ... N ⁺ diffusion layer 39 ... Interlayer insulating film 39 ₁ ... TEOS oxide film 40 ... Groove 41 ... TiN 42 ... gate electrode 42 ₁ ... aluminum 43 ... interlayer insulating film 44 ... upper wiring 81 ... n ⁺ diffusion layer 82 ... cobalt silicide

Continuation of the front page (56) Reference JP-A-5-315608 (JP, A) JP-A-10-178170 (JP, A) JP-A-11-126902 (JP, A) JP-A-63-110642 (JP , A) JP-A-3-248433 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/78

Claims (5)

(57) [Claims] 1. An M formed on a (111) silicon substrate.
A semiconductor device including an OSFET, wherein the gate insulating film of the MOSFET has a single-layer Si—O bonding layer in which silicon atoms and oxygen atoms are bonded on the outermost surface of the silicon substrate, and on the Si—O bonding layer. Formed in
A semiconductor device comprising: an insulating layer made of a high dielectric material or a ferroelectric material. 2. The gate length of the MOSFET is 0.85 μm.
The silicon oxide film equivalent effective film thickness of the gate insulating film is 2.6 nm or less, and the Si concentration in the insulating layer is less than 0.1 atom%.
The semiconductor device according to. 3. A step of forming a dummy gate in a predetermined region on a (111) silicon substrate of the first conductivity type, and an impurity of the second conductivity type being introduced into the surface of the silicon substrate using the dummy gate as a mask. Forming a source / drain region, forming an interlayer insulating film on the silicon substrate so as to cover the dummy gate, planarizing the surface of the interlayer insulating film, and exposing the dummy gate. A step of forming a groove by selectively removing the dummy gate, a single-layer Si in which silicon atoms and oxygen atoms on the outermost surface of the silicon substrate exposed on the bottom surface of the groove are combined. Forming an —O coupling layer, forming an insulating layer made of a high dielectric or a ferroelectric on the Si—O coupling layer, and embedding a gate electrode in the groove. And a step of forming the semiconductor device. 4. After the insulating layer is formed, all processes are
The method for manufacturing a semiconductor device according to claim 3, wherein the method is performed at a temperature of 00 ° C. or less. 5. The semiconductor device according to claim 3, wherein after the step of forming the dummy gate, silicide is formed in a self-aligned manner on the silicon substrate in a region to be the source / drain region. Production method.