JP2005277223A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 72
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 72
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
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- 229910052757 nitrogen Inorganic materials 0.000 claims 1
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- 238000007740 vapor deposition Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 15
- 239000007772 electrode material Substances 0.000 abstract description 9
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- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
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- MZCHLVMRAOQSDA-UHFFFAOYSA-N hafnium;1-methoxy-2-methylpropan-2-ol Chemical compound [Hf].COCC(C)(C)O.COCC(C)(C)O.COCC(C)(C)O.COCC(C)(C)O MZCHLVMRAOQSDA-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
Abstract
Description
本発明は、半導体装置およびその製造方法に関し、特に高誘電率絶縁膜をゲート絶縁膜に有する半導体装置およびその製造方法に関するものである。 The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a high dielectric constant insulating film as a gate insulating film and a manufacturing method thereof.
情報化社会を支えている半導体集積回路技術は、素子の微細化と回路の高密度化を推進することで性能向上が図られている。微細化の中でも特に重要なのは、トランジスタのゲート絶縁膜の薄膜化であり、半導体技術ロードマップによると、2006年ごろには、シリコン酸化膜の膜厚に換算して、１ｎｍ以下の膜厚にまで薄くすることが要求されている。 The performance of semiconductor integrated circuit technology that supports the information society has been improved by promoting device miniaturization and circuit density. Of particular importance in miniaturization is the thinning of the gate insulating film of the transistor. According to the semiconductor technology roadmap, the film thickness of the silicon oxide film is reduced to 1 nm or less around 2006. Thinning is required.
トランジスタのゲート絶縁膜には従来、シリコン酸化膜が用いられているが、絶縁膜厚さが１ｎｍレベルになると、この絶縁膜を介して直接トンネル機構による漏れ電流が流れ、素子性能を阻害することが大きな問題となる。これを解決する手段として高誘電率絶縁膜材料を用いたゲート絶縁膜が注目を集めている。高誘電率絶縁膜はシリコン酸化膜に比べて比誘電率が大きいので、物理膜厚の厚い薄膜でも１ｎｍ膜厚のシリコン酸化膜と同等の性能が発揮でき、さらに、シリコン酸化膜で問題となる漏れ電流を小さくすることが可能である。高誘電率絶縁膜に対する期待は大いに高まっている。 Conventionally, a silicon oxide film is used as the gate insulating film of a transistor. However, when the insulating film thickness reaches 1 nm level, a leakage current due to a direct tunneling mechanism flows through this insulating film, which impedes device performance. Is a big problem. As a means for solving this problem, a gate insulating film using a high dielectric constant insulating film material has attracted attention. A high dielectric constant insulating film has a relative dielectric constant larger than that of a silicon oxide film, so that even a thin film having a large physical thickness can exhibit the same performance as a silicon oxide film having a thickness of 1 nm. It is possible to reduce the leakage current. Expectations for high dielectric constant insulating films are greatly increasing.
しかしながら、高誘電率絶縁膜をゲートに用いたトランジスタを試作した場合、しきい値電圧が設計値からずれてしまうことが問題となっている（例えば、非特許文献１）。特に問題となっているのは、Ｎ型トランジスタおよびＰ型トランジスタのしきい値電圧の絶対値がいずれも大きくなる現象であり、これは従来のシリコン酸化膜をゲート絶縁膜に用いた場合には起こらなかった問題である。しきい値電圧はトランジスタのオン・オフ動作を規定する電圧であり、これが設計値からずれることは、トランジスタ性能の劣化ひいては集積回路の不良につながる。しきい値電圧は回路を設計する上で重要なパラメーターである。 However, when a transistor using a high dielectric constant insulating film as a gate is prototyped, there is a problem that the threshold voltage deviates from a design value (for example, Non-Patent Document 1). Particularly problematic is the phenomenon that the absolute values of the threshold voltages of the N-type transistor and the P-type transistor both increase. This is the case when a conventional silicon oxide film is used as the gate insulating film. This is a problem that did not occur. The threshold voltage is a voltage that defines the on / off operation of the transistor. If this threshold voltage deviates from the design value, the transistor performance is deteriorated and the integrated circuit is defective. The threshold voltage is an important parameter in designing a circuit.
Ｎ型トランジスタおよびＰ型トランジスタのしきい値電圧の絶対値が大きくなる現象は、ゲート電極材料と高誘電率絶縁膜の界面でフェルミレベルピンニング現象が発生し、ゲート電極材料の仕事関数が、本来とは異なるエネルギー位置に固定されるためであることが理解されている。 The phenomenon that the absolute value of the threshold voltage of the N-type transistor and the P-type transistor increases is due to the Fermi level pinning phenomenon at the interface between the gate electrode material and the high dielectric constant insulating film. Is understood to be fixed at a different energy position.
すなわち、高誘電率絶縁膜を導入したことによる最大の問題の一つは、ゲート電極との界面にフェルミレベルピンニング現象が生じることである。本発明者は、ゲート電極材料と高誘電率絶縁膜の界面で生じるフェルミレベルピンニング現象を解消するためには、高誘電率絶縁膜とゲート電極の間に、シリコン酸化膜を挿入する必要があるという考えに到った。先にも記したように、従来のゲート電極材料とシリコン酸化膜の界面では、フェルミレベルピンニング現象が問題になっていないことからも、シリコン酸化膜を挿入する方法が有効であると推測できる。ところが、厚いシリコン酸化膜を挿入すると、フェルミレベルピンニングの解消に十分な効果が期待できるものの、ゲート絶縁膜の膜厚が大きく増加し、近い将来に要求されている１ｎｍ以下というゲート絶縁膜の仕様が実現できない。要約すると、フェルミレベルピンニング現象を解消し、かつ、ゲート絶縁膜の膜厚増大を阻止するためには、高誘電率絶縁膜の表面を完全に被覆し、かつ、単原子層レベルにまで膜厚を薄く制御した、高度なシリコン酸化膜形成技術が要求される。しかしながら、従来技術ではこのような要請を満足させることはできない。 That is, one of the biggest problems due to the introduction of the high dielectric constant insulating film is that Fermi level pinning occurs at the interface with the gate electrode. In order to eliminate the Fermi level pinning phenomenon that occurs at the interface between the gate electrode material and the high dielectric constant insulating film, the present inventor needs to insert a silicon oxide film between the high dielectric constant insulating film and the gate electrode. The idea was reached. As described above, since the Fermi level pinning phenomenon is not a problem at the interface between the conventional gate electrode material and the silicon oxide film, it can be estimated that the method of inserting the silicon oxide film is effective. However, when a thick silicon oxide film is inserted, a sufficient effect can be expected to eliminate Fermi level pinning, but the thickness of the gate insulating film is greatly increased, and the specification of a gate insulating film of 1 nm or less required in the near future is required. Cannot be realized. In summary, in order to eliminate the Fermi level pinning phenomenon and prevent the increase in the thickness of the gate insulating film, the surface of the high dielectric constant insulating film is completely covered and the film thickness reaches the monoatomic layer level. Advanced silicon oxide film formation technology that controls the thickness of the film is required. However, the prior art cannot satisfy such a demand.
一方で、高誘電率ゲート絶縁膜では、漏れ電流の低減効果が期待されているものの、トランジスタの製作工程で加えられる高温熱処理などによって、結晶化といった相変化が生じることがあり、その際に膜を貫通する結晶粒界が発生すると、漏れ電流の低減効果が小さくなるという問題も指摘されている。 On the other hand, although a high dielectric constant gate insulating film is expected to reduce leakage current, a phase change such as crystallization may occur due to high-temperature heat treatment applied in the transistor manufacturing process. It has also been pointed out that the generation of crystal grain boundaries penetrating the crystal reduces the effect of reducing leakage current.
本発明者は、高誘電率絶縁膜の内部にシリコン酸化膜層を挿入することが出来れば、高誘電率絶縁膜が相変化して結晶化する際に、結晶粒はシリコン酸化膜層の上下に分断されるので、膜を貫通する結晶粒界の発生が防止でき、漏れ電流の低減効果に貢献できると考えた。この場合にも、前記のように、シリコン酸化膜には、完全被覆性および、単原子層レベルに薄く制御した膜厚という、2つの厳しい条件が要請されるが、従来技術では、その実現は困難である。
本発明は、上述した従来技術の問題点を解決すべくなされたものであって、その目的は、第１に、高誘電率絶縁膜をゲート絶縁膜に導入したことに起因するフェルミレベルピンニング現象を解消できるようにすることであり、第２に、高誘電率絶縁膜を貫通して流れる漏れ電流を抑制できるようにすることであり、第３に、第１、第２の目的を達成するために形成される低誘電率絶縁膜が、高誘電率絶縁膜の表面を完全に被覆し、かつ、等価的酸化物膜厚（ＥＯＴ）を厚くすることのないように単原子層レベルにまで膜厚を薄くできるようにすることである。そして、これらの目的を達成することにより、しきい値電圧のずれ、および、漏れ電流の抑制された、超微細のトランジスタを実現できるようにしようとするものである。 The present invention has been made to solve the above-mentioned problems of the prior art, and its purpose is firstly a Fermi level pinning phenomenon caused by introducing a high dielectric constant insulating film into a gate insulating film. Secondly, the leakage current flowing through the high dielectric constant insulating film can be suppressed, and thirdly, the first and second objects are achieved. Therefore, the low dielectric constant insulating film formed for this purpose completely covers the surface of the high dielectric constant insulating film and does not increase the equivalent oxide thickness (EOT) to the monoatomic layer level. It is to be able to reduce the film thickness. By achieving these objects, an attempt is made to realize an ultrafine transistor in which threshold voltage deviation and leakage current are suppressed.
上記の目的を達成するため、本発明によれば、高誘電率絶縁膜上にゲート電極が形成されたＭＩＳ構造を有する半導体装置において、前記高誘電率絶縁膜と前記ゲート電極との間には単原子層または膜厚１ｎｍ以下の低誘電率絶縁物膜が形成されていることを特徴とする半導体装置、が提供される。 In order to achieve the above object, according to the present invention, in a semiconductor device having a MIS structure in which a gate electrode is formed on a high dielectric constant insulating film, the high dielectric constant insulating film and the gate electrode are disposed between the high dielectric constant insulating film and the gate electrode. A semiconductor device is provided in which a monoatomic layer or a low dielectric constant insulator film having a thickness of 1 nm or less is formed.
また、上記の目的を達成するため、本発明によれば、高誘電率絶縁膜上にゲート電極が形成されたＭＩＳ構造を有する半導体装置において、前記高誘電率絶縁膜は、単原子層または膜厚１ｎｍ以下の１ないし複数層の低誘電率絶縁物膜により複数層に分離されていることを特徴とする半導体装置、が提供される。
そして、好ましくは、上記の低誘電率絶縁物膜は、シリコン酸化膜またはシリコン酸窒化膜である。
In order to achieve the above object, according to the present invention, in a semiconductor device having a MIS structure in which a gate electrode is formed on a high dielectric constant insulating film, the high dielectric constant insulating film is a monoatomic layer or a film. Provided is a semiconductor device characterized by being separated into a plurality of layers by one or a plurality of low dielectric constant insulator films having a thickness of 1 nm or less.
Preferably, the low dielectric constant insulator film is a silicon oxide film or a silicon oxynitride film.
また、上記の目的を達成するため、本発明によれば、ゲート絶縁膜に高誘電率絶縁膜を含むＭＩＳ構造を有する半導体装置の製造方法において、高誘電率絶縁膜上に気相成長法により単原子層で成長が実質的に停止する条件でシリコン酸化膜を成膜することを特徴とする半導体装置の製造方法、が提供される。 In order to achieve the above object, according to the present invention, in a method of manufacturing a semiconductor device having a MIS structure including a high dielectric constant insulating film in a gate insulating film, a vapor phase growth method is performed on the high dielectric constant insulating film. There is provided a method for manufacturing a semiconductor device, characterized in that a silicon oxide film is formed under conditions where growth is substantially stopped in a monoatomic layer.
また、上記の目的を達成するため、本発明によれば、ゲート絶縁膜に高誘電率絶縁膜を含むＭＩＳ構造を有する半導体装置の製造方法において、高誘電率絶縁膜上に有機ケイ化物を原料とする化学気相成長法によりシリコン酸化膜を膜厚１ｎｍ以下の膜厚に成膜することを特徴とする半導体装置の製造方法、が提供される。
そして、好ましくは、上記の原料に、アルコキシド系化合物またはアミノ系化合物を用いる。また、一層好ましくは、６００℃以下の温度で成膜がなされる。
In order to achieve the above object, according to the present invention, in a method of manufacturing a semiconductor device having a MIS structure including a high dielectric constant insulating film in a gate insulating film, an organic silicide is used as a raw material on the high dielectric constant insulating film. A method of manufacturing a semiconductor device is provided, in which a silicon oxide film is formed to a thickness of 1 nm or less by a chemical vapor deposition method.
Preferably, an alkoxide compound or an amino compound is used as the raw material. More preferably, the film is formed at a temperature of 600 ° C. or lower.
本発明による半導体装置は、高誘電率絶縁膜とゲート電極との界面に、低誘電率絶縁膜を挿入しているので、フェルミレベルピニングを解消し、高誘電率ゲート絶縁膜を用いたトランジスタで問題となっているしきい値ずれを改善することができる。
また、本発明による半導体装置は、高誘電率絶縁膜の層間に低誘電率絶縁膜を挿入しているので、高誘電率絶縁膜を貫通した結晶粒界の発生を防ぐことができ、高誘電率ゲート絶縁膜における漏れ電流低減性能を十分に発揮させることができる。
そして、高誘電率絶縁膜上、または、高誘電率絶縁膜間に挿入される低誘電率絶縁膜は単原子層程度の膜厚に抑えられるので、等価的酸化物膜厚（ＥＯＴ）を増加させることなく上記の効果を享受することができる。
In the semiconductor device according to the present invention, since the low dielectric constant insulating film is inserted at the interface between the high dielectric constant insulating film and the gate electrode, the Fermi level pinning is eliminated and the transistor using the high dielectric constant gate insulating film is used. The threshold shift in question can be improved.
In addition, since the semiconductor device according to the present invention has a low dielectric constant insulating film inserted between the high dielectric constant insulating films, the generation of crystal grain boundaries penetrating the high dielectric constant insulating film can be prevented. The leakage current reduction performance in the rate gate insulating film can be sufficiently exhibited.
Further, since the low dielectric constant insulating film inserted on the high dielectric constant insulating film or between the high dielectric constant insulating films can be suppressed to a thickness of about a monoatomic layer, the equivalent oxide film thickness (EOT) is increased. The above-described effects can be enjoyed without making them.
本発明の低誘電率絶縁膜の形成方法においては、本質的に高誘電率絶縁膜の表面のイオン分極を利用して、共有結合性を有する有機金属原料である、Ｓｉ系原料の分解反応を促進し、シリコン酸化膜の形成を実現している。高誘電率材料は一般にイオン結合性が強い材料であり、その膜の表面はイオン結合性の原子間結合で構成されている。Ｓｉ系有機金属原料は共有結合性が強く、熱分解温度が高いことで知られている。Ｓｉ系有機金属原料を、例えば600℃以下の温度に保たれた基板上に供給した場合、通常、シリコン酸化膜は形成されない。ところが、本発明者は、詳細な実験を行った結果、基板表面に高誘電率材料のイオン分極性の原子間結合サイトが存在すると、このイオン分極部分がＳｉ系原料の分解を促進し、シリコン酸化膜の形成が可能になることを見出した。このことは、本発明の本質に関わる、重要な現象をもたらす。すなわち、高誘電率絶縁膜の表面に、十分な量のＳｉ系有機原料を供給することで、高誘電率絶縁膜表面に存在する全てのイオン分極性の結合サイトにおいて、シリコン酸化膜の形成反応が、余すところなく進行し、シリコン酸化膜による表面の完全な被覆が実現でき、さらに、シリコン酸化膜で覆われた表面ではイオン分極の効果は遮蔽されるので、さらなるＳｉ原料の分解反応、言い換えればシリコン酸化膜の成長は阻止されることになる。すなわち、シリコン酸化膜の成長は、究極的には、単原子層で自動的に終端することが可能であり、膜の表面粗さによって発生する分解反応サイトの増加や、熱統計的に起きると想定されるＳｉ系原料の自己分解反応といった作用による成長量を多めに見積もっても、１ｎｍ以下の膜厚に留めることができる。 In the method for forming a low dielectric constant insulating film of the present invention, a decomposition reaction of a Si-based raw material, which is an organic metal raw material having a covalent bond, is essentially performed by utilizing ionic polarization on the surface of the high dielectric constant insulating film. Promote and realize the formation of silicon oxide film. A high dielectric constant material is generally a material having strong ionic bonding, and the surface of the film is composed of ionic bonding interatomic bonds. Si-based organometallic raw materials are known for their strong covalent bonding and high thermal decomposition temperatures. When the Si-based organometallic raw material is supplied onto a substrate maintained at a temperature of 600 ° C. or lower, for example, a silicon oxide film is usually not formed. However, as a result of detailed experiments, the present inventor has found that when an ion-polarizable interatomic bond site of a high dielectric constant material exists on the substrate surface, this ion-polarized portion promotes decomposition of the Si-based material, and silicon It has been found that an oxide film can be formed. This leads to an important phenomenon related to the essence of the present invention. That is, by supplying a sufficient amount of Si-based organic raw material to the surface of the high dielectric constant insulating film, the formation reaction of the silicon oxide film at all ion polarizable binding sites existing on the surface of the high dielectric constant insulating film However, the process proceeds to the full, and complete surface coverage with the silicon oxide film can be realized. Further, since the effect of ion polarization is shielded on the surface covered with the silicon oxide film, further decomposition reaction of the Si raw material, in other words, In this case, the growth of the silicon oxide film is prevented. In other words, the growth of the silicon oxide film can ultimately be automatically terminated with a monoatomic layer. If the decomposition reaction sites increase due to the surface roughness of the film, Even if a large amount of growth due to an effect such as a self-decomposition reaction of a Si-based material is estimated, the film thickness can be kept to 1 nm or less.
図１（ａ）は、本発明の第１の実施の形態を示す断面図である。図1（ａ）に示すように、シリコン基板上１上には、高誘電率絶縁膜２が形成されており、その上にシリコン酸化膜３ａが形成され、これを介してゲート電極材料層４が形成されている。シリコン基板と高誘電率絶縁膜の界面に界面層が挿入されていることもある。
本実施の形態によれば、ゲート電極の直下にシリコン酸化膜が形成されたことにより、ゲート電極と高誘電率絶縁膜との界面でフェルミレベルピンニング現象が発生することを防止することができる。
図１（ｂ）は、本発明の第１の実施の形態の変更例を示す断面図である。この変更例では、図1（ａ）に示すシリコン酸化膜３ａに代えてシリコン酸窒化膜３ｂが用いられている。シリコン酸化膜に代えシリコン酸窒化膜を用いる場合にもシリコン酸化膜を用いた場合と同様の効果を期待することができる。
Fig.1 (a) is sectional drawing which shows the 1st Embodiment of this invention. As shown in FIG. 1A, a high dielectric constant
According to the present embodiment, the Fermi level pinning phenomenon can be prevented from occurring at the interface between the gate electrode and the high dielectric constant insulating film because the silicon oxide film is formed immediately below the gate electrode.
FIG.1 (b) is sectional drawing which shows the example of a change of the 1st Embodiment of this invention. In this modification, a
図２（ａ）は、本発明の第２の実施の形態を示す断面図である。図２（ａ）に示すように、シリコン基板１上には、間にシリコン酸化膜３ａが挿入された高誘電率絶縁膜２が形成されており、その上にはゲート電極材料層４が形成されている。
本実施の形態によれば、高誘電率絶縁膜２がシリコン酸化膜３ａにより分断されたことにより、高誘電率絶縁膜２を貫通する結晶粒界が発生することを防止することができ、ＭＩＳ構造における漏れ電流を低減させることができる。図示した例は、シリコン酸化膜が１層挿入したものであるが、２層ないしそれ以上の層数のシリコン酸化膜を高誘電率絶縁膜２中に挿入するようにしてもよい。
図２（ｂ）は、本発明の第２の実施の形態の変更例を示す断面図である。この変更例では、図２（ａ）に示すシリコン酸化膜３ａに代えてシリコン酸窒化膜３ｂが用いられている。シリコン酸化膜に代えシリコン酸窒化膜を用いる場合にもシリコン酸化膜を用いた場合と同様の効果を期待することができる。
FIG. 2A is a cross-sectional view showing a second embodiment of the present invention. As shown in FIG. 2A, a high dielectric constant
According to the present embodiment, since the high dielectric constant
FIG.2 (b) is sectional drawing which shows the example of a change of the 2nd Embodiment of this invention. In this modification, a
図３（ａ）は、本発明の第３の実施の形態を示す断面図である。図３（ａ）に示すように、シリコン基板１上には、間にシリコン酸化膜３ａが挿入された高誘電率絶縁膜２が形成されており、その上にシリコン酸化膜３ａが形成され、これを介してゲート電極材料層４が形成されている。高誘電率絶縁膜２中に形成されるシリコン酸化膜３ａは２層以上であってもよい。
本実施の形態によれば、上記した第１の実施の形態の効果と第２の実施の形態の効果とを併せ持つ半導体装置を得ることができる。
図３（ｂ）は、本発明の第３の実施の形態の変更例を示す断面図である。この変更例では、図３（ａ）に示すシリコン酸化膜３ａに代えてシリコン酸窒化膜３ｂが用いられている。シリコン酸化膜に代えシリコン酸窒化膜を用いる場合にもシリコン酸化膜を用いた場合と同様の効果を期待することができる。
上記の実施の形態において、シリコン酸化膜３ａ、シリコン酸窒化膜３ｂは、本発明にしたがって、究極的には単原子層レベルの膜厚の絶縁膜であり、かつ、高誘電率絶縁膜表面を完全に被覆している膜である。
上記の実施の形態では、シリコン基板上にＭＩＳ構造を形成していたが、本発明はこれに限定されず、ＳＯＩ基板のシリコン層を用いてもよい。
FIG. 3A is a cross-sectional view showing a third embodiment of the present invention. As shown in FIG. 3A, a high dielectric constant
According to the present embodiment, a semiconductor device having both the effects of the first embodiment and the effects of the second embodiment can be obtained.
FIG.3 (b) is sectional drawing which shows the example of a change of the 3rd Embodiment of this invention. In this modification, a
In the above embodiment, the
In the above embodiment, the MIS structure is formed on the silicon substrate. However, the present invention is not limited to this, and a silicon layer of an SOI substrate may be used.
本発明の実施例においては、高誘電率絶縁膜として、化学気相成長法で形成したＨｆＯ２膜を使用し、その表面に化学気相成長法でＳｉ系有機原料を供給することで試料を作成した。基板には主面を（００１）面とするシリコン基板を使用した。化学気相成長法の基板温度は５００℃、反応室圧力は１００Ｐａに保ち、有機原料と酸素ガスを供給した。 In an embodiment of the present invention, an HfO 2 film formed by chemical vapor deposition is used as the high dielectric constant insulating film, and a sample is prepared by supplying Si-based organic raw material to the surface by chemical vapor deposition. Created. As the substrate, a silicon substrate having a (001) plane as the main surface was used. In the chemical vapor deposition method, the substrate temperature was kept at 500 ° C., the reaction chamber pressure was kept at 100 Pa, and organic raw materials and oxygen gas were supplied.
本発明の実施例において、ＨｆＯ２の形成に用いた有機原料は、Ｈｆ（ＭＭＰ）４〔テトラキス（１−メトキシ−２−メチル−２−プロポキシ）ハフニウム〕、シリコン酸化膜の形成に用いた有機原料はＳｉ（ＭＭＰ）４〔テトラキス（１−メトキシ−２−メチル−２−プロポキシ）シリコン〕である。これらは、具体的には次のような化学式で表される、有機金属原料である。
Ｈｆ（Ｏ−Ｃ（ＣＨ３）２−ＣＨ２−Ｏ−ＣＨ３）４
Ｓｉ（Ｏ−Ｃ（ＣＨ３）２−ＣＨ２−Ｏ−ＣＨ３）４
In the embodiment of the present invention, the organic raw material used for forming HfO 2 is Hf (MMP) 4 [tetrakis (1-methoxy-2-methyl-2-propoxy) hafnium], the organic material used for forming the silicon oxide film. The raw material is Si (MMP) 4 [tetrakis (1-methoxy-2-methyl-2-propoxy) silicon]. Specifically, these are organometallic raw materials represented by the following chemical formula.
Hf (O—C (CH 3 ) 2 —CH 2 —O—CH 3 ) 4
Si (O—C (CH 3 ) 2 —CH 2 —O—CH 3 ) 4
シリコン基板の上に薄い酸化膜を形成し、この上にＳｉ（ＭＭＰ）４原料を供給してシリコン酸化膜の形成を試みた。エリプソメーターでシリコン酸化膜の膜厚を測定したところ、最初の下地酸化膜と膜厚に変化が見られなかった。すなわち、シリコン酸化膜は形成されなかった。
ＨｆＯ２膜を１０ｎｍ形成した後に、Ｓｉ原料を供給することなく、あるいは、Ｓｉ原料を一定量供給し、その後、Ｘ線光電子分光法（ＸＰＳ）で分析を行った。図４には、基準試料のＨｆＯ２膜の測定結果を示す。ＨｆＯ２膜表面で分析した場合、Ｈｆ−４ｆ信号は現れるが、シリコン基板からの信号は表面に到達しないので、Ｓｉ−２ｐに起因する信号は現れていない。一方、ＨｆＯ２膜表面にＳｉ原料を供給した試料で測定した結果を、図５に示す。この場合には、Ｓｉ−２ｐに相当する信号が現れており、そのエネルギー位置から、酸化したシリコンであることが分かる。すなわち、シリコン酸化膜が形成されている。
A thin oxide film was formed on a silicon substrate, and an Si (MMP) 4 raw material was supplied thereon to try to form a silicon oxide film. When the film thickness of the silicon oxide film was measured with an ellipsometer, no change was found in the film thickness of the first base oxide film. That is, no silicon oxide film was formed.
After the HfO 2 film was formed to a thickness of 10 nm, the Si raw material was not supplied or a fixed amount of Si raw material was supplied, and then analysis was performed by X-ray photoelectron spectroscopy (XPS). FIG. 4 shows the measurement result of the HfO 2 film of the reference sample. When the analysis is performed on the surface of the HfO 2 film, the Hf-4f signal appears, but the signal from the silicon substrate does not reach the surface, so the signal due to Si-2p does not appear. On the other hand, FIG. 5 shows the results of measurement using a sample in which the Si raw material is supplied to the surface of the HfO 2 film. In this case, a signal corresponding to Si-2p appears, and it can be seen from the energy position that the silicon is oxidized. That is, a silicon oxide film is formed.
ＸＰＳ分析のＨｆ−４ｆ信号の強度とＳｉ−２ｐ信号の強度の比率から、表面を被覆しているシリコン酸化膜の膜厚を解析した。シリコン原料の供給量と、形成されたシリコン酸化膜の膜厚の関係を図６に示す。シリコン酸化膜の膜厚は、１．５ｘ１０１７分子／ｃｍ２量のシリコン原料を供給した場合において、およそ０．２５ｎｍ厚さを実現している（図中、原点の隣のデータ）。因みに、この供給量は、本発明者が実験を行った化学気相成長装置において、５０分という非常に長い成膜時間に相当する供給量であり、本発明を単原子層厚さに相当する０．２ｎｍ膜厚の形成に用いる場合にも、膜厚の制御性が十分に高いことが示された。さらにシリコン原料を供給して作成した試料においても、形成されたシリコン酸化膜の膜厚は０．６ｎｍ以下であり、膜の成長に終端機能が存在することが示された。 The film thickness of the silicon oxide film covering the surface was analyzed from the ratio of the intensity of the Hf-4f signal and the intensity of the Si-2p signal in XPS analysis. FIG. 6 shows the relationship between the amount of silicon raw material supplied and the thickness of the formed silicon oxide film. The thickness of the silicon oxide film is approximately 0.25 nm when a silicon raw material of 1.5 × 10 17 molecules / cm 2 is supplied (data adjacent to the origin in the figure). Incidentally, this supply amount is a supply amount corresponding to a very long film formation time of 50 minutes in the chemical vapor deposition apparatus in which the inventor conducted an experiment, and the present invention corresponds to a monoatomic layer thickness. It was also shown that the controllability of the film thickness is sufficiently high when used for the formation of a 0.2 nm film thickness. Further, in the sample prepared by supplying the silicon raw material, the thickness of the formed silicon oxide film was 0.6 nm or less, and it was shown that the termination function exists in the film growth.
シリコン酸化膜の膜厚が、単原子層に相当する０．２ｎｍから、少しずつ増加していることについては、３つの原因を推定している。一つは下地となるＨｆＯ２膜の表面が長時間にわたる成膜時間中に次第に荒れ、シリコン酸化膜の形成がその波打った表面を被覆して生成したために、シリコン酸化膜の膜厚が厚くなったように見えている可能性である。二つ目は、生成したシリコン酸化膜が長時間にわたって５００℃という成膜温度に曝されている間に、その一部が次第にＨｆＯ２膜中に拡散し、再びイオン結合性が現れたＨｆＯ２膜表面部分に新たなシリコン酸化膜が形成された可能性である。三つ目は、Ｓｉ系原料の自己分解が非常に小さい確率ながらも発生したか、あるいはＨｆＯ２膜表面のイオン分極性がほんのわずかながら、シリコン酸化膜の表面にも染み出しているために、シリコン酸化膜の形成がゆっくりと進行した可能性である。いずれにせよ、１ｎｍ以下の膜厚でシリコン酸化膜が形成しており、その成長様式から勘案して、高誘電率絶縁膜ＨｆＯ２膜表面は完全に被覆されている。 Three causes are estimated for the fact that the thickness of the silicon oxide film gradually increases from 0.2 nm corresponding to the monoatomic layer. One is that the surface of the underlying HfO 2 film is gradually roughened during a long film formation time, and the formation of the silicon oxide film is generated by covering the wavy surface, so that the silicon oxide film is thick. It is possible that it seems to have become. Second, while the resulting silicon oxide film is exposed to the deposition temperature of 500 ° C. for a long time, HfO 2, a part of gradually diffused into the HfO 2 film, ionic bonding reappeared This is the possibility that a new silicon oxide film was formed on the film surface. Third, because the self-decomposition of the Si-based material occurred with a very small probability, or the ion polarizability on the surface of the HfO 2 film is very slight, but it also oozes out on the surface of the silicon oxide film. It is possible that the formation of the silicon oxide film has progressed slowly. In any case, a silicon oxide film is formed with a thickness of 1 nm or less, and the surface of the high dielectric constant insulating film HfO 2 film is completely covered in consideration of the growth mode.
本発明の実施例においてはＳｉ系原料にアルコキシド系原料のＳｉ（ＭＭＰ）４を用いているが、同様の効果は同じアルコキシド系に属し、性質が類似したＳｉ（Ｏ−ＣＨ２−ＣＨ３）４（一般名称：ＴＥＯＳ）でも可能である。さらに、Ｓｉ（Ｎ−（ＣＨ３）２）４といったアミノ系材料でも可能である。 In the examples of the present invention, Si (MMP) 4 which is an alkoxide-based material is used as the Si-based material, but the same effect belongs to the same alkoxide system, and Si (O—CH 2 —CH 3 ) having similar properties. 4 (general name: TEOS) is also possible. Furthermore, an amino material such as Si (N— (CH 3 ) 2 ) 4 is also possible.
本発明の実施例において、積層構造試料の表面に電極を堆積してＭＩＳ構造を形成してＣ−Ｖ測定を行い、フラットバンド電圧Ｖｆｂを調べた。ＭＩＳ構造のフラットバンド電圧は、トランジスタにおけるしきい値に対応するもので、そこから得られる情報は等価なものである。電極にはＡｕを用いた。ＭＩＳ構造の絶縁膜は、比較を行うために、（ａ）２２ｎｍのシリコン酸化膜から成る基準試料、（ｂ）２２ｎｍのシリコン酸化膜の上に１ｎｍのＨｆＯ２を堆積した構造から成る参照試料、（ｃ）２２ｎｍのシリコン酸化膜の上に１ｎｍのＨｆＯ２を堆積しその上に本願発明のシリコン酸化膜を形成した構造から成る実施例試料、の３つを作成した。
図７には、Ｃ−Ｖ測定の結果を示す。（ａ）に比較して（ｂ）の試料ではＶｆｂが正バイアス方向に約１．０Ｖずれている。これに対して、（ｃ）の試料ではＶｆｂのずれ量が０．６Ｖに留まっており、ゲート電極材料と高誘電率材料の界面で発生しているフェルミレベルピンニングの解消に貢献していることが分かる。
In the example of the present invention, an electrode was deposited on the surface of the laminated structure sample to form a MIS structure, CV measurement was performed, and a flat band voltage V fb was examined. The flat band voltage of the MIS structure corresponds to the threshold value in the transistor, and information obtained therefrom is equivalent. Au was used for the electrode. For comparison, the insulating film having the MIS structure includes (a) a reference sample made of a 22 nm silicon oxide film, and (b) a reference sample made of a structure in which 1 nm of HfO 2 is deposited on the 22 nm silicon oxide film, (C) Three sample samples, each having a structure in which 1 nm of HfO 2 was deposited on a 22 nm silicon oxide film and the silicon oxide film of the present invention was formed thereon, were prepared.
FIG. 7 shows the results of CV measurement. Compared to (a), in the sample of (b), V fb is shifted by about 1.0 V in the positive bias direction. On the other hand, in the sample of (c), the deviation amount of V fb remains at 0.6 V, which contributes to the elimination of Fermi level pinning occurring at the interface between the gate electrode material and the high dielectric constant material. I understand that.
１ シリコン基板
２ 高誘電率絶縁膜
３ａ シリコン酸化膜
３ｂ シリコン酸窒化膜
４ ゲート電極材料層
DESCRIPTION OF
Claims (10)
9. The semiconductor device according to claim 5, wherein a silicon oxynitride film is formed by replacing part of oxygen in a silicon oxide film formed by heat treatment or plasma treatment with nitrogen. Manufacturing method.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004090640A JP2005277223A (en) | 2004-03-25 | 2004-03-25 | Semiconductor device and its manufacturing method |
| PCT/JP2005/004949 WO2005093845A1 (en) | 2004-03-25 | 2005-03-18 | Semiconductor device and method for manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| JP2004090640A JP2005277223A (en) | 2004-03-25 | 2004-03-25 | Semiconductor device and its manufacturing method |
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| JP2005277223A true JP2005277223A (en) | 2005-10-06 |
Family
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| Application Number | Title | Priority Date | Filing Date |
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| JP2004090640A Pending JP2005277223A (en) | 2004-03-25 | 2004-03-25 | Semiconductor device and its manufacturing method |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2005277223A (en) |
| WO (1) | WO2005093845A1 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006086151A (en) * | 2004-09-14 | 2006-03-30 | Fujitsu Ltd | Method of manufacturing semiconductor apparatus |
| JP2007081211A (en) * | 2005-09-15 | 2007-03-29 | Fujitsu Ltd | Insulated gate semiconductor device and method of manufacturing same |
| JP2007158065A (en) * | 2005-12-06 | 2007-06-21 | Nec Electronics Corp | Semiconductor device and manufacturing method thereof |
| JP2007266552A (en) * | 2006-03-30 | 2007-10-11 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| JP2007287856A (en) * | 2006-04-14 | 2007-11-01 | Toshiba Corp | Method for manufacturing semiconductor device |
| JP2010135793A (en) * | 2008-12-05 | 2010-06-17 | Xerox Corp | Electronic device |
| JP2011014614A (en) * | 2009-06-30 | 2011-01-20 | Fujitsu Semiconductor Ltd | Semiconductor device and manufacturing method therefor |
| US8729639B2 (en) | 2012-09-27 | 2014-05-20 | Kabushiki Kaisha Toshiba | Semiconductor device and method for producing the same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3357861B2 (en) * | 1998-06-04 | 2002-12-16 | 株式会社東芝 | MIS semiconductor device and nonvolatile semiconductor memory device |
| US6407435B1 (en) * | 2000-02-11 | 2002-06-18 | Sharp Laboratories Of America, Inc. | Multilayer dielectric stack and method |
| JP3792589B2 (en) * | 2001-03-29 | 2006-07-05 | 富士通株式会社 | Manufacturing method of semiconductor device |
| JP4104834B2 (en) * | 2001-04-13 | 2008-06-18 | 株式会社東芝 | Manufacturing method of MIS field effect transistor |
| JP4643884B2 (en) * | 2002-06-27 | 2011-03-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
-
2004
- 2004-03-25 JP JP2004090640A patent/JP2005277223A/en active Pending
-
2005
- 2005-03-18 WO PCT/JP2005/004949 patent/WO2005093845A1/en active Application Filing
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006086151A (en) * | 2004-09-14 | 2006-03-30 | Fujitsu Ltd | Method of manufacturing semiconductor apparatus |
| JP2007081211A (en) * | 2005-09-15 | 2007-03-29 | Fujitsu Ltd | Insulated gate semiconductor device and method of manufacturing same |
| JP2007158065A (en) * | 2005-12-06 | 2007-06-21 | Nec Electronics Corp | Semiconductor device and manufacturing method thereof |
| JP2007266552A (en) * | 2006-03-30 | 2007-10-11 | Fujitsu Ltd | Semiconductor device and its manufacturing method |
| JP2007287856A (en) * | 2006-04-14 | 2007-11-01 | Toshiba Corp | Method for manufacturing semiconductor device |
| US8609487B2 (en) | 2006-04-14 | 2013-12-17 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
| JP2010135793A (en) * | 2008-12-05 | 2010-06-17 | Xerox Corp | Electronic device |
| JP2011014614A (en) * | 2009-06-30 | 2011-01-20 | Fujitsu Semiconductor Ltd | Semiconductor device and manufacturing method therefor |
| US8729639B2 (en) | 2012-09-27 | 2014-05-20 | Kabushiki Kaisha Toshiba | Semiconductor device and method for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2005093845A1 (en) | 2005-10-06 |
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