JP2633584B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a semiconductor device, in particular, a capacitor formed by sandwiching a high dielectric layer containing an oxide of a transition metal between two electrodes. Semiconductor device and a method of manufacturing the same.

(Prior Art and Problems) As DRAM devices become finer and more highly integrated, the area of memory cells is reduced in accordance with the scaling rule. Although this memory cell is composed of a capacitor, a minimum capacity is required for this capacitor regardless of a reduction in cell area due to a demand for prevention of a soft error and securing a sense amplifier margin. In order to reduce the cell area while maintaining the minimum capacity, the following measures have conventionally been taken.

(1) In a planar capacitor, a dielectric (usually an oxide film) constituting the capacitor is thinned.

(2) A trench is dug in the semiconductor substrate to form a trench capacitor.

(3) A multilayer capacitor is formed using a poly oxide film.

However, each of the above means has the following problems.

(1) The thickness of the oxide film is currently limited to a thickness of 60 to 70 mm, while a DRAM having a storage capacity of 4 Mbits requires a capacity of 40 fF per cell, for example. Is required to have a thickness of 20 to 30 mm corresponding to the intrinsic breakdown limit of the silicon oxide film. Therefore, it cannot be applied to the manufacture of a DRAM having a storage capacity of 4 Mbits or more.

(2) In order to secure a capacitance of 40 fF in a trench capacitor, even if the thickness of the oxide film is 100 mm, the size of one side of the opening must be 0.8 to 1.0 μm and the depth of the groove is about 3 μm.
An aspect ratio of 3 to 4 is required. When the aspect ratio is increased as described above, the cleaning of the inside of the groove becomes difficult with the conventional technology, and the reliability is reduced due to poor cleaning. In addition, the stress around the groove increases, and a leak current flows through the substrate due to the generation of crystal defects. This problem becomes more severe as the degree of integration increases.

(3) FIG. 6 shows the structure of the multilayer capacitor. An impurity diffusion layer 2 is formed on a semiconductor substrate 1, an oxide film 3 is deposited thereon, and three polysilicon layers 4, 5, 6 are formed.
Is buried. Also, one impurity diffusion layer 2 has
The bit line contact electrode 7 is connected. The polysilicon layer 4 is used as a transfer gate, and the polysilicon layers 5 and 6 constitute both electrodes of the capacitor.
However, the thickness of the oxide film between the polysilicon layers 5 and 6 is limited to 200 to 300 ° in the current technology. This is because forming an oxide film on polysilicon involves more technical difficulties than forming an oxide film on a single crystal substrate. However, a 4 Mbit DRAM has a thickness of 100 mm.
Oxide film thickness of the order is required. In addition, since the thickness h of the polysilicon layer 5 is about 1 μm in the figure, the aspect ratio of the contact hole for the bit line contact electrode 7 reaches about 3, and an advanced contact wiring technique is required.

As described above, any of the means (1) to (3)
There is a limit to the manufacture of DRAM having a capacity of more than a bit.
Therefore, as a fourth method, a means of increasing the dielectric constant of a dielectric material constituting a capacitor has attracted attention. This is intended to constitute a capacitor to be a memory cell by sandwiching a high dielectric layer made of a transition metal oxide such as Ta ₂ O ₅ between two electrodes.

FIG. 7 shows an example of a capacitor using Ta ₂ O ₅ . An element isolation oxide film 8 is formed on the surface of the semiconductor substrate 1, and a capacitor is formed in a portion surrounded by the element isolation oxide film 8. That is, as a high dielectric layer
A Ta ₂ O ₅ layer 9 is sandwiched between a semiconductor substrate 1 serving as a lower electrode and an upper electrode 10 made of polysilicon or aluminum to form a capacitor. Since the dielectric constant of Ta ₂ O ₅ is much higher than that of SiO ₂ , sufficient capacitance can be maintained even if the capacitor area is reduced.

However, the technology of forming a capacitor using such a high dielectric layer has the following problems, and has not yet been put to practical use. First, Ta ₂ O ₅
When a transition metal oxide such as that described above is directly deposited on the semiconductor substrate 1 made of silicon, a silicon oxide film is generated at the interface between the two by a reaction with silicon of the substrate,
The point is that the dielectric constant is substantially reduced. Second, the upper electrode 10 is easy to process,
Polysilicon excellent in heat resistance, oxidation resistance, chemical resistance and the like is generally used, but there is a problem that the polysilicon reacts with a transition metal. For example,
If using the Ta ₂ O ₅ as a high-dielectric _{layer, 13Si + 2Ta 2 O 5 →} 4TaSi 2 + 5SiO 2 made reaction occurs, that the leakage current is increased dramatically has been confirmed by the generation of TaSi _2.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device having a capacitor using a high-dielectric layer containing an oxide of a transition metal without lowering the dielectric constant and generating a leak current. .

[Configuration of the invention]

(Means for Solving the Problems) The semiconductor device of the present invention includes a MOS transistor and a capacitor having a structure in which a high dielectric layer containing a transition metal oxide is sandwiched between an upper electrode and a lower electrode made of silicon. An apparatus for configuring a memory cell, comprising: a first electrode provided on a capacitor region and a source / drain region of the memory cell on a silicon substrate as a lower electrode, for preventing a reaction between the silicon substrate and the high dielectric layer. A first high melting point metal compound layer made of a high melting point metal silicide, and a second high melting point metal compound layer made of a high melting point metal nitride, carbide or boride on its upper surface. The first barrier film comprising: a silicon electrode and a high dielectric layer, which are provided between a silicon electrode and a high dielectric layer constituting an upper electrode, and are formed by a high melting point metal compound layer; And a second barrier film for preventing the above reaction.

Further, the manufacturing method of the present invention is a method of manufacturing the above-described semiconductor device, comprising: a first refractory metal compound layer made of a refractory metal silicide; and a refractory metal nitride, carbide or boron on the upper surface thereof. Forming a first barrier film including a second refractory metal compound layer made of a compound on a region where a capacitor is to be formed and a source and a drain of the memory cell on a silicon substrate; Forming a high dielectric layer on the barrier layer, and forming a high melting point metal compound layer on the high dielectric layer to prevent a reaction between the silicon electrode serving as an upper electrode and the high dielectric layer. Forming a barrier film.

(Operation) According to the present invention, since the first barrier layer is provided on the capacitor region and the source and drain regions of the memory cell, unnecessary chemical reaction between the silicon substrate and the high-dielectric layer is prevented. And a second barrier layer is provided between the silicon electrode and the high-dielectric layer, so that the reaction between the silicon electrode and the high-dielectric layer is prevented, thereby preventing a decrease in the dielectric constant and the occurrence of a leak current. Is done. Furthermore, the resistance between the silicon substrate and the second barrier layer is reduced by the presence of the first refractory metal compound layer made of the refractory metal silicide contained in the first barrier layer.

(Example) 1st Example Hereinafter, it demonstrates based on the Example which illustrates this invention. FIG. 1 shows TEG (Test El) manufactured by the method according to the present invention.
FIG. 2 is a cross-sectional view illustrating a structure of an example of a capacitor. First, on a P-type semiconductor substrate 1 made of silicon,
The blocking isolation oxide film 8 is formed, and a capacitor is formed in a portion surrounded by the blocking isolation oxide film 8.
A TiSi ₂ layer 11 is deposited to a thickness of 500 ° on the exposed silicon surface of the capacitor formation region by a high-speed sputtering method using a TiSi ₂ alloy target as a refractory metal compound. Then, using the same sputtering apparatus, the TiN film 1 was formed by a chemical sputtering method using plasma of nitrogen and argon.
2 is continuously deposited at a thickness of 500 mm. Subsequently, a Ta ₂ O ₅ film 13 is deposited to a thickness of 100 to 1000 ° by chemical sputtering using plasma of oxygen and argon. At this time, for example, a 6N Ta target may be used as the target. Thereafter, a TiN film 14 is deposited to a thickness of 500 ° by the same method as described above, and a polysilicon layer 15 is deposited thereon by a LPCVD method to a thickness of 4000 °.

Thereafter, in a POCl ₃ atmosphere, 900 ° C., after doping phosphorus into the polysilicon layer 15 at 30 minutes of conditions, resist patterning for forming the capacitor upper electrode, BCl ₃ gas to it to mask The layers 11 to 15 are simultaneously etched and removed by performing RIE etching using, and a structure as shown in FIG. 1 is obtained. In this embodiment, the effective area of one capacitor is about 1 mm ³ .

FIG. 2 is a graph showing the relationship between the thickness of the Ta ₂ O ₅ layer and the dielectric constant. Here, curve A is data on a capacitor manufactured by the conventional method having the structure shown in FIG. 7, and curve B is manufactured by the method according to the present invention having the structure shown in FIG. It is data about a capacitor. As shown in curve A, in the conventional device, the dielectric constant decreases as the film thickness decreases. This is because, as described above, the SiO ₂ film is generated at the interface between the semiconductor substrate made of silicon and the Ta ₂ O ₅ layer. On the other hand, in the apparatus according to the present invention, as shown by the curve B, no decrease in the dielectric constant with a decrease in the film thickness was observed, and the dielectric constant value of Ta ₂ O _{5 as} a bulk throughout was 2525. was gotten.

FIG. 3 is a graph showing the relationship between the applied voltage V and the leak current I for a capacitor having a Ta ₂ O ₅ layer having a thickness of 200 °. All are data measured by applying a negative voltage to the upper electrode side. Here, curves A and B are data on capacitors manufactured by the conventional method having the structure shown in FIG.
Represents aluminum, and curve B represents polysilicon. On the other hand, curve C is data for a capacitor having the structure shown in FIG. 1 and manufactured by the method according to the present invention. According to the method according to the present invention, it can be seen that the leak current is also suppressed. This is because the reaction between Ta ₂ O ₅ and polysilicon or aluminum constituting the upper electrode was prevented by the barrier film.

Second Embodiment Next, an embodiment in which the present invention is applied to the manufacture of an actual DRAM memory cell will be described with reference to the process chart of FIG. First, an oxide film 8 for element isolation is formed on a semiconductor substrate 1 made of silicon by a known planar method, and then a first diffusion layer 16, a second diffusion layer 17, and a silicon oxide film 1 are formed.
8. A MOS transistor having an LDD structure having a polysilicon gate 19 is formed. The first diffusion layer 16 is formed by phosphorus ion implantation, and the second diffusion layer 17 is formed by As ion implantation.
Each is formed. The state up to this point is shown in FIG.

Subsequently, by self-alignment, a Ti film is deposited on the blocking region by sputtering at about 800 ° C, and then at 650 ° C for 20 seconds.
Anneal in a nitrogen atmosphere, react silicon and Ti on the substrate, form a TiSi film 20, and
The _{Ti, H 2 O 2, NH} 4 OH, is removed by boiling with a mixture of H ₂ O. FIG. 4B shows the state up to this point.

Thereafter, annealing is performed in an NH ₃ atmosphere at 900 ° C. for 20 seconds, and the TiSi film 20 is converted into a TiSi ₂ film 21 (lower layer) and a TiN film 22 (upper layer).
In a two-layer structure. In this example, when each film thickness was measured by the RBS method, it was 700 ° and 300 °, respectively. The state up to this point is shown in FIG.

Subsequently, similarly to the first embodiment, a Ta ₂ O ₅ film 23 is deposited to a thickness of 200 ° by chemical conversion sputtering. This state is shown in FIG.

Next, a TiN film 24 is deposited to a thickness of 500 mm by chemical conversion sputtering, and a polysilicon layer 2 is formed thereon by LPCVD.
5 is deposited to a thickness of 4000 mm. The state up to this point is shown in FIG.

Furthermore, after placing in a POCl ₃ atmosphere at 900 ° C. for 30 minutes, doping phosphorus into polysilicon, register patterning for forming an upper electrode of the capacitor is performed, and using this resist as a mask, BCl ₃ gas is used. The layers 24 and 25 are removed by RIE etching. The state up to this point is shown in FIG.

Finally, As ion implantation is performed under the conditions of an ion acceleration voltage of ¹⁶ keV and an ion density of 1 × 10 ¹⁶ cm ⁻¹ to form a high concentration diffusion layer 26 of a transistor having an LDD structure. The state up to this point is shown in FIG. Thereafter, the insulating film is covered by a known process, and wiring to the diffusion layer 26 is performed.

If the manufacturing is performed by the above steps, the Ta ₂ O ₅ film 23 becomes a TiN film.
A sandwiched state is formed by the layers 22 and 23, and the reaction with the silicon substrate 1 or the polysilicon layer 25 is prevented.

Effects of the Second Embodiment Also in the second embodiment, as in the first embodiment, the dielectric constant becomes almost 25 regardless of the film thickness, and the leakage as shown by the curve C in FIG. Current characteristics were obtained.

The top view showing the positional relationship near the transfer gate of one memory cell of the DRAM manufactured by the second embodiment is shown in FIG.
It is shown in FIG. Here, the polysilicon gate 19 has a width of
L ₁ = 1.0 μm and length L ₂ = 15 μm. Fig. 5 (b)
FIG. 2 is a side sectional view of this device. A contact hole 28 is opened in a protective insulating layer 27, and a wiring 29 made of aluminum is provided here. As shown in FIG. 5 (a), the distance between the polysilicon gate 19 and the contact hole 28 is L ₃ = 20 μm on the source side, L ₄ = 2 μm on the drain side,
The opening dimension L ₅ of the contact hole 28 was 1.2 μm.

In this transfer gate, the fifth
As shown in FIG. (B), the TiSi ₂ layer 21 and the TiN layer
22 are formed. These layers contribute to the reduction of the layer resistance of the diffusion layer constituting the source / drain, and also to the reduction of the contact resistance in the fine contact due to the barrier metal effect. In fact, in the semiconductor device according to this embodiment, the drain and gate voltages are 5 V and the substrate voltage is −3 V
When the drain current value was measured, an increase of 20 to 30% as compared with the conventional device was confirmed. This was mainly due to the measurement of the layer resistance of the diffusion layer due to the effect of reducing the parasitic resistance in the source side diffusion layer.
In contrast to Ω, in the present example, it was confirmed to be improved to 3 to 5 Ω. Further, the contact resistance between the wiring layer 29 and the conventional device showed a variation of 1 × 10 ^{−6 to} 5 × 10 ⁻⁶ Ωcm ² , whereas the contact resistance with the wiring layer 29 in the present embodiment was 3 × 10 ⁻⁷ to 5 × 10 ⁻⁶ Ωcm ^2.
The resistance value was reduced to 5 × 10 ⁻⁷ Ωcm ² , good contact was obtained, and variation was reduced.

Other Embodiments (1) In the above embodiment, an example was described in which Ta ₂ O ₅ was used as the high dielectric layer. However, in addition, any other transition metal oxide such as HfO ₂ or ZrO ₂ may be used. May be used. Further, a composite material such as Ta ₂ O ₅ —TiO ₂ may be used, or Ta ₂ O ₅ to which impurities such as Ti and Si are added may be used. And the effect of increasing the dielectric constant). In addition, as a raw film method, a Ta ₂ O ₅ film was formed by using a chemical sputtering method, but other methods such as a thermal oxidation method of a Ta sputtered film, an RF sputtering method using a Ta ₂ O ₅ target, and a CVD method were used. A method may be used.

(2) In the above embodiment, a planar capacitor is formed on a single crystal silicon substrate. However, the present invention can be similarly applied to a case where a trench capacitor is formed on a single crystal silicon substrate. The same applies to a case where a multilayer capacitor using polysilicon as a substrate is formed. Further, the upper electrode is not limited to polysilicon, but may be other metals or silicides thereof (W, Mo, Ti, WSix, MoSix, TiSix, etc.).
May be used.

(3) The method of forming a high-melting point metal compound as a barrier film is not limited to the chemical sputtering method. For example, if a high-melting point metal nitride film is to be formed, the high-melting point metal or its silicide film may be formed of N ₂ , A method of performing high-temperature heat treatment in an atmosphere such as NF ₃ or NH ₃ and directly nitriding may be employed.

(4) Although an example in which TiN, that is, a metal nitride film is used as the barrier film has been described, a carbide film such as TiC or a boride film such as TiB may be used.

(5) In the manufacture of the DRAM memory cell in the second embodiment, the TiN / TiSi ₂ film is formed by a self-alignment method using a salicide process. For example, the TiSi ₂ film and the TiN film are entirely formed by sputtering. After being deposited on the PEP
Alternatively, it may be removed by dry etching while leaving only necessary regions. In this case, there is no problem if the TiN / TiSi ₂ region extends to the region where the oxide film for blocking isolation or the oxide film on the transfer gate is formed.

〔The invention's effect〕

As described above, the present invention provides an apparatus for forming a memory cell having a capacitor in which a MOS transistor and a high dielectric layer containing a transition metal oxide are sandwiched between an upper electrode and a lower electrode made of silicon, and such an apparatus. Wherein a first barrier layer is provided on each of a capacitor region and a source / drain region on a silicon substrate as a lower electrode, and a first barrier layer is provided between the silicon electrode as an upper electrode and the high dielectric layer. A second barrier layer is provided, which prevents a reaction between the high dielectric layer and silicon, thereby preventing a decrease in dielectric constant and generation of a leak current. Furthermore, the resistance between the silicon substrate and the second barrier layer is reduced by the presence of the first high-melting-point metal compound layer made of silicide of the high-melting-point metal contained in the first barrier layer.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device manufactured by the method according to the present invention, FIG. 2 is a graph showing the effect of suppressing a decrease in dielectric constant in the method according to the present invention, and FIG. FIG. 4 is a graph showing a current suppressing effect, FIG. 4 is a process diagram of one embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG. 5 is a view showing the vicinity of a transfer gate of a DRAM manufactured by the method shown in FIG. FIG. 6 is a structural sectional view of a conventional multilayer capacitor, and FIG. 7 is a structural sectional view of a conventional capacitor using a high dielectric layer. 1 ... silicon semiconductor substrate, 2 ... impurity diffusion layer, 3 ...
... Oxide film, 4,5,6 ... Polysilicon layer, 7 ... Bit line contact electrode, 8 ... Oxide film for element isolation, 9 ...
Ta ₂ O ₅ layers, 10 …… Top electrode, 11… TiSi ₂ layers, 12… TiN
Film, 13 Ta ₂ O ₅ film, 14 TiN film, 15 polysilicon layer, 16 first diffusion layer, 17 second diffusion layer, 18
Silicon oxide film, 19 ... Polysilicon gate, 20 ... Ti
Si film, 21 ... TiSi ₂ film, 22 ... TiN film, 23 ... Ta ₂ O ₅ film, 2
4 ... TiN film, 25 ... Polysilicon layer, 26 ... High concentration diffusion layer, 27 ... Protective insulating layer, 28 ... Contact hole, 29 ...
... aluminum wiring.

Claims (7)

(57) [Claims] 1. A semiconductor device constituting a memory cell having a MOS transistor and a capacitor having a structure in which a high dielectric layer containing a transition metal oxide is sandwiched between an upper electrode and a lower electrode made of silicon. A source / drain region and a gate electrode serving as constituent elements of a transistor are formed; and the silicon substrate is provided on the capacitor region and the source / drain region of the memory cell on the silicon substrate as the lower electrode. Barrier film for preventing a reaction between the first refractory metal layer and the high dielectric layer, the first refractory metal compound layer comprising a refractory metal silicide, and a refractory metal nitride or carbide on the upper surface thereof. Or the first barrier film including a second refractory metal compound layer made of boride; a silicon electrode forming the upper electrode; and the high dielectric layer. It provided between, and a semiconductor device characterized by comprising a second barrier film that prevents the reaction between the refractory metal compound layer and the high dielectric layer and the silicon electrode is formed by. 2. The semiconductor device according to claim 1, wherein said high dielectric layer is formed of a transition metal compound such as Ta ₂ O ₅ , HfO ₂ , or ZrO ₂ . 3. A method for manufacturing a semiconductor device forming a memory cell having a MOS transistor and a capacitor having a structure in which a high dielectric layer containing a transition metal oxide is sandwiched between an upper electrode and a lower electrode made of silicon. A source / drain region and a gate electrode, which are constituent elements of the MOS transistor, are formed on the capacitor formation region of the memory cell and the source / drain formation region on the silicon substrate as the lower electrode; A first barrier film for preventing a reaction between the silicon substrate and the high dielectric layer, the first barrier film being made of a refractory metal silicide;
Forming the first barrier layer including a second refractory metal compound layer made of nitride, carbide or boride of the refractory metal on the upper surface thereof; and forming the high dielectric substance on the first barrier layer. Forming a layer, and forming a second barrier film on the high dielectric layer, which is formed of the high melting point metal compound layer and which prevents a reaction between the silicon electrode serving as the upper electrode and the high dielectric layer. A method of manufacturing a semiconductor device, comprising: 4. The method for manufacturing a semiconductor device according to claim 3, wherein said high dielectric layer is formed of a transition metal compound such as Ta ₂ O ₅ , HfO ₂ , or ZrO ₂ . 5. The method according to claim 1, wherein the high dielectric layer is formed by a chemical conversion sputtering method of a transition metal oxide, an RF sputtering method, a CVD method, or a thermal oxidation method of a transition metal. 5. The method for manufacturing a semiconductor device according to claim 3 or 4. 6. The first refractory metal compound layer and the second refractory metal compound layer.
6. The method for manufacturing a semiconductor device according to claim 3, wherein said barrier film is formed by chemical conversion sputtering of a refractory metal nitride. 7. The first refractory metal compound layer and the second refractory metal compound layer.
6. The semiconductor device according to claim 3, wherein said barrier film is formed by performing high-temperature heat treatment in an atmosphere containing a high-melting-point metal containing nitrogen or nitride. Manufacturing method.