JP5040676B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device having a buried structure in which a bit line is formed of an impurity diffusion layer, and more particularly to an embedded semiconductor memory device that is silicided and includes a peripheral circuit region and a logic circuit region of a memory cell array region. It is preferable.

  Non-volatile semiconductor memory devices (non-volatile memory) that do not lose stored information even when the power is turned off include EPROM, flash EEPROM, etc., and logic semiconductor devices include MPU, MCU, etc., which are manufactured separately. It is common to do.

  In the nonvolatile memory, research and development of a silicide structure is progressing rapidly for further miniaturization and improvement of operation speed. On the other hand, for the same reason, a logic transistor adopts a source / drain silicide structure or a silicide structure of a source / drain and a gate electrode (salicide structure).

  In recent years, research and development of a hybrid semiconductor device in which a nonvolatile memory and a logic semiconductor device are provided on the same substrate are rapidly progressing. For this reason, silicidation has become necessary even in conventional hybrid semiconductor devices.

  A nonvolatile memory that can be electrically written and erased includes a memory cell array region, a peripheral circuit region, and a connection region on a semiconductor substrate. In the embedded semiconductor device, a logic region including an SRAM or the like is added to the above configuration. It is configured.

  In the memory cell array region of such a nonvolatile memory, it is required to reduce the number of manufacturing processes. As a suitable technique, a buried bit line structure in which a bit line is formed as an impurity diffusion layer on a substrate surface layer has been proposed. .

Here, an example of a conventional nonvolatile memory in which the memory cell array region has a buried bit line structure is shown.
FIG. 13 is an enlarged schematic cross-sectional view showing a memory cell in the memory cell array region and a select transistor in the peripheral circuit region in the nonvolatile memory having the bit line structure, and FIG. 14 is a schematic cross-sectional view along the word line of the memory cell. It is.

  The memory cell and the selection transistor are separated from each other by a field oxide film 108. In the memory cell, for example, as shown in FIG. 14, a first oxide film 120, a charge storage nitride film 121, a first oxide film on a semiconductor substrate 101 are formed. Two oxide films 122 and word lines (WL) 102 are sequentially stacked to form a gate electrode structure. In the select transistor, a gate insulating film 111 and a gate electrode 112 are sequentially stacked on the semiconductor substrate 101 to form a gate electrode structure. Is configured.

  In the memory cell, impurities are ion-implanted into a silicon substrate 101 to form a bit line (BL) 103, an insulating layer 104 is formed on the bit line 103 by thermal oxidation, and the bit line 103 and the word line 102 are insulated. The bit line 103 and the source / drain 113 of the select transistor are insulated and separated by the layer 104, and the contact hole 105 that opens through the insulating layer 104 and opens over the bit line 103 and the contact hole 106 that opens over the source / drain 113 Are connected by a metal wiring 107.

  Next, in a non-volatile memory cell having a floating gate and a control gate, in Patent Document 1, a peripheral circuit portion and a bit line are connected by providing an impurity region.

JP-A-10-98170

  In the conventional nonvolatile memory described above, when silicidation is performed, if the silicide is also formed in the memory cell array region, the adjacent bit line 103 is short-circuited by the silicide, so that the bit line 103 of the memory cell is silicided as described above. Instead, only the peripheral circuit region is silicided. Therefore, in this case, only the memory cell array region is covered with a mask, which causes a problem that the manufacturing process becomes complicated.

  Further, in this case, when the metal wiring 107 is formed, the surface of the bit line 103 which is not silicided is exposed in the contact hole 105 of the memory cell, whereas the silicided source is exposed in the contact hole 106 of the selection transistor. / The surface of the drain 113 is exposed. As described above, when the contact hole is formed, a portion where the silicide is exposed and a portion where the silicon substrate is exposed are mixed, and therefore, if the pretreatment for filling the silicide-side contact hole 106 is performed, the contact on the non-silicide side is performed. There is a problem in that the exposed portion of the hole 105 is damaged, resulting in poor contact, and a desired resistance cannot be obtained.

  Accordingly, an object of the present invention has been made in view of the above problems, and when silicide is formed in a buried bit line structure, silicide formation only in the peripheral circuit region (and logic circuit region) is easily performed with a small number of steps. In addition, when the memory cell array region and the peripheral circuit region (and logic circuit region) are connected to each other by connecting them with the second impurity diffusion layer, the difference in the exposed portion of the opening of the contact hole between the two This is to eliminate the inconvenience caused by the problem. Furthermore, since there is a problem that the overlapping portion of the first impurity diffusion layer and the second impurity diffusion layer constituting the bit line has a high resistance, silicide is formed to suppress an increase in resistance value. This is because, since there is an insulating layer above the first impurity diffusion layer, the impurity does not enter the end of the first impurity diffusion layer even if ion implantation is performed when forming the second impurity diffusion layer. The part is narrow and the resistance is high.

  As described above, the present invention solves various problems caused by the buried bit line structure, enables reliable silicide formation, and achieves further miniaturization and higher speed operation with low resistance and high reliability. An object is to provide a semiconductor memory device.

  As a result of intensive studies, the present inventor has conceived the following aspects of the invention.

A semiconductor memory device according to the present invention includes a memory cell array region in which a word line and a bit line intersect via an insulating layer, and a memory cell is formed at the intersection, and a peripheral having a selection transistor of the memory cell The bit line is composed of a first impurity diffusion layer formed below the insulating layer, and a connection portion between the memory cell array region and the peripheral circuit region. The second impurity diffusion layer is connected to the first impurity diffusion layer at one end, and the insulating layer is not formed on the overlap portion, and the overlap portion is the peripheral circuit. Silicide is formed on the surface layer of the second impurity diffusion layer belonging to the region and including the overlapping portion, and the surface layer of the third impurity diffusion layer constituting the source / drain of the selection transistor In the gate electrode structure of the memory cell, a first insulating film, a charge storage nitride film, a second insulating film, and the word line are sequentially stacked, and between the adjacent bit lines, At least one of the first insulating film, the storage nitride film, and the second insulating film is formed , and the second impurity diffusion layer and the third impurity diffusion layer are separated from each other by an element isolation insulating film. A first plug connected to the second impurity diffusion layer; a second plug connected to the third impurity diffusion layer; the first plug and the second plug; Are connected to each other .

  According to the present invention, when silicidation is performed in a buried bit line structure, it is possible to easily form silicide only in the peripheral circuit region (and logic circuit region) with a small number of steps, and in addition to the memory cell array region and the peripheral circuit. When connecting the regions (and the logic circuit region), the two are connected by the second impurity diffusion layer, so that the inconvenience due to the difference in the exposed portions of the contact holes of the two is eliminated. Further, silicide can be formed at the overlapping portion of the first impurity diffusion layer and the second impurity diffusion layer constituting the bit line, and an increase in resistance value can be suppressed. As described above, the present invention solves various problems due to the buried bit line structure, enables reliable silicide formation, and enables further miniaturization and high-speed operation with low resistance. A semiconductor memory device is realized.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments to which the present invention is applied will be described in detail with reference to the drawings.

(First embodiment)
First, the first embodiment will be described. This nonvolatile semiconductor memory device (nonvolatile memory) has a buried bit line structure, and silicide is formed only in the peripheral circuit region and logic circuit region of the memory cell array region.
FIG. 1 is a schematic plan view showing the nonvolatile memory of the present embodiment, and shows the vicinity of the boundary portion between the memory cell array region and the peripheral circuit region. 2A is a schematic cross-sectional view along II ′ in FIG. 1, FIG. 2B is a schematic cross-sectional view along II-II ′ in FIG. 1, and FIG. FIG. 3 is a schematic cross-sectional view along III-III ′ in FIG. 1.

  This non-volatile memory includes a memory cell array region 2 and a peripheral circuit region 3 (and a logic circuit region: not shown) on a p-type silicon substrate 1, and both are separated by a field oxide film 4. . Here, a so-called SOI (Silicon On Insulator) substrate may be used as the silicon substrate 1 to reduce the parasitic capacitance and increase the operation speed.

  In the memory cell array region 2, the bit line 11 and the word line 12 intersect (orthogonal) via the insulating layer 13, and each memory cell is formed at the intersection. The bit line 11 is formed as an impurity diffusion layer by ion-implanting n-type impurities, here arsenic (As), into the surface layer of the silicon substrate 1, and an insulating layer 13 formed by thermal oxidation is formed on the bit line. Insulation between the line 11 and the word line 12 is ensured. Between the adjacent bit lines 11, a first oxide film 20, a storage nitride film 21, and a second oxide film 22 are stacked to ensure insulation. Here, the bit lines 11 except for the portion overlapping the word line 12 may be insulated with at least one of 20 to 22, but in this example, the case where all of them are provided between the bit lines 11 is illustrated.

  The gate electrode structure of the memory cell is composed of the first oxide film 20, the storage nitride film 21, the second oxide film 22 and the connecting portion where the word line 12 intersects. In this memory cell, the bit line 11 also serves as a source / drain, and charges are stored and released by the storage nitride film 21 to function as a memory.

  As shown in FIG. 2C, a channel stopper layer 23 formed by ion-implanting p-type impurities for threshold control is formed on the surface layer of the silicon substrate 1 immediately below the first oxide film 20. Also good.

  On the other hand, the peripheral circuit region 3 is configured by providing a plurality of selection transistors. The selection transistors are formed by patterning gate electrodes 16 on a gate insulating film 15, and silicon substrates on both sides of the gate electrodes 16. An n-type impurity, here arsenic (As), is ion-implanted into the surface layer 1 to form a source / drain 17.

  In this example, the first oxide film 20, the storage nitride film 21, and the second oxide film 22 are formed only on the memory cell array region 2 side (lower side in FIG. 1) with the line segment MM ′ in FIG. An n-type impurity, here arsenic (As), is formed on the surface layer of the silicon substrate 1 at the connection portion between the memory cell array region 2 and the peripheral circuit region 3 above the line segment MM ′ in FIG. Are ion-implanted to form an impurity diffusion layer 14. This impurity diffusion layer 14 also serves as the source / drain 17 of the selection transistor in part.

  Here, as shown in FIG. 2 (a), the bit line 11 and the impurity diffusion layer 14 are connected with one end thereof being overlapped, and the portion above the line segment MM ′ in FIG. That is, the surface layer of the source / drain 17 of the selection transistor in the peripheral circuit region 3 and the surface layer of the impurity diffusion layer 14 including the overlapping portion 14a are silicided with a refractory metal, here Ti and Si, and the titanium silicide layer 18 is formed. Is formed.

  Then, as shown in FIGS. 1 and 2A, the contact hole 31 and the source for exposing a part of the surface of the titanium silicide layer 18 on the impurity diffusion layer 14 to the interlayer insulating film 19 and the BPSG film 35 covering the entire surface. A contact hole 32 exposing a part of the surface of the titanium silicide layer 18 on the / drain 17 is formed, followed by a tungsten (W) plug 34 for embedding these, and the bit line via the impurity diffusion layer 14 and the source / drain 17 A metal wiring 33 for connecting the transistor 11 and the selection transistor is formed in a pattern.

  In this example, the case where the impurity diffusion layer 14 and the source / drain 17 of the selection transistor are silicided is illustrated. In addition, the impurity diffusion layer in the logic circuit region is silicided and various gate electrodes are polycide. Even if it does, it is suitable.

Hereinafter, the method for manufacturing the nonvolatile memory according to the present embodiment will be described.
3 to 6 are schematic cross-sectional views illustrating the method of manufacturing the nonvolatile memory according to the present embodiment in the order of steps. Here, FIGS. 3B and 3C, FIGS. 4B and 4C, FIGS. 5A and 5B, and FIGS. 6A and 6B are the same steps with different cross-sectional portions. Is shown.

  First, a field oxide film 4 (shown in FIG. 2A) that separates the memory cell array region 2 and the peripheral circuit region 3 on the surface of a p-type silicon substrate 1 (an SOI substrate may be used) by selective oxidation. Is formed to a film thickness of about 200 nm to 500 nm by the LOCOS method. At this time, a so-called STI (Shallow Trench Isolation) element isolation method in which a groove is formed in the element isolation region and an insulator is embedded in the groove may be used.

Next, as shown in FIG. 3A, the first oxide film 20 is formed on the entire surface by thermal oxidation at 900 ° C. to a film thickness of about 5 nm to 10 nm, and the storage nitride film is formed by CVD at about 6 nm to 12 nm. A second oxide film is sequentially formed at a temperature of 1000 ° C. to a thickness of about 4 nm to 10 nm by a thermal oxidation method, and a resist pattern 44 is formed so as to open only a part of the memory cell array region 2 (at this time, oblique ion implantation is performed). For example, boron (B) may be applied to the surface layer of the substrate 1 under the conditions of an acceleration energy of 60 keV and a dose of 2 × 10 ^{13 to} 5 × 10 ¹³ / cm ² ), the first oxide film 20, The storage nitride film 21 and the second oxide film 22 are dry etched.

Subsequently, as shown in FIGS. 3B and 3C, the n-type impurity, here arsenic (As), is accelerated in order to form the bit line 11 also serving as the source / drain using the resist pattern 44 as a mask. Ions are implanted at an energy of 50 keV and a dose of 2 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² . Thereafter, the resist pattern 44 is peeled off, and the insulating layer 4 is formed on the bit line 11 on the bit line 11 by thermal oxidation at a temperature of about 800 nm to about 200 nm.

  Thereafter, the first oxide film is formed only on the peripheral circuit region 3 (upper portion in FIG. 1) including the connection portion between the memory cell array region 2 and the peripheral circuit region 3 with the line segment MM ′ in FIG. 20. The storage nitride film 21 and the second oxide film 22 are dry-etched. These 20 to 22 are left on the memory cell array region 2 excluding the part.

  Subsequently, as shown in FIG. 4A, after the gate insulating film 15 is formed on the peripheral circuit region 2 by thermal oxidation at 900 ° C. to a thickness of about 5 nm to 18 nm, the word line 12 and the gate are formed on the entire surface. A polycrystalline silicon film to be the electrode 16 is deposited to a thickness of about 70 nm to 150 nm, and an n-type impurity, here phosphorus (P), is diffusely doped so that the resistance value is about 100 Ω · cm. At this time, an amorphous silicon film doped with phosphorus may be used instead of the polycrystalline silicon film. A tungsten silicide film 41 is formed thereon with a film thickness of about 100 nm to 180 nm, and a resist antireflection plasma oxynitride film 42 is formed over this with a film thickness of about 30 nm to 150 nm, followed by resist patterning. Thereafter, the polycrystalline silicon film, the tungsten silicide film 41 and the plasma oxynitride film 42 are dry-etched.

Subsequently, in order to form the impurity diffusion layer 14 and the source / drain 17 of the selection transistor at the connection portion between the memory cell array region 2 and the peripheral circuit region 3, an n-type impurity, here phosphorus (P), is accelerated by energy 40 keV, Ion implantation is performed under the condition of a dose of 2 × 10 ¹³ to 4 × 10 ¹³ / cm ² .

  Subsequently, as shown in FIG. 4B, an oxide film is deposited on the entire surface by a CVD method to a thickness of about 70 nm to 150 nm, and then the entire surface is anisotropically etched (etched back) to form sidewall spacers 43. To do. At this time, as shown in FIG. 4C, any one or more of the first oxide film 20, the storage nitride film 21, and the second oxide film 22 are formed on IV-IV ′ of the memory cell portion. The insulating film is left.

Subsequently, an n-type impurity, here, arsenic (As) is applied to the connection portion between the memory cell array region 2 and the peripheral circuit region 3 under the conditions of an acceleration energy of 60 keV and a dose of 2 × 10 ¹⁵ to 4 × 10 ¹⁵ / cm ² . Ion implantation is performed at a high concentration to form the impurity diffusion layer 14 and the selection transistor. At this time, the impurity diffusion layer constituting the bit line 11 and the source / drain 17 (here, the source / drain 17 also serves as the impurity diffusion layer 14) are overlap-connected at one end.

  Subsequently, as shown in FIG. 5A, a refractory metal, here, titanium (Ti) is formed by sputtering to a film thickness of about 20 nm to 30 nm. Next, for example, after heat treatment is performed at 700 ° C. to react Si and Ti, the unreacted layer is etched back, and then heat treatment is performed at 800 ° C. to form the surface layer of the impurity diffusion layer 14 and the source / drain 17. A titanium silicide layer 18 is formed on the surface layer. At this time, a cobalt silicide layer may be formed instead of titanium silicide.

  Here, as shown in FIG. 5B, on the III-III ′ of the memory cell array region 2 (between adjacent bit lines 11), the first oxide film 20, the storage nitride film 21, and the second oxide film are formed. Since any insulating film of the film 22 remains, no silicide is formed in the memory cell array region 2.

  Subsequently, as shown in FIG. 5C, an interlayer insulating film 19 and a BPSG film 35 are formed to a thickness of about 50 nm to 150 nm and about 400 nm to 1000 nm, respectively, by CVD.

  Subsequently, as shown in FIGS. 6A and 6B, after resist patterning, contact holes 31 and 32 are formed by dry etching, and buried tungsten 34 is formed. Then, a metal made of an aluminum alloy is used as a material. A wiring 33 is formed.

  Thereafter, multilayer metal wiring is performed in the same manner as in a normal MOS integrated circuit, a surface passivation film is formed, and a nonvolatile memory is completed.

  As described above, according to the present embodiment, it is possible to easily form a silicide only in the peripheral circuit region 3 (and the logic circuit region) with a small number of steps in the embedded bit line nonvolatile memory. In addition, when the memory cell array region 2 and the peripheral circuit region 3 (and the logic circuit region) are connected, both are connected by the impurity diffusion layer 14, so that the exposed portions of the contact holes 31 and 32 are both silicided. The presence of the layer 18 does not cause inconvenience. Furthermore, since silicide is also formed at the overlapping portion between the impurity diffusion layer and the impurity diffusion layer 14 constituting the bit line 11, an increase in resistance value is suppressed. Thus, according to this example, various problems caused by the buried bit line structure can be solved, reliable silicide formation can be performed, and reliability that enables further miniaturization and higher speed operation with low resistance. A highly nonvolatile memory is realized.

(Second Embodiment)
Next, a second embodiment will be described. Here, a nonvolatile memory having a buried bit line structure is disclosed as in the first embodiment, but is different in that the connection form between the memory cell array region and the peripheral circuit region is different.
FIG. 7 is a schematic plan view showing the nonvolatile memory of this embodiment, and shows the vicinity of the boundary portion between the memory cell array region and the peripheral circuit region. FIG. 8 is a schematic cross-sectional view along II ′ in FIG. In addition, the same code | symbol is described about the same thing as the structural member etc. which were disclosed by 1st Embodiment.

  As in the first embodiment, the non-volatile memory includes a memory cell array region 2 and a peripheral circuit region 3 (and a logic circuit region: not shown) on the p-type silicon substrate 1, both of which are field oxidized. They are separated by a membrane 4. However, unlike the first embodiment, both are completely separated by the field oxide film 4.

  Furthermore, also in this example, in the memory cell array region 2, the bit line 11 and the word line 12 intersect (orthogonal) via the insulating layer 13, and each memory cell is configured at the intersection. The bit line 11 is formed as an impurity diffusion layer by ion-implanting n-type impurities into the surface layer of the silicon substrate 1, and an insulating layer 13 is formed on the bit line by thermal oxidation so that the bit line 11 and the word line 12 are formed. Insulation is ensured. Between the adjacent bit lines 11, a first oxide film 20, a storage nitride film 21, and a second oxide film 22 are stacked to ensure insulation.

  The gate electrode structure of the memory cell is composed of the first oxide film 20, the storage nitride film 21, the second oxide film 22 and the connecting portion where the word line 12 intersects. In this memory cell, the bit line 11 also serves as a source / drain, and charges are stored and released by the storage nitride film 21 to function as a memory.

  On the other hand, the peripheral circuit region 3 is configured by providing a plurality of selection transistors. The selection transistors are formed by patterning gate electrodes 16 on a gate insulating film 15, and silicon substrates on both sides of the gate electrodes 16. A source / drain 17 is formed by ion-implanting n-type impurities into one surface layer.

  In this example, the first oxide film 20, the storage nitride film 21, and the second oxide film 22 are formed only on the memory cell array region 2 side (lower side in FIG. 7) with the line segment NN ′ in FIG. 7 as a boundary. An n-type impurity, here arsenic (As), is formed in the surface layer of the silicon substrate 1 at the connection portion between the memory cell array region 2 and the peripheral circuit region 3 above the line segment NN ′ in FIG. Are ion-implanted to form an impurity diffusion layer 14. This impurity diffusion layer 14 also serves as the source / drain 17 of the selection transistor in part. Here, the connection portion, that is, the impurity diffusion layer 14 is provided on the memory cell array region 2 side separated by the field oxide film 4.

  Here, as shown in FIG. 8, the bit line 11 and the impurity diffusion layer 14 are connected to each other with one end overlapped, and the portion above the line segment NN ′ in FIG. 7, that is, the peripheral circuit. The surface layer of the source / drain 17 of the selection transistor in the region 3 and the surface layer of the impurity diffusion layer 14 including the overlapping portion 14a are silicided with a refractory metal, here Ti and Si, and the titanium silicide layer 18 is formed. Yes.

  Then, a contact hole 31 that exposes part of the surface of the titanium silicide layer 18 on the impurity diffusion layer 14 to the interlayer insulating film 19 and the BPSG film 35 covering the entire surface and a surface of the titanium silicide layer 18 on the source / drain 17 are exposed. A contact hole 32 exposing the portion is formed, followed by a tungsten (W) plug 34 for embedding them, and a metal wiring 33 for connecting the bit line 11 and the selection transistor through the impurity diffusion layer 14 and the source / drain 17 is patterned. Is formed.

Hereinafter, the method for manufacturing the nonvolatile memory according to the present embodiment will be described.
9 to 12 are schematic cross-sectional views illustrating the method of manufacturing the nonvolatile memory according to the present embodiment in the order of steps. Here, FIGS. 10 (a) and 10 (b), FIGS. 11 (a) and 11 (b), FIGS. 11 (c) and 11 (d), and FIGS. Is shown.

  First, as shown in FIG. 9A, a field oxide film for separating the memory cell array region 2 and the peripheral circuit region 3 on the surface of a p-type silicon substrate 1 (an SOI substrate may be used) by a selective oxidation method. 4 is formed to a film thickness of about 200 nm to 500 nm by the LOCOS method. Here, unlike the first embodiment, it is assumed that the memory cell array region 2 and the peripheral circuit region 3 are completely separated by the field oxide film 4. At this time, a so-called STI (Shallow Trench Isolation) element isolation method in which a groove is formed in the element isolation region and an insulator is embedded in the groove may be used.

Next, as shown in FIG. 9B, the first oxide film 20 is formed on the entire surface by a thermal oxidation method at 900 ° C. to a film thickness of about 5 nm to 10 nm, and the storage nitride film is formed by a CVD method to about 6 nm to 12 nm. A second oxide film is sequentially formed at a temperature of 1000 ° C. to a thickness of about 4 nm to 10 nm by a thermal oxidation method, and a resist pattern 44 is formed so as to open only a part of the memory cell array region 2 (at this time, oblique ion implantation is performed). For example, boron (B) may be applied to the surface layer of the substrate 1 under the conditions of an acceleration energy of 60 keV and a dose of 2 × 10 ^{13 to} 5 × 10 ¹³ / cm ² ), the first oxide film 20, The storage nitride film 21 and the second oxide film 22 are dry etched.

Subsequently, as shown in FIGS. 10A and 10B, the n-type impurity, here arsenic (As), is accelerated in order to form the bit line 11 also serving as the source / drain using the resist pattern 44 as a mask. Ions are implanted at an energy of 50 keV and a dose of 2 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² . Thereafter, the resist pattern 44 is peeled off, and the insulating layer 4 is formed on the bit line 11 on the bit line 11 by thermal oxidation at a temperature of about 800 nm to about 200 nm.

  Thereafter, the first oxide film is formed only on the peripheral circuit region 3 (upper portion in FIG. 7) including the connection portion between the memory cell array region 2 and the peripheral circuit region 3 with the line segment NN ′ in FIG. 7 as a boundary. 20. The storage nitride film 21 and the second oxide film 22 are dry-etched. These 20 to 22 are left on the memory cell array region 2 excluding the part.

  Subsequently, as shown in FIG. 10C, a gate insulating film 15 is formed on the peripheral circuit region 2 by thermal oxidation at 900 ° C. to a film thickness of about 5 nm to 18 nm, and then the word line 12 and the gate are formed on the entire surface. A polycrystalline silicon film to be the electrode 16 is deposited to a thickness of about 70 nm to 150 nm, and an n-type impurity, here phosphorus (P), is diffusely doped so that the resistance value is about 100 Ω · cm. At this time, an amorphous silicon film doped with phosphorus may be used instead of the polycrystalline silicon film. A tungsten silicide film 41 is formed thereon with a film thickness of about 100 nm to 180 nm, and a resist antireflection plasma oxynitride film 42 is formed over this with a film thickness of about 30 nm to 150 nm, followed by resist patterning. Thereafter, the polycrystalline silicon film, the tungsten silicide film 41 and the plasma oxynitride film 42 are dry-etched.

Subsequently, in order to form the impurity diffusion layer 14 and the source / drain 17 of the selection transistor at the connection portion between the memory cell array region 2 and the peripheral circuit region 3, an n-type impurity, here phosphorus (P), is accelerated by energy 40 keV, Ion implantation is performed under the condition of a dose of 2 × 10 ¹³ to 4 × 10 ¹³ / cm ² . Here, in this example, since the memory cell array region 2 and the peripheral circuit region 3 are completely separated by the field oxide film 4, the connection part is provided in the memory cell array region 2.

  Subsequently, as shown in FIG. 11A, an oxide film is deposited on the entire surface to a thickness of about 70 nm to 150 nm by the CVD method, and then the entire surface is anisotropically etched (etched back) to form sidewall spacers 43. To do. At this time, as shown in FIG. 11B, any one or more of the first oxide film 20, the storage nitride film 21, and the second oxide film 22 are formed on IV-IV ′ of the memory cell portion. The insulating film is left.

Subsequently, an n-type impurity, here, arsenic (As) is applied to the connection portion between the memory cell array region 2 and the peripheral circuit region 3 under the conditions of an acceleration energy of 60 keV and a dose of 2 × 10 ¹⁵ to 4 × 10 ¹⁵ / cm ² . Ion implantation is performed at a high concentration to form the impurity diffusion layer 14 and the selection transistor. At this time, the impurity diffusion layer and the impurity diffusion layer 14 constituting the bit line 11 are overlapped and connected at one end.

  Subsequently, as shown in FIG. 11C, a refractory metal, here, titanium (Ti) is formed to a thickness of about 20 nm to 30 nm by a sputtering method. Next, for example, after heat treatment is performed at 700 ° C. to react Si and Ti, the unreacted layer is etched back, and then heat treatment is performed at 800 ° C. to form the surface layer of the impurity diffusion layer 14 and the source / drain 17. A titanium silicide layer 18 is formed on the surface layer. At this time, a cobalt silicide layer may be formed instead of titanium silicide.

  Here, as shown in FIG. 11D, on the III-III ′ of the memory cell array region 2 (between adjacent bit lines 11), the first oxide film 20, the storage nitride film 21, the second oxide film are formed. Since any insulating film of the film 22 remains, no silicide is formed in the memory cell array region 2.

  Subsequently, as shown in FIG. 12A, an interlayer insulating film 19 and a BPSG film 35 are formed to have a film thickness of about 50 nm to 150 nm and about 400 nm to 1000 nm, respectively, by CVD.

  Subsequently, as shown in FIGS. 12B and 12C, after resist patterning, contact holes 31 and 32 are formed by dry etching, buried tungsten 34 is formed, and then a metal made of aluminum alloy is used as a material. A wiring 33 is formed.

  Thereafter, multilayer metal wiring is performed in the same manner as in a normal MOS integrated circuit, a surface passivation film is formed, and a nonvolatile memory is completed.

  As described above, according to the present embodiment, it is possible to easily form a silicide only in the peripheral circuit region 3 (and the logic circuit region) with a small number of steps in the embedded bit line nonvolatile memory. In addition, when the memory cell array region 2 and the peripheral circuit region 3 (and the logic circuit region) are connected, both are connected by the impurity diffusion layer 14, so that the exposed portions of the contact holes 31 and 32 are both silicided. The presence of the layer 18 does not cause inconvenience. Furthermore, since silicide is also formed at the overlapping portion between the impurity diffusion layer and the impurity diffusion layer 14 constituting the bit line 11, an increase in resistance value is suppressed. Thus, according to this example, various problems caused by the buried bit line structure can be solved, reliable silicide formation can be performed, and reliability that enables further miniaturization and higher speed operation with low resistance. A highly nonvolatile memory is realized.

In the first and second embodiments, the following means can be used.
(1) The impurity diffusion layer in the peripheral circuit region 3 (and logic circuit region) is silicided or the silicide structure of the gate electrode 15 and the impurity diffusion layer is used, and at the same time, the word line 12 in the memory cell array region 2 has a silicide structure or a polycide structure. To do.
(2) A nitride film or a nitrided oxide film is formed on each gate electrode to prevent reflection during exposure and to function as an etching stopper, thereby realizing desired etching.

  Hereinafter, various aspects of the present invention will be described together.

(Supplementary Note 1) A word line and a bit line intersect with each other through an insulating layer, and a memory cell array region in which a memory cell is formed at the intersection, and a peripheral circuit region having a selection transistor of the memory cell. A semiconductor storage device comprising:
The bit line includes a first impurity diffusion layer formed under the insulating layer,
A connection portion between the memory cell array region and the peripheral circuit region has a second impurity diffusion layer overlapped with the first impurity diffusion layer at one end;
A semiconductor memory device, wherein silicide is formed on a surface layer of the second impurity diffusion layer including the overlapping portion and a surface layer of a third impurity diffusion layer constituting a source / drain of the selection transistor.

  (Supplementary note 2) A part of the second impurity diffusion layer is formed in common with one of the third impurity diffusion layers constituting the source / drain. Semiconductor memory device.

  (Supplementary note 3) The semiconductor memory device according to supplementary note 1, wherein the second impurity diffusion layer is formed independently of the third impurity diffusion layer constituting the source / drain.

  (Additional remark 4) The said memory cell and the said selection transistor are what the said 2nd impurity diffusion layer and the said 3rd impurity diffusion layer are wiring-connected through each said silicide, The additional remark characterized by the above-mentioned The semiconductor memory device according to any one of 1 to 3.

  (Supplementary Note 5) The gate electrode structure of the memory cell includes a first insulating film, a charge storage nitride film, a second insulating film, and the word line, which are sequentially stacked. The semiconductor memory device according to any one of the above.

  (Supplementary note 6) The supplementary note 5, wherein at least one of the first insulating film, the storage nitride film, and the second insulating film is formed between the adjacent bit lines. Semiconductor memory device.

  (Supplementary note 7) The silicide according to any one of supplementary notes 1 to 6, wherein silicide is formed on the peripheral circuit region and no silicide is present on the impurity diffusion layer in the memory cell array region. Semiconductor memory device.

  (Supplementary note 8) The semiconductor memory device according to any one of supplementary notes 1 to 7, further comprising a logic circuit region having a predetermined transistor, wherein the predetermined transistor is silicided.

(Additional remark 9) The process of partitioning the 1st element formation area of a peripheral circuit area and / or a logic circuit area, and the 2nd element formation area of a memory cell on a semiconductor substrate,
After the first oxide film, the storage nitride film, and the second oxide film are stacked in the first and second element formation regions, the first oxide film only in the first element formation region, Patterning the storage nitride film and the second oxide film into a predetermined shape;
Forming a first impurity diffusion layer to be a bit line by selectively introducing impurities into the second element formation region, and then forming an insulating layer on the first impurity diffusion layer;
The first oxide film, the storage nitride film, and the second oxide film are removed only in the first element formation region and a connection portion between the first element formation region and the second element formation region. Process,
Forming a gate insulating film in the first element formation region;
After forming a silicon film in the first element formation region and the second element formation region, the silicon film is patterned, and a gate electrode is formed on the gate insulating film in the first element formation region. Forming a word line on each of the first oxide film, the storage nitride film, and the second oxide film in a second element formation region;
Impurities are introduced into the connection site and the first element formation region, and a second impurity diffusion layer is connected to the connection site so as to overlap with the first impurity diffusion layer at one end, Forming a third impurity diffusion layer to be a source / drain in the element formation region;
And a step of forming silicide on a surface layer of the second impurity diffusion layer including the overlapping portion and a surface layer of the third impurity diffusion layer constituting the source / drain of the selection transistor. Manufacturing method.

  (Supplementary note 10) The method of manufacturing a semiconductor memory device according to supplementary note 9, wherein a part of the second impurity diffusion layer is formed in common with one of the third impurity diffusion layers.

1 is a schematic plan view showing a nonvolatile memory according to a first embodiment. It is a schematic sectional drawing which shows the non-volatile memory of 1st Embodiment. It is a schematic sectional drawing which shows the manufacturing method of the non-volatile memory by 1st Embodiment to process order. FIG. 4 is a schematic cross-sectional view showing the method of manufacturing the nonvolatile memory according to the first embodiment in order of processes following FIG. 3. FIG. 5 is a schematic cross-sectional view showing the method of manufacturing the nonvolatile memory according to the first embodiment in order of processes following FIG. 4. FIG. 6 is a schematic cross-sectional view showing the method of manufacturing the nonvolatile memory according to the first embodiment in order of processes following FIG. 5. It is a schematic plan view which shows the non-volatile memory of 2nd Embodiment. It is a schematic sectional drawing which shows the non-volatile memory of 2nd Embodiment. It is a schematic sectional drawing which shows the manufacturing method of the non-volatile memory by 2nd Embodiment to process order. FIG. 10 is a schematic cross-sectional view illustrating the method of manufacturing the nonvolatile memory according to the second embodiment in the order of processes following FIG. 9. FIG. 11 is a schematic cross-sectional view illustrating the method of manufacturing the nonvolatile memory according to the second embodiment in the order of processes following FIG. 10. FIG. 12 is a schematic cross-sectional view illustrating the method of manufacturing the nonvolatile memory according to the second embodiment in the order of processes following FIG. 11. It is a schematic sectional drawing which shows the conventional non-volatile memory. In the conventional non-volatile memory, it is a schematic sectional drawing along the word line of the memory cell.

Explanation of symbols

1 silicon substrate 2 memory cell array region 3 peripheral circuit region 4 field oxide film 11 bit line 12 word line 13 insulating layer 14 impurity diffusion layer 15 gate insulating film 16 gate electrode 17 source / drain 18 titanium silicide layer 19 interlayer insulating film 20 first Oxide film 21 Storage nitride film 22 Second oxide film 23 Channel stopper layer 31, 32 Contact hole 33 Metal wiring 34 Tungsten (W) plug 35 BPSG film 41 Tungsten (W) silicide film 42 Plasma nitrided oxide film 43 Side wall spacer 44 resist pattern

Claims (1)

A semiconductor memory comprising a memory cell array region in which a word line and a bit line intersect via an insulating layer and a memory cell is formed at the intersection, and a peripheral circuit region having a selection transistor of the memory cell A device,
The bit line includes a first impurity diffusion layer formed under the insulating layer,
A connection portion between the memory cell array region and the peripheral circuit region has a second impurity diffusion layer overlapped with the first impurity diffusion layer at one end;
The insulating layer is not formed on the overlapping portion, and the overlapping portion belongs to the peripheral circuit region,
Silicide is formed on the surface layer of the second impurity diffusion layer including the overlapping portion and the surface layer of the third impurity diffusion layer constituting the source / drain of the selection transistor,
The gate electrode structure of the memory cell has a first insulating film, a charge storage nitride film, a second insulating film, and the word line sequentially stacked.
Between the adjacent bit lines, at least one of the first insulating film, the storage nitride film, and the second insulating film is formed ,
The second impurity diffusion layer and the third impurity diffusion layer are separated from each other by an element isolation insulating film;
A first plug connected to the second impurity diffusion layer;
A second plug connected to the third impurity diffusion layer;
A semiconductor memory device comprising: a wiring interconnecting the first plug and the second plug .

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