JP3679922B2 - Nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device in which data can be electrically written / erased, and in particular, two or more insulating films are used as a charge storage layer, and the vicinity of the interface between these two or more insulating films. That is, the present invention relates to a nonvolatile semiconductor memory device that accumulates electric charges at or near the interface.
[0002]
[Prior art]
15 and 16 show a conventional nonvolatile semiconductor memory device having a NAND structure. Of these figures, FIG. 15 is a three-dimensional perspective view of the word line portion formed on the semiconductor substrate with the interlayer insulating film removed. FIG. 16A is a plan view of the nonvolatile semiconductor memory device, and FIG. 16B is a cross-sectional view thereof.
[0003]
As can be seen from FIG. 15, a plurality of lower oxide films 102 are continuously formed in the word line direction on the surface of the semiconductor substrate 100 of the nonvolatile semiconductor memory device. Similarly, a nitride film 104 is continuously formed on the lower oxide film 102 in the word line direction. Similarly, an upper oxide film 106 is continuously formed on the nitride film 104 in the word line direction. The lower oxide film 102, the nitride film 104, and the upper oxide film 106 described above constitute the charge storage layer 107. On the surface of the upper oxide film 106, word lines 108 are continuously formed in the word line direction. This word line is made of polysilicon doped with impurities.
[0004]
As can be seen from FIG. 16B, a bit line 110 is formed above the word line 108 in the bit line direction via an interlayer insulating film 109. As can be seen from FIG. 16A, a contact hole 112 is provided on the upper side of the bit line 110 in the drawing, and is electrically connected to the drain region D formed on the surface side of the semiconductor substrate 100. A source / drain region SD is formed between the word lines 108 on the surface side of the semiconductor substrate 100. As can be seen from FIG. 15, a channel region CH is formed on the surface side of the semiconductor substrate 100 below the word line 108. As can be seen from the portion surrounded by the alternate long and short dash line in FIG. 16, one word line 108 and two source / drain regions SD positioned above and below in the drawing constitute a 1-bit memory cell transistor. In the lower side of the lower memory cell transistor in the figure, the source region S is formed continuously in the word line direction.
[0005]
[Problems to be solved by the invention]
As can be seen from FIG. 16B, conventionally, the nitride film 104 of the charge storage layer 107 is continuously provided in the word line direction. That is, in the nonvolatile semiconductor memory device in which charges are accumulated near the interface between two or more different types of insulating films, the interfaces between the insulating films are continuous in the word line direction. This is because, in the prior art, since the charge storage layer 107 is formed of an insulating film, it is considered that charges held near the interface do not move.
[0006]
However, it has been found that the charge held near the interface between the lower oxide film 102 and the nitride film 104 may move and spread due to aging or use in a high temperature state. That is, since the nitride film 104 which is an insulating film is not separated for each memory cell transistor, the retained charge can move in the vicinity of this interface. When the charge held in the vicinity of the interface moves in this way, the threshold value of the memory transistor fluctuates, the data retention characteristics in the nonvolatile semiconductor memory device deteriorate, and a problem arises in reliability.
[0007]
Accordingly, the present invention has been made in view of the above problems, and a nonvolatile semiconductor with improved data retention characteristics and reliability by preventing retained charges from moving near the interface between two or more insulating films. An object is to provide a storage device. Specifically, among the two or more types of insulating films, the nitride film is divided for each memory cell transistor, thereby dividing the interface for holding charges in the word line direction so that the movement of the held charges does not occur. An object is to provide a nonvolatile semiconductor memory device.
[0008]
[Means for Solving the Problems]
The nonvolatile semiconductor memory device according to the present invention is
A non-volatile semiconductor memory device having a plurality of memory cell transistors arranged in a matrix in a row direction and a column direction,
Each of the memory cell transistors is
A charge storage layer formed by stacking two or more insulating films on a semiconductor substrate so as to be able to store electric charges in the vicinity of an interface between the two or more insulating films, wherein the two or more insulating films Out of part By separating the insulating film for each memory cell transistor, the interface between the two or more insulating films is separated for each memory cell transistor. However, the remaining insulating film of the part of the insulating film is not separated, A charge storage layer;
A word line formed on the charge storage layer for applying a voltage to the charge storage layer;
Source / drain regions formed on the semiconductor substrate surface side located on both sides of the charge storage layer,
The plurality of memory cell transistors arranged in the column direction are connected in series in the column direction so as to share the source / drain regions, and both ends of the plurality of memory cell transistors connected in series are connected to each other. Select transistors are connected continuously, and for each column, a NAND memory cell is configured,
Each of the word lines is formed continuously in the row direction so as to be commonly connected to the respective charge storage layers of the plurality of memory cell transistors arranged in the row direction.
It is characterized by that.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
The first embodiment of the present invention is a nonvolatile semiconductor memory device having a NAND memory cell transistor in which two or more insulating films are stacked and used as a charge storage layer, and at least one of the interfaces of the two or more insulating films. The memory cell transistor is separated for each memory cell transistor so that the trapped charges are not moved and spread in the vicinity of the interface, thereby suppressing fluctuations in the threshold value of the memory cell transistor and improving data retention. It is an improvement. Hereinafter, the present embodiment will be described in detail based on the drawings.
[0011]
First, the structure of the nonvolatile semiconductor memory device according to this embodiment will be described with reference to FIGS. FIG. 1A is a plan view showing through an interlayer insulating film of a nonvolatile semiconductor memory device, and FIG. 1B is a cross-sectional view taken along line (b)-(b) in FIG. FIG. 2 is a perspective view showing the word line portion of the nonvolatile semiconductor memory device in three dimensions by removing the interlayer insulating film.
[0012]
As can be seen from FIG. 1B, an element isolation region 12 having an impurity concentration higher than that of the semiconductor substrate 10 is formed on the surface side of the semiconductor substrate 10 made of a p-type silicon substrate. The element isolation region 12 is continuously formed in the bit line direction (column direction), and prevents field inversion between the memory cell transistors arranged in the word line direction (row direction). A charge storage layer 20 is formed on the semiconductor substrate 10. The charge storage layer 20 includes a lower oxide film 23 formed in an island shape for each memory cell transistor, and a nitride film 24 formed in an island shape for each memory cell transistor thereon. It is equipped with. That is, as can be seen from FIG. 1A, the nitride film 24 is also divided in the word line direction and formed for each memory cell transistor. Further, as can be seen from FIG. 1B, the charge storage layer 20 includes an upper oxide film 26 continuously formed in the word line direction so as to cover the lower oxide film 23 and the nitride film 24. Yes. That is, the charge storage layer 20 is composed of three insulating films composed of the lower oxide film 23, the nitride film 24, and the upper oxide film 26.
[0013]
Similarly, as can be seen from FIG. 1B, word lines 30 made of polysilicon or the like are continuously formed in the word line direction above the charge storage layer 20. That is, as can be seen from FIG. 1A, the word line 30 is formed so as to cover the plurality of nitride films 24 arranged in the word line direction. As can be seen from FIG. 1B again, an interlayer insulating film 32 is formed on the upper side of the word line 30 so as to cover the surface of the nonvolatile semiconductor memory device. A bit line 34 is formed on the interlayer insulating film 32. As can be seen from FIG. 1A, the bit line 34 is continuously formed in the bit line direction. A contact hole 36 is provided on the upper side of the bit line 34 in the drawing, and the bit line 34 is connected to the drain region D formed on the surface side of the semiconductor substrate 10 through the contact hole 36. . A selection transistor having an upper oxide film 26 is connected to the lower side of the drain region D, and a memory cell transistor is positioned below the selection transistor. Source / drain regions SD are formed between the nitride films 24 arranged in series in the bit line direction. Further, a selection transistor having an upper oxide film 26 is provided below the lowermost nitride film 24 in the drawing, and a common source region S is formed below the selection transistor. As can be seen from FIG. 2, a channel region CH is formed between the source / drain regions SD below the word line 30.
[0014]
A circuit diagram of a nonvolatile semiconductor memory device having such a NAND memory cell transistor is shown in FIG. As can be seen from FIG. 3, the NAND type memory cell transistors are connected in series so that the memory cell transistors share the source / drain region SD. Further, one select transistor is continuously connected to both ends of the memory cell transistors connected in series.
[0015]
Next, a method for manufacturing the nonvolatile semiconductor memory device according to this embodiment will be described with reference to FIGS. 4 to 7 and FIG.
[0016]
First, as can be seen from FIG. 4, an oxide film 22A is formed on the surface side of the semiconductor substrate 10 made of a p-type silicon substrate by thermal oxidation. In this embodiment, the oxide film 22A is formed with a thickness of 100 to 200 angstroms. Subsequently, a resist is applied on the upper side of the oxide film 22A and patterned by photolithography to form a resist 40 having slit-like resist openings 40a. Next, an impurity such as boron is implanted into the semiconductor substrate 10 by ion implantation to form a p-type element isolation region 12. That is, by implanting an impurity from the resist opening 40a, the element isolation region 12 having an impurity concentration higher than the impurity concentration in the channel region CH of the semiconductor substrate 10 is formed.
[0017]
Next, as can be seen from FIG. 5, after the resist 40 is removed, the oxide film 22A is removed by wet etching, and the lower oxide film 23A is formed by thermal oxidation to a thickness of, for example, 50 to 80 angstroms. Subsequently, a nitride film 24A is formed on the upper side of the lower oxide film 23A by CVD. In this embodiment, the nitride film 24A is deposited with a thickness of 80 to 150 angstroms. Next, a resist is coated on the upper side of the nitride film 24A and patterned by photolithography, thereby forming a resist 42 having a slit-like resist opening 42a so that the resist remains only in a region where a memory cell transistor is to be formed. . Subsequently, the lower oxide film 23A and the nitride film 24A are etched by RIE to form the lower oxide film 23B and the nitride film 24B. That is, portions of the lower oxide film 23A and the nitride film 24A other than the memory cell transistor formation region are removed, and the lower oxide film 23B and the nitride film 24B are formed.
[0018]
Next, as can be seen from FIG. 6, after removing the resist 42, this is thermally oxidized to form an upper oxide film 26A on this surface. In this thermal oxidation, the upper oxide film 26A on the nitride film 24B is formed to be thinner than the upper oxide film 26A on the semiconductor substrate 10. Further, as can be seen from FIG. 7, since the surface of the semiconductor substrate 10 is also exposed in the select transistor formation scheduled region, the oxide film 26A for the select transistor is also formed thick. Subsequently, as can be seen from FIG. 6, a polysilicon 30A is formed on the upper side of the upper oxide film 26A by CVD. Next, a resist is applied to the upper side of the polysilicon 30A and patterned by photolithography to form a resist 44 that continuously extends in the word line direction. Subsequently, by performing RIE, the upper oxide film 26A, the nitride film 24B, and the lower oxide film 23B are etched. That is, by etching using the resist 44 as a mask, the upper oxide film 26A, the nitride film 24B, and the lower oxide film 23B are separated in the bit line direction. Thereby, the lower oxide film 23 and the nitride film 24 separated for each memory cell transistor are formed. Further, the upper oxide film 26 and the word line 30 that continuously extend in the word line direction are formed.
[0019]
Next, as can be seen from FIG. 1, after removing the resist 44, an impurity such as arsenic is implanted into the semiconductor substrate 10 by ion implantation using a resist pattern having openings only in the source / drain regions. A drain region D, an n-type source / drain region SD, and an n-type source region S are formed. Subsequently, an interlayer insulating film 32 is formed on the intermediate nonvolatile semiconductor memory device by CVD. Next, a contact hole 36 is opened on the drain region D in the interlayer insulating film 32 by photolithography and RIE. Subsequently, a wiring layer made of aluminum or the like is deposited on the intermediate nonvolatile semiconductor memory device by sputtering, and the bit line 34 is formed by etching the wiring layer by photolithography and RIE. Through the above process, the nonvolatile semiconductor memory device shown in FIG. 1 is obtained.
[0020]
As described above, according to the nonvolatile semiconductor memory device according to the first embodiment, as can be seen from FIG. 1, the nitride film 24 in the charge storage layer 20 is separated for each memory cell transistor. The movement can be prevented. More specifically, electric charges are trapped in the vicinity of the interface between the lower oxide film 23 and the nitride film 24, that is, in the interface or in the vicinity thereof. The trapped charges can move and spread along the vicinity of the interface due to aging and use of high temperature conditions. However, in the present embodiment, since the nitride film 24 is divided for each memory cell transistor, the interface between the nitride film 24 and the lower oxide film 23 is also divided for each memory cell transistor. For this reason, the movement of the trapped charge can be suppressed and data retention can be improved.
[0021]
[Second Embodiment]
In the second embodiment, by applying the present invention to a ground cell array type nonvolatile semiconductor memory device, the trapped electric charges do not spread near the interface between two or more insulating films, so that the memory cell transistor The data retention is improved by suppressing the fluctuation of the threshold value. Hereinafter, the present embodiment will be described in detail based on the drawings.
[0022]
First, the structure of the nonvolatile semiconductor memory device according to the second embodiment will be described with reference to FIGS. 8 is a plan view showing through the interlayer insulating film of the nonvolatile semiconductor memory device according to the second embodiment, FIG. 9 is a cross-sectional view taken along the line IX-IX in FIG. 8, and FIG. FIG.
[0023]
As can be seen from FIG. 9, an n-type drain region D and an n-type source region S are formed on the surface side of the semiconductor substrate 50 made of p-type silicon. As can be seen from FIG. 8, the drain region D and the source region S are continuously formed in the bit line direction. As can be seen from FIG. 9, a charge storage layer 60 is formed on the upper side of the semiconductor substrate 50. The charge storage layer 60 includes a lower oxide film 63, a nitride film 64, and an upper oxide film 66. The lower oxide film 63 and the nitride film 64 are formed separately for each memory cell transistor. The upper oxide film 66 is continuously formed so as to cover the nitride films 64 arranged in the word line direction. A word line 68 made of polysilicon is formed on the upper oxide film 66 continuously in the word line direction. The word line 68, the nitride film 64, the lower oxide film 63, the drain region D, the source region S, and the channel region CH constitute one memory cell transistor. On the upper side of the word line 68, an interlayer insulating film 70 is formed so as to cover the nonvolatile semiconductor memory device.
[0024]
As can be seen from FIG. 8, an element isolation region 72 for preventing field inversion is formed in the semiconductor substrate 50 between the nitride film 64 of each memory cell transistor in the bit line direction. That is, as can be seen from FIG. 10, a p-type element isolation region 72 having an impurity concentration higher than that of the semiconductor substrate 50 is formed between the bit line directions of the memory cell transistors. That is, the element isolation region 72 having an impurity concentration higher than that of the channel region CH (see FIG. 9) is formed. As can be seen from FIG. 8, a contact hole 74 is formed at one end of the word line 68. In the present embodiment, the contact holes 74 are alternately formed on the left and right sides for each word line 68. Similarly, a contact hole 75 is also formed at one end of the drain region D and the source region S. In the present embodiment, the contact holes 75 are alternately formed in the top and bottom in the drain region D and the source region S. Through these contact holes 74 and 75, the word line 68 and the source / drain regions S and D are electrically connected to the wiring layer. A plurality of memory transistors are also connected in series in the word line direction, but are not shown in FIG.
[0025]
A circuit diagram of such a ground cell array type nonvolatile semiconductor memory device is shown in FIG. As can be seen from FIG. 11, in the ground cell array type nonvolatile semiconductor memory device, a plurality of memory cell transistors are connected so as to commonly use one source S and one drain region D.
[0026]
Next, a method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment will be described with reference to FIGS. 12 to 14, 8, and 9.
[0027]
As can be seen from FIG. 12, an oxide film 62A is formed on the surface side of the semiconductor substrate 50 made of a p-type silicon substrate by thermal oxidation. In the present embodiment, the oxide film 62A is formed with a thickness of 100 to 200 angstroms. Subsequently, a resist is applied on the upper side of the oxide film 62A and patterned by photolithography to form a slit-like resist 80 having a resist opening 80a. Next, an impurity isolation region 72A is formed by implanting impurities such as boron into the semiconductor substrate 50 by ion implantation. That is, by implanting impurities from the resist opening 80a, an element isolation scheduled region 72A having an impurity concentration higher than that of the semiconductor substrate 50 is formed.
[0028]
Next, as can be seen from FIG. 13, after removing the resist 80, the oxide film 62A is removed by wet etching, and a lower oxide film 63A is formed by thermal oxidation to a thickness of, for example, 50 to 80 angstroms. Subsequently, a nitride film 64A is formed above the lower oxide film 63A by CVD. In the present embodiment, the nitride film 64A is deposited with a thickness of 80 to 150 Å. Next, a resist is applied on the upper side of the nitride film 64A and patterned by photolithography to form a resist 82 having a resist opening 82a. The resist opening 82a is formed in the resist 82 in a slit shape. Subsequently, the lower oxide film 63A and the nitride film 64A are etched by RIE, thereby forming the lower oxide film 63B and the nitride film 64B. That is, lower oxide film 63A and nitride film 64A are separated in the word line direction so as to be separated from adjacent memory cell transistors. Next, n-type drain region D and source region S are formed by implanting ions of arsenic, phosphorus, or the like from this slit opening 82a. At this time, since the concentration of arsenic, phosphorus or the like implanted into the drain region D and the source region S is higher than the concentration of boron or the like previously implanted into the element isolation planned region 72A, the drain region D and the source region S are divided. It will never be done. An element isolation region 72 (see FIG. 8) is formed by the remaining element isolation scheduled region 72A in which the drain region D and the source region S are not formed.
[0029]
Next, as can be seen from FIG. 14, after removing the resist 82, it is thermally oxidized to form an upper oxide film 66A on this surface. In this thermal oxidation, the upper oxide film 66A on the nitride film 64B is formed to be thinner than the upper oxide film 66A on the semiconductor substrate 50. Subsequently, a polysilicon 68A is formed on the upper side of the upper oxide film 66A by CVD. Next, a resist is applied to the upper side of the polysilicon 68A and patterned by photolithography to form a resist 84 having slits 84a and continuously extending in the word line direction. Subsequently, the upper oxide film 66A, the nitride film 64B, and the lower oxide film 63B are etched by RIE. That is, the upper oxide film 66A, the nitride film 64B, and the lower oxide film 63B are separated in the bit line direction by etching using the resist 84 as a mask. As a result, a lower oxide film 63 and a nitride film 64 separated for each memory cell transistor are formed. In addition, an upper oxide film 66 and a word line 68 that continuously extend in the word line direction are formed.
[0030]
Next, as can be seen from FIGS. 8 and 9, after removing the resist 84, an interlayer insulating film 70 is formed thereon by CVD. Next, as can be seen from FIG. 8 in particular, contact holes 74 and 75 are formed in the interlayer insulating film 70 located on one end of the word line 68 by photolithography and RIE. Subsequently, a wiring layer made of aluminum or the like is deposited thereon by sputtering, and this wiring layer is etched by photolithography and RIE, whereby the word line wiring, the source line, and the bit line (all not shown). Form. Through the above steps, the nonvolatile semiconductor memory device shown in FIGS. 8 and 9 is obtained.
[0031]
As described above, according to the nonvolatile semiconductor memory device according to the second embodiment, in the ground cell array type nonvolatile semiconductor memory device, charges are accumulated near the interface between the different types of insulating films. A semiconductor memory device can be miniaturized. More specifically, in a conventional nonvolatile semiconductor memory device in which a floating gate is formed using a conductive member such as polysilicon, a capacitor C1 between the floating gate and the channel region, and between the control gate and the floating gate. Capacitance C2 occurs, and capacitive coupling occurs. In order to apply a sufficient voltage to the floating gate even if this capacitive coupling occurs, it is necessary to make the capacitance C2 larger than the capacitance C1 to some extent. For this purpose, it is necessary to form a large floating gate and increase the capacitance C2 generated between the floating gate and the control gate, which is an obstacle to reducing the distance between the memory cell transistors. In other words, the necessity of increasing the floating gate in this way has hindered miniaturization of the conventional nonvolatile semiconductor memory device. On the other hand, in the nonvolatile semiconductor memory device according to this embodiment, since the interface between the lower oxide film 62 and the nitride film 64 is used as the charge storage layer 60, each film of the stacked film The write / erase voltage can be suppressed by the thickness, and the distance between the memory cell transistors can be reduced. That is, the nonvolatile semiconductor memory device can be miniaturized.
[0032]
Further, as can be seen from FIG. 9, since the nitride film 64 in the charge storage layer 60 is separated for each memory cell transistor, the movement of charges held near the interface between the nitride film 64 and the lower oxide film 63 is prevented. be able to. Thereby, the data retention property with respect to aging and use in a high temperature state can be improved.
[0033]
In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible. For example, the charge storage layers 20 and 60 can be configured as a two-layer structure of the lower oxide films 23 and 63 and the nitride films 24 and 64. However, if the three-layer structure is used as in the present embodiment, the charges lost in the vicinity of the interface between the lower oxide films 23 and 63 and the nitride films 24 and 64 are transferred to the upper nitride films 24 and 64 and the upper oxide film. 26 and 66 can be captured in the vicinity of the interface.
[0034]
In FIG. 5 of the first embodiment, a resist 42 may be applied after an upper oxide film 26A is further deposited on the nitride film 24A. Similarly, in FIG. 13 of the second embodiment, a resist 82 may be applied after further depositing an upper oxide film 66A on the nitride film 64A. However, in both cases of the first and second embodiments, it is necessary to separately form an oxide film on the surface before depositing polysilicon for forming the word lines 30 and 68.
[0035]
Furthermore, in the above embodiment, the oxide film and the nitride film are used as the two or more types of insulating films, but the present invention is not limited to this. For example, the oxide film and polysilicon not doped with impurities are used. A combination may be used.
[0036]
【The invention's effect】
As described above, according to the nonvolatile semiconductor memory device of the present invention, the charge storage layer is formed by stacking two or more types of insulating films so that charges can be stored near the interface between the two or more types of insulating films. In addition, by forming at least one of these two or more types of insulating films separately for each memory cell transistor, the interface of the insulating film is separated from other adjacent memory cell transistors. Therefore, the data stored in the vicinity of the interface of the insulating film can be prevented from spreading to the range of other memory cell transistors, and data retention characteristics can be improved.
[Brief description of the drawings]
1A and 1B are a plan view and a cross-sectional view of a nonvolatile semiconductor memory device according to a first embodiment of the invention.
FIG. 2 is a perspective view of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
FIG. 3 is a circuit diagram of a nonvolatile semiconductor memory device having NAND type memory cell transistors.
FIG. 4 is a view showing a part of the manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
FIG. 5 is a view showing a part of the manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
FIG. 6 is a view showing a part of the manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
7 is a sectional view taken along line VII-VII in FIG.
FIG. 8 is a plan view of a nonvolatile semiconductor memory device according to a second embodiment of the invention.
9 is a cross-sectional view taken along the line IX-IX of the nonvolatile semiconductor memory device shown in FIG.
10 is a cross-sectional view taken along line XX of the nonvolatile semiconductor memory device shown in FIG.
FIG. 11 is a circuit diagram of a ground cell array type nonvolatile semiconductor memory device.
FIG. 12 is a view showing a part of the manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the invention.
FIG. 13 is a view showing a part of the manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the invention.
FIG. 14 is a view showing a part of the manufacturing process of the nonvolatile semiconductor memory device according to the second embodiment of the invention.
FIG. 15 is a perspective view of a conventional nonvolatile semiconductor memory device.
16A and 16B are a plan view and a cross-sectional view of a conventional nonvolatile semiconductor memory device.
[Explanation of symbols]
10 Semiconductor substrate
12 Device isolation region
20 Charge storage layer
22 Oxide film
23 Lower oxide film
24 Nitride film
26 Upper layer oxide film
30 word lines

Claims (4)

A non-volatile semiconductor memory device having a plurality of memory cell transistors arranged in a matrix in a row direction and a column direction,
Each of the memory cell transistors is
A charge storage layer formed by stacking two or more insulating films on a semiconductor substrate so as to be able to store electric charges in the vicinity of an interface between the two or more insulating films, wherein the two or more insulating films by separating a part of the insulating film of each said memory cell transistor, although the interface of the two or more insulating films are separated for each of the memory cell transistor, the remaining portion of the insulating film The charge storage layer is not separated , and
A word line formed on the charge storage layer for applying a voltage to the charge storage layer;
Source / drain regions formed on the semiconductor substrate surface side located on both sides of the charge storage layer,
The plurality of memory cell transistors arranged in the column direction are connected in series in the column direction so as to share the source / drain regions, and both ends of the plurality of memory cell transistors connected in series are connected to each other. Select transistors are connected continuously, and for each column, a NAND memory cell is configured,
Each of the word lines is formed continuously in the row direction so as to be commonly connected to the respective charge storage layers of the plurality of memory cell transistors arranged in the row direction.
A non-volatile semiconductor memory device. On the surface side of the semiconductor substrate between the columns of the plurality of NAND memory cells formed in the column direction, an element isolation region having the same conductivity type as the channel region and having an impurity concentration higher than that of the channel region Are formed in the column direction,
The nonvolatile semiconductor memory device according to claim 1. The charge storage layer is a stack of the two or more insulating films,
A lower oxide film formed on a semiconductor substrate and formed separately for each memory cell transistor;
A nitride film formed on the lower oxide film and formed separately for each memory cell transistor; and
The nonvolatile semiconductor memory device according to claim 2, further comprising: The charge storage layer is a laminate of the two or more insulating films,
An upper oxide film formed on the nitride film,
The nonvolatile semiconductor memory device according to claim 3, wherein the nonvolatile semiconductor memory device is provided.

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