JPH0194645A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent decrease of dielectric constant and leakage of current in a semiconductor device having a capacitor produced by a high dielectric layer containing an oxide of a transition metal, by interposing barrier films of a high-melting point metallic compound between a silicon electrode and the high dielectric layer. CONSTITUTION:In order to manufacture a semiconductor device in which a high dielectric layer 13 containing an oxide of a transition metal is interposed between two electrodes to produce a character and at least one of the electrodes is formed of silicon, barrier films 11, 12 and 14 of a compound of a highmelting point metal are interposed between the silicon electrode and the high dielectric layer 13. For example, a TiSi2 layer 11 is deposited on the silicon exposed surface of a region of a P-type semiconductor substrate 1 surrounded by an element isolating oxide film 8 to a thickness of 500Angstrom , and then a TiN film 12 is deposited also to a thickness of 500Angstrom . Subsequently, a Ta2O5 film 13 is deposited to a thickness of 100-1000Angstrom and then a polysilicon layer 15 is deposited thereon to a thickness of 4000Angstrom and doped with phosphorus.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a capacitor by sandwiching a high dielectric layer containing a transition metal oxide between two electrodes. The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor device is formed.

(Prior Art and Problems) As DRAM devices become smaller and more highly integrated, the area of memory cells is also reduced in accordance with the scaling law. This memory cell is constituted by a capacitor, and in order to prevent soft errors and secure a sense amplifier margin, the capacitor is required to have a minimum capacitance regardless of the reduction in the cell area. In order to reduce the cell area while maintaining this minimum capacity, the following measures have been conventionally taken.

(1) In a planar capacitor, the dielectric (usually an oxide film) forming the capacitor is made thinner.

(2) Dig a trench in the semiconductor substrate to form a trench capacitor.

(3) Form a stacked capacitor using a polyoxide film.

However, each of the above-mentioned means has the following problems.

(1) Current oxide film thinning technology is limited to a thickness of 60 to 70 people, whereas a DRAM with a storage capacity of 4 Mbits, for example, requires a capacity of 40 fF per cell; To ensure the capacity, a thickness of 20 to 30 people is required, which corresponds to the intrinsic dielectric breakdown limit of a silicon oxide film. Therefore, it cannot be applied to manufacturing RAMs with a storage capacity of 4 Mbit or more.

(2) In order to secure a capacitance of 40 fF with a trench type capacitor, even if the thickness of the oxide film is 100, the dimension of one side of the opening must be 0.8 to 1.0 μm, and the depth of the groove must be approximately 3 μm. Therefore, an aspect ratio of 3 to 4 is required. When the aspect ratio becomes large in this way, it becomes difficult to clean the inside of the groove using conventional techniques, leading to a decrease in reliability due to poor cleaning. In addition, the stress around the groove increases,
A leakage current flows through the substrate due to the occurrence of crystal defects. This problem becomes more serious as the degree of integration increases.

(3) Figure 6 shows the structure of a multilayer capacitor.

An impurity diffusion layer 2 is formed on a semiconductor substrate 1,
An oxide film 3 is deposited on this and three polysilicon layers 4, 5, 6 are buried therein. Further, a bit line contact electrode 7 is connected to one impurity diffusion layer 2 . Polysilicon layer 4 is used as a transfer gate, and polysilicon layers 5 and 6 constitute the picture electrode of the capacitor.

However, the thickness of the oxide film between the polysilicon layers 5 and 6 is limited to 200 to 300 mm with current technology. This is because forming an oxide film on polysilicon is technically more difficult than forming an oxide film on a single crystal substrate. However, for a DRAM with a capacity of 4 Mbits, an oxide film thickness of approximately 100 mm is required. Furthermore, since the thickness h of the polysilicon layer 5 in the figure is approximately 1 μm, the aspect ratio of the contact hole for the bit line contact electrode 7 reaches approximately 3, which requires sophisticated contact wiring technology.

As mentioned above, any of the means (1) to (3) can be applied to 4M
There are limits to the manufacture of DRAMs with a capacity greater than bits. Therefore, as a fourth method, increasing the dielectric constant of the dielectric material constituting the capacitor is attracting attention. This is an attempt to construct a capacitor serving as a memory cell by sandwiching a high dielectric constant layer made of an oxide of a transition metal such as Ta 2 O between two electrodes.

FIG. 7 shows an example of a capacitor using Ta205. An element isolation oxide film 8 is formed on the surface of the semiconductor substrate 1, and a capacitor is formed in a portion surrounded by the element isolation oxide film 8. That is, a Ta205 layer 9 serving as a high dielectric constant layer is sandwiched between a semiconductor substrate 1 serving as a lower electrode and an upper electrode 10 made of polysilicon or aluminum to form a capacitor.

Since the dielectric constant of Ta205 is considerably larger than that of S102, sufficient capacitance can be maintained even if the capacitor area is reduced.

However, the technology of configuring a capacitor using such a high dielectric layer has the following problems.
It has not yet been put into practical use. First of all, Ta205
When a transition metal oxide, such as The point is that it causes a decline.

Second, polysilicon is generally used for the upper electrode 10 because it has excellent processability, heat resistance, oxidation resistance, chemical resistance, etc., but this polysilicon reacts with transition metals. I have problem ability 5 of putting it away. for example,
It has been confirmed that when Ta 20 s is used as a high dielectric layer, the reaction 13Si+2Ta205 →4TaSi2+5SiO2 occurs, and the leakage current increases due to the generation of Ta512.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a manufacturing method that does not cause a decrease in dielectric constant or generation of leakage current in a semiconductor device having a capacitor using a high dielectric layer containing an oxide of a transition metal. .

[Structure of the invention]

(Means for Solving the Problems) According to the present invention, a capacitor is formed by sandwiching a high dielectric layer containing a transition metal oxide between two electrodes,
A method for manufacturing a semiconductor device in which at least one of the electrodes is made of silicon, in which a barrier film made of a high melting point metal compound is interposed between the electrode made of silicon and the high dielectric layer. It is.

(Function) According to the method of the present invention, since a barrier film made of a high melting point metal compound is inserted between the high dielectric layer and silicon, unnecessary chemical reactions do not occur, and the dielectric It is possible to prevent a decrease in efficiency and the occurrence of leakage current.

(Embodiments) First Embodiment The present invention will be described below based on illustrative embodiments. 1st
The figure shows TEG (
FIG. 2 is a cross-sectional view showing the structure of an example of a Test Element Group (Test Element Group) capacitor. First, an element isolation oxide film 8 is formed on a P-type semiconductor substrate 1 made of silicon, and a capacitor is formed in a portion surrounded by this element isolation oxide film 8. TiSi2 as a high melting point metal compound is applied to the silicon exposed surface of this capacitor formation region.
By high-speed sputtering method using an alloy target, Ti5
12 layers 11 are deposited to a thickness of 500 people. Thereafter, using the same sputtering equipment, a TiN film 12 with a thickness of 500 nm was formed by chemical sputtering using nitrogen and argon plasma.
Continuously deposit a person's thickness. Next, Ta was deposited by chemical sputtering using oxygen and argon plasma.
205 film 13 is deposited to a thickness of 100 to 1000 layers. At this time, the target is, for example, 6N Ta.
You can use a target. Thereafter, a TiN film 14 is deposited to a thickness of 500 nm using the same method as described above, and a polysilicon layer 15 is further deposited on top of it to a thickness of 400 nm using the LPCVD method.
Deposits to a thickness of 0 people.

Thereafter, phosphorus was doped into the polysilicon layer 15 at 900°C for 30 minutes in a POCl3 atmosphere, resist buttering was performed to form the capacitor upper electrode, and BCl3 gas was applied using this as a mask. RIE used
Etching is carried out to simultaneously etch away layers 1.1-15, resulting in a structure as shown in FIG. In this embodiment, the effective area of one capacitor is approximately 1-.

Effects of the First Example FIG. 2 is a graph showing the relationship between the film thickness and dielectric constant of the Ta205 layer. Here, curve A is data for a capacitor manufactured by the conventional method having the structure shown in FIG. 7, and curve B is data for a capacitor manufactured by the method according to the present invention having the structure shown in FIG. This is data about capacitors. As shown in curve A, the dielectric constant of the conventional device decreases as the film thickness decreases. As mentioned above, this is a semiconductor substrate made of silicon and a TaO
This is because an S t 02 film is generated at the interface between the layers. On the other hand, in the device according to the present invention, as shown in curve B, there is no decrease in the dielectric constant as the film thickness decreases, and the bulk dielectric constant value of T a 20 s ~ 25 was gotten.

FIG. 3 is a graph showing the relationship between applied voltage V and leakage current ■ for a capacitor having a Ta205 layer with a thickness of 200 mm. Both data are measured by applying a negative voltage to the upper electrode side. Here, curves A and B are data for a capacitor manufactured by a conventional method having the structure shown in FIG. . On the other hand, curve C is shown in Figure 1 (1
This is data on a capacitor manufactured by the method according to the present invention having a structure of 11. It can be seen that leakage current is also suppressed by the method according to the present invention.
This is because the reaction between a205 and polysilicon or aluminum constituting the upper electrode was blocked by the barrier film.

Second Embodiment Next, an embodiment in which the present invention is applied to the manufacture of an actual DRAM memory cell will be described with reference to the process diagram of FIG. 4. First, an oxide film 8 for element isolation is formed on a semiconductor substrate 1 made of silicon using a known planar method, and then a first diffusion layer 16, a second diffusion layer 17, a silicon oxide film 18, An LDD structure MOS transistor having a polysilicon gate 19 is formed. The first diffusion layer 16 is formed by ion implantation of phosphorus, and the second diffusion layer 17 is formed by ion implantation of As. The state up to this point is shown in FIG. 4(a).

Next, a Ti film of about 800 layers was deposited on the element area by sputtering using self-alignment, and then heated at 650°C for 2 hours.
Annealing was performed for 0 seconds in a nitrogen atmosphere to cause the silicon on the substrate to react with Ti to form a TiSi film 20, and the Ti on the silicon oxide film 18 was removed using a mixed 22° solution of HONHOH and H2O. Remove by boiling. The state up to this point is shown in FIG. 4(b).

Thereafter, annealing is performed at 900° C. for 20 seconds in an NH3 atmosphere to form a two-layer structure of a TiSi film 20 film type 0512 film 21 (lower layer) and a TiN film 22 (upper layer). In this example, when the thickness of each film was measured using the RBS method, the thicknesses were 700 and 300, respectively. The state up to this point is shown in FIG. 4(e).

Subsequently, as in the first embodiment, a Ta205 film 23 is deposited to a thickness of 200 nm by chemical sputtering.

The closed state is shown in FIG. 4(d).

Next, a TiN film 24 is deposited to a thickness of 500 nm by chemical sputtering, and a polysilicon layer 25 is deposited thereon to a thickness of 4000 nm by LPCVD. The state up to this point is shown in FIG. 4 ((1)).

Furthermore, after placing it in a POCl3 atmosphere at 900° C. for 30 minutes and doping phosphorus into the polysilicon, resistor patterning was performed to form the upper electrode of the capacitor.
Using this resist as a mask, R
Remove layer 24.25 by IE etching. The state up to this point is shown in FIG. 4(f).

Finally, As ion implantation was performed at an ion acceleration voltage of 16 keV.
, carried out under the conditions of ion density I x 10 "am-',
A heavily doped diffusion layer 26 of a transistor having an LDD structure is formed. The state up to this point is shown in FIG. 4(g). After this, an insulating film is covered by a known process, and the diffusion layer 2 is
Perform wiring to 6.

By performing the manufacturing process as described above, the Ta205 film 23 is sandwiched between the TiN films 22 and 23, and reaction with the silicon substrate 1 or the polysilicon layer 25 is prevented.

Effects of the second embodiment In this second embodiment, as well as in the first embodiment described above,
The dielectric constant is approximately 25 regardless of the film thickness, and the third
A leakage current characteristic as shown by curve C in the figure was obtained.

FIG. 5(a) is a top dimensional diagram showing the positional relationship in the vicinity of the transfer gate of one memory cell of the DRAM manufactured according to the second embodiment. Here, the polysilicon gate 19 has a width L1-1.0 μm and a length L2-15 μm. FIG. 5(b) is a side sectional view of this device, in which a contact hole 28 is opened in the protective insulating layer 27, and two wirings made of aluminum are provided therein. Figure 5(a)
As shown in , the distance between the polysilicon gate 19 and the contact hole 28 is L3-20μm1 on the source side.
On the drain side, the opening size of the contact hole 28 was L5-11.2 μm.

In this transfer gate, a Ti512 layer 21 and a TiN layer 22 are formed on the source/drain QRFd, as shown in FIG. 5(b). These layers contribute to reducing the layer resistance of the diffusion layers constituting the source and drain, and also contribute to reducing the contact resistance in fine contacts due to the barrier metal effect. In fact, in the semiconductor device according to this embodiment, the drain and gate voltages are set to 5V.
When the drain current value was measured with the substrate voltage set to -3V, it was confirmed that the drain current value increased by 20 to 30% compared to the conventional device. This is mainly due to the effect of reducing the parasitic resistance in the source side diffusion layer. When the layer resistance of the diffusion layer was measured, it was confirmed that while it was 50Ω in the conventional device, it was improved to 3 to 5Ω in this example. Further, the contact resistance with the wiring layer 29 is 1Xl in the conventional device.
While a variation of 0' to 5 x 10' Qc- was observed, in this example the resistance value decreased to 3 x 10 to 5 x 10' Ωcj, and good contact was obtained and the variation was also reduced.

Other Examples (+) In the above example, Ta20 is used as the high dielectric layer.
Although an example using Hf OZ r
In short, any acid 2' oxide of a transition metal, such as O2, may be used. Further, a composite material such as Ta205T102 may be used, or Ta205 with impurities such as Ti and St may be used (these composite materials and added impurities reduce leakage current and increase the dielectric constant). (has an increasing effect). In addition, as a biofilm method, we used a chemical sputtering method to
5 film was formed, but other methods such as thermal oxidation method of Ta sputtered film, RF using Ta205 target
A sputtering method, a CVD method, or the like may be used.

(2) In the above embodiment, a planar capacitor is formed on a single-crystal silicon substrate, but the present invention is similarly applicable to a case where a trench-type capacitor is formed on a single-crystal silicon substrate. The same applies to the case where a multilayer capacitor using polysilicon as a substrate is formed. Furthermore,
The upper electrode may be made of not only polysilicon but also other metals or their silicides (W, Mo, Tt, ws i
x.

MoSix, TiSix, etc.) may also be used.

(3) The biofilm method for forming a high melting point metal compound to become a barrier film is not limited to the chemical sputtering method. For example, if a film of a high melting point metal nitride is to be made, the high melting point metal or its silicide film is coated with N2. NF3. Alternatively, a method may be adopted in which high-temperature heat treatment is performed in an atmosphere such as NH3 and direct nitridation is performed.

(4) As the barrier film, we have shown an example using TiNs, that is, a metal nitride film, but a carbide film such as TiC,
A boride film such as TiB may also be used.

(5) In manufacturing the DRAM memory cell in the second embodiment, the TiN/TiSi2 film was formed by a self-alignment method using a salicide process. After being deposited over the entire surface, it may be removed by PEP and dry etching, leaving only the required areas. In this case, there is no problem even if the TiN/T iS i 2 region extends to the region where the element isolation oxide film or the oxide film on the transfer gate is formed.

〔Effect of the invention〕

As described above, according to the present invention, a capacitor is formed by sandwiching a high dielectric layer containing a transition metal oxide between two electrodes, and a semiconductor device in which at least one of the electrodes is made of silicon. In the method of manufacturing,
Since a barrier layer made of a high melting point metal compound is interposed between the electrode made of silicon and the high dielectric layer, a decrease in dielectric constant and generation of leakage current can be suppressed.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device manufactured by the method according to the present invention, FIG. 2 is a graph showing the effect of suppressing a decrease in dielectric constant in the method according to the present invention, and FIG. 3 is a graph showing leakage in the method according to the present invention. A graph showing the current suppression effect, FIG. 4 is a process diagram of an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 5 is a diagram showing the vicinity of the transfer gate of a DRAM manufactured by the method shown in FIG. 4. , FIG. 6 is a structural cross-sectional view of a conventional multilayer capacitor, and FIG. 7 is a structural cross-sectional view of a conventional capacitor using a high dielectric layer. 1... Silicon semiconductor substrate, 2... Impurity diffusion layer,
3... Oxide film, 4.5.6... Polysilicon layer, 7
... Bit line contact electrode, 8... Oxide film for element isolation, 9... Ta 206 layer, 10... Upper electrode, 1l-TiSi layer, 12- TiN film, 13-
Ta205 film, 14... TiN film, 15... polysilicon layer, 16... first diffusion layer, 17... second diffusion layer, 18... silicon oxide film, 19... Polysilicon gate, 20...TiSi film, 21...Ti
Si2 film, 22...TiN film, 23-Ta205 film,
24-T1. N film, 25... Polysilicon layer, 26
...High concentration diffusion layer, 27...Protective insulating layer, 28...
・Contact hole, 29...aluminum wiring. Applicant's agent Sato -Yu

Claims (1)

[Claims] 1. Manufacturing a semiconductor device in which a capacitor is formed by sandwiching a high dielectric layer containing a transition metal oxide between two electrodes, and at least one of the electrodes is made of silicon. 1. A method for manufacturing a semiconductor device, comprising the step of interposing a barrier film made of a high melting point metal compound between the electrode made of silicon and the high dielectric layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the high dielectric constant layer is formed of a transition metal oxide such as Ta_2O_5, HfO_2, or ZrO_2. 3. The high dielectric constant layer is formed using a transition metal oxide chemical sputtering method;
3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by an RF sputtering method, a CVD method, or a transition metal thermal oxidation method. 4. Manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the barrier film is formed of a high-melting point metal nitride, silicide, carbide, or boride. Method. 5. The method of manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that the barrier film is formed by chemical sputtering of a high-melting point metal compound. 6. Any one of claims 1 to 4, characterized in that the barrier film is formed by subjecting a high-melting point metal or its silicide to high-temperature heat treatment in an atmosphere containing nitrogen or nitride. A method for manufacturing a semiconductor device according to . 7. A high melting point metal film or a high melting point metal silicide film is formed on the semiconductor substrate, a barrier film made of a high melting point metal compound is formed on this, and a high dielectric film containing a transition metal oxide is further formed on top of this. 7. The method of manufacturing a semiconductor device according to claim 6, further comprising forming a body layer.