TW541430B - Test device for semiconductor wafers - Google Patents

Test device for semiconductor wafers Download PDF

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Publication number
TW541430B
TW541430B TW89117199A TW89117199A TW541430B TW 541430 B TW541430 B TW 541430B TW 89117199 A TW89117199 A TW 89117199A TW 89117199 A TW89117199 A TW 89117199A TW 541430 B TW541430 B TW 541430B
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TW
Taiwan
Prior art keywords
test
contact
semiconductor substrate
pin
test signal
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Application number
TW89117199A
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Chinese (zh)
Inventor
Susumo Kondo
Original Assignee
Advantest Corp
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Publication of TW541430B publication Critical patent/TW541430B/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31903Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191Calibration
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2882Testing timing characteristics
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511Wafer Test
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505Test of Modular systems, e.g. Wafers, MCM's

Abstract

A test device for semiconductor wafers is to send a plurality of test signals to the component portion formed from wafers and to determine if the component portion is good or defective based on test results. The test device for semiconductor wafers comprises: a plurality of needles electrically contacting with the component portion; a probe card with a grounding portion disposed on its main surface at the vicinity of the needle; a contact portion electrically contacting the needle; and a wafer for test with a needle disposed on its main surface electrically contacting the grounding portion.

Description

541430 五、發明說明(1) 發明所屬技術領域 本發明係有關於用以測試製入了半導體積體電路元件 等之半導體基板(以下代表性的稱為晶圓)之半導體基板測 試裝置,尤其係有關於可高精度的量測自測試器本體送出 之測試信號之波形。 習知技術 半導 複數後, 子元件。 试在完成 尤其 BGA(Bal1 為普及, 因此 在測 上’例如 半導體基 之晶圓後 之接點接 可是 試頭向I C 號。例如 異種之測 計頻率之 肢檟脰電路元件係在矽晶圓或玻璃板等基板製作 經由切割、打線以及封裝等各製程完成,作為電 這種IC組件在出貨前進行動作測試,但是這種測 品之狀態或是晶圓之狀態都進行。 近年來,隨著半導體製造技術之進展,採用了如 Grid Array)型1〇組件之晶片尺寸封裝之 在件:在晶圓之狀態封t,然後切:廣 1曰^圓之^態進行組件之動作測試的不少。 ^ : I : 5 tlC組件之半導體基板測試裝置 巳知在實開平5〜1 ^ 4 cm Α &罝 板測試裝置,藉著曰二A艮所公開的。在這種 ’令設於探測卡之二真空吸附係被測試件 觸,進行測試。(針狀接點)和在晶圓所製入 之動作測試時,自測試器本體^ ’送出圖4所示之測試J種”之既定之測試信 組件測試,-般在實際:二因無法進行在高時 “式刚硯測圖4所示之測541430 V. Description of the invention (1) Technical field of the invention The present invention relates to a semiconductor substrate testing device for testing a semiconductor substrate (hereinafter referred to as a wafer) in which a semiconductor integrated circuit element and the like are incorporated. It can measure the waveform of the test signal sent from the tester body with high accuracy. Known Techniques Semiconducting complex numbers, subcomponents. The test is completed especially BGA (Bal1 is popular, so when testing 'such as semiconductor-based wafers, the contact point can be the test head to the IC number. For example, the limb circuit components of different kinds of frequency measurement are on silicon wafers. The production of substrates such as glass plates is completed through various processes such as dicing, wire bonding and packaging. IC components such as electricity are tested for operation before shipment, but the state of this test product or the state of the wafer is performed. In recent years, With the development of semiconductor manufacturing technology, wafer-sized packages such as Grid Array) type 10 components are used in the package: sealed in the state of the wafer, and then cut: the state of the circle to test the operation of the module A lot. ^: I: 5 tlC semiconductor substrate test device. Known in real Kaiping 5 ~ 1 ^ 4 cm Α & 板 board test device, disclosed by the two Agen. In this way, the vacuum suction system provided on the probe card is touched and the test is performed. (Needle contact) and during the test of the operation of the wafer, self-tester ^ 'send out the test letter J test shown in Figure 4' as the test module assembly,-generally in practice: two reasons can not Perform the test shown in Figure 4 at high time.

2〇30-3398-?F-ptd 試信號a 'b發生相=,號b Q這種 541430 五、發明說明(2) 試信號之波形,藉此進行兩測試信號之相位修正。 在稱為處理裔之以係成品之I C組件為測試對象之測試 裝置,一般藉著將波形觀測用之示波器和測試頭之觸腳連 接進行相位修正,但是測試頭之觸腳和接地點(接地、 GND)遠離時’在向示波器輸出之波形混入雜訊等,無法得 到正確之波形。例如,如圖5所示,對於正常之波形X,觀 測到,波形y或波形z之波形。因而,若在觸腳之附近有接 地點就,用之,若在附近無接地點就另外設置接地基座。 ,可是,在以晶圓為測試對象之半導體基板測試裝置, 相當於處理器之觸腳之針因以1 50 // m之窄間隔排列,在針 之附近δ又置接地點係極困難。 #因而,使用以比較寬之間隔配置之探測卡之配線圖案 4等觀’則測忒化號之波形,但是在這種方法,因不是觀 側輸入晶圓之名且件$垃上 1 >士、# 口备士 细夕# # A 4件之接點之測试指號本身,而是將遠離那 ”、、乍為輪入部量測測試信號之波形,在 之正確性有問題。 T行q及办 發明之概述 =日i之目的在於提供一種半導體基板測試装置,可 = 測自測試器本體送出之測試信號之波形等之信 測古ϋ依Λ本發明之第一形態’提供一種半導體基板 信號後測試體基板所形成之組件部送出複數測試 板測試襄置包括^果判別組件部之好壞’該半導體基 第一針狀接點’在電氣上和組件部接2〇30-3398-? F-ptd The phase of the test signal a 'b == b Q 541430 V. Description of the invention (2) The waveform of the test signal is used to correct the phase of the two test signals. In a test device called a processing IC that uses a finished IC component as a test object, the phase correction is generally performed by connecting the oscilloscope for waveform observation and the contact pins of the test head, but the contact pins of the test head and the ground point (ground , GND) When far away, noise is mixed into the waveform output to the oscilloscope, and the correct waveform cannot be obtained. For example, as shown in Fig. 5, for a normal waveform X, a waveform of a waveform y or a waveform z is observed. Therefore, if there is a contact point near the contact pin, use it. If there is no ground point near the contact point, another grounding base is provided. However, in a semiconductor substrate testing device that uses a wafer as a test object, the pins corresponding to the pins of the processor are arranged at a narrow interval of 1 50 // m, and it is extremely difficult to set a ground point near the pins δ. #Thus, using the wiring pattern 4 and the like of the probe card arranged at a relatively wide interval to measure the waveform of the number, but in this method, because it is not the name of the input wafer on the viewing side and the number of pieces is $ 1 > 士, # 口 备 士 细 夕 # # A The test sign of the contact point of the 4 pieces, but it will be far away from that ", at first, the waveform of the test signal measured by the turn-in department, there is a problem in its correctness. T line q and the summary of the invention = The purpose of the day i is to provide a semiconductor substrate testing device that can measure the waveform of the test signal sent from the tester body and so on. The test method is provided by the first form of the present invention. A semiconductor substrate signal is sent to a component part formed by a test body substrate to send a plurality of test boards for testing. The test set includes determining whether the component part is good or bad, 'the semiconductor-based first needle contact' is electrically connected to the component part.

2030-3398-??.ptd 第5頁 M14302030-3398-??. Ptd Page 5 M1430

五、發明說明(3) 觸;探測卡,在1 u 在其一主面設 之接地部,在雷畜 ..,,在電上和測試 .+,觸,以及量測用晶 和接,部接觸之第二針狀接 本發明,該量測用晶 :點與接地部之排列具有構 接點與接觸部更好。 又在本發明,最好還包 測用晶片相對於該探測卡之 此外,在本發明,最好 f基板並令該組件部和該探 量測用晶片設於該基板工作 在本發明,也可還包括 用晶片之輪出端子連接,並 在本發明之測試信號之 列舉測試信號之信號波形。 (2) 若依據本發明之第二 測試裝置用探測卡,在電氣 試頭基板連接,且在一主面 之組件部接觸之複數針狀接 設置接地部。 在本發明,該接地部係 地部或者和複數針狀接點共 (3) 若依據本發明之第二 置設於該第一針狀接點之附近 頭基板連接,接觸部,在電氣 片’在其一主面設置在電氣上 點。 、 片按照該探測卡之該第一針狀 成一對或一對以上之第二針狀 括里測用晶片工作台,令含亥量 第一針狀接點與接地部移動。 還包括基板工作台,保持半導 測卡之第一針狀接點接觸,該 台。 L 5虎特性1測裝置,和該量測 輪出該測試信號之特性。 特性未特別限定,但是例如可 1形態,提供一種半導體基板 上和半導體基板測試裝置之測 設置了在電氣上和半導體基板 點’其中在該針狀接點之附近 對於一個針狀接點設置一個接 同設置都可。 1形態,提供一種半導體基板V. Description of the invention (3) Touch; probe card, grounding part on 1 u on one of its main faces, on the thunder animal .., on electricity and test. +, Touch, and measuring crystal and connection, The second needle-like connection of the contact of the present invention is better. The arrangement of the measuring crystal: the point and the grounding portion has a structured contact point and a contact portion. In the present invention, it is preferable that a test wafer is provided with respect to the probe card. In the present invention, it is preferable that the substrate and the module and the measurement wafer are provided on the substrate to work in the present invention. It may further include a signal waveform of a test signal which is connected with a wheel-out terminal of a chip and enumerated in the test signal of the present invention. (2) If the probe card for the second test device according to the present invention is connected to the base board of the electric test head, and a plurality of pins are connected in contact with the component part on a main surface, a ground part is provided. In the present invention, the grounding part is a ground part or a plurality of pin contacts. (3) If the second substrate according to the present invention is connected to the head substrate near the first pin contact, the contact part is connected to the electrical chip. 'Electric point is set on one of the main surfaces. According to the first needle shape of the probe card, the wafers form a pair or more of the second needle shape, including the wafer table for measuring, so that the first needle contact and the grounding portion with a high content are moved. It also includes a substrate table, which holds the first pin contact of the semi-conductive card, and this table. L 5 Tiger characteristic 1 measurement device, and the characteristics of the test signal from the measurement wheel. The characteristics are not particularly limited, but for example, it is possible to provide a semiconductor substrate test device and a semiconductor substrate test device in one form. The electrical and semiconductor substrate points are provided. One of the needle contact points is provided near the needle contact point. Follow the settings. 1 form, providing a semiconductor substrate

^1430 五、發明說明(4) :ΐϋ之量測用晶片’包括:接觸㉝,在電氣上和設於 …探測卡之第-針狀接點接觸;及第 地部接觸。電軋上和設於該第一針狀接點之附近之接 板測依之據二二明,第四形態,提 所形成之ΐ:! ΐ號特性之量測方法,向在半導體基板 別該組件部出;,信號後測試,按照其結果判 組件部接觸之部^之^以和該半導體基板測試裝置之該 性。 刀 夕附近為接點,量測測試信號之特 可列舉=號“特性未特別限定,但是例如 送測i i ί:針:ί:f基板測試裝置具有向該組件部傳 部,將這些針狀=:設於該針狀接點之附近之接地 之特性更好。 /、妾地部作為輸入部量測該測試信號^ 1430 V. Description of the invention (4): The wafer for measuring radon 'includes: contact radon, which is in electrical contact with the-pin contact provided on the ... detection card; and the ground contact. According to the second form, the fourth form, the measurement of the splicing plate on the electric rolling and the vicinity of the first needle-shaped contact is provided. The component part is tested after the signal. According to the result, the part contacting the component part ^ is determined to be the same as the semiconductor substrate test device. The vicinity of the knife is a contact point, and the measurement test signal can be specifically listed as "No." The characteristics are not particularly limited, but for example, send the test ii: pin: ί: f The board test device has a transmission part to the module part, and these needles are shaped like =: The grounding characteristics near the pin contact are better. / 、 The ground part is used as the input part to measure the test signal.

在上述之發明,>BT 半導體基板之前或者=2係測試對象之晶圓或玻璃基板等 狀接點、量測用B曰只'、忒之途中,令量測用晶片之第二針 探測卡之第一針::3觸部各自接觸探測卡之接地部、 測用晶片之第二針妝拉後,在此狀態送出測試信號。在量 之半導體基板之組件i點與接觸部輸人和輸人係測試對象 波器等信號特性量洌::=相同之測試信號,將其向示 同等之電氣環境量、%置輸出。因此,可在和實際之測試 …測剛試信號之特性,量測結果之可靠性Before the above invention, > BT semiconductor substrate or = 2 series of test objects such as wafers or glass substrates, etc., the measurement B is only used, and on the way, the second pin of the measurement wafer is detected. The first pin of the card :: The 3 contact parts are in contact with the ground part of the probe card and the second pin of the test chip, and the test signal is sent in this state. The signal characteristics of the input device and the input device of the semiconductor substrate at the point i of the component and the input of the test object are as follows: The same test signal is output to the same amount of electrical environment. Therefore, you can test the actual signal… and test the characteristics of the test signal, and the reliability of the measurement result.

2030-3398-FF-ptd 第7頁 541430 五、發明說明(5) 顯著提南。又,因在本發明在探測卡 近設置接地部’在自接地部經由 接點之% 號混入雜訊等之可能性也極小。 aa片侍到之挪軾信 對探測卡之各針狀接點或幾個之“ 這種量測,因而令量測用晶片移至各、—各、、且(對)進行 量測用晶片設置複數對第二針狀—針狀接點。若在 測向複數第-針狀接點各自測^ =部’可同時量 全部之第-針狀接點之量測時間。』,號’可縮短對於 設置了一對或少數對第二針狀接點盥2 ’在對量測用晶片 示波器等信號特性量測裝置之電甓符ί觸部之情況’對於 」,藉著在半導體基板: = a 專用之工作台裝置, ^用曰曰片’不需要量測用晶片 圖式簡單說明 在費用上空間上都有利。 為讓本發明之上 懂,下文特舉較佳每=、、特徵、和優點能更明顯易 如下: 佳…列,並配合所附圖式,作詳細說明 圖1係表示本發明 圖2係表示圖丄之主道千触'體&板測試裝置之整體圖。 面圖。 導體基板測試裴置之主要部分之剖 圖3係表示圖1之 B 4 # ^ ^ a τ p衣測卡之平面圖。 ^ 衣不自1(:測試裝置(測嚐哭士 號之一例之波形圖。 減π本體)輸出之測試信 圖5係用以說明太 本發明之課題之波形圖。 § 2030-3398-PF-ptd 5414302030-3398-FF-ptd Page 7 541430 V. Description of the invention (5) Significantly raise the South. Further, in the present invention, since a grounding portion is provided near the detection card, the possibility of mixing noise or the like through the% number of the contact from the grounding portion is extremely small. The aa tablet sent the letter to each pin-shaped contact or several of the probe card for this measurement, so the measurement wafer was moved to each, each, and (for) the measurement wafer. Set a plurality of pairs of second needle-needle contacts. If you measure each of the multiple needle-needle contacts in the direction of measurement ^ = section 'You can measure all the first needle-like contacts at the same time.', No. ' It is possible to shorten the time when the pair of second pin contacts are provided, or the number of contact points of a signal characteristic measuring device such as a chip oscilloscope for measurement. : = A Dedicated workbench device, ^ said "chip", no need to measure the wafer pattern, simple explanation is advantageous in terms of cost and space. In order to make the present invention understandable, the following enumerations are preferred, features, and advantages can be more obvious and easy as follows: Good ... column, and in accordance with the accompanying drawings for detailed description, FIG. 1 shows the present invention, FIG. 2 The overall view of the main body of the touch panel & board test device shown in FIG. Face view. Sectional view of the main part of the conductor substrate test Pei Zhi FIG. 3 is a plan view showing the B 4 # ^ a τ p clothing test card of FIG. 1. ^ Yi Bu Zi 1 (: waveform diagram of a test device (testing example of the Weeping Sword. Minus π body) output test letter Figure 5 is a waveform diagram for explaining the subject of the present invention. § 2030-3398-PF -ptd 541430

五、發明說明(6) 發明之實施例 侧之量測用晶片3 5 在圖3表示2個量測用晶片,但是 係將左側之量測用晶片翻面表示之圖 如圖1所示,本實施例之半導體基板測 :器本體Η 出測試信號後測試;測試頭2 0衣:由J: 寺和m式為本體10連接;以及探針3〇 二 之晶圓w並令逐次移動成令測試頭20之 式件 在該晶圓w所製入之複數組件部。 接.,,、έ)接觸 、,在探針30,係被測試件之晶圓w係在_片 多半導體電路(組件部)的,在測試之情況被晶圓吸嘴^ ^ 略圖示)真空吸附,保持在高精度之位置對準狀口態。因 :板3曰曰;於晶圓工作台31 ’該晶圓工作台;相對於 底板32可在圖1所不之χγ平面内高精度的移動,又,Β曰 工作台31整體或只有晶圓吸嘴可在ζ軸方向升降。 —一此外,雖省略圖示,在對晶圓W施加既定之溫度後進 行高溫測試之情況’經由内裝於晶圓吸嘴之加熱器又 W加熱。 μ 在本貝施例之探針3 0,在晶圓工作台3 1上部設置 卡夾具3 3,在此保持探測卡3 4。本例之探測卡3 4具有由陶 竟或石夕構成之形成矩形之基板341,在其一主面(在圖1、2 $下面,在圖3為表面)設置複數針342 (相當於本發明之第 。針狀接點),如圖3所示排成複數列配置。又,在基板 〕41之相同之主面,在針342之列之間形成和地線連接之接 地部343之圖案。5. Description of the invention (6) The measurement wafer 3 on the side of the embodiment of the invention 5 Fig. 3 shows two measurement wafers, but the figure on the left side of the measurement wafer is shown in Fig. 1, The semiconductor substrate test of this embodiment: the device body test after the test signal; test head 20: connected by J: Temple and m-type for the body 10; and the wafer w of the probe 302 and sequentially moved into The test head 20 is placed in a plurality of component parts made in the wafer w. Then ,,,, and) contact, at the probe 30, the wafer w being tested is in a _chip multi-semiconductor circuit (assembly part), and is tested by the wafer suction nozzle in the case of testing ^ ^ ) Vacuum suction, keep the alignment state in high precision position. Because: plate 3 is said; on wafer table 31 'the wafer table; relative to the bottom plate 32 can be moved with high accuracy in the χγ plane not shown in Fig. 1, and B is the whole or only table 31 The circular nozzle can be raised and lowered in the z-axis direction. -In addition, although the illustration is omitted, a case where a high temperature test is performed after a predetermined temperature is applied to the wafer W 'is heated by a heater built in the wafer suction nozzle. μ In the probe 30 of this embodiment, a card holder 3 3 is set on the upper part of the wafer table 31, and a detection card 34 is held here. The detection card 34 of this example has a rectangular base plate 341 made of Tao Jing or Shi Xi, and a plurality of pins 342 (equivalent to this Invention No .. Needle-shaped contacts) are arranged in a plurality of rows as shown in FIG. 3. On the same main surface of the substrate 41, a pattern of a ground portion 343 connected to the ground is formed between the rows of the pins 342.

541430 五、發明說明(7) 針3 4 2如和在晶圓w聚集形成之一個組件部之端子(打 線前之狀態之接點)接觸般例如直立設置,藉著在χγζ空間 内令逐次移動上述之晶圓工作台31,可接觸應測試之組件 部之各端子。 又,本實施例之探測卡34在基板341之反側之主面(在 圖1、2為上面,在圖3為背面)組裝由零插拔力連接器等構 成之連接之一方344。 此外,零插拔力連接器(Zer〇 Inserti〇n F(D:ree Connector)意指在和設於後述之測試頭2〇側之另一方之零 插拔力連接器22 1相插拔時不必在插拔方向施力之型式之7 連接f,可使用例如利用缸令驅動在縱向組入連接^内之 2道前後移動,令和執道卡合之凸輪上下動作,利用該凸 輪之上下動作擴大縮小夾住觸腳之插座觸片之間隔之方 式,或別的方式。 f針342和零插拔力連接器344之各接點利用在探測卡 土板341上所形成之配線圖案或通孔(都省略圖示 電軋上連接。 此外,在本發明之半導體基板測試裝置,在電氣 接探測卡34和測試頭20之裝置未口限定矣卜.+、 : f* 妾™,係別的種類之連接器或連接端子也無任何問題。 ,’半導體基板測試裝置i之測試聊位於晶圓工作 〇产上部’雖省略圖*,在此設置性能板等各種基板。 f該測試頭20之最下面如圖!與圖2所示固定頂面板 遇在该頂面板21之下面固定接觸環22。又,在該接觸541430 V. Description of the invention (7) The pin 3 4 2 is set upright, for example, in contact with a terminal (a contact point in a state before wire bonding) of an assembly part formed on the wafer w, and is sequentially moved in the χγζ space. The wafer table 31 described above can contact each terminal of the component part to be tested. In addition, the probe card 34 of this embodiment is assembled on the opposite side of the substrate 341 (tops in Figs. 1 and 2 and back in Fig. 3) with one of the connections 344 consisting of a zero insertion force connector and the like. In addition, Zero Insertion Force Connector (Z: Zero Insertion F (D: ree Connector) means that when inserting and removing 1 phase with the Zero Insertion Force Connector 22 on the other side of the test head, which will be described later, on the 20 side. It is not necessary to apply the connection type 7 of the type 7 in the direction of insertion and removal. For example, the cylinder can be used to drive the 2 forward and backward movements in the vertical connection ^ to move the cam engaged with the track up and down. The method of expanding or reducing the interval between the socket contact pieces that pinches the contact pins, or other methods. Each contact of the f-pin 342 and the zero insertion force connector 344 uses a wiring pattern formed on the detection card soil plate 341 or Through-holes (both are omitted for connection on the electric rolling. In addition, in the semiconductor substrate test device of the present invention, the device for electrically connecting the probe card 34 and the test head 20 is not limited. +,: F * 妾 ™, system There are no problems with other types of connectors or connection terminals. "The test chat of the semiconductor substrate test device i is located on the wafer work and the upper part of the production" Although the figure * is omitted, various substrates such as performance boards are installed here. F This test head The bottom of 20 is shown in figure! In this case the top plate 21 of the stationary panel following contact ring 22. Also, the contacting

541430 五、發明說明(8) — 環22固定上述之零插拔力連接器之另一方221。纟圖2之剖 面圖表不該零插拔力連接器221、344之安裝狀態。 。 此外,雖然省略詳細之圖示,上述之探測卡34和接 ί哀22之位置對準係藉著令設於探測卡34側之 觸環22之導襯卡合等進行。 又、接 又,設於接觸環2 2側之零插拔力連接器2 2 J和測試頭 20内之性能板利用多條配線或子板在電氣上連接。 尤_其在本實施例之探針30,圖3所示量測用晶片35如 圖2所不朝上的設於晶圓工作台31之凸緣311。該量測用晶 片35具有和探測卡34之基板341相同之由陶瓷或矽構成之 基板351,在該基板351之一主面(在圖i、2為上面,在圖3 之左圖為下面,在圖3之右圖為上面)形成一支針352(相當 於本啦明之第二針狀接點)和與地線連接之一個接觸部3 5 3 之圖案。這些針3 5 2和接觸部3 5 3之間隔設成與上述之探測 卡3 4之針3 4 2和接地部3 4 3之間隔大致相等,如圖2所示, 令ΐ測用晶片35接近探測卡34之一對針342與接地部343 日守,1測用晶片之接觸部3 5 3、探測卡3 4之針3 4 2分別同時 接觸探測卡34之接地部343、量測用晶片35之接觸部353。 此外,量測用晶片35之針352與接觸部353如圖3之右 圖所示,經由電纜等和示波器40連接,觀測該所量測之測 試信號之波形。 其次說明作用。541430 V. Description of the invention (8) — The ring 22 fixes the other side 221 of the zero insertion force connector described above. (2) The cross-sectional diagram of FIG. 2 is not the installation state of the zero insertion force connectors 221 and 344. . In addition, although detailed illustrations are omitted, the positional alignment of the probe card 34 and the receiver 22 described above is performed by engaging the guide pad of the contact ring 22 provided on the probe card 34 side or the like. Furthermore, the zero insertion force connector 2 2 J provided on the contact ring 22 side and the performance board in the test head 20 are electrically connected by a plurality of wires or daughter boards. In particular, in the probe 30 of this embodiment, the measuring wafer 35 shown in FIG. 3 is a flange 311 provided on the wafer table 31 as shown in FIG. The measurement wafer 35 has a substrate 351 made of ceramic or silicon, which is the same as the substrate 341 of the probe card 34. On one of the main surfaces of the substrate 351 (the upper side in FIGS. I and 2 and the lower side in FIG. 3 is the lower side). On the right in Fig. 3, a pattern is formed of a pin 352 (equivalent to Ben Lamin's second pin-shaped contact) and a contact portion 3 5 3 connected to the ground wire. The distance between these pins 3 5 2 and the contact portion 3 5 3 is set to be approximately equal to the distance between the above-mentioned probe card 3 4, the pins 3 4 2 and the ground portion 3 4 3, as shown in FIG. One pair of pins 342 and the grounding part 343 approaching the detection card 34, 1 the contact part of the test chip 3 5 3, the 3 3 pin of the detection card 3 4 2 simultaneously touch the grounding part 343 of the detection card 34, and the measurement The contact portion 353 of the wafer 35. In addition, the pin 352 and the contact portion 353 of the wafer 35 for measurement are connected to the oscilloscope 40 via a cable or the like as shown in the right figure of Fig. 3, and the waveform of the measured test signal is observed. Next, the role will be explained.

在測試晶圓W之情況,首先在晶圓吸嘴將該晶圓w定位 下吸附保持之狀態,如探測卡34之針342接觸目的之晶圓WIn the case of testing the wafer W, first, the wafer w is positioned and sucked and held by the wafer suction nozzle, for example, the probe card 34 pin 342 contacts the target wafer W.

2030-3398-PFp t d 第11頁 五 '發明說明(9) ----- 之組件部之接點般在χγ 上升。藉此,測試某幾:::;圓,作台31邊對t位置邊 時,令晶圓工作台= '旦是在此之測試完τ Τ - ^ ^ , 月倣下降,如探測卡34之針342接觸 ;上;;=在π平面令晶圓工作台31邊對準位置邊 cm複此動作,測試在全部之區域之請之 裝丄在對於!晶圓w進行高溫測試之情況,令内 。。為::D之加熱态動作,冑晶,加熱升溫至例如10。 J_、_p尤,、在本貝^例之半導體基板測試裝置1,在進行 二圓測試,前,或者在進行晶圓測試之途中發生需 :m測自測试|§本體i 〇經由測試頭2〇向組件部送出之 測成信號之波形後,進行各測試信號之相位修正。 即’令晶圓工作台31在χγ平面内移動’令固定於凸緣 1之量測用晶片35位於探測卡34之下方。在此,如探測 4之一支針342、在其附近所形成之接地部343各自和接 7部353、針352接觸般令晶圓工作台上升。然後,在此狀 悲自測試器本體10送出既定之測試信號後’用示波器觀測 之。 在本例,因在和實際輸入測試信號之晶圓w之組件部 ^致相同之位置,即將探測卡34之針342之前端作為測試 信號之對示波器40之輸入部,用該示波器觀測之測試信號 之波形和實際輸入的變成大致相等。又,因在探測卡34在 針3 4 2之附近設置接地部3 4 3,也極力抑制雜訊等混入用示 波器40觀測之信號波形,結果,可得到正確之測試信號波2030-3398-PFp t d page 11 5 'Explanation of the invention (9) ----- The contact point of the component part generally rises at χγ. With this, test a few :::; circle, when the table 31 side to the t position side, let the wafer table = 'once the test is completed here τ Τ-^ ^, such as the detection card 34 Needle 342 contacts; up;; = make the wafer table 31 align with cm while repeating this operation on the π plane, and test the installation in all areas. In the case where wafer w is subjected to a high temperature test, it is within. . It is: the heating state of D, the crystal is heated, and the temperature is raised to, for example, 10; J_, _p, especially, in the semiconductor substrate test device 1 of this example, before the two-circle test is performed, or during the wafer test, it takes: m test self test | § body i 〇 through the test head 20 After the waveform of the measured signal sent to the module, the phase of each test signal is corrected. That is, "Move the wafer table 31 in the χγ plane" so that the measurement wafer 35 fixed to the flange 1 is located below the probe card 34. Here, if a pin 342 of the probe 4 and a ground portion 343 formed in the vicinity of the probe 4 are in contact with the 7 portions 353 and the pins 352, the wafer table is raised. Then, after sending the predetermined test signal from the tester body 10 in this state, it is observed with an oscilloscope. In this example, because it is at the same position as the component part of the wafer w where the test signal is actually input, the front end of the pin 342 of the probe card 34 is used as the test signal input part to the oscilloscope 40. The waveform of the signal becomes approximately equal to the actual input. In addition, since the grounding portion 3 4 3 is provided near the pin 3 4 2 on the detection card 34, noise and other signal waveforms observed with the oscilloscope 40 are also extremely suppressed, and as a result, a correct test signal wave can be obtained.

2030-3398-PF.ptd 第12頁2030-3398-PF.ptd Page 12

Claims (1)

541430 _ 虎 891171QQ φ ^ C\l 0 ,1 "、申請專利範圍 之纟且1株如種半導體基板測試裝置,向在革專體基板所形成 部之好ί迗出複數測試信號後測試,按照其結果判別組件 々展’該半導體基板測試裝置包括: 弟 針狀接點,在電氣上和組件部接觸; 之接=卡2其一主面設置設於該第-針狀接點之附近 4 ’在電氣上和測試頭基板連接; $觸部’在電氣上和針接觸;以及 之第:::ί::在其一主面設置在電氣上和接地部接觸 量測2用ΐ t請專利範圍第1項之半導體基板測試裝置’該 列且右:按照該探測卡之該第一針狀接點與接地部之排 ”有構成一對或一對以上之第二針狀接點與接觸部。 包括量= 第1八項之半導體基板測試裝置,還 <弟一針狀接點與接地部移動。 」下 包括4其Γ申請專利範圍第1項之半導體基板測試裝置,還 卡之ΐ反::乍# ’保持半導體基板並令該組件部和該探測 卞之弟一針狀接點接觸; 該量測用晶片設於該基板工作台。 t 範圍第i項之半導體基板測試裝置 ,信號特性量測裝置,和該量測用晶片之輸出端子連 接’並輸出該測試信號之特性。 、6.如申請專利範圍第5項之半導體基板測試裝置,該 測試信號之特性係信號波形。 Λ 2030-3398-PFl.ptc 第14頁 B 月 曰 Mikity 891171QA 申請專利範圍 ^ 種半導體基板測試裝置用探測卡,在電氣上和半 γ,板測試裝置之測試頭基板連接,且在一主面設置了 ,氣上和半導體基板之組件部接觸之複數針狀接點, 在該針狀接點之附近設置接地部。 8 ·如申請專利範圍第7項之半導體基板測試裝置用探 /〇 ’該接地部和複數針狀接點共同設置。 9 · 一種半導體基板測試裝置之量測用晶片,包括: ^妾觸部,在電氣上和設於半導體基板測試裝置用探測 卞之第一針狀接點接觸;及 第二針狀接點,在電氣上和設於該第一針狀接點之附 近之接地部接觸。 1、〇·種在半導體基板測試裝置之測試信號特性之量 二、〃=,使用一探測卡向在半導體基板所形成之組件部送 出禝數測試信號後測試,按照其結果判別該組件部之好 展,該探測卡在電氣上和半導體基板測試 板連接,且名_ 士 & % @ 7 , 置^列式頭基 邻接觸夕、-f 汉置在電氣上和半導體基板之組件 2=1針狀接點、及靠近該等針狀接點而配置 或途^向4半導體基板所形成之組件部送出測試信號之前 準備:量測用晶片,該量測用晶片在一主面設置 1 述第1針狀接點接觸之接觸部、及在電氣上盤 刖这接地部接觸之第2針狀接點; -、 使前述探測卡之第丨針狀接點與前述量測用晶片之接541430 _ Tiger 891171QQ φ ^ C \ l 0, 1 ", one of the patent application scopes and one type of semiconductor substrate test device, test the signal after the complex test signal is formed on the substrate of the leather substrate, According to the results, the module development is judged. The semiconductor substrate test device includes: a pin-shaped contact, which is in electrical contact with the component; a connection = card 2 with one main surface provided near the first pin-shaped contact; 4 'Electrically connected to the test head substrate; $ contact' is in electrical contact with the pin; and No. ::: ί :: It is provided on one of the main surfaces to be electrically and electrically connected to the ground contact measurement 2 ΐ t Please refer to the semiconductor substrate test device in the first scope of the patent, 'the column and the right: according to the row of the first pin-shaped contact and the grounding part of the probe card', there is a second pin-shaped contact that constitutes a pair or more And the contact part. Including the semiconductor substrate test device with the quantity = item 18, and the contact between the needle contact and the ground part is also included. "The semiconductor device test device including item 1 in the scope of its patent application is also included below. The card is wrong :: Enabling the assembly portion and the probe needle contacts Bian contacting a brother; measuring the wafer provided on the substrate stage. The semiconductor substrate test device of the range i, the signal characteristic measurement device, is connected to the output terminal of the measurement wafer and outputs the characteristics of the test signal. 6. If the semiconductor substrate testing device of item 5 of the patent application scope, the characteristic of the test signal is a signal waveform. Λ 2030-3398-PFl.ptc Page 14B Month Mikity 891171QA Patent application scope ^ A probe card for a semiconductor substrate test device is electrically connected to the test head substrate of a half-gamma, board test device, and on one main surface A plurality of pin-shaped contacts that are in contact with the component portion of the semiconductor substrate are provided, and a ground portion is provided near the pin-shaped contacts. 8 · If a probe for a semiconductor substrate test device according to item 7 of the scope of patent application is used, the grounding portion and a plurality of needle contacts are provided together. 9 · A wafer for measuring a semiconductor substrate testing device, comprising: a contact portion electrically contacting a first pin-shaped contact provided on the probe of the semiconductor substrate testing device; and a second pin-shaped contact, Electrically contact a ground portion provided near the first pin-shaped contact. 1. The amount of test signal characteristics in a semiconductor substrate test device 2. 〃 =, use a probe card to send a test signal to the component part formed on the semiconductor substrate and test it, and judge the component part according to the result Fortunately, the probe card is electrically connected to the semiconductor substrate test board, and the name is _ 士 &% @ 7, the column head is adjacent to the base, -f is placed on the electrical and semiconductor substrate components 2 = 1 Needle-shaped contacts, and are arranged or routed close to these needle-shaped contacts ^ Prepare before sending a test signal to the component part formed by 4 semiconductor substrates: a wafer for measurement, the measurement wafer is set on one main surface 1 The contact portion of the first pin-shaped contact and the second pin-shaped contact that is electrically contacted with the ground portion;-, the first pin-shaped contact of the probe card and the measurement chip Pick up 2030-3398-PFl.ptc2030-3398-PFl.ptc 年月e 、, _案號 89117199_年月日__ . ,B IT - Λ 六、申請專利範圍 觸部,以及前述探測卡之接地部與前述量測用晶片之第2 針狀點,構成電氣上之接觸; 送出測試信號給前述探測卡,並輸入至前述量測用晶 片; 測試輸入至前述量測用晶片之測試信號。 11.如申請專利範圍第1 0項之在半導體基板測試裝置 之測試信號特性之量測方法,該測試信號之特性係信號波 形。 1 2.如申請專利範圍第1 0項或第11項之在半導體基板 測試裝置之測試信號特性之量測方法,更包括:將前述經 測定後之測試信號之特性與正規的測試信號之特性進行比 較;以及,按照前述比較結果而修正測試信號。Year e,, _ case number 89117199_ year month date __., B IT-Λ VI. Patent application contact, and the grounding part of the aforementioned probe card and the second needle-like point of the aforementioned measurement chip, constitute Electrical contact; sending a test signal to the probe card and inputting it to the measurement chip; testing the test signal input to the measurement chip. 11. According to the method for measuring the characteristics of a test signal on a semiconductor substrate test device under the scope of the patent application No. 10, the characteristic of the test signal is a signal waveform. 1 2. If the method for measuring the characteristics of the test signal on a semiconductor substrate test device according to item 10 or 11 of the scope of the patent application, the method further includes: combining the characteristics of the aforementioned test signal with the characteristics of a regular test signal Performing comparison; and correcting the test signal according to the aforementioned comparison result. 2030-3398-PFl.ptc 第16頁2030-3398-PFl.ptc Page 16
TW89117199A 1999-09-02 2000-08-25 Test device for semiconductor wafers TW541430B (en)

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