TW531832B - Manufacturing method for shallow trench isolation structure - Google Patents

Manufacturing method for shallow trench isolation structure Download PDF

Info

Publication number
TW531832B
TW531832B TW90129228A TW90129228A TW531832B TW 531832 B TW531832 B TW 531832B TW 90129228 A TW90129228 A TW 90129228A TW 90129228 A TW90129228 A TW 90129228A TW 531832 B TW531832 B TW 531832B
Authority
TW
Taiwan
Prior art keywords
trench isolation
shallow trench
isolation structure
dielectric layer
manufacturing
Prior art date
Application number
TW90129228A
Other languages
Chinese (zh)
Inventor
Bau-Ching Peng
Fang-Jeng Chen
Ming-Huan Tsai
Hung-Yuan Tau
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Priority to TW90129228A priority Critical patent/TW531832B/en
Application granted granted Critical
Publication of TW531832B publication Critical patent/TW531832B/en

Links

Landscapes

  • Element Separation (AREA)

Abstract

A manufacturing method for shallow trench isolation (STI), which uses the spin-type wet etching method to remove the pad oxide layer, wherein the etching solution is uniformly sprayed on the substrate, and adjusting suitable rotational speed to make the substrate rotating horizontally, so as to conduct uniform etching on the pad oxide layer; then, with nitrogen and centrifugal force to remove the residual etching solution to prevent causing the divot of the dielectric layer between the shallow trench isolation structure and the active area.

Description

531832 A7 B7 ____ 五、發明説明() 發明領域: 一種淺溝渠隔離(Shallow Trench Isolation; STI)結構 之製造方法,特別是有關於利用旋轉式(Spin-Type)濕蝕刻 (Wet Etching)法去除墊氧化層,但其應用不僅限用於本領 域。 發明背景: 經濟部智慧財產局員工消費合作社印製 在往製作集積度更高的積體電路(Integrated Circuit; 1C) 時,隨著線寬與線距愈趨細微、閘氧化層變薄、深寬比更高, 為了避免產生短路,淺溝渠隔離製程取代了區域氧化隔離 (Localized Oxidation Isolation Method; LOCOS)製程,逐漸 成為隔離製程之主流。其中基材(Substrate)蝕刻、介電層 (Dielectric Layer)形成與化學機械研磨(Chemical Mechanical Polishing ; CMP)平坦化(Planarization)等主要製 程步驟之間的相關因素,更決定了隔離結構在淺溝渠隔離製 程模組中的實際表現。淺溝渠隔離技術是目前〇·18//ιη以下 CMOS之關鍵技術,具有良好的元件隔離效果,並可提高元 件密度及平坦度。對於淺溝渠隔離製程而言,濕蝕刻法是最 傳統、最簡易也是最與現階段製程設備組配相容的製程途 徑,亦是目前最普遍使用的方式,其具步驟簡易、量產機能 性高與製作成本低的優點,不過在高密度細線化的需求^, 2 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 531832 A7 B7 五、發明說明() 線寬與線距逐漸縮小時,其製作難度亦將隨之增加。對於淺 溝渠隔離製程而言,其對介電層形成的結果要求,是在以化 學機械研磨平坦化後,以濕蝕刻法去除主動區域以及墊氧化 層時’不造成溝渠内介電層的凹陷(Div〇t),以維持淺溝渠隔 離結構之完整。 請參考第1A圖至第1E圖,為習知技術在基材上進行 淺溝渠隔離結構之製程剖面圖。請參考第1A圖,首先提供 基材100,此基材100上依序堆疊有墊氧化層(Pad 〇xide Layer)l〇2與第一介電層104,其中墊氧化層i〇2之材料係 例如二氧化矽(Silicon Dioxide; Si02),而第一介電層104 之材料係例如氮化石夕(Silicon Nitride ; SiNx)。利用微影製 程,在基材100上定義第一介電層104與墊氧化層102, 使第一介電層104轉變為第一介電層1〇6,係用以定義出 複數個主動區域(Active Area)108a、主動區域l〇8b、與主 動區域108c,並暴露出部分之基材100,再於暴露之基材 1 〇〇中利用例如乾蝕刻法,形成複數個淺溝渠隔離結構開 口 ll〇a與淺溝渠隔離結構開口 110b,然後形成擴散阻障層 (Diffusion Barrier Layer) 1 1 2覆蓋在淺溝渠隔離結構開口 1 1 〇a與淺溝渠隔離結構開口 1 1 0b中,如第1 B圖所示之結 構。接著例如以化學氣相沉積(Chemical Vapor Deposition ; CVD)法、電漿加強型化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition ; PECVD)法、或高密 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) (請先閱讀背面之注意事項再填寫本頁) ·* n βϋ n mmmmmw m aMMmm n X ^ § i emt n t 線丨# 經濟部智慧財產局員工消費合作社印制农 531832 經濟部智慧財產局員工消費合作社印製 A7 B7_ 五、發明說明() 度電漿化學氣相沉積(High Density Plasm a-Chemical Vapor Deposition ; HDP-CVD)法,沉積第二介電層(Dielectric Laye〇l 14於第一介電層106之表面及淺溝渠隔離結構開口 1 1 0 a與淺溝渠隔離結構開口 1 1 〇 b中,如第1 C圖所示之結 構,其中第二介電層114之材料係例如二氧化矽(Silicon Dioxide ; SiO 2)。進行化學機械研磨製程,去除部分之第二 介電層114至約暴露出第一介電層1〇6之表面,使覆蓋在 第一介電層106上之第二介電層114轉變如第1 D圖所示 之第二介電層1 1 4a與第二介電層1 1 4b的結構。之後例如 以熱磷酸(Phosphoric acid; H3PO4)來剝除第一介電層106, 再利用例如以槽式(Bench-Type)濕蝕刻法去除墊氧化層 102,使第二介電層114a與第二介電層11 4b轉變如第1 E 圖所示之第二介電層1 14a’與第二介電層1 14b,的結構,形 成複數個淺溝渠隔離結構1 1 6a與淺溝渠隔離結構1 1 6b。 如上述習知之方法,在化學機械研磨製程之後,係應用 槽式濕蝕刻法去除墊氧化層1 〇 2。傳統上為了機具成本低 廉、製程簡單且產能(Throughput)大之考量,通常在蝕刻反 應槽中進行槽式濕蝕刻法。但因槽式濕蝕刻法係利用化學反 應來進行薄膜的去除,反應時無特定方向性,加工側向誤差 大’並且在將基材100垂直放入姓刻反應槽時,基材各 部份接觸蝕刻反應液的時間不一,造成蝕刻程度不均。上述 原因使得在去除塾氧化層102之過程中,靠近第一介電層 4 本纸張尺度適用中國國家標準(CNS)A4規格(210 X 297公餐) (請先閱讀背面之注意事項再填寫本頁) .-------訂---------線丨----} —--------------- 531832 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明() 106之淺溝渠隔離結構1 i6a與淺溝渠隔離結構n6b内之第 二介電層114a’與第二介電層n4b,,容易產生複數個凹陷 1 18a與凹陷1 18b,如第1E圖所示,這會衍生許多問題。首 先,淺溝渠隔離結構内之凹陷1 1 8 a與凹陷1 1 8 b猶如寄生性 的電容,會造成起始電壓降低,使主動區域108a、主動區域 108b、與主動區域108c產生寄生性的隆起現象(Hump Phenomenon),造成上述之主動區域的惡化。當積體電路的 線寬與線距愈趨細微時,閘電極也愈趨狹窄,相對地主動區 域108a、主動區域l〇8b、與主動區域108c的邊緣會產生很 強的電場,使得有效的啟始電壓下降,這種與電路線寬的狹 寬變化相反的現象即稱為逆狹寬效應(Inverse Narrow-Width Effect ; INWE)。 此外,在清洗槽中進行濕蝕刻反應時,蝕刻液及其他 清洗液容易殘留在凹陷1 18a與凹陷1 18b中,造成後續製 程中元件的漏電流。而且在進行傳統槽式濕蝕刻法時,基 材100為垂直放入蝕刻反應槽中,因此基材1〇〇各部份的 蝕刻處理時間會有差異,不易控制中央與邊緣之間的均一 性,甚至需要較長的過度蝕刻來解決這個問題。另一方面, 凹陷1 1 8a與凹陷1 1 8b也會限制後續形成之閘極與間隙壁 (Spacer)等的可容忍度(Process Window” 發明目的及概述: 5 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公f ) (請先閱讀背面之注意事項再填寫本頁) 訂------ 線丨# n taMmm flu m Λτ§ an n _ 531832 A7 B7 五、發明說明() (請先閱讀背面之注意事項再填寫本頁) 鐾於上述之發明背景中,習知形成淺溝渠隔離結構的 製程中’應用槽式濕蝕刻法去除墊氧化層,所造成淺溝渠 隔離結構内之凹陷,不僅產生逆狹寬效應,也會造成後續 製程中元件的漏電流,並減少閘極與間隙壁的可容忍度。 本發明針對濕式蝕刻法,提供一種旋轉式(Spin-Type) 濕蚀刻法’係將蝕刻溶液均勻喷灑在基材上,調整適當的 轉速使基材水平旋轉,以均勻地進行蝕刻,之後借助氮氣 與離心力將基材上殘留之蝕刻溶液去除,以避免造成淺溝 渠隔離結構與主動區域之間介電層的凹陷。 因此’本發明的主要目的之一為提供一種淺溝渠隔離 結構之製造方法,其係以旋轉式濕蝕刻法去除墊氧化層, 即將基材水平旋轉,把基材各部份的蝕刻處理時間差異降 至隶小’使塾氧化層得以均勻去除,不僅提高钱刻之均勻 性(Uniformity),更改善槽式濕蝕刻法蝕刻不均的缺點。 經濟部智慧財產局員工消費合作社印製 本發明之另一目的為提供一種淺溝渠隔離結構之製造 方法,其係以旋轉式濕蝕刻法去除墊氧化層時,可借助離 心力將基材上殘留之蝕刻溶液去除,以避免造成淺溝渠隔 離結構與主動區域之間介電層的凹陷。 本紙張尺度適用中國國家標準(CNS)A4規烙(210 x 297公餐) 經濟部智慧財產局員工消費合作社印製 531832 A7 --— B7 五、發明說明() 本發明之又一目的為提供一種淺溝渠隔離結構之製造 方法’其旋轉式濕蝕刻法不僅可應用於去除墊氧化層,更 可應用在其他相關之氧化層之去除,例如進行離子植入製 权時犧牲乳化層(Sacrificed 〇xide Layer)之#刻、閘氧化層 (Gate Oxide Layer)之蝕刻、閘氧化層兩側形成間隙壁後其 上方殘留之間隙壁(P 〇 s t - S p a c e r)的ϋ刻、用來防止金屬石夕化 物形成的金屬矽化物阻擋層(silicide Block Layer)之蝕 刻、以及形成金屬前之蝕刻(Pre-Metal Dip)等。 本發明之又一目的為提供一種淺溝渠隔離結構之製造 方法,不論單片晶圓(Single-Wafer)或多片晶圓(Muiti, Wafers) ’均可應用本發明之旋轉式濕蝕刻法進行蝕刻反 應。 根據以上所述之目的,本發明更提供了 一種淺溝渠隔 離結構之製造方法,至少包含:提供基材,此基材上依序 堆疊有墊氧化層與第一介電層;定義第一介電層與墊氧化 層’藉以形成複數個主動區域並暴露出部分之基材;形成 複數個淺溝渠隔離結構開口於暴露之基材中,然後形成擴 散阻障層覆蓋在複數個淺溝渠隔離結構開口中;接著例如 以化學氣相沉積法、電漿加強型化學氣相沉積法、或高密 度電漿化學氣相沉積法,沉積第二介電層於工作區域之表 面及複數個淺溝渠隔離結構開口中;進行化學機械研磨製 本纸張尺度適用中國國家標準(CNS)A4規格(210 x 297公t ) I n n ϋ ti n i i n n Mmm— n I « n n a— n an n n ^aj 9 n Mi ϋ MMmaw n I n I I t 2请先聞讀背¾<t事項再填寫衣頁) 531832 A7 B7 五、發明說明() 程,以去除部分之第二介電層,藉以在複數個淺溝渠隔離 結構開口中形成複數個淺溝渠隔離結構;去除第一介電 層;利用旋轉式濕蝕刻法去除墊氧化層;以及清洗及乾燥 基材。 圖式簡單說明: 本發明的較佳實施例將於往後之說明文字中辅以下列 圖形做更詳細的闡述,其中: 第1 A圖至第1 E圖為習知技術進行淺溝渠隔離結構之 製程剖面圖;以及 第2A圖至第2E圖為本發明之一較佳實施例進行淺溝 渠隔離結構之製程剖面圖。 圖號對照說明: 100 基材 102 墊氧化層 104 第一介電層 106 第一介電層 108a 、 108b 、 108c 主動區域 1 10a、1 10b 淺溝渠隔離結構開口 112 擴散阻障層 114 第二介電層 114a、1 14b 第二介電層 114a’、114b’ 第二介電層 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公t ) (請先閱讀背面之注意事項再填寫本頁) 訂--- 線丨· 經濟部智慧財產局員工消費合作社印製 531832 A: B7 五、發明說明() 經濟部智慧財產局員工消費合作社印製 116a 、1 16b 淺溝 渠隔離結構 1 18a 、1 18b 凹陷 200 基材 202 墊氧化層 204 第一介 電層 206 第一介電 層 208a 、208b 、 208c 主動區域 210a 、210b 淺溝 渠隔離結構開 σ 212 擴散阻 障層 214 第二介電 層 214a 、214b 第二 介電層 214a ’ 、214b’ 第 二介電層 216a 、216b 淺溝 渠隔離結構 發明 詳細說明 : 本發明揭 露一 種淺溝渠隔離 結構之製造 方法,其係 利 用旋轉式濕蝕 刻法 去除墊氧化層 。為了使本 發明之敘述 更 加詳 盡與完備 ,可 參照下列描述 並配合第2Α圖至第2Ε 圖 之圖 示0 請參照第 2A圖至第2E圖, 其所繪示為 本發明之一 較 佳實 施例之淺 k溝渠 隔離結構之製 程剖面圖。 請參考第 2Α 圖, 首先提供 基材 200,此基材 200上依序 堆疊有墊氧 化 層202與第一 •介電 層204 ,其中 墊氧化層202之材料例 如 為二氧化矽、氮化矽、氮氧化矽(Silicon Oxy-Nitride ; (請先閱讀背面之注意事項再填寫本頁) ··---- 訂---------線丨-----Γ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公t ) 531832 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明()531832 A7 B7 ____ 5. Description of the invention () Field of invention: A method for manufacturing a Shallow Trench Isolation (STI) structure, in particular, it relates to the removal of a pad by a spin-type wet etch (Wet Etching) method An oxide layer, but its application is not limited to the field. Background of the Invention: When the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed a higher integrated circuit (Integrated Circuit; 1C), as the line width and line spacing became finer, the gate oxide layer became thinner and deeper. The aspect ratio is higher. In order to avoid short circuit, the shallow trench isolation process replaces the Localized Oxidation Isolation Method (LOCOS) process and gradually becomes the mainstream of the isolation process. The relevant factors between the main process steps such as substrate etching, dielectric layer formation, and chemical mechanical polishing (CMP) planarization also determine the isolation structure in shallow trenches. Actual performance in isolated process modules. Shallow trench isolation technology is currently the key technology of CMOS below 18 // ιη. It has good element isolation effect and can improve element density and flatness. For shallow trench isolation processes, wet etching is the most traditional, easiest and most compatible process at the current stage. It is also the most commonly used method. It has simple steps and mass production functionality. The advantages of high production cost and low production cost, but in the need of high-density thinning ^ 2 This paper size applies Chinese National Standard (CNS) A4 specifications (210X297 mm) 531832 A7 B7 V. Description of the invention () Line width and line spacing As it shrinks, its production difficulty will increase. For the shallow trench isolation process, the result of the formation of the dielectric layer is that after planarization by chemical mechanical polishing, the active area and the pad oxide layer are removed by wet etching method, which does not cause the dielectric layer in the trench to be depressed. (Div0t) to maintain the integrity of the shallow trench isolation structure. Please refer to FIG. 1A to FIG. 1E, which are cross-sectional views of a conventional process for forming a shallow trench isolation structure on a substrate. Please refer to FIG. 1A. First, a substrate 100 is provided. A pad oxide layer 102 and a first dielectric layer 104 are sequentially stacked on the substrate 100. The material of the pad oxide layer i02 The material is, for example, Silicon Dioxide (Si02), and the material of the first dielectric layer 104 is, for example, Silicon Nitride (SiNx). The lithography process is used to define the first dielectric layer 104 and the pad oxide layer 102 on the substrate 100, so that the first dielectric layer 104 is transformed into the first dielectric layer 106, which is used to define a plurality of active regions. (Active Area) 108a, 108b, and 108c, and a part of the substrate 100 is exposed, and then a plurality of shallow trench isolation structure openings are formed in the exposed substrate 100 using, for example, dry etching. 110a and the shallow trench isolation structure opening 110b, and then forming a diffusion barrier layer (Diffusion Barrier Layer) 1 1 2 covers the shallow trench isolation structure opening 1 1 〇a and the shallow trench isolation structure opening 1 1 0b, as in Section 1 The structure shown in Figure B. Then, for example, a chemical vapor deposition (CVD) method, a plasma enhanced chemical vapor deposition (PECVD) method, or a high-density paper size is applied to the Chinese National Standard (CNS) A4 specification ( 210 x 297 mm) (Please read the notes on the back before filling in this page) · * n βϋ n mmmmmw m aMMmm n X ^ § i emt nt line 丨 # Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Cooperative, Printed Agriculture 531832 Economy Printed by the Consumer Cooperative of the Ministry of Intellectual Property Bureau A7 B7_ 5. Description of the invention () High Density Plasm a-Chemical Vapor Deposition (HDP-CVD) method to deposit a second dielectric layer (Dielectric Laye. The structure of the first dielectric layer 106 on the surface of the first dielectric layer 106 and the shallow trench isolation structure opening 1 1 0 a and the shallow trench isolation structure opening 1 1 0b is shown in FIG. 1C, in which the second dielectric layer 114 The material is silicon dioxide (Silicon Dioxide; SiO 2). A chemical mechanical polishing process is performed to remove a portion of the second dielectric layer 114 to approximately expose the surface of the first dielectric layer 106 to cover the surface. The second dielectric layer 114 on the first dielectric layer 106 changes the structure of the second dielectric layer 1 1 4a and the second dielectric layer 1 1 4b as shown in FIG. 1D. Then, for example, Phosphoric acid; H3PO4) to strip the first dielectric layer 106, and then remove the pad oxide layer 102 by, for example, a bench-type wet etching method, so that the second dielectric layer 114a and the second dielectric layer 11 4b are transformed The structures of the second dielectric layer 114a 'and the second dielectric layer 114b, as shown in Fig. 1E, form a plurality of shallow trench isolation structures 1 1 6a and shallow trench isolation structures 1 1 6b. Known method, after the chemical mechanical polishing process, a groove wet etching method is used to remove the pad oxide layer 102. Traditionally, in order to consider the low cost of the equipment, the simple process and the high throughput, it is usually performed in an etching reaction tank. Slot wet etching method. However, since the slot wet etching method uses a chemical reaction to remove the thin film, there is no specific directionality during the reaction, and the processing side error is large. , The time that each part of the substrate contacts the etching reaction solution is different, resulting in The degree of etching is uneven. The above reasons make it close to the first dielectric layer 4 in the process of removing the hafnium oxide layer 102. The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 meals) (please read the back first) (Please note this page before filling in this page) .------- Order --------- line 丨 ----} ----------------- 531832 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (106) The second dielectric layer 114a 'and the second dielectric layer n4b within the shallow trench isolation structure 1 i6a and the shallow trench isolation structure n6b, It is easy to generate a plurality of depressions 118a and 118b, as shown in FIG. 1E, which will cause many problems. First of all, the depressions 1 1 8 a and 1 1 8 b in the shallow trench isolation structure are like parasitic capacitors, which will cause the initial voltage to decrease, and cause parasitic ridges in the active region 108 a, the active region 108 b, and the active region 108 c. The phenomenon (Hump Phenomenon) causes the deterioration of the above active area. As the line width and line pitch of the integrated circuit become more and more fine, the gate electrode also becomes narrower. Relatively active edges 108a, 108b, and edges of the active area 108c will generate a strong electric field, making the effective The starting voltage drops. This phenomenon, which is opposite to the narrow change of the line width of the circuit, is called the inverse narrow effect (INWE). In addition, when the wet etching reaction is performed in the cleaning tank, the etchant and other cleaning liquids are likely to remain in the depressions 118a and 118b, causing leakage current of the components in the subsequent processes. Moreover, when performing the traditional wet groove etching method, the substrate 100 is vertically placed in the etching reaction tank, so the etching processing time of each part of the substrate 100 may be different, and it is difficult to control the uniformity between the center and the edges. And even longer over-etching is needed to solve this problem. On the other hand, the depressions 1 1a and 1 1b will also limit the tolerance of the subsequently formed gates and spacers (Process Window). The purpose and summary of the invention: 5 This paper size applies to Chinese national standards ( CNS) A4 specification (210x297 male f) (Please read the precautions on the back before filling this page) Order ------ Line 丨 # n taMmm flu m Λτ§ an n _ 531832 A7 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) 鐾 In the above background of the invention, in the process of forming a shallow trench isolation structure, it is known that 'the trench wet etching method is used to remove the pad oxide layer, resulting in the shallow trench isolation structure. The depression not only produces the reverse narrowing effect, but also causes the leakage current of components in subsequent processes, and reduces the tolerance of the gate and the spacer. The present invention provides a spin-type method for wet etching. The "wet etching method" is to uniformly spray the etching solution on the substrate, adjust the appropriate rotation speed to rotate the substrate horizontally to uniformly etch, and then remove the remaining etching solution on the substrate by nitrogen and centrifugal force to avoid Caused a depression in the dielectric layer between the shallow trench isolation structure and the active region. Therefore, one of the main objectives of the present invention is to provide a method for manufacturing a shallow trench isolation structure, which is to remove the pad oxide layer by a rotary wet etching method. The substrate is rotated horizontally, reducing the difference in the etching time of each part of the substrate to a small amount, so that the hafnium oxide layer can be uniformly removed, which not only improves the uniformity of the money engraving (Uniformity), but also improves the uneven etching of the trench wet etching Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Another object of the present invention is to provide a method for manufacturing a shallow trench isolation structure. When the pad oxide layer is removed by rotary wet etching, the substrate can be removed by centrifugal force. The remaining etching solution is removed to avoid the depression of the dielectric layer between the shallow trench isolation structure and the active area. This paper size applies the Chinese National Standard (CNS) A4 (210 x 297 meals) Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee consumer cooperative 531832 A7 --- B7 V. Description of the invention () Another object of the present invention is to provide a shallow trench isolation structure The manufacturing method's rotary wet etching method can not only be applied to remove the pad oxide layer, but also can be used to remove other related oxide layers, such as sacrificed 〇xide Layer when performing ion implantation. Engraving, etching of Gate Oxide Layer, engraving of the spacers (Po s-S pacer) that remain after the barrier oxides are formed on both sides of the gate oxide, metal used to prevent the formation of metal oxides Etching of a silicide block layer and Pre-Metal Dip before forming a metal. Yet another object of the present invention is to provide a method for manufacturing a shallow trench isolation structure. Regardless of a single wafer (Single-Wafer) or multiple wafers (Muiti, Wafers), the rotary wet etching method of the present invention can be used. Etching reaction. According to the above-mentioned object, the present invention further provides a method for manufacturing a shallow trench isolation structure, which at least includes: providing a substrate on which a pad oxide layer and a first dielectric layer are sequentially stacked; defining the first dielectric The electrical layer and the pad oxide layer are used to form a plurality of active areas and expose a part of the substrate; a plurality of shallow trench isolation structures are formed to be opened in the exposed substrate, and then a diffusion barrier layer is formed to cover the plurality of shallow trench isolation structures. In the opening; then, for example, by chemical vapor deposition, plasma enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition, a second dielectric layer is deposited on the surface of the work area and a plurality of shallow trenches to isolate it In the structure opening; the size of the paper produced by chemical mechanical grinding is in accordance with Chinese National Standard (CNS) A4 (210 x 297 mm t) I nn ϋ ti niinn Mmm— n I «nna— n an nn ^ aj 9 n Mi ϋ MMmaw n I n II t 2 Please read the back first and then fill in the clothing page) 531832 A7 B7 V. Description of the invention () process to remove part of the second dielectric layer, so as to isolate in a plurality of shallow trenches Forming a plurality of openings configured shallow trench isolation structure; removing the first dielectric layer; removing the pad oxide layer is formed by a rotary wet etching method; and washing and drying the substrate. Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures, where: Figures 1A to 1E are conventional trench isolation structures FIG. 2A to FIG. 2E are process sectional views of a shallow trench isolation structure according to a preferred embodiment of the present invention. Comparative description of drawing numbers: 100 substrate 102 pad oxide layer 104 first dielectric layer 106 first dielectric layer 108a, 108b, 108c active area 1 10a, 1 10b shallow trench isolation structure opening 112 diffusion barrier layer 114 second dielectric Electrical layer 114a, 114b Second dielectric layer 114a ', 114b' Second dielectric layer The paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 gt) (Please read the precautions on the back before filling (This page) Order --- Line 丨 · Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 531832 A: B7 V. Invention Description () Printed by the Consumers ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 116a and 1 16b Shallow trench isolation structure 1 18a 1 18b depression 200 substrate 202 pad oxide layer 204 first dielectric layer 206 first dielectric layer 208a, 208b, 208c active area 210a, 210b shallow trench isolation structure opening σ 212 diffusion barrier layer 214 second dielectric layer 214a, 214b Second dielectric layer 214a ', 214b' Second dielectric layer 216a, 216b Shallow trench isolation structure Detailed description of the invention: The present invention discloses a shallow trench A method for manufacturing isolation structures, which system utilizing a rotary Removal wet etching the pad oxide layer. In order to make the description of the present invention more detailed and complete, you can refer to the following description and cooperate with the diagrams of Figures 2A to 2E. 0 Please refer to Figures 2A to 2E, which illustrate a preferred implementation of the present invention. An example of a process cross-section of a shallow-k trench isolation structure. Referring to FIG. 2A, a substrate 200 is first provided, and a pad oxide layer 202 and a first dielectric layer 204 are sequentially stacked on the substrate 200. The material of the pad oxide layer 202 is, for example, silicon dioxide, silicon nitride. 、 Silicon Oxy-Nitride; (Please read the precautions on the back before filling this page) ·· ---- Order --------- Line 丨 ----- Γ This paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 metric tons) 531832 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention ()

SiOxNy)、或高介電常數介電質(High k Dielecuics)。而第 一介電層之材料係例如氮化矽。利用微影製程在基材2〇〇 上定義第一介電層2 04與墊氧化層202,使第一介電層204 轉變為第一介電層206,用以定義出複數個主動區域2〇8a、 主動區域208b、以及主動區域2〇8c,並暴露出部分之基材 2 00,再於暴露之基材200中利用例如乾蝕刻法,形成複數 個淺溝渠隔離結構開口 2 1 〇 a與淺溝渠隔離結構開口 2 1 Ob,然後形成擴散阻障層2 1 2覆蓋在淺溝渠隔離結構開 口 210a與淺溝渠隔離結構開口 2i〇b中,如第2B圖所示之 結構。接著例如以化學氣相沉積法、電漿加強型化學氣相 沉積法、或向後度電漿化學氣相沉積法,沉積第二介電層 214於第一介電層206之表面、淺溝渠隔離結構開口 21“ 與淺溝渠隔離結構開口 210b中,如第2C圖所示之結構, 其中第一介電層2 1 4之材料係例如二氧化石夕。 接著’進行化學機械研磨製程,去除部分之第二介電 層214至約暴露出第一介電層206之表面,使覆蓋在第一 介電層206上之第一介電層214轉變如第2d圖所示之第二 介電層214a與第二介電層214b的結構。之後,利用例如 熱鱗酸來剝除第一介電層206 ’再利用旋轉式濕蝕刻法剝 除墊氧化層202 ’係將姓刻溶液均勻噴灑在基材2〇〇上, 調整適當的轉速’使基材200水平旋轉以均勻地進行姓 刻,把基材200各部份的#刻處理時間差降至最小,使塾 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) <請先閱讀背面之注意事項再填寫本頁) 訂·丨 丨線丨— 531832 A7 R7 五、發明說明() 氧化層202均勻去除,使第二介電層214a與第二介電層 214b轉變成第二介電層214a,與第二介電層214b,的結構, 形成淺溝渠隔離結構2 1 6 a以及淺溝渠隔離結構2 1 6 b,如第 2E圖所示之結構。 移除墊氧化層202之步驟時,其特徵在於利用旋轉式 濕蝕刻法,係將蝕刻溶液均勻噴灑在基材2 0 0上,調整適 當的轉速使基材200水平旋轉,以均勻地進行墊氧化層202 之蝕刻,之後借助氮氣與離心力將殘留之蝕刻溶液去除, 以避免造成淺溝渠隔離結構與主動區域之間介電層的凹 陷。其中所使用之蝕刻溶液為經稀釋之50%氫氟酸(DilutedSiOxNy), or High k Dielecuics. The material of the first dielectric layer is, for example, silicon nitride. The lithography process is used to define the first dielectric layer 204 and the pad oxide layer 202 on the substrate 2000, so that the first dielectric layer 204 is transformed into the first dielectric layer 206, which is used to define a plurality of active regions 2 〇8a, the active region 208b, and the active region 208c, and a part of the substrate 200 is exposed, and then a plurality of shallow trench isolation structure openings 2 are formed in the exposed substrate 200 using, for example, a dry etching method. The shallow trench isolation structure opening 2 1 Ob is formed, and then a diffusion barrier layer 2 1 2 is formed to cover the shallow trench isolation structure opening 210a and the shallow trench isolation structure opening 2i0b, as shown in FIG. 2B. Then, for example, a chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, or a backward plasma chemical vapor deposition method is used to deposit a second dielectric layer 214 on the surface of the first dielectric layer 206 and isolate the shallow trenches. The structure opening 21 "is separated from the shallow trench by the structure opening 210b, as shown in FIG. 2C, wherein the material of the first dielectric layer 2 1 4 is, for example, SiO 2. Then, a chemical mechanical polishing process is performed to remove a part The second dielectric layer 214 exposes approximately the surface of the first dielectric layer 206, so that the first dielectric layer 214 overlying the first dielectric layer 206 is transformed into a second dielectric layer as shown in FIG. 2d. 214a and the second dielectric layer 214b. After that, the first dielectric layer 206 is stripped using, for example, hot-scale acid, and the pad oxide layer 202 is stripped by a rotary wet etching method. On the substrate 200, adjust the appropriate rotation speed to make the substrate 200 rotate horizontally to uniformly carry out the last name engraving, and reduce the #etching processing time difference of each part of the substrate 200 to the minimum, so that the standard of this paper is in accordance with Chinese national standards. (CNS) A4 size (210 x 297 mm) < Please Read the precautions on the back and fill in this page again.) · 丨 丨 Line 丨 — 531832 A7 R7 V. Description of the invention () The oxide layer 202 is evenly removed, so that the second dielectric layer 214a and the second dielectric layer 214b are transformed into the second The structures of the dielectric layer 214a and the second dielectric layer 214b form a shallow trench isolation structure 2 1 6 a and a shallow trench isolation structure 2 1 6 b, as shown in FIG. 2E. The pad oxide layer 202 is removed. In the step, it is characterized by using a rotary wet etching method to uniformly spray the etching solution on the substrate 200, adjust the appropriate rotation speed to rotate the substrate 200 horizontally, and uniformly etch the pad oxide layer 202. After that, the remaining etching solution is removed by means of nitrogen and centrifugal force to avoid the depression of the dielectric layer between the shallow trench isolation structure and the active area. The etching solution used is a diluted 50% hydrofluoric acid (Diluted

Hydrofluoric Acid ; DHF),其中所含50°/〇氫氟酸與水之體 積比介於約1 : 500至約1 : 30,以介於約1 : 100至約1 : 50為較佳;進行蝕刻製程時之溫度介於約〇。〇至约1 〇〇 °c 之間,以約為室溫為較佳;並配合旋轉之轉數介於約600 rpm至約3000 rpm之間。之後以去離子水清洗基材上殘留 之蝕刻溶液,此時旋轉之轉數介於約500 rpm至約2000 rpm 之間。接著導入氮氣(Nitrogen ; N2),並配合旋轉之轉數介 於約500 rpm至約3000 rpm之間,借助氮氣與離心力使基 材表面得以乾燥。 上述之製程僅為本發明其中一實施例,本發明之旋轉 式濕蝕刻法除了應用在墊氧化層之移除外,更可應用至其 π 本紙張尺度適用中國國家標準(CNs)A4規格(210 x 297公t ) (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 ^eJ« ϋ n ϋ n n ·ϋ I n n n n «n *1— n 531832 — A7 B7 五、發明說明( 他相關氧化層之移^ % ’例如進行離子植入製程時犧牲氧仆 層、閘氧化層、間隙 味壁、金屬矽化物阻擋層、以及形成 屬前之姓刻等。此休 (請先閱讀背面之注意事項再填寫本頁) 不論早片晶圓或多片晶圓’均可鹿用 本發明之旋轉式渴執& … …、钱刻法進行蝕刻反應。而進行旋轉式渴 蝕刻法之設備,亦i … 可獨立應用或結合其他製程設備來鹿 用。 … 本發明之一優^ _ 點就是在提供一種淺溝渠隔離結構之製 造方法,其係以旋鲑』 ^ 说 疋轉式濕蝕刻法去除墊氧化層,即將基材 水平旋轉,把基鉍々 W各部份的蝕刻處理時間差異降至最小, 使墊氧化層知以均勻去,,不僅提高蝕刻之均勻性,更改 善槽式濕#刻法麵刻不均的缺點。 本發明之另一優點為提供一種淺溝渠隔離結構之製造 方法’其係以旋轉式濕蝕刻法去除墊氧化層時,可借助離 心力將基材上殘留之蝕刻溶液去除,以避免造成淺溝渠隔 離結構與主動區域之間介電層的凹陷。 經晋部智慧財產局員工消費合作社印製 本發明之又一優點為提供一種淺溝渠隔離結構之製造 方法’其旋轉式濕蝕刻法不僅可應用於去除墊氧化層,更 可應用在其他相關之氧化層之蝕刻,例如進行離子植入製 程時犧牲氧化層之蝕刻、閘氧化層之蝕刻、閘氧化層兩側 形成間隙壁後其上方殘留之間隙壁的蝕刻、用來防止金屬 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 531832 A7 B7_ 五、發明說明() 矽化物形成的金屬矽化物阻擋層之蝕刻、以及形成金屬前 之蝕刻等。 本發明之又一優點為提供一種淺溝渠隔離結構之製造 方法,不論單片晶圓或多片晶圓,均可應用本發明之旋轉 式濕蝕刻法進行蝕刻反應。 如熟悉此技術之人員所暸解的,以上所述僅為本發明 之較佳實施例而已,並非用以限定本發明之申請專利範 圍;凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾,均應包含在下述之申請專利範圍内。 Γ 一良 n If I n n n 11-·« n «n mmm§ fl_n an I a tmmt memme n t— n m fla— , 11 in an In in n n· I i i-i (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張又度適用中國國家標準(CNS)A4規格(210 X 297公釐)Hydrofluoric Acid; DHF), wherein the volume ratio of 50 ° / 〇 hydrofluoric acid to water is between about 1: 500 to about 1:30, preferably between about 1: 100 to about 1:50; The temperature during the etching process is about 0 °. The temperature is preferably between about 0 ° C and about 100 ° C, and about room temperature is preferred; and the number of rotations with the rotation is between about 600 rpm and about 3000 rpm. After that, the remaining etching solution on the substrate is washed with deionized water, and the rotation speed at this time is between about 500 rpm and about 2000 rpm. Next, nitrogen gas (Nitrogen; N2) is introduced, and the rotation speed is between about 500 rpm and about 3000 rpm, and the surface of the substrate is dried by means of nitrogen and centrifugal force. The above process is only one of the embodiments of the present invention. In addition to the removal of the pad oxide layer, the rotary wet etching method of the present invention can also be applied to its π. This paper size is applicable to Chinese National Standards (CNs) A4 specifications ( 210 x 297 t) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ eJ «ϋ n ϋ nn · ϋ I nnnn« n * 1— n 531832 — A7 B7 V. Description of the invention (% of the relevant oxidation layer shifts ^% 'For example, during the ion implantation process, the sacrificial oxygen layer, the gate oxide layer, the interstitial taste wall, the metal silicide barrier layer, and the formation of the former name etc. Hugh (Please read the precautions on the back before filling this page) Regardless of early wafers or multiple wafers, you can use the rotary thirst & ... of the present invention to perform the etching reaction. The equipment of the rotary thirst etching method can also be used independently or in combination with other process equipment.… One of the advantages of the present invention is to provide a manufacturing method of a shallow trench isolation structure, which is based on spinning salmon. ^ Talking about turning wet The etching method removes the pad oxide layer, that is, the substrate is rotated horizontally to minimize the difference in the etching processing time of each part of the base bismuth and W, so that the pad oxide layer is uniformly removed, which not only improves the uniformity of the etching, but also improves the groove. The disadvantage of non-uniform engraving on the wet surface is that another type of the present invention provides a method for manufacturing a shallow trench isolation structure. When the pad oxide layer is removed by a rotary wet etching method, the substrate can be removed by centrifugal force. Residual etching solution is removed to avoid the depression of the dielectric layer between the shallow trench isolation structure and the active area. Printed by the Consumers Cooperative of the Intellectual Property Bureau of the Ministry of Jinjiang, another advantage of the present invention is to provide a shallow trench isolation structure. Method 'The rotary wet etching method can be applied not only to remove the pad oxide layer, but also to the etching of other related oxide layers, such as etching of sacrificial oxide layers during ion implantation, etching of gate oxide layers, and gate oxidation. After the gap wall is formed on both sides of the layer, the etching of the gap wall above it is used to prevent the metal paper size from applying the Chinese National Standard (CNS) A4 specification ( (210 X 297 mm) 531832 A7 B7_ V. Description of the invention () Etching of a metal silicide barrier layer formed by silicide, and etching before forming a metal, etc. Another advantage of the present invention is to provide a manufacturing of a shallow trench isolation structure Method, regardless of single wafer or multiple wafers, the rotary wet etching method of the present invention can be used to perform the etching reaction. As understood by those skilled in the art, the above description is only a preferred embodiment of the present invention. It is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the scope of patent application below. Γ 一 良 n If I nnn 11- · «n« n mmm§ fl_n an I a tmmt memme nt— nm fla—, 11 in an In in nn · I i ii (Please read the notes on the back before filling out this page) Intellectual Property Bureau, Ministry of Economic Affairs The paper printed by the employee consumer cooperative is again applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

531832 A8 B8 C8 D8 六、申請專利範圍 經濟部智慧財產局員工消費合作社印製 1 · 一 種淺溝渠隔離(Shallow Trench Isolation ; STI)結構 之製造方法,至少包含: 提供一基材,其中該基材上已堆疊有一墊氧化層與一 第一介電層; 定義該第一介電層、該墊氧化層及該基材,於該基材 上形成複數個淺溝渠隔離結構開口; 形成一第二介電層覆蓋該第一介電層、該墊氧化層及 該些淺溝渠隔離結構開口; 去除部分之該第二介電層至暴露出該第一介電層之表 面; 去除該第一介電層; 利用旋轉式濕蝕刻法去除該墊氧化層;以及 清洗及乾燥該基材。 2·如申請專利範圍第丨項所述之淺溝渠隔離結構之製 造方法’其中該墊氧化層之材料係為二氧化碎(silic〇n Oxide ; Si〇2) 〇 3 ·如申請專利範圍第1項所述之淺溝渠隔離結構之製 造方法,其中該第一介電層之材料係為氮化矽(siHc〇n Nitride ; SiNx)。 (請先閱讀背面之注意事項再填寫本頁) 訂---------線1#· .齊Γ — — — — — — — — — 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 531832 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 申請專利範圍 4·如申請專利範圍第i頊所述之淺溝渠隔離結構之製 造方法,其中該第一介電層之材料係為氮氧化矽(SiHc〇n Oxy-Nitride ; SiOxNy) 〇 5. 如申請專利範圍第丨項所述之淺溝渠隔離結構之製 造方法,其中該第一介電層之材料係為高介電常數介電質 (High k Dielectrics)。 6. 如申請專利範圍第1項所述之淺溝渠隔離結構之製 造方法,其中形成該些淺溝渠隔離結構開口之後,更包括 形成一擴散阻障層(Diffusion Barrier Layer)於該些淺溝渠 隔離結構開口中。 7·如申請專利範圍第1項所述之淺溝渠隔離結構之製 造方法,其中該第二介電層之材料係為二氧化矽(Silicon Dioxide ; Si02)。 8 ·如申請專利範圍第1項所述之淺溝渠隔離結構之製 造方法,其中沉積該第二介電層之步驟係利用一化學氣相 沉積(Chemical Vapor Deposition ; CVD)法0 9.如申請專利範圍第1項所述之淺溝渠隔離結構之製 15 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -m n n m am fi m n in Ha ·>ϋ n· I flu n I— m n n in 一 心、i i i n 1 n ·ϋ n 線丨*---- (請先閱讀背面之注意事項再填寫本頁) 531832 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8六、申請專利範圍 造方法,其中沉積該第二介電層之步驟係利用一高密度電 渡化學氣相沉積(High Density Plasma-Chemical Vapor Deposition ; HDP-CVD)法。 10.如申請專利範圍第丨項所述之淺溝渠隔離結構之製 造方法,其中去除部分之該第二介電層之步驟係利用一化 學機械研磨(Chemical Mechanical Polishing ; CMP)製程。 1 1.如申請專利範圍第1項所述之淺溝渠隔離結構之製 造方法,其中該利用旋轉式濕蝕刻法去除該墊氧化層之步 驟中,係使用經稀釋之 490/〇氫說酸(Diluted Hydrofluoric Acid ; DHF)為一蝕刻溶液,其中所含49%氫氟酸與水之體 積比的範圍介於約1 : 5 0 0至約1 ·· 3 0。 1 2 .如申請專利範圍第1 1項所述之淺溝渠隔離結構之 製造方法,其中該利用旋轉式濕蝕刻法去除該墊氧化層之 步驟中,係使用經稀釋之49%氫氟酸為該蝕刻溶液,而該 蝕刻溶液所含49%氫氟酸與水之體積比的範圍介於約1 : 100 至約 1 : 50。 1 3 ·如申請專利範圍第 n項所述之淺溝渠隔離結構之 製造方法’其中該利用旋轉式濕蝕刻法去除該墊氧化層之 步驟中’旋轉之轉數介於約400 rpm至約3000 rpm之間。 (請先閱讀背面之注意事項再填寫本頁) y IV · m 1 1 言 線-參- ▼ —— — ill-7. — — — — — — 16 I紙張尺度顧+ ®國家標準(CNS)A4規格(210 X 297公f 531832 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 14·如申請專利範圍第1 1項所述之淺溝渠隔離結構之 製造方法,其中該清洗該基材之步驟中,係以去離子水清 洗該基材上殘留之該蝕刻溶液,此時旋轉之轉數介於約500 rpm至約2000 rpm之間。 1 5 ·如申請專利範圍第1項所述之淺溝渠隔離結構之製 造方法,其中該乾燥該基材之步驟中,更導入一氮氣 (Nitrogen; N2),並配合旋轉之轉數介於約义0 r^jru^約3000 rpm 之間。 16.如申請專利範圍第1項所述之淺溝渠隔離結構之製 造方法,其中該利用旋轉式濕蝕刻法去除該墊氧化層之步 驟中,一製程溫度介於約0 °C至約100 °C之間。 1 7 ·如申請專利範圍第1 6項所述之淺溝渠隔離結構之 製造方法,其中該利用旋轉式濕蝕刻法去除該墊氧化層之 步驟中,該製程溫度約為室溫。 1 8. —種淺溝渠隔離結構之製造方法,至少包含: 提供一基材,其中該基材上已形成一介電層;以及 利用旋轉式濕蝕刻法處理該介電層。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 訂---------線 1 -----l·------ 531832 經濟部智慧財產局員工消費合作社印製 A8 B8 C3 D8 六、申請專利範圍 19.如申請專利範圍第18項所述之淺溝渠隔離結構之 製造方法’其中該介電層之材料係選自於由二氧化石夕、氮 化矽、氮氧化矽、及高介電常數介電質所組成之一族群。 20·如申請專利範圍第18項所述之淺溝渠隔離結構之 製造方法’其中該利用旋轉式濕蝕刻法處理該介電層之步 驟中,係使用經稀釋之49%氫氟酸為一蝕刻溶液,其中所 含4 9 %氫氟酸與水之體積比的範圍介於約1 : 5 0 0至約1 : 30。 2 1 ·如申凊專利範圍第2 0項所述之淺溝渠隔離結構之 製造方法’其中該利用旋轉式濕蝕刻法處理該介電層之步 驟後,更包含一清洗之步驟,係以去離子水清洗該基材上 殘留之該独刻溶液,此時旋轉之轉數介於約《〇 rpm ^約 2000 rpm 之間。 x lvl 打·“” .一-一一!°一*· 1 22. 如申請專利範圍第18項所述之淺溝渠隔離結構之 製造方法’其中該利用旋轉式濕蝕刻法處理該介電層之步 驟中,一製程溫度約為室溫。 23. 如申請專利範圍第18項所述之淺溝渠隔離結構之 製造方法,其中該利用旋轉式濕蝕刻法處理該介電層之步 驟中,旋轉之轉數介於約400 rpm至約3000 rpm之間。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -----:---.------------^--------·線 — Φ------- (請先閱讀背面之注意事項再填寫本頁) 531832 A8 B8 C8 D8 六、申請專利範圍 24·如申請專利範圍第23項所述之淺溝渠隔離結構之 製造方法,其中在該清洗之步驟後更包含一乾燥之步驟, 係導入一氮氣,並配合旋轉之轉數介於約500 irpm至約3000 rpm之間。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 訂-________-------r------------------- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)531832 A8 B8 C8 D8 VI. Application for Patent Scope Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs1. A manufacturing method of a Shallow Trench Isolation (STI) structure, including at least: providing a substrate, wherein the substrate A pad oxide layer and a first dielectric layer have been stacked thereon; the first dielectric layer, the pad oxide layer and the substrate are defined, and a plurality of shallow trench isolation structure openings are formed on the substrate; a second A dielectric layer covers the first dielectric layer, the pad oxide layer and the openings of the shallow trench isolation structures; removing a portion of the second dielectric layer to a surface exposing the first dielectric layer; removing the first dielectric An electrical layer; removing the pad oxide layer by a rotary wet etching method; and cleaning and drying the substrate. 2. The manufacturing method of the shallow trench isolation structure as described in item 丨 of the scope of the patent application, wherein the material of the pad oxide layer is silicon oxide (SiO2); 〇3. The method for manufacturing a shallow trench isolation structure according to item 1, wherein the material of the first dielectric layer is silicon nitride (SiHcOn Nitride; SiNx). (Please read the precautions on the back before filling this page) Order --------- Line 1 # ·. 齐 Γ — — — — — — — — — This paper size applies to China National Standard (CNS) A4 Specifications (210 X 297 mm) 531832 A8 B8 C8 D8 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Patent application scope 4. The manufacturing method of the shallow trench isolation structure as described in the patent application scope i), where the first The material of the dielectric layer is silicon oxynitride (SiHcOn Oxy-Nitride; SiOxNy). 5. The method for manufacturing a shallow trench isolation structure as described in item 丨 of the patent application scope, wherein the material of the first dielectric layer is System is high-k dielectrics (High k Dielectrics). 6. The method for manufacturing a shallow trench isolation structure as described in item 1 of the scope of patent application, wherein after forming the openings of the shallow trench isolation structures, it further comprises forming a diffusion barrier layer to isolate the shallow trenches. Structure opening. 7. The method for manufacturing a shallow trench isolation structure as described in item 1 of the scope of the patent application, wherein the material of the second dielectric layer is silicon dioxide (Silicon Dioxide; SiO2). 8. The method for manufacturing a shallow trench isolation structure as described in item 1 of the scope of the patent application, wherein the step of depositing the second dielectric layer is by a chemical vapor deposition (Chemical Vapor Deposition; CVD) method. The system of the shallow trench isolation structure described in item 1 of the patent scope 15 This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) -mnnm am fi mn in Ha · > ϋ n · I flu n I— mnn in Yixin, iiin 1 n · ϋ n line 丨 * ---- (Please read the precautions on the back before filling out this page) 531832 Printed by A8, B8, C8, D8, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs The method of patent scope, wherein the step of depositing the second dielectric layer uses a high density electrochemical vapor deposition (High Density Plasma-Chemical Vapor Deposition; HDP-CVD) method. 10. The method for manufacturing a shallow trench isolation structure as described in item 丨 of the patent application, wherein the step of removing a portion of the second dielectric layer uses a chemical mechanical polishing (CMP) process. 1 1. The method for manufacturing a shallow trench isolation structure as described in item 1 of the scope of the patent application, wherein in the step of removing the pad oxide layer by a rotary wet etching method, a diluted 490 / 〇hydrogen acid ( Diluted Hydrofluoric Acid (DHF) is an etching solution containing 49% hydrofluoric acid to water in a volume ratio ranging from about 1: 500 to about 1.30. 12. The method for manufacturing a shallow trench isolation structure as described in item 11 of the scope of the patent application, wherein in the step of removing the pad oxide layer by a rotary wet etching method, a diluted 49% hydrofluoric acid is used as The etching solution, and the volume ratio of 49% hydrofluoric acid to water contained in the etching solution ranges from about 1: 100 to about 1:50. 1 3 · The manufacturing method of a shallow trench isolation structure as described in item n of the scope of the patent application 'wherein the step of removing the pad oxide layer by a rotary wet etching method' has a rotation number of about 400 rpm to about 3000 between rpm. (Please read the precautions on the reverse side before filling out this page) y IV · m 1 1 Speech Line-Reference-▼ —— — ill-7. — — — — — — 16 I Paper Scale Gu + ® National Standard (CNS) A4 specifications (210 X 297 male f 531832 printed by employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 VI. Application for patent scope 14 · Manufacturing method of shallow trench isolation structure as described in item 11 of patent scope, where In the step of cleaning the substrate, the etching solution remaining on the substrate is cleaned with deionized water, and the number of rotations at this time is between about 500 rpm and about 2000 rpm. The method for manufacturing a shallow trench isolation structure according to item 1, wherein in the step of drying the substrate, a nitrogen gas (Nitrogen; N2) is further introduced, and the number of rotations corresponding to the rotation is between about 0 r ^ jru ^ about 3000 rpm. 16. The method for manufacturing a shallow trench isolation structure as described in item 1 of the patent application scope, wherein in the step of removing the pad oxide layer by a rotary wet etching method, a process temperature is between about 0 ° C to about 100 ° C. 1 7 · If applying for a patent The method for manufacturing a shallow trench isolation structure according to item 16, wherein in the step of removing the pad oxide layer by a rotary wet etching method, the process temperature is about room temperature. 1 8. —A kind of shallow trench isolation structure The manufacturing method at least comprises: providing a substrate, wherein a dielectric layer has been formed on the substrate; and processing the dielectric layer by a rotary wet etching method. The paper size is applicable to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) (Please read the notes on the back before filling this page) Order --------- Line 1 ----- l · ------ 531832 Intellectual Property Bureau of the Ministry of Economic Affairs Printed by employee consumer cooperative A8 B8 C3 D8 6. Application for patent scope 19. Manufacturing method of shallow trench isolation structure as described in item 18 of the scope of patent application 'wherein the material of the dielectric layer is selected from the group consisting of stone dioxide , Silicon nitride, silicon oxynitride, and high-k dielectrics. 20. A method for manufacturing a shallow trench isolation structure as described in item 18 of the scope of the patent application, wherein the rotary wet etching is used. In the step of processing the dielectric layer, The diluted 49% hydrofluoric acid is an etching solution, and the volume ratio of 49% hydrofluoric acid to water is in the range of about 1: 500 to about 1: 30. 2 1 Rushen Patent The method for manufacturing a shallow trench isolation structure according to the scope of item 20, wherein after the step of processing the dielectric layer by a rotary wet etching method, the method further includes a cleaning step of cleaning the substrate with deionized water. The remaining single solution, at this time, the number of rotations is between about 0 rpm and about 2000 rpm. x lvl "·".-1-1! ° 1 * · 1 22. The manufacturing method of the shallow trench isolation structure as described in item 18 of the scope of patent application, wherein the dielectric layer is processed by a rotary wet etching method In one step, a process temperature is about room temperature. 23. The method for manufacturing a shallow trench isolation structure as described in item 18 of the scope of patent application, wherein in the step of processing the dielectric layer by a rotary wet etching method, the number of rotations is about 400 rpm to about 3000 rpm between. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -----: ---.------------ ^ -------- · Line — Φ ------- (Please read the precautions on the back before filling in this page) 531832 A8 B8 C8 D8 VI. Application for patent scope 24 · Shallow trench isolation structure as described in item 23 of the scope of patent application The manufacturing method further includes a drying step after the cleaning step. A nitrogen gas is introduced, and the number of rotations with the rotation is between about 500 irpm and about 3000 rpm. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -________------- r ----------------- -This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
TW90129228A 2001-11-26 2001-11-26 Manufacturing method for shallow trench isolation structure TW531832B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW90129228A TW531832B (en) 2001-11-26 2001-11-26 Manufacturing method for shallow trench isolation structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW90129228A TW531832B (en) 2001-11-26 2001-11-26 Manufacturing method for shallow trench isolation structure

Publications (1)

Publication Number Publication Date
TW531832B true TW531832B (en) 2003-05-11

Family

ID=28787855

Family Applications (1)

Application Number Title Priority Date Filing Date
TW90129228A TW531832B (en) 2001-11-26 2001-11-26 Manufacturing method for shallow trench isolation structure

Country Status (1)

Country Link
TW (1) TW531832B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9257323B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method for forming the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9257323B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method for forming the same
TWI580049B (en) * 2013-03-11 2017-04-21 台灣積體電路製造股份有限公司 Semiconductor device and method for forming the same
US9953878B2 (en) 2013-03-11 2018-04-24 Taiwan Semiconductor Manufacturing Company Method of forming a semiconductor device

Similar Documents

Publication Publication Date Title
KR100459724B1 (en) Semiconductor device having a SiN etch stopper by low temperature ALD and fabricating method the same
TW531832B (en) Manufacturing method for shallow trench isolation structure
JPH11121621A (en) Method of forming self-aligned contact hole
KR20050003758A (en) The method for forming shall trench isolation in semiconductor device
KR100465601B1 (en) A method for forming a semiconductor device
KR20020017764A (en) Method for making capacitor
JPH07302791A (en) Formation of field oxidized film of semiconductor element
KR100305026B1 (en) Manufacturing method of semiconductor device
JP2003298049A (en) Manufacturing method for semiconductor device
JP2001332510A (en) Semiconductor and its manufacturing method
KR100688778B1 (en) Method for manufacturing semiconductor device
KR101204662B1 (en) Method for fabricating transistor in semiconductor device
KR100455094B1 (en) Method of forming an isolation film in semiconductor device
KR100688777B1 (en) Method for manufacturing semiconductor device
KR100929426B1 (en) Dual gate oxide film formation method of semiconductor device
KR100507380B1 (en) Method of forming an isolation layer in a semiconductor device
TW409346B (en) Process avoiding generation of recess in the corner of shallow trench isolation
KR100561974B1 (en) A Manufacturing Method of Semiconductor Element
KR100458120B1 (en) Method for isolating a shallow trench
JP2002289680A (en) Method for forming element isolating structure in semiconductor device
KR20010048349A (en) A method for forming cylindrical storage node in semiconductor device
JPH0878515A (en) Fabrication of semiconductor device
KR20060135222A (en) Method for manufacturing semiconductor device
KR20030000436A (en) Method for manufacturing isolation of semiconductor device
KR20050012652A (en) Method for forming element isolation layer of semiconductor device

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent