JP2002289680A - Method for forming element isolating structure in semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming an element isolating structure in a semiconductor device, which does not cause cracks in heat treatment and can perform an etching process using a reversal pattern with a substantially similar etching rate even if a different reaction chamber is used for deposition, and consequently can increase a production capacity (throughput), while improving the quality of an oxide film for burying element isolating trenches. SOLUTION: In forming the element isolating structure in which a silicon oxide film is filled in trenches formed on the surface of a semiconductor substrate, the surface of the semiconductor substrate, on which the trenches are formed, is pretreated by plasma including N to change the film quality, and then CVD using TEOS and ozone is performed to deposit the silicon oxide film to the inside and outside of the trenches and fill the trenches with the silicon oxide film. Then the silicon oxide film deposited inside and outside the trenches is heat-treated under a specified condition. Consequently, the etching process using the reversal pattern of the silicon oxide film deposited by a different reaction chamber substantially has a similar etching rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buried device isolation method (ShallowTrench) which is one of semiconductor device isolation technologies.
The present invention relates to a method for forming an element isolation structure of a semiconductor device using Isolation (hereinafter, referred to as STI method).

[0002]

2. Description of the Related Art To form an element isolation structure of a semiconductor element,
The STI method is used. Hereinafter, the STI method will be described with reference to the process sectional views shown in FIGS. As shown in these figures, a surface of a semiconductor substrate 10 made of silicon (Si) is oxidized to form an oxide film 12, and a silicon nitride film 14 is deposited thereon (FIG. 6A).
Then, the nitride film 14 is formed by a photolithography process.
A resist pattern 16 having an opening at a position where a separation groove (trench) 18 is to be formed is formed thereon (FIG. 6B).

Subsequently, using the resist pattern 16 as a mask, the nitride film 14, the oxide film 12, and the silicon substrate 10 are etched in this order by dry etching to form an isolation groove 18 in an isolation region. Then, after removing the resist pattern 16, the silicon on the side walls and the bottom surface of the separation groove 18 is thinly thermally oxidized to obtain the separation groove 18 whose surface is covered with the silicon oxide film (FIG. 6C1). Next, a silicon oxide film 20 is formed inside and outside (on the surface of the nitride film 14) of the isolation groove 18 on the semiconductor substrate 10 on which the structure such as the isolation groove 18 is formed, so that the isolation groove is buried. It is deposited (FIG. 6 (d1)).

As a device for filling the isolation groove (trench) 18, for example, a high-density plasma (HDP) CVD device using silane and oxygen as raw materials, ozone and TEOS
Pressure or Sub-Atmosphere using as raw material
ic pressure (SA) CVD equipment
O ₃ -TEOS CVD apparatus).
Hereinafter, O ₃ -TEOS is used for depositing the silicon oxide film 20.
It is assumed that a CVD apparatus is used and O ₃ -TEO
O ₃ -T
It is called an EOS film.

[0005] Thereafter, a chemical mechanical polishing (CMP) method is used.
And the nitride film 14 as a stopper _Three-TEOS film 2
0 is etched back to flatten. Lower half of nitride film 14
The semiconductor substrate surface area is formed by semiconductor elements such as transistors.
This is the active area to be formed. Therefore, the CMP method
In the flattening process, the inside of one semiconductor substrate and the
And multiple devices that are processed simultaneously for semiconductor device manufacturing.
Consistent even considering variations within semiconductor substrates (lots)
The nitride film 14 having the above thickness remains, and the
With the protection region protected, the O _Three-TEO
It is necessary to completely remove the S film 20.

The polishing rate of the nitride film 14 by the CMP method is O
_Since the polishing rate of the _3- TEOS film 20 is slower, the nitride film can be used as a stopper. But,
While the thickness of the O ₃ -TEOS film 20 is about 500 to 1000 nm, the thickness of the nitride film 14 is 100 to 160 n.
Since the thickness is as thin as about m, the range of allowable process condition variation (process margin) is narrow. Also, O ₃ -TEOS
The film has a low resistance to wet etching immediately after deposition. Therefore, in a wet cleaning process or the like after the CMP, the shoulder of the O ₃ -TEOS film 20 buried in the isolation groove 18 is etched, and the current-voltage characteristics of the semiconductor element (transistor) formed in the active region are kinked. The problem of the occurrence of this occurs.

[0007] O_Three -Wet etching of TEOS film 20
O to increase resistance to _Three -TEOS film 20
Heat treatment (annealing) is effective for
You. However, due to this heat treatment, two new
Problems arise. (1) By heat treatment, O_Three -The TEOS film 20 contracts
Cracks in the film. (2) O_Three -Chemical polishing of TEOS film 20
The polishing speed is reduced, and the process margin is further reduced.

For this reason, as disclosed in, for example, Japanese Patent No. 2687948, after an isolation groove 18 is buried with an oxide film, an inverted pattern (a mask used for forming the isolation groove) is formed before polishing by a CMP method. (A pattern obtained by inverting the above pattern) to remove an oxide film on the active region. That is, FIG.
After depositing the O ₃ -TEOS film 20 on the silicon substrate 10 so that the inside of the separation groove 18 is buried as shown in (d1), as shown in FIG. A resist pattern (inversion pattern 22) having an opening in a portion to be a region is formed.

Using the inverted pattern 22 as a mask, O ₃ − deposited on the surface of the nitride film 14 on the active region is used.
After removing the TEOS film 20 entirely or by a predetermined thickness by dry etching such as plasma etching, the inverted pattern 22 is removed. At this time, a projection 24 is formed in the separation region (FIG. 7 (f1)). After this, CMP
Using the nitride film 14 as a stopper, the O ₃ -TEOS film 2 is etched back until the surface of the nitride film 14 is exposed.
0 is flattened (FIG. 7 (g)). Thereafter, the nitride film 14 and the oxide film 12 are peeled off to form an active region.

By adopting such a method,
O on the surface of the nitride film 14_Three -When the TEOS film 20 is small
Is also partially removed and the film thickness is reduced,
The amount of CMP polishing is reduced, and the process
Gin is enlarged. Also, O _Three-Heat treatment of TEOS film 20
Naturally, etching is performed using the inverted pattern 22 as a mask.
It is conceivable to do it after a while. That is, FIG.
Heat treatment is performed in the state of 1), and heat treatment O_Three-TEOS film 2
1 (FIG. 7 (f2)). Nitride film 1
O deposited on the surface of No. 4_Three -When the TEOS film 20 is small
Is also partially removed and O on the nitride film 14 is removed._Three -TEOS film 2
By performing the heat treatment in a state where the film thickness of 0 is thin,
O_Three -Crack due to shrinkage of TEOS film 20
It is expected to get worse.

[0011] However, O ₃ -TE
When the embedding of the OS film 20 is performed in a plurality of reaction chambers (chambers), a difference in film quality occurs between the reaction chambers. In particular, this tendency is remarkable in a film deposited by a normal pressure (or SA) O ₃ -TEOS CVD apparatus. Therefore, the etching speed using the inversion pattern is different for each reaction chamber. For this reason, even when the film thicknesses in the respective reaction chambers are made uniform when the O ₃ -TEOS film 20 is buried in the separation grooves 18, the remaining film thickness after etching using the inversion pattern is different for each reaction chamber. The result is different. Due to this difference in film thickness, the process margin of the CMP process is narrowed. Therefore, when the O ₃ -TEOS film 20 is buried in the separation trenches 18 of a plurality of different semiconductor substrates in a plurality of different reaction chambers, a sufficient process margin cannot be secured and a normal CMP process cannot be performed. The problem arises. Therefore, the separation groove 1 by the O ₃ -TEOS film 20
For example, it is necessary to limit the embedding into the reaction chamber 8 in a single reaction chamber.

Incidentally, for example, Japanese Patent Application Laid-Open No. 2000-12674
In Japanese Patent Application Laid-Open No. H10-264, after a second CVD oxide film such as an O ₃ -TEOS film as an insulating material is buried in a shallow groove, a heat treatment is performed before polishing by a CMP method, so that an STI buried CTI film is formed.
It is disclosed that the VD oxide film is densified. In the planarization method described in this publication, a CVD oxide film is deposited in a shallow groove and on a first nitride film, and then a second nitride film is further deposited thereon, and a photoresist is deposited thereon. After coating, the second nitride film on the element region is removed by photolithography, and the protrusion of the CVD oxide film is exposed on the active region.
The oxide film is densified, and then the protrusion is removed by CMP using the first and second nitride films as stoppers to planarize the oxide film. It is disclosed that the heat treatment may be performed immediately after the trench is filled with the CVD oxide film. However, in the flattening method described in this publication, although etching using an inverted pattern is performed, only the second nitride film is etched, and the oxide film is not etched. Therefore, the protrusions of the oxide film are formed not in the isolation region but in the active region. Further, this publication does not disclose cracking of an oxide film during heat treatment or a difference in film quality between a plurality of reaction chambers, and does not disclose any solution to these problems.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, to prevent the occurrence of cracks during heat treatment and to form a silicon oxide film such as an O ₃ -TEOS film on a plurality of semiconductor substrate surfaces. Even if the deposition of each is performed using different reaction chambers, it is possible to make the rate of etching and the like using a reverse pattern constant, and to use a plurality of reaction chambers for depositing a silicon oxide film, It is an object of the present invention to provide a method for forming an element isolation structure of a semiconductor device, which can improve production capacity (throughput).

[0014]

According to the present invention, there is provided a method for forming an element isolation structure in which a silicon oxide film is buried in a groove formed on a surface of a semiconductor substrate. CVs made of TEOS and ozone as raw materials inside and outside the grooves on the surface of the semiconductor substrate where the grooves are formed.
D, depositing the silicon oxide film to bury the groove, and a heat treatment step of heat treating the silicon oxide film deposited inside and outside the groove on the surface of the semiconductor substrate under specific conditions; An etching step of etching a portion of the heat-treated silicon oxide film using a reverse pattern of the groove as a mask, wherein the silicon oxide film on the different semiconductor substrate has been subjected to the deposition step and the heat treatment step, respectively. A method for forming an element isolation structure, wherein the etching rates in the etching step are substantially the same.

It is preferable that the deposition step is performed on the different semiconductor substrates in different reaction chambers.

Further, the present invention is a method for forming an element isolation structure in which a silicon oxide film is buried in a groove formed on a surface of a semiconductor substrate, the method comprising: A deposition step of depositing the silicon oxide film by performing CVD using TEOS and ozone as raw materials inside and outside the groove, and embedding the groove, and the silicon oxide film deposited inside and outside the groove on the surface of the semiconductor substrate 95
A method for forming an element isolation structure, comprising: a heat treatment step of performing a heat treatment at a temperature of 0 ° C. or more; and an etching step of etching a part of the heat-treated silicon oxide film using a reverse pattern of the groove as a mask. To provide.

Here, before depositing the silicon oxide film,
It is preferable that the method further includes a pretreatment step of modifying a surface of the semiconductor substrate in which the groove is formed. Further, it is preferable that the surface of the semiconductor substrate is modified by treating the surface of the semiconductor substrate with a plasma containing nitrogen.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for forming an element isolation structure of a semiconductor device according to the present invention will be described in detail below with reference to preferred embodiments shown in the accompanying drawings.

According to the method for forming an element isolation structure of a semiconductor device of the present invention, before embedding a groove formed on the surface of a semiconductor substrate with a silicon oxide film, the surface (inside and outside of the groove) of the semiconductor substrate formed with this groove is formed. Pretreatment is performed with plasma containing nitrogen for reforming. A silicon oxide film is deposited by performing CVD using TEOS and ozone as raw materials inside and outside the grooves on the surface of the semiconductor substrate pretreated as described above to fill the grooves. Subsequently, a silicon oxide film deposited on the inside and outside of the groove on the surface of the semiconductor substrate is subjected to a heat treatment under a specific condition, whereby a reverse pattern to be performed later on the silicon oxide film deposited on a different semiconductor substrate is performed. The present invention is characterized in that the utilized etching rates are made substantially the same.

FIGS. 1 and 2 are sectional views showing the steps of an example of a method for forming an element isolation structure of a semiconductor device according to the present invention. The method for forming the element isolation structure of the semiconductor device of the present invention shown in FIGS. 1 and 2 is based on the conventional method for forming the element isolation structure of the semiconductor device shown in FIGS. Pretreatment step (c2) and heat treatment step (d
2) and a heat treatment step (f2) of the conventional method, and a similar step except for a difference in film quality due to these treatments. Similar steps and elements are denoted by the same reference numerals, and a detailed description thereof will be omitted.

In the method of forming an element isolation structure according to the present invention, as shown in FIGS. 1 (a) to 1 (c1), FIGS.
After forming a thermal oxide film 12 and a silicon nitride film 14 on a semiconductor substrate 10 as in the conventional method shown in FIG.
1A, a resist pattern 16 having an opening in an isolation region on the nitride film 14 is formed by a photolithography process (FIG. 1B). After the separation groove 18 is formed by etching and the resist pattern 16 is removed, the thin thermal oxide film 12 is formed on the side wall and the bottom surface of the separation groove 18.
Is formed (FIG. 1 (c1)).

Next, the isolation groove 18 of the Si substrate 10 is formed by a silicon oxide film (hereinafter, represented by an O ₃ -TEOS film).
Prior to the embedding with 20, as a pretreatment, the isolation groove 18 having the thin thermal oxide film 12 formed on its side wall and bottom surface and the nitride film 14 on the substrate surface outside the isolation groove 18 are plasma-treated using a gas containing nitrogen. To process. This pretreatment step is one of the characteristic steps of the method for forming an element isolation structure of the present invention, and includes N before performing the O ₃ -TEOS film deposition step shown in FIG. The surface of the semiconductor substrate is modified by performing a plasma pretreatment on the surface of the semiconductor substrate using a gas. That is, the thermal oxide film 12 on the side wall and bottom surface of the isolation groove 18 is modified into a surface-modified thermal oxide film 13, and the nitride film 14 outside the isolation groove 18 is modified into a surface-modified nitride film 15 (FIG. 1).
(C2)). Thus, the surface of the semiconductor substrate serving as the base of the O ₃ -TEOS film 20 deposited in the deposition step shown in FIG. 1D1 is modified, and as a result, the surface-modified thermal oxide film 13 and the surface of the surface of the semiconductor substrate 10 are modified. The quality of the O ₃ -TEOS film 20 deposited on the modified nitride film 15 is improved.

More specifically, by subjecting the surface of the semiconductor substrate to plasma pretreatment with a gas containing nitrogen, a heat treatment step (see FIG. 2 (d2)) which is another characteristic step of the method of the present invention described later. ) O ₃ -TEOS film 2
A heat shrinkage of 0 decreases. Thereby, O ₃ -TEOS
Even when the film 20 is heat-treated while the film thickness is still large, that is, in a state where etching using an inversion pattern described later (see FIG. 2 (f1)) is not performed, O ₃ -TEOS
The generation of cracks in the film is prevented.

In the method for forming an element isolation structure according to the present invention, the gas containing nitrogen used for the plasma pretreatment is typically N ₂ or NH ₃ . This plasma pretreatment step can be performed using a general parallel plate type plasma generator used for plasma CVD or plasma etching. However, the gas containing N that can be used is limited by the method of applying high-frequency power.

In the case of an upper electrode applied type plasma generator, the lower electrode is grounded, and no self-bias is applied to the substrate disposed on the lower electrode side. Therefore, when using relatively dissociated difficult N _2, insufficient active species that can reach the substrate, it may be impossible to obtain a sufficient modification effect. Therefore, the gas containing nitrogen is preferably NH ₃ which is relatively easily dissociated. On the other hand, in the case of a lower electrode application type in which a high voltage is applied to the lower electrode on which the substrate is disposed, a self-bias is applied to the substrate side, so that N ₂ which is relatively hard to dissociate in a gas containing nitrogen is used. However, the active species efficiently reach the substrate, and a sufficient modifying effect can be obtained. Therefore, when a lower electrode application type device is used, any of NH ₃ and N ₂ may be used as the gas containing nitrogen.

In the method for forming an element isolation structure according to the present invention,
The RF power required for this plasma processing is as described above.
It depends on the method of electrode application of the device. Set the electrode side
In the case of an upper electrode applied type device that does not have a
If the gas containing nitrogen is NH_ThreeRF500W or more using
It is necessary to perform a plasma treatment. On the other hand, the cell
In the case of a lower electrode application type device to which bias is applied, nitrogen
As a gas containing _ThreeOr N_TwoUse one of
Therefore, the plasma processing may be performed at an RF of 100 W or more.
However, if the self-bias is too strong, the underlying film may be hit by ions.
Since there is a danger of being damaged by the impact of
Implement with a bias of -100V to -300V.
Preferably. When self bias is less than -100V
Is O_Three -Eliminating the underlayer dependence of the TEOS film 20
And self-bias exceeding -300 V
The underlayer is damaged by the impact of the implantation.

Next, a plurality of semiconductor substrates whose surfaces have been modified by the pretreatment process are prepared, and an O ₃ -TEOS film 20 is deposited thereon using different reaction chambers, thereby forming the separation grooves 18. Embedding (see FIG. 1 (d1)). That is, this O ₃ -TEOS film deposition step is performed so that the inside of the isolation trench 18 is buried so that the surface of the surface-modified thermal oxide film 13 and the surface-modified nitride film 14 inside the isolation trench 18 on the semiconductor substrate 10 are buried. This is a step of depositing a silicon oxide film 20 on the entire upper surface. Here, the plurality of reaction chambers are reaction chambers having the same structure provided in the same CVD apparatus, and the set values of the deposition conditions are also the same. However, in reality, the deposition rates differ from one another due to individual differences between the reaction chambers, and the film quality of the deposited films also differs from one another, as described later. Regarding the difference in the deposition rate, the deposition rate on the monitor substrate (a silicon substrate on which the grooves 18 and the thermal oxide film 12 and the nitride film 14 are not formed) is measured in advance, and the deposition time is adjusted. This can be solved by doing so. That is, O ₃ -TEO deposited on a plurality of substrates
The mutual difference in the thickness of the S film can be suppressed. However, in order to eliminate the difference in film quality, it is necessary to perform heat treatment under specific conditions, as described later.

Subsequently, before the O ₃ -TEOS film etching process using an inversion pattern described later (see FIGS. 2E and 2F), the O ₃ -TEOS film 20 is heat-treated under specific conditions. Thus, a heat-treated O ₃ -TEOS film 21 is formed (see FIG. 2D2). This heat treatment step is another characteristic step of the method of the present invention. In the heat treatment step, the etching rate of the O ₃ -TEOS film 21 on a different semiconductor substrate in an etching process using an inverted pattern (see FIG. This is a step for making them substantially the same.

[0029] The specific conditions are as follows: O ₃ -TEO
Cr is not generated in the S film 20 and O on the different semiconductor substrate at the time of etching using the reverse pattern.
_This is a condition under which the etching rate of the _3- TEOS film 21 becomes substantially the same. Here, it has been confirmed that the etching rate at the time of etching using an inverted pattern generally performed using a fluorine-based gas is affected by the stress of the O ₃ -TEOS film 21. Therefore, if the heat treatment conditions under which the stress of the O ₃ -TEOS film 21 becomes substantially the same are selected, substantially the same etching rate can be obtained.

FIG. 3 shows the stress of the O ₃ -TEOS film deposited using three different reaction chambers (chambers 1, 2, 3) when the heat treatment time was changed at 1000 ° C. in an N ₂ atmosphere. Shows the change in As is clear from the figure, when heat treatment is performed in an N ₂ atmosphere, O ₃
-The stress of the TEOS film changes abruptly, but after a heat treatment of about 5 minutes, the change becomes gentle and approaches a constant value. Also, O ₃ -TEO deposited using different reaction chambers
The difference in stress between the S films is also reduced by performing the heat treatment. That is, by performing the heat treatment at 1000 ° C. for about 5 minutes or more, preferably about 20 minutes or more, the plasma etching rates of the O ₃ -TEOS films deposited using different reaction chambers can be made substantially the same.

FIG. 4 shows a change in polishing rate (polishing rate) in the CMP process at the same heat treatment temperature for reference. From FIG. 4, it can be confirmed that the etching rate in the CMP treatment also shows the same tendency as the stress of the O ₃ -TEOS film shown in FIG. That is, the etching rate sharply decreases at first, gradually changes after about 5 minutes, approaches a constant value, and the difference between different reaction chambers decreases.

On the other hand, the heat treatment needs to be performed under the condition that no crack occurs in the O ₃ -TEOS film. O ₃ -TEO
The occurrence of cracks in the S film has been found to be related to the stress and shrinkage of the film, and as the stress and shrinkage increase, the likelihood of cracking increases. FIG. 3 shows that as the heat treatment time increases, the O ₃ -TEO
It can be confirmed that the stress of the S film increases. 5, N ₂
It shows the change in the shrinkage of the O ₃ -TEOS film when the heat treatment time is changed at 1000 ° C. in an atmosphere, and also shows the same tendency as the change in the stress. That is,
At first, the contraction rate sharply increases, but after about 5 minutes, the change becomes gentle and approaches a constant value. However, since the film quality at the time of deposition differs between the reaction chambers, the difference in the shrinkage between the reaction chambers is not reduced even if the heat treatment time is lengthened.

With reference to these measurement results, O ₃ -T
It is sufficient to select heat treatment conditions that are substantially the same on semiconductor substrates having different etching rates when etching using an inverted pattern without causing cracks in the EOS film. In the method for forming an element isolation structure of the present invention, the heat treatment is preferably performed at a temperature of 950 ° C. or higher, more specifically, at 950 to 1100 ° C. for 20 to 40 ° C.
The procedure is carried out in the range of minutes.

Here, when the surface of the semiconductor substrate was not subjected to the reforming treatment by the plasma containing nitrogen, cracks occurred even under the heat treatment condition of lower temperature and shorter time than the case where the modification treatment was performed. For this reason, within the scope of the experiment,
O deposited in different reaction chambers without cracking
No condition was found in which the etching rate in the etching process using the reverse pattern of the _3- TEOS film was made substantially the same. On the other hand, it was also studied to change the conditions of the reforming treatment using the plasma containing nitrogen to suppress the difference in the film quality of the O ₃ -TEOS films deposited in different reaction chambers without heat treatment. However, as long as the base film was not damaged, deposition was performed in a different reaction chamber without heat treatment. O ₃ −
The etching rate of the TEOS film could not be made substantially the same.

That is, in order to make the etching rates of O ₃ -TEOS films deposited in different reaction chambers substantially the same without causing cracks in the range where the experiment was performed, it is necessary to use the O ₃ -TEOS film. Before the deposition, it was necessary to perform a modification treatment of the substrate surface under appropriate conditions, and further to perform a heat treatment under appropriate conditions after the deposition. As a heat treatment atmosphere, nitrogen can be typically used.
However, it is also possible to use an atmosphere other than nitrogen, such as argon and oxygen.

As shown in FIG. 2E, a heat treatment is performed on the heat-treated O ₃ -TEOS film 21 which has been heat-treated under specific conditions to have desired characteristics, as shown in FIG. Next, a reverse pattern 22 made of a resist is formed by a photolithography process. Next, using the inverted pattern 22 as a mask, a heat treatment O ₃ on the active region is performed.
After the TEOS film 21 is at least partially removed by plasma etching using a fluorine-based gas, the inversion pattern 22 is removed. At this time, the projections 24
Is formed (see FIG. 2 (f1)).

By setting the etching film thickness, it is possible to remove all the heat-treated O ₃ -TEOS film on the active region and expose the surface of the surface-modified nitride film 15. It is also possible to leave the heat-treated O ₃ -TEOS film on the active region thin. In consideration of the purpose of the above-described inversion pattern etching, it is preferable to increase the thickness of the etched film as much as possible in order to reduce the thickness of the O ₃ -TEOS film, increase the process margin of the CMP process, and prevent cracks. Can be expected to be preferable. However, in reality, the O ₃ -TEO deposited on the active area
The thickness of the S film is not constant, depends on the size and density of the groove, and varies within the semiconductor substrate. Accordingly, the average deposition thickness portion of the O ₃ -TEOS film to set the etching thickness to be removed completely, O ₃ -TEOS
In the portion where the film thickness is small, the surface of the surface-modified nitride film 15 is exposed to plasma for etching the O ₃ -TEOS film for a long time, causing the film thickness to decrease and suffering plasma damage. In the nitride film thus damaged, C
The ability as a stopper in the MP processing is reduced, and conversely, the process margin is narrowed. Therefore, in general, O ₃
It is preferable to set the etching film thickness such that the O ₃ -TEOS film slightly remains or is removed even at the thinnest portion within the range of the variation in the deposited film thickness of the −TEOS film.

At this time, the heat-treated O ₃ -TEOS film 21
The etch rates are substantially the same even when deposited in different reaction chambers. Therefore, if the deposited film thickness is made uniform, the O ₃ -TEOS film 21 having the same film thickness can be left, and the subsequent CMP process can be easily performed.
Subsequently, the O ₃ -TEOS film 2 on the surface-modified nitride film 15 is formed by CMP using the surface-modified nitride film 15 as a stopper.
The O ₃ -TEOS film 21 is planarized by CMP until 1 is completely removed (FIG. 2G). Thereafter, the surface-modified nitride film 15 and the oxide film 12 are peeled off to form an active region. The method for forming an element isolation structure of a semiconductor device according to the present invention is basically configured as described above.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for forming an element isolation structure of a semiconductor device according to the present invention will be specifically described below based on embodiments. In this embodiment, the depth of the isolation groove 18 is 400 nm, and the thicknesses of the pad oxide film 12 and the nitride film 14 are 13 nm and 150 nm, respectively.
Three semiconductor substrates having the structure shown in FIG. 1A were manufactured, and processed according to the following procedure. (1) Modification of semiconductor substrate surface using gas containing nitrogen (2) Deposition of O ₃ -TEOS film using different reaction chamber (3) Heat treatment (4) O ₃ -TEOS film using inversion mask Etching (5) CMP

First, in the step of FIG. 1 (c2), plasma treatment was performed under the following conditions using an upper electrode power application type device using NH ₃ as a N-containing gas. N ₂ : 1494 sccm NH ₃ : 71 sccm RF power: 700 W Pressure: 5 Torr Electrode interval: 400 mils Processing time: 30 sec

Subsequently, as a step of FIG. 1 (d 1), a normal pressure O ₃ -TEOS C
By using different reaction chambers (chambers 1, 2, 3) of the VD apparatus, O was formed on the monitor substrate so as to have a film thickness of 700 nm.
_{A 3-} TEOS film 20 was deposited. Next, FIG. 2 (d2)
As a step, the semiconductor substrate on which the O ₃ -TEOS film 20 was deposited was heat-treated at 1000 ° C. for 30 minutes in an N ₂ atmosphere. In the microscopic inspection after the heat treatment, the O ₃ -TEOS film 21
Did not show any cracks. Next, FIG.
(E) and an etching process using a reversal mask in the procedure of the process shown in FIG. 2 (f1) using a parallel plate type reactive ion etching (RIE) device using a CF ₄ / CHF ₃ type etching gas. Was carried out. O ₃ -TE
The etching time was set so that the etching thickness of the OS film became 500 nm. At this time, an O ₃ -TEOS film of approximately 200 nm, which is the difference between the above-described deposited film thickness and the etched film thickness, remains on the wide active region. The remaining film thickness in other parts may be different from this. For example, on the narrow active region adjacent to the separation groove, the residual film thickness is small because the deposited film thickness is smaller than the deposited film thickness on the monitor substrate. At this time, O ₃ -TEO deposited in different reaction chambers
No significant difference was found in the etching rate between the S films (chamber 1: 437.0 nm / min, chamber 2: 436.8 nm / min, chamber 3: 436.
5 nm / min).

Thereafter, as a step of FIG.
The O ₃ -TEOS film outside the groove was removed by the method. CMP
No significant difference was observed between the reaction chambers in the amount of the remaining nitride film on the semiconductor substrate after the treatment (chamber 1: 7).
5.3 nm, chamber 2: 75.9 nm, chamber 3: 75.7 nm). From these results, according to the method for forming an element isolation structure of the present invention, even when an O ₃ -TEOS film is deposited on a semiconductor substrate surface using a different reaction chamber, the etching rate using an inversion pattern is improved. Are substantially the same. Therefore, if the deposited film thickness of the O ₃ -TEOS film during film formation is controlled to be the same, it is guaranteed that the remaining film amount of the nitride film after the CMP process is substantially the same. Thereby, in the manufacture of a semiconductor device, O ₃ -T
The deposition of the EOS film can be performed in a plurality of different reaction chambers, which contributes to an improvement in the production capacity of the semiconductor device.

(Reference Example) As a reference example, an element isolation structure was formed by a procedure in which steps (3) and (4) of the example were interchanged. The procedure for forming the element isolation structure in the reference example is as follows.
It is as follows. In addition, the procedure up to the formation of the separation groove and the thermal oxidation of the separation groove side wall and the bottom surface is described in Example 1.
And the same. (1) Surface modification of semiconductor substrate using nitrogen-containing gas (2) Deposition of O ₃ -TEOS film using different reaction chamber (3) Etching of O ₃ -TEOS film using inversion mask (4) Heat treatment (5) CMP

Here, the process margins of the above Examples and Reference Examples were evaluated under the following conditions. First, the specification of the remaining film thickness of the nitride film after CMP is set to 8
5 ± 25 nm. In addition, the following values were assumed based on the actual values as variations in film formation due to deposition of the O ₃ -TEOS film in a plurality of reaction chambers. -Adjustable range of average film thickness in each reaction chamber: 700 ± 8 nm-Fluctuation of average film thickness in lot (25 sheets) due to continuous film formation: ± 10 nm-Uniform specification of in-plane film thickness: 5% or less ( In-plane fluctuation range 7
0 nm)

Further, the following values were also assumed for the MP process based on the actual values. The variation at the time of depositing the O ₃ -TEOS film is maintained until just before the CMP. The CMP process is performed so that the average film thickness in the lot becomes the center value, and the variation of the average film thickness in the lot due to the CMP process is 1.5 nm. The polishing rate ratio between the nitride film and the O ₃ -TEOS film in the CMP process is 0.35. After the CMP process, a nitride film thickness variation width of の of the in-plane film thickness variation width at the time of depositing the O ₃ -TEOS film occurs.

The estimation results based on the above preconditions are as follows:
It is as follows.・ In-plane from allowable width (50nm for nitride film) in CMP processing
(O) _Three-In-plane uniformity during TEOS film deposition
1 with 70 nm in-plane fluctuation width when the uniformity is set to the upper limit of 5%
/ 35 nm) was subtracted from the in-lot wafers.
This is the allowable width allowed for the film thickness average of C.・ Allowable width of 15 nm for average film thickness of wafers in lot
(Nitride film)_ThreeThe value converted with the TEOS film is 42.9.
nm (15 nm / 0.35). -Allowable width 42.9 allowed for average film thickness of wafers in lot
nm to O_Three-Control between chambers of TEOSCVD equipment
Subtracting the adjustment error and the fluctuation due to continuous film formation, 6.9 nm
(42.9-36.0 nm). This 6.9nm
Of the fluctuation width of the average thickness in the lot in the CMP process_Three-T
EOS film equivalent value (1.5 nm (nitride film) ÷ 0.35 =
4.3 nm (O_Three2.6 minus (TEOS film))
nm is O using an inversion mask._Three-Edge of TEOS film
This is the variation width of the film thickness in the lot allowed in the chucking process.

[0047] In the reference example was carried by interchanging some steps of _Example, O 3 O ₃ with -TEOS CVD apparatus -
When the deposition of the TEOS film was performed in a plurality of reaction chambers, the actual variation in the average thickness in the lot in the etching process of the O ₃ -TEOS film using the inversion mask was about 7.0 nm. Therefore, the above tolerance cannot be satisfied. On the other hand, in the example using the method of the present invention, the actually measured value of the fluctuation width of the in-lot film thickness in the etching step of the O ₃ -TEOS film using the reverse pattern was 1.0 nm or less. In other words, it can be seen that the etching rate using the reverse pattern can be made substantially the same in the sense that the above-mentioned allowable value can be satisfied. This allows O
It has been confirmed that the deposition of the _3- TEOS film can be performed in a plurality of reaction chambers.

In the above embodiment, the O ₃ -TE is formed on each of a plurality of semiconductor substrates by using a plurality of different reaction chambers.
An OS film was deposited. Then, by performing heat treatment under specific conditions, the etching rates of the O ₃ -TEOS films on different semiconductor substrates in the etching process using the inverted pattern were made substantially the same. As described above, in an oxide film deposited using a normal pressure (or SA) O ₃ -TEOS CVD apparatus, there is a large difference in film quality between reaction chambers. In fact, in the above reference example, the allowable value of the thickness variation width within the lot could not be satisfied, and it was essential to use the method of the present invention. However, even if the O ₃ -TEOS film is deposited using the same reaction chamber, there may be a difference in film quality on different semiconductor substrates depending on various conditions. In order to eliminate such a difference in film quality and to increase the process margin, O ₃ −
Even in the case of depositing a TEOS film, the method of the present invention in which heat treatment is performed under specific conditions before etching using an inverted pattern to make the etching rates substantially the same is effective.

As described above, in the range where the experiment was performed, the surface of the semiconductor substrate was modified by performing a pretreatment with a plasma containing nitrogen before depositing the O ₃ -TEOS film by a heat treatment. It is necessary to make the etching rates using the inverted pattern of the O ₃ -TEOS films deposited on different semiconductor substrates substantially the same without causing cracks. However, the modification of the surface of the semiconductor substrate can be performed by a method other than the plasma treatment containing nitrogen. For example, by depositing a silicon oxide film containing nitrogen by a plasma CVD method, the state of the surface of the semiconductor substrate can be adjusted, that is, reformed. Naturally, if the improvement of the O ₃ -TEOS CVD technique can suppress the occurrence of cracks without modifying the surface of the semiconductor substrate, it is possible to perform a pretreatment for modifying the substrate surface. No longer required. Even in this case, the method of the present invention in which heat treatment is performed under specific conditions before etching using the inverted pattern to make the etching rates substantially the same is effective for increasing the process margin.

[0050]

As described in detail above, according to the present invention,
The etching rate in the etching step of the silicon oxide film using the inversion mask can be made substantially the same without being affected by the difference in the reaction chamber used for depositing the silicon oxide film such as the O ₃ -TEOS film. . Therefore, according to the present invention, even when a silicon oxide film is deposited on a plurality of semiconductor substrates in different reaction chambers, by controlling the thickness of the silicon oxide film during deposition to be the same, The remaining film thickness after etching using an inverted pattern and the remaining film thickness after the subsequent CMP process do not cause a difference between semiconductor substrates, and the remaining film thickness of the nitride film is substantially the same. Can be. Thus, according to the present invention, in the manufacture of a semiconductor device, a silicon oxide film such as an O ₃ -TEOS film can be deposited in a plurality of different reaction chambers, and the production capacity of the semiconductor device can be improved. it can.

[Brief description of the drawings]

FIGS. 1A to 1D are process cross-sectional views illustrating an example of a method for forming an element isolation structure of a semiconductor device according to the present invention.

2 (d2) to 2 (g) are process cross-sectional views showing a continuation of FIG.

FIG. 3 shows the relationship between the stress of an O ₃ -TEOS film and N ₂ atmosphere;
It is the graph which showed the relationship with the time of heat processing at 000 degreeC.

FIG. 4 shows a CMP rate of an O ₃ -TEOS film and N
₄ is a graph showing the relationship between the time of heat treatment at 1000 ° C. under _two atmospheres.

FIG. 5 shows the contraction rate of the O ₃ -TEOS film and the N ₂ atmosphere.
It is the graph which showed the relationship with the time of 1000 degreeC heat processing.

FIGS. 6A to 6D are process cross-sectional views illustrating a conventional method for forming an element isolation structure of a semiconductor device.

7 (e) to 7 (g) are process cross-sectional views showing a continuation of FIG.

[Explanation of symbols]

10 a silicon substrate 12 oxide film 13 surface modified thermally oxidized film 14 a silicon nitride film 15 surface-modified silicon nitride film 18 separation groove 20 O ₃ -TEOS film 21 heat treatment O ₃ -TEOS film 22 reverse pattern 24 protrusion

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yasuhiro Takenaka 2-3-2 Uchisaiwai-cho, Chiyoda-ku, Tokyo F-term (reference) 5F032 AA34 AA44 AA45 AA77 DA04 DA22 DA23 DA26 DA58 DA74 DA78 5F058 BE10 BF02 BF25 BF29 BH04 BH12 BJ06

Claims (5)

[Claims] 1. A method for forming an element isolation structure in which a silicon oxide film is buried in a groove formed on a surface of a semiconductor substrate, wherein the device isolation structure is formed inside and outside the groove on a surface of the semiconductor substrate having the groove formed. A step of depositing the silicon oxide film by performing CVD using TEOS and ozone as raw materials and filling the groove, and the silicon oxide film deposited inside and outside the groove on the surface of the semiconductor substrate under specific conditions. A heat treatment step of performing a heat treatment underneath, and an etching step of etching a portion of the heat-treated silicon oxide film using a reverse pattern of the groove as a mask. An etching speed of the silicon oxide film on the semiconductor substrate in the etching step is substantially the same. Forming method. 2. The method according to claim 1, wherein the deposition step is performed on the different semiconductor substrates in different reaction chambers. 3. A method for forming an element isolation structure in which a silicon oxide film is buried in a groove formed on a surface of a semiconductor substrate, wherein the element isolation structure is formed on a surface of the semiconductor substrate having the groove formed inside and outside the groove. Depositing the silicon oxide film by performing CVD using TEOS and ozone as raw materials, and filling the trench with the silicon oxide film; and depositing the silicon oxide film deposited inside and outside the trench on the surface of the semiconductor substrate at 950 ° C. or higher. A method of forming an element isolation structure, comprising: a heat treatment step of performing a heat treatment at a temperature of; and an etching step of etching a part of the heat-treated silicon oxide film using the inverted pattern of the groove as a mask. 4. The method for forming an element isolation structure according to claim 1, further comprising modifying a surface of the semiconductor substrate in which the groove is formed before depositing the silicon oxide film. A method of forming an element isolation structure, comprising: 5. The method according to claim 4, wherein the surface of the semiconductor substrate is modified by treating the surface of the semiconductor substrate with a plasma containing nitrogen.