JP2000349144A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flatten an embedded material by an STI method without damaging an element region or degrading a flattening process by refraining from etching- removal of the film of an embedded material deposited on the element region of the specified width or less. SOLUTION: With a place where the width of an element region is narrow while that of a separation channel is wide provided, the film-thickness of an embedded material 20 deposited over it is thinner than that of the embedded material 20 deposited on the element region except for it. Related to an inverted pattern 22, a place of an element region whose width is narrower than a specified dimension is not opened. With the inverted pattern 22 as a mask, the embedded material 20 is etched. The place of a narrow element region is not etched since it is masked with the inverted pattern 22. When the embedded material 20 is flattened, by a CMP method, a protruding part comprising the embedded material 20 which is on the narrow element region is firstly scraped, and then polishing proceeds as a whole for flattening, resulting in good flatness after releasing of the nitride film 14 and a pad oxide film 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buried device isolation method (ShallowTrench) which is one of semiconductor device isolation technologies.
Isolation (hereinafter, referred to as STI method).

[0002]

2. Description of the Related Art The above-mentioned STI method is used as an element isolation technique for a fine LSI. Hereinafter, the STI method will be described with reference to a process cross-sectional view shown in FIG. As shown in FIG. 1, first, the surface of a silicon (Si) substrate 10 is oxidized to form a pad (PAD) oxide film 12, and a silicon nitride film 14 is deposited thereon (FIG. 10A). By the photolithography process, on this nitride film 14,
A resist pattern 1 having an opening at a location to be an isolation region
6 is formed (FIG. 10B).

Subsequently, using the resist pattern 16 as a mask, the nitride film 14, the pad oxide film 12, and the silicon substrate 10 are etched in this order by dry etching to form an isolation groove 18, and then the resist pattern 16 is removed. The silicon on the side wall of the isolation groove 18 is thinly thermally oxidized (FIG. 1).
0 (c)). Subsequently, for example, O ₃ -TEOS (OzoneTet
ra-Ethyl-Ortho-Silicate) CVD (Chemical Vapor De
position), the inside of the isolation groove 18 and the nitride film 1 are formed.
A film 20 of a filling material (in this case, a silicon oxide film) is deposited on the entire surface of the substrate 4 (FIG. 10D).

After that, the CMP (Chemical Mechanical Po
lishing) method, using the nitride film 14 as a stopper.
The burying material film 20 is flattened by etching back. Here, the burying material film 20 deposited on the surface of the nitride film 14
For example, Japanese Patent No. 2687948 discloses that a buried material film on an element region is anisotropically etched before polishing by a CMP method because the CMP characteristics are different depending on the element region pattern. It has been proposed to etch away 20.

Referring to FIG. 11, a buried material film 20 is formed according to the method of manufacturing a semiconductor device disclosed in the publication.
Will be described. As shown in FIG.
After depositing an oxide film 20 as an embedding material inside the isolation groove 18 and the entire surface of the nitride film 14, a resist pattern in which a portion to be an element region is opened by a photolithography process, that is, a reverse pattern 22 of the resist pattern 16 Is formed (FIG. 11E).

Using the inverted pattern 22 as a mask, the buried material film 20 deposited on the entire surface of the nitride film 14 is etched, and then the inverted pattern 22 is removed. At this time, a projection 24 is formed in the separation region.
(F)). Subsequently, the buried material film 20 is flattened by CMP using the nitride film 14 as a stopper until the surface of the nitride film 14 is exposed (FIG. 11).
(G)). Thereafter, the nitride film 14 and the pad oxide film 12
Is peeled off to form an element region.

In the CMP method, since the minute projections 24 have the property of being quickly polished and removed, the flattening of the buried material film 20 is facilitated according to the method of manufacturing a semiconductor device disclosed in the same publication. There are advantages. By the way, as a method of depositing the filling material of the STI method, the above-mentioned O ₃ -TE
The OS CVD method or the like is used, but the deposited film thickness differs depending on the underlying element region pattern as described above.

As shown in FIG. 12, when the width of the element region is sufficiently large, O ₃ -TEOS CVD
The film thickness is normal (FIG. 12A). That is, this is equivalent to the case where the deposition is performed on a substrate having no pattern.
Also, when the width of the isolation groove is sufficiently small (when the element regions are densely packed), the O ₃ -TEOS CV
The degree of decrease in the film thickness of the D film is small (FIG. 12B). However, when the width of the element region is small and isolated (when the width of the isolation groove is wide), the thickness of the O ₃ -TEOS CVD film deposited on the element region is significantly reduced (see FIG. 12 (c)).

[0009] Such a change in film thickness is caused by O ₃ -TEOS.
This is because the CVD method is a deposition method having fluidity. That is, when an oxide film is deposited by the O ₃ -TEOS CVD method, the oxide film is deposited in a low shape on the substrate surface, in this case, a surface shape flowing into the separation groove 18. This phenomenon is caused by O ₃ and TEO in the CVD reaction atmosphere.
It is understood that the reaction with S produces siloxane oligomers, which occur when the oligomers flow on the substrate surface.

By employing such a deposition method having fluidity, it is possible to completely embed a fine separation groove, for example, a separation groove having a width of less than 0.5 μm. O ₃
-Even when the oxide film is deposited by the TEOS CVD method,
Depending on the setting of conditions, deposition without fluidity can be performed. However, in this case, fine separation grooves cannot be buried. Therefore, the filling material film 20
As a deposition method, it is preferable to employ a deposition method having fluidity.

In addition to the O ₃ -TEOS CVD method, fluidity can be obtained by a CVD method that generates oligomers in a reaction atmosphere. For example, it is known that fluidity can be obtained also in CVD using silane and hydrogen peroxide as source gases. In addition, other than the CVD method, for example, a coating method can be used to deposit a buried material film having fluidity. At least when using a coating method, it is possible to deposit not only an oxide film but also various kinds of filling materials. For example, it is also possible to deposit a film of an organic material.

When a film of a filling material is deposited by such a deposition method having fluidity, the above-mentioned Japanese Patent No. 26879 is used.
No. 48, applying the method of manufacturing a semiconductor device disclosed in
If the buried material film is anisotropically etched using the inversion pattern as a mask before polishing by the CMP method, the element region is damaged or the CMP is performed in a portion where the width of the element region is narrow and the width of the separation groove is wide. There is a problem that the flatness after polishing by the method deteriorates.

The above problems will be described below with reference to FIGS.
This will be described in detail with reference to the process sectional views shown in FIG.

First, the sectional view shown in FIG.
This corresponds to the step of 1 (e). In the cross-sectional view shown in FIG. 2A, as described above, a portion where the width of the element region is narrow and the width of the isolation groove is wide is provided, and the film thickness of the burying material film 20 deposited thereon is provided. Is smaller than the film thickness of the burying material film 20 deposited on the other element regions. Further, as described above, the inverted pattern 22 has an opening at a portion that becomes a narrow element region.

When the buried material film 20 is etched using the inverted pattern 22 as a mask, the portion of the narrow element region surrounded by the wide separation groove is over-etched because the film thickness is small (FIG. 13 ( b)). Subsequently, when the buried material film 20 is planarized by the CMP method, silicon in the element region is directly exposed to the CMP during overpolishing and polished, and the element region is damaged (FIG. 14C). After that, when the nitride film 14 and the pad oxide film 12 are peeled and removed, the flatness is remarkably deteriorated (FIG. 14D).

As described above, in accordance with the conventional method of manufacturing a semiconductor device utilizing the STI method, a film 20 to be an embedding material is deposited on the entire surface of the semiconductor substrate including the inside of the isolation trench 18 by a deposition method having fluidity. , This buried material film 2
0 is anisotropically etched using the inversion pattern 22 as a mask, and then polished by a CMP method. If the element region is narrow and the separation groove 18 is wide, the element region may be damaged or polished. There is a problem that the flatness afterwards may be deteriorated.

[0017]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art by embedding the STI method in a simple process without damaging the element region or deteriorating the flatness. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of planarizing a material.

[0018]

In order to achieve the above object, the present invention provides a semiconductor substrate having an isolation region in which an isolation groove is formed and a plurality of element regions surrounded by the isolation region. Depositing a film of a filling material so as to fill the separation groove by a deposition method having fluidity, and selectively removing the film of the filling material deposited on at least a part of the plurality of element regions by etching. Later, CM
Forming a separation structure in which the burying material is buried in the separation trenches by flattening by a P method, wherein the step of selectively etching and removing the film of the burying material comprises A method of manufacturing a semiconductor device, wherein the film of the filling material deposited on the element region is not removed by etching.

Further, according to the present invention, the isolation groove is buried on a semiconductor substrate having an isolation region in which an isolation groove is formed and a plurality of element regions surrounded by the isolation region by a deposition method having fluidity. Depositing a film of an embedding material as described above, and selectively etching and removing the film of the embedding material deposited on at least a part of the plurality of element regions. Forming an isolation structure in which the burying material is buried in a groove, wherein the film of the burying material is selectively removed by etching, wherein the burying material is deposited on the densely arranged element regions. A film of the material is removed, and a film of the burying material deposited on the element region having a width equal to or less than a specific dimension other than the densely arranged element regions is etched. There is provided a method of manufacturing a semiconductor device characterized in that it does not grayed removed.

Here, in the semiconductor device having the dummy element region, it is preferable that the width of the dummy element region is larger than the specific dimension.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to preferred embodiments shown in the accompanying drawings.

Each step of the method of manufacturing a semiconductor device according to the present invention is basically the same as that of the prior art except that an inversion pattern used when anisotropically etching a buried material such as a CVD film is different from the conventional method. Patent No. 26 mentioned in the description of
This is the same as each step of the method for manufacturing a semiconductor device disclosed in Japanese Patent No. 87948. That is, each step of the method for manufacturing a semiconductor device of the present invention is as shown in FIGS. 10 and 11, and therefore, in this embodiment, the same description is not repeated.

Before describing the inversion pattern used in the method of manufacturing a semiconductor device according to the present invention, an example will be given of the relationship between the deposited film thickness of the burying material on the element region and the width of the element region and the isolation groove. A description is given below. In addition,
The following embodiment is an example in which the depth of the isolation groove is 4000 °, the thickness of the pad oxide film is 130 °, the thickness of the nitride film is 1500 °, and the filling material is deposited by O ₃ -TEOS CVD.

FIG. 1 is a graph of one embodiment showing the relationship between the width of an element region and the thickness of a buried material deposited thereon. This graph, as shown in FIG.
An element region (convex pattern) is isolated in a separation region having a sufficiently large width, and the film thickness of an embedding material deposited thereon is plotted using the width of the element region as a parameter. The axis indicates the width (μm) of the element region, and the axis of ordinate indicates the film thickness (Å) of the burying material with the nitride film as the reference plane. Here, the point where the width of the element region is 0 is the film thickness when the element is deposited in a wide separation groove having no element region.

Similarly, FIG. 4 is a graph of one embodiment showing the relationship between the width of the line and space and the thickness of the embedding material deposited thereon. This graph shows that the width (line and space) of the element region and the isolation trench is 1:
The width of the line and space is plotted using the width of the line and space as a parameter. The horizontal axis represents the line and space width (μm), and the vertical axis represents the nitride film. The film thickness (Å) of the embedding material as a reference surface is shown.

On the other hand, FIG. 2 is a graph of one embodiment showing the relationship between the width of the separation groove and the film thickness of the burying material deposited thereon. In this graph, as shown in FIG. 3B, isolation trenches (concave patterns) are arranged in isolation in an element region having a sufficiently wide width, and the separation trench (depression pattern) is deposited thereon using the width of the isolation trench as a parameter. The thickness of the embedded material is plotted, and the horizontal axis is the width of the separation groove (μ
m), the vertical axis indicates the thickness (埋 め 込 み) of the embedding material based on the lower surface of the separation groove. Here, the point where the width of the separation groove is 0 is the film thickness on a wide element region without the separation groove.

In the graphs of FIGS. 1, 2 and 4, the circles indicate the state at the center of the wafer, and the triangles indicate the state at the periphery of the wafer, as measured by cross-sectional SEM (scanning electron microscope). Is plotted.

First, as shown in the graph of FIG. 1, the deposited film thickness of the burying material on the element region becomes thinner as the width of the element region becomes narrower. In this embodiment, the width of the element region is 1 μm or less. It can be seen that the number begins to decrease significantly. Also, comparing the graphs of FIG. 1 and FIG. 4, it can be seen that the film thicknesses of both are substantially equal. From this result, it is understood that the deposited film thickness of the burying material on the element region becomes smaller as the width of the element region becomes narrower in this embodiment, regardless of the width of the separation groove.

On the other hand, as shown in the graph of FIG.
The deposited film thickness of the filling material in the separation groove increases as the width of the separation groove decreases. In the case of this embodiment, the deposition thickness of the burying material in the separation groove is such that the width of the separation groove is about 1.5 μm.
When it is less than 0.5 μm, it begins to increase. That is, if the width of the separation groove is less than 0.5 μm, it cannot be considered that the element regions are separated from each other.

Next, with reference to the process charts shown in FIGS. 5 and 6, a procedure for creating an inverted pattern corresponding to the results shown in the above-described graphs will be described.

The mask pattern shown in FIG. 5A is obtained by masking an element region (black background) and opening an isolation region (white background). In the figure, the width of the leftmost and second element region from the right is a certain dimension, in this embodiment, a width of 1 μm or less (dimension in the resist pattern: the same applies hereinafter), and the width of the other element regions is 1 μm or less. Is also big. Further, the width of the isolation region between the left end and the element region on the right side is a specific dimension, in this embodiment, a width of less than 0.5 μm, and the width of the other isolation regions is 0.5 μm or more.

First, in order to erase an opening of a mask pattern corresponding to an isolation region having a width smaller than a specific size and which cannot be regarded as being separated from the element regions, FIG.
Is expanded (expanded) (FIG. 5B). In the case of this embodiment, in order to erase the isolation region having a width of less than 0.5 μm, the periphery of the element region is
Expand by m. As shown in FIG. 5B, the widths of the element regions on both sides are enlarged by 0.24 μm and merged,
The opening of the mask pattern corresponding to the isolation region up to 0.48 μm width disappears.

Subsequently, the mask pattern shown in FIG. 5B is reduced (shrinked) in order to erase a mask pattern corresponding to an element region having a width smaller than a specific dimension and having a remarkably reduced thickness of the burying material. (FIG. 5 (c)). In the case of this embodiment, the periphery of the element region is reduced by 0.74 μm in order to erase the element region having a width of 1.0 μm or less.
After enlarging the periphery of the element region by 0.24 μm at a time, 0.7
The area around the element region is 0.5 μm to reduce by 4 μm.
The mask pattern corresponding to the element region having a width of 1.0 μm or less, in the illustrated example, the mask pattern corresponding to the second element region from the right disappears.

Subsequently, in order to return the mask pattern to the original size, the pattern shown in FIG. 5C is enlarged again (FIG. 6D). If the periphery of the element region is enlarged by 0.5 μm at a time, the mask pattern can be completely returned to the original size. However, in order to allow a margin for misalignment in manufacturing, in this embodiment, the element region Is enlarged by 0.3 μm at a time. Then, an inverted pattern is obtained by inverting the data of the mask pattern shown in FIG.
(E)).

FIG. 6F shows a positional relationship between the element region and the isolation region and the inverted pattern. As shown in the figure, in the portion where the width of the separation region is smaller than a specific dimension, in this embodiment, smaller than 0.5 μm, the corresponding portion of the inverted pattern is opened and is selectively etched.
In the case where the width of the element region is equal to or less than a specific dimension, and in the case of this embodiment, 1 μm or less, the corresponding portion of the inverted pattern is not opened and is not etched.

Here, as shown in FIG. 5 (a), the width of the element region on the left end is 1 μm or less, but the width of the isolation region between the element region on the right side thereof is less than 0.5 μm. ,
As shown in FIG. 5B, when the periphery of the element region is enlarged, the separation region between the left end and the element region on the right side thereof disappears, and the two are integrated. Therefore, in this embodiment, 1
Even in an element region having a width of not more than μm, a portion where the width of an isolation region between adjacent element regions is less than 0.5 μm is removed by etching.

In the above-described embodiment, the mask pattern is temporarily enlarged to erase the pattern corresponding to the separation region having a size smaller than a specific size. However, the present invention is not limited to this.
Without performing the step (b), regardless of the width of the isolation region,
A pattern corresponding to an element region having a width of the element region equal to or smaller than a specific dimension may be erased. In this case, the separation region between the leftmost device region and the rightmost device region is not etched.

As shown in the graph of FIG. 2 and the cross-sectional view of FIG. 7A, the difference between the film thicknesses of the embedding material on the separation groove and the element region is almost the same at the place where the width of the separation groove is smaller than a specific dimension. Therefore, it cannot be considered that adjacent element regions are separated from each other. In the present invention, when the step of FIG. 5B is omitted, as in the case of the conventional method, as shown in the cross-sectional view of FIG. The projections will also remain at the location of.

On the other hand, in the present invention, FIG.
When the step is performed, as shown in the cross-sectional view of FIG. 7 (c), no projection remains at a portion where the width of the separation groove is smaller than a certain dimension after etching. Due to the characteristics of the CMP method, the fine projections as shown in FIG. 7B are quickly polished and removed, so that there is no problem. However, for example, when the deposition thickness on the separation groove is large, FIG. Needless to say, it is preferable not to leave the protrusion on the separation groove as shown in FIG.

The specific dimensions of the element region and the isolation region vary depending on, for example, the depth of the isolation groove, the type of the filling material, the deposition method, the deposition conditions, and other process conditions. It should be determined appropriately according to the conditions.

Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to the process sectional views shown in FIGS.

First, the sectional view shown in FIG.
This corresponds to the step (e). In the cross-sectional view shown in FIG. 13A, similarly to the case of FIG. 13A, a portion where the width of the element region is small and the width of the separation groove is large is provided, and the portion is deposited thereon. The film thickness of the filling material 20 is smaller than the film thickness of the filling material 20 deposited on the other element regions. Also, the inversion pattern 22
In the device, a portion that becomes a narrow element region having a certain dimension or less is not opened.

The burying material 20 is etched using the inverted pattern 22 as a mask (FIG. 8B). As shown in the figure, the location of the narrow element region is the reverse pattern 2
2 is not etched because it is masked. Subsequently, when the embedding material 20 is flattened by the CMP method, the projections including the embedding material 20 on the narrow element region are first scraped off, and thereafter the entire polishing is performed to be flattened (FIG. 9). (C)). The flatness after peeling off the nitride film 14 and the pad oxide film 12 is also good (FIG. 9D).

The method of manufacturing a semiconductor device according to the present invention is basically as described above. Note that the present invention is not limited to a normal element region, but can be applied to a dummy element region. In the STI method, when the burying material is planarized by the CMP method, a nitride film formed on the element region is used as a stopper. Therefore, it is common practice to arrange a dummy element region around an isolated element region and increase the area of a nitride film serving as a stopper.

As described above, even when the dummy element region is arranged around the isolated element region, the width of the dummy element region must be equal to or more than a specific width. Is preferably 1 μm or more. As described above, the method for manufacturing a semiconductor device of the present invention has been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.

[0046]

As described above in detail, according to the method of manufacturing a semiconductor device of the present invention, basically, an isolation region including an isolation groove is formed around an element region and a semiconductor including the inside of the isolation groove is formed. An embedding material is deposited on the entire surface of the substrate, and only the embedding material deposited on an element region having a width larger than a specific dimension is selectively etched away, and then the entire surface of the embedding material is planarized by CMP. Things.
According to the method of manufacturing a semiconductor device of the present invention, a simple step of creating an inversion mask for selectively etching away only a burying material deposited on an element region having a width larger than a specific dimension is added. Thus, there is an advantage that the surface of the filling material can be completely flattened without damaging the element region. Also,
Since a deposition method having fluidity can be used as a method for depositing an embedding material without causing a problem of damage to an element region or deterioration of flatness, a fine separation structure can be easily formed. .

[Brief description of the drawings]

FIG. 1 is a graph of one embodiment illustrating the relationship between the width of an element region and the thickness of a buried material deposited thereon.

FIG. 2 is a graph of one embodiment illustrating the relationship between the width of a separation groove and the thickness of a buried material deposited thereon.

FIGS. 3A and 3B are cross-sectional views of an example showing a state of an embedding material deposited on an element region and an isolation groove, respectively.

FIG. 4 is a graph of one embodiment illustrating the relationship between the width of a line and space and the thickness of the embedding material deposited thereon.

FIGS. 5A to 5C are schematic views of one embodiment showing a process of forming an inverted pattern used in the method of manufacturing a semiconductor device according to the present invention.

FIGS. 6D to 6F are schematic diagrams showing a continuation of FIG. 5;

FIGS. 7A to 7C are cross-sectional concepts of one embodiment for explaining a difference between a conventional method of manufacturing a semiconductor device and a method of manufacturing a semiconductor device of the present invention when the width of an isolation groove is narrow; FIG.

FIGS. 8A and 8B are process cross-sectional views of one embodiment illustrating a method for manufacturing a semiconductor device of the present invention.

FIGS. 9C and 9D are process cross-sectional views illustrating a continuation of FIG. 8;

FIGS. 10A to 10D are process cross-sectional views of an example illustrating the STI method.

11 (e) to (g) are cross-sectional views showing a continuation of FIG.

FIGS. 12A to 12C are conceptual cross-sectional views of an embodiment showing a relationship between an element region and an isolation groove and a film thickness of a burying material deposited thereon.

13A and 13B are cross-sectional views illustrating an example of a process for explaining a conventional method for manufacturing a semiconductor device.

14 (c) and (d) are process cross-sectional views illustrating a continuation of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Silicon substrate 12 Pad oxide film 14 Nitride film 16 Resist pattern 18 Separation groove 20 Filling material film 22 Inversion pattern 24 Projection

Claims (3)

[Claims] An embedding material is formed on a semiconductor substrate having an isolation region in which an isolation groove is formed and a plurality of element regions surrounded by the isolation region so as to fill the isolation groove by a deposition method having fluidity. After selectively depositing and removing the film of the burying material deposited on at least a part of the plurality of element regions,
Forming a separation structure in which the burying material is buried in the separation groove, wherein the film of the burying material is selectively removed by etching. A method for manufacturing a semiconductor device, wherein a film of the burying material deposited on the element region is not removed by etching. 2. An embedding material for embedding the isolation trench by a deposition method having fluidity on a semiconductor substrate having an isolation region in which an isolation trench is formed and a plurality of element regions surrounded by the isolation region. After selectively depositing and removing the film of the burying material deposited on at least a part of the plurality of element regions,
Forming a separation structure in which the burying material is buried in the separation groove, and selectively removing the film of the burying material by etching in the separation groove. While removing the film of the filling material deposited on the element region, the film of the filling material deposited on the element region having a width equal to or less than a specific dimension other than the densely arranged element regions. A method for manufacturing a semiconductor device, wherein the semiconductor device is not removed by etching. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a width of the dummy element region is larger than the specific dimension. .