KR100929426B1 - Dual gate oxide film formation method of semiconductor device - Google Patents

Dual gate oxide film formation method of semiconductor device Download PDF

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KR100929426B1
KR100929426B1 KR1020020086131A KR20020086131A KR100929426B1 KR 100929426 B1 KR100929426 B1 KR 100929426B1 KR 1020020086131 A KR1020020086131 A KR 1020020086131A KR 20020086131 A KR20020086131 A KR 20020086131A KR 100929426 B1 KR100929426 B1 KR 100929426B1
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oxide film
gate oxide
forming
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high voltage
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KR20040059726A (en
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이종곤
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Microelectronics & Electronic Packaging (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract

본 발명은 반도체 소자의 제조시에 고전압용 게이트 산화막을 3중 구조로 형성하여 필드 산화막의 손실을 최소화하여 전기적 특성을 높일 수 있도록한 반도체 소자의 듀얼 게이트 산화막 형성 방법에 관한 것으로, 고전압 소자 형성 영역과 코아 영역을 갖는 반도체 기판 상에 제 1 산화막, 질화막, 제 2 산화막을 형성하는 단계; 상기 코아 영역이 오픈 되도록 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 이용하여 코아 영역의 제 1 산화막, 질화막, 제 2 산화막을 제거하는 단계; 상기 코아 영역에 코아 게이트 산화막을 형성하고 어닐 공정으로 고전압 소자 형성 영역의 제 1 산화막, 질화막, 제 2 산화막이 적층된 고전압 소자 게이트 산화막을 형성하는 단계를 포함한다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a dual gate oxide film of a semiconductor device in which a high voltage gate oxide film is formed in a triple structure at the time of manufacturing a semiconductor device, thereby minimizing the loss of the field oxide film, thereby improving electrical characteristics. Forming a first oxide film, a nitride film, and a second oxide film on a semiconductor substrate having a core region; Forming a photoresist pattern to open the core region; Removing the first oxide film, the nitride film, and the second oxide film in the core region using the photoresist pattern; Forming a core gate oxide film in the core region and forming a high voltage device gate oxide film in which a first oxide film, a nitride film, and a second oxide film are stacked in the high voltage device formation region by an annealing process.

HV, 듀얼 게이트HV, dual gate

Description

반도체 소자의 듀얼 게이트 산화막 형성 방법{Method for fabricating dual gate oxide of semiconductor device} Method for fabricating dual gate oxide of semiconductor device             

도 1a내지 도 1d는 본 발명에 따른 듀얼 게이트 산화막 형성 공정을 위한 공정 단면도
1A to 1D are cross-sectional views of a process for forming a dual gate oxide film according to the present invention.

-도면의 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing

10. 반도체 기판 11. 소자 격리층10. Semiconductor substrate 11. Device isolation layer

12. 제 1 산화막 13. 질화막12. First oxide film 13. Nitride film

14. 제 2 산화막 15. 포토레지스트 패턴14. Second oxide film 15. Photoresist pattern

16. 코아 게이트 산화막 17. 고전압 소자 게이트 산화막
16. Core Gate Oxide 17. High Voltage Device Gate Oxide

본 발명은 반도체 소자의 제조에 관한 것으로, 구체적으로 고전압용 게이트 산화막을 3중 구조로 형성하여 필드 산화막의 손실을 최소화하여 전기적 특성을 높 일 수 있도록한 반도체 소자의 듀얼 게이트 산화막 형성 방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of a semiconductor device, and more particularly, to a method of forming a dual gate oxide film of a semiconductor device in which a high voltage gate oxide film is formed in a triple structure to minimize the loss of the field oxide film and thus improve electrical characteristics. .

LDI(LCD Driver IC) 제품과 같은 전력소자(power device) 제품들은 소자 구동시 로직 회로(LOGIC circuit) 구동을 위한 로우 전압(Low Voltage:이하, LV라 한다) 동작과 LCD 구동을 위한 하이 전압(High Voltage:이하, HV라 한다) 동작을 모두 필요로 하므로 게이트 산화막을 듀얼 게이트 구조로 가져가야 할 뿐 아니라 미세 선폭의 추세에 따라 TI(Trench Isolation) 공정의 채용이 불가피한 상태이다.Power device products, such as LCD Driver IC (LDI) products, operate a low voltage (hereinafter referred to as LV) to drive a logic circuit when driving the device and a high voltage to drive an LCD. High Voltage (hereinafter referred to as HV) operation is required, so the gate oxide film must be brought into the dual gate structure, and the TI (Trench Isolation) process is inevitable due to the trend of fine line width.

하지만 TI 공정 결과 형성된 STI 구조에 듀얼 게이트 산화막 제조 공정을 그대로 적용하면 HV용 듀얼 게이트 산화막을 형성할 때 LV 영역의 STI 리세스(recess)가 과도하게 발생하여 소자 특성에 치명적인 손상이 가해지게 된다.However, if the dual gate oxide film fabrication process is applied to the STI structure formed as a result of the TI process, excessive STI recesses in the LV region are excessively generated when the dual gate oxide film for HV is formed, thereby damaging the device characteristics.

이는 STI 구조의 갭 필(gap fill)에 사용되는 막질은 USG나 HDP와 같은 CVD 산화막인 반면 게이트 산화막으로는 열산화막(thermal oxide) 재질의 막질이 사용되므로, 열산화막으로 듀얼 산화막을 형성할 때 열산화막과 CVD 산화막 간의 습식식각률(wet etch rate) 차이에 의해 액티브영역과 필드영역의 경계면에서 심하게 덴트(dent)가 발생되기 때문이다.This is because the film quality used for the gap fill of the STI structure is a CVD oxide film such as USG or HDP, while the thermal oxide film is used as the gate oxide film. This is because severe dents are generated at the interface between the active region and the field region due to the difference in wet etch rate between the thermal oxide layer and the CVD oxide layer.

종래 기술에서는 고 전압용 소자의 게이트 산화막 두께는 매우 두꺼운데 반하여 코아 로직 소자의 게이트 산화막 두께는 아주 얇다.In the prior art, the gate oxide film thickness of a high voltage device is very thick, whereas the gate oxide film thickness of a core logic device is very thin.

이와 같은 종래 기술의 게이트 산화막 형성 방법을 적용하면 초기에 성장시킨 산화막의 두께가 너무 두꺼워 산화막 식각시 필드 산화막의 로스가 심하여 로직 소자의 게이트 산화막 특성이 열화된다. When the gate oxide film forming method of the related art is applied, the thickness of the initially grown oxide film is so thick that the loss of the field oxide film during the etching of the oxide film is severe and the gate oxide film characteristics of the logic device are degraded.                         

예를 들어, 종래 기술에서 800Å과 50Å의 두께를 가진 듀얼 게이트 산화막을 제조할 경우에 780Å정도의 산화막을 웨이퍼의 전면에 성장시킨 후 마스크와 습식각을 통하여 50Å이 성장할 부위를 식각 시키고 마스크를 제거한다.For example, in the case of manufacturing a dual gate oxide film having a thickness of 800 kHz and 50 Å in the prior art, an oxide layer of about 780 Å is grown on the entire surface of the wafer, and then the portion where 50 Å will be grown is etched through a mask and a wet etching and the mask is removed. do.

그리고 다시 전면에 50Å 정도의 산화막을 성장시켜 최종 두께가 800Å과 50Å이 되게 만든다.Then, an oxide film of about 50 kW is grown on the front surface so that the final thickness is 800 kW and 50 kW.

이 경우 50Å이 성장할 부위를 식각시킬 때 최하 1000Å 이상의 습식각이 필요하므로 산화막의 로스가 매우 크다. 필드 산화막의 로스는 필드 산화막을 포함하는 게이트 산화막의 특성을 저하시킨다.In this case, at least 1000 kW or more of wet etching is required to etch a region where 50 kW is to be grown, so the loss of the oxide film is very large. Loss of the field oxide film lowers the characteristics of the gate oxide film including the field oxide film.

그러나 이와 같은 종래 기술의 반도체 소자의 듀얼 게이트 산화막 형성 공정은 다음과 같은 문제점이 있다.However, the dual gate oxide film forming process of the semiconductor device of the prior art has the following problems.

종래 기술에서는 게이트 산화막을 듀얼 게이트 구조로 형성하는 것이 필요할 경우에는 미세 선폭의 추세에 따라 TI(Trench Isolation) 공정의 채용이 불가피한 상태이다.In the prior art, when it is necessary to form the gate oxide layer in a dual gate structure, it is inevitable to adopt a trench isolation process according to the trend of fine line width.

하지만 TI 공정 결과 형성된 STI 구조에 듀얼 게이트 산화막 제조 공정을 그대로 적용하면 HV용 듀얼 게이트 산화막을 형성할 때 LV 영역의 STI 리세스(recess)가 과도하게 발생하여 소자 특성에 치명적인 손상이 가해지게 된다.However, if the dual gate oxide film fabrication process is applied to the STI structure formed as a result of the TI process, excessive STI recesses in the LV region are excessively generated when the dual gate oxide film for HV is formed, thereby damaging the device characteristics.

소자 격리층의 손상은 게이트 산화막의 열화를 가져온다.
Damage to the device isolation layer results in degradation of the gate oxide film.

본 발명은 이와 같은 종래 기술의 반도체 소자의 듀얼 게이트 산화막 형성 공정의 문제를 해결하기 위하여 안출한 것으로, 고전압용 게이트 산화막을 3중 구조로 형성하여 필드 산화막의 손실을 최소화하여 전기적 특성을 높일 수 있도록한 반도체 소자의 듀얼 게이트 산화막 형성 방법을 제공하는데 그 목적이 있다.
The present invention has been made to solve the problem of the dual gate oxide film forming process of the prior art semiconductor device, by forming a high voltage gate oxide film in a triple structure to minimize the loss of the field oxide film to improve the electrical characteristics It is an object of the present invention to provide a method for forming a dual gate oxide film of a semiconductor device.

이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 듀얼 게이트 산화막 형성 방법은 고전압 소자 형성 영역과 코아 영역을 갖는 반도체 기판상에 제 1 산화막, 질화막, 제 2 산화막을 형성하는 단계; 상기 코아 영역이 오픈되도록 포토레지스트 패턴을 형성하는 단계; 상기 포토레지스트 패턴을 이용하여 코아 영역의 제 1 산화막, 질화막, 제 2 산화막을 제거하는 단계; 상기 코아 영역에 코아 게이트 산화막을 형성하고 어닐 공정으로 고전압 소자 형성 영역의 제 1 산화막, 질화막, 제 2 산화막이 적층된 고전압 소자 게이트 산화막을 형성하는 단계를 포함하는 것을 특징으로 한다.A dual gate oxide film forming method of a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a first oxide film, a nitride film, a second oxide film on a semiconductor substrate having a high voltage element formation region and a core region; Forming a photoresist pattern to open the core region; Removing the first oxide film, the nitride film, and the second oxide film in the core region using the photoresist pattern; And forming a high voltage device gate oxide film including a first oxide film, a nitride film, and a second oxide film stacked in the high voltage device formation region by forming a core gate oxide film in the core region and performing an annealing process.

본 발명에 따른 반도체 소자의 듀얼 게이트 산화막 형성 방법의 바람직한 실시예에 관하여 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the method of forming a dual gate oxide film of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 1a내지 도 1d는 본 발명에 따른 듀얼 게이트 산화막 형성 공정을 위한 공정 단면도이다.1A to 1D are cross-sectional views of a process for forming a dual gate oxide film according to the present invention.

본 발명은 고 전압용 게이트 산화막을 삼중 구조로 만드는데 먼저 습식 산화막을 성장시키고 질화막을 원하는 두께만큼 성장시킨 후 화학 기상 증착법에 의한 산화막을 다시 성장시킨다. The present invention makes a high voltage gate oxide film in a triple structure. First, a wet oxide film is grown, a nitride film is grown to a desired thickness, and the oxide film by chemical vapor deposition is grown again.                     

이는 후속되는 게이트 식각을 건식 식각과 습식 식각을 차례로 실시하므로 건식 식각의 선택비에 비하여 다른 부분의 손실 없이 원하는 부분만 식각시킬 수 있고, 고 전압용 게이트 산화막의 전기적 특성은 후속 고온 어닐링을 통하여 확보한다.This is because the subsequent gate etching is performed by dry etching and wet etching in sequence, so that only the desired portion can be etched without loss of other portions compared to the selectivity of dry etching. do.

이와 같은 본 발명에 따른 듀얼 게이트 산화막 형성 방법을 고전압 소자용 게이트 산화막을 800Å 두께로 형성하고, 코아 게이트 산화막을 50Å의 두께를 가진 듀얼 게이트 산화막의 형성을 예로 들어 설명한다.The method for forming a dual gate oxide film according to the present invention will be described taking an example of forming a dual gate oxide film having a thickness of 800 kV and a core gate oxide film having a thickness of 50 kV.

먼저, 도 1a에서와 같이, 반도체 기판(10)의 소자 격리 영역에 STI(shallow trench isolation) 공정으로 소자 격리층(11)을 형성한다.First, as shown in FIG. 1A, the device isolation layer 11 is formed in a shallow trench isolation (STI) process in the device isolation region of the semiconductor substrate 10.

소자 격리층(11)은 전면에 마스크용 나이트라이드막을 형성하고 활성 영역상에만 남도록 패터닝한 후에 이를 마스크로 하여 노출된 기판을 일정 깊이 식각하여 트렌치를 형성한다.The device isolation layer 11 forms a mask nitride film on the entire surface and is patterned so as to remain only on the active region, and then forms a trench by etching the exposed substrate using a mask.

그리고 트렌치를 매립하는 절연 물질을 증착하고 CMP 공정등으로 평탄화하여 형성한다.The insulating material filling the trench is deposited and planarized by a CMP process.

이와 같은 공정으로 소자 격리층(11)을 형성한 후에 습식 산화 방식으로 100Å 두께의 제 1 산화막(12)과 1150Å 두께의 질화막(13) 그리고 100Å 두께의 화학 기상 증착법에 의한 제 2 산화막(14)을 형성한다.After the device isolation layer 11 is formed in this manner, the first oxide film 12 having a thickness of 100 Å, the nitride film 13 having a thickness of 1150 Å, and the second oxide film 14 having the chemical vapor deposition method having a thickness of 100 Å are formed by a wet oxidation method. To form.

여기서, 제 1 산화막(12)을 750~850℃ 정도에서 습식 산화를 실시하여 형성한다. Here, the first oxide film 12 is formed by wet oxidation at about 750 to 850 ° C.                     

그리고 질화막(13)은 SiH2Cl2가스화 NH3가스를 1:2~10정도로 사용하고, 온도는 700~800℃정도, 압력은 100~500m Torr 정도에서 성장시킨다.The nitride film 13 uses SiH 2 Cl 2 gasified NH 3 gas at about 1: 2 to about 10, grows at a temperature of about 700 to 800 ° C., and a pressure of about 100 to 500 m Torr.

이어, 도 1b에서와 같이, 포토 마스크를 이용하여 로직 코아용 소자가 형성될 부분을 구분한다.Subsequently, as shown in FIG. 1B, the portion where the logic core element is to be formed is divided using a photo mask.

포토레지스트 패턴(15)은 고전압 소자 형성 영역에 형성되어 코아 영역이 오픈되도록 형성한다.The photoresist pattern 15 is formed in the high voltage element formation region so as to open the core region.

그리고 도 1c에서와 같이, 상기 포토레지스트 패턴(15)을 마스크로 하여 건식각과 습식각을 차례로 실시하여 로직 코아 부분에 형성된 절연막들 즉, 제 1 산화막(12),질화막(13),제 2 산화막(14)을 선택적으로 식각한 후에 포토레지스트 패턴(15)을 제거한다.As shown in FIG. 1C, the photoresist pattern 15 is used as a mask, followed by dry etching and wet etching, that is, the first oxide film 12, the nitride film 13, and the second oxide film formed on the logic core portion. After selectively etching (14), the photoresist pattern 15 is removed.

이어, 도 1d에서와 같이, 로직 코아 부분에 사용될 코아 게이트 산화막(16)을 50Å의 두께로 형성한다.Subsequently, as shown in FIG. 1D, a core gate oxide film 16 to be used for the logic core portion is formed to a thickness of 50 μs.

이때 고 전압용 게이트 부분에는 질화막의 산소 투과 장치로 인하여 산화막이 전혀 성장하지 않는다.At this time, the oxide film does not grow at all due to the oxygen permeation device of the nitride film.

그리고 게이트 산화막 형성시 고전압 소자 게이트 산화막(17)의 특성 향상을 위하여 고온에서 30분 정도의 어닐을 실시한다.When the gate oxide film is formed, annealing is performed at a high temperature for about 30 minutes to improve the characteristics of the high voltage device gate oxide film 17.

즉, 코아 게이트 산화막(16)을 온도는 650~750℃ 정도에서 습식 산화를 실시하여 형성하고 산화 후에 800~900℃에서 20분~1시간정도 N2와 No 희석 가스를 이용하여 어닐을 실시하고 고온 N2 가스를 이용하여 실시한다. That is, the core gate oxide film 16 is formed by wet oxidation at a temperature of about 650 to 750 ° C. and then annealed using N 2 and No dilution gas at 800 to 900 ° C. for 20 minutes to 1 hour after oxidation. It is carried out using high temperature N 2 gas.

이와 같은 본 발명에 따른 반도체 소자의 듀얼 게이트 산화막 형성 방법은 고전압용 게이트 산화막을 3중 구조로 형성하여 필드 산화막의 손실을 최소화하여 전기적 특성을 높일 수 있도록한 것이다.The dual gate oxide film forming method of the semiconductor device according to the present invention is to form a high-voltage gate oxide film in a triple structure to minimize the loss of the field oxide film to improve the electrical characteristics.

이상 설명한 내용을 통해 당업자라면 본 발명의 기술 사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

따라서, 본 발명의 기술적 범위는 실시예에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의하여 정해져야 한다.
Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

이상에서 설명한 본 발명에 따른 반도체 소자의 듀얼 게이트 산화막 형성 방법은 다음과 같은 효과가 있다.The method of forming the dual gate oxide film of the semiconductor device according to the present invention described above has the following effects.

본 발명은 고전압 소자 게이트 산화막을 삼중 구조로 형성하여 소자 격리층의 손상을 억제하여 게이트 산화막의 열화를 막는다.The present invention forms a high voltage device gate oxide film in a triple structure to suppress damage to the device isolation layer, thereby preventing deterioration of the gate oxide film.

이는 소자의 동작 특성을 향상시키고, 신뢰성을 높이는 효과를 갖는다.This has the effect of improving the operating characteristics of the device and increasing the reliability.

Claims (3)

고전압 소자 형성 영역과 코아 영역을 갖는 반도체 기판상에 제 1 산화막,질화막,제 2 산화막을 형성하는 단계;Forming a first oxide film, a nitride film, and a second oxide film on a semiconductor substrate having a high voltage element formation region and a core region; 상기 코아 영역이 오픈되도록 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern to open the core region; 상기 포토레지스트 패턴을 이용하여 코아 영역의 제 1 산화막,질화막,제 2 산화막을 제거하는 단계;Removing the first oxide film, the nitride film, and the second oxide film of the core region using the photoresist pattern; 상기 코아 영역에 코아 게이트 산화막을 형성하고 어닐 공정으로 고전압 소자 형성 영역의 제 1 산화막,질화막,제 2 산화막이 적층된 고전압 소자 게이트 산화막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 듀얼 게이트 산화막 형성 방법.Forming a high voltage device gate oxide film including a first oxide film, a nitride film, and a second oxide film stacked in the high voltage device formation region by forming a core gate oxide film in the core region and performing an annealing process. Oxide film formation method. 제 1 항에 있어서, 제 1 산화막을 750~850℃ 정도에서 습식 산화를 실시하고 질화막과 제 2 산화막은 저압 기상 화학 증착법에 의하여 성장시키는 것을 특징으로 하는 반도체 소자의 듀얼 게이트 산화막 형성 방법.The method of forming a dual gate oxide film of a semiconductor device according to claim 1, wherein the first oxide film is wet oxidized at about 750 ° C. to 850 ° C., and the nitride film and the second oxide film are grown by low pressure vapor deposition. 제 1 항에 있어서, 질화막을 SiH2Cl2가스화 NH3가스를 1:2~10정도로 사용하고, 온도는 700~800℃정도, 압력은 100~500m Torr 정도에서 성장시킨는 것을 특징으로 하는 반도체 소자의 듀얼 게이트 산화막 형성 방법.The semiconductor device according to claim 1, wherein the nitride film is grown at a temperature of about 700 to 800 ° C. and a pressure of about 100 to 500 m Torr using SiH 2 Cl 2 gasified NH 3 gas at about 1: 2 to 10. Method of forming a dual gate oxide film.
KR1020020086131A 2002-12-28 2002-12-28 Dual gate oxide film formation method of semiconductor device KR100929426B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990084321A (en) * 1998-05-04 1999-12-06 윤종용 Semiconductor device having an open drain input and output terminal and a manufacturing method therefor
KR20000025228A (en) * 1998-10-09 2000-05-06 김영환 Method for forming gate insulator of semiconductor devices
JP2000164726A (en) 1998-11-25 2000-06-16 Ricoh Co Ltd Manufacture of semiconductor device
KR20020051283A (en) * 2000-12-22 2002-06-28 박종섭 Method for fabricating dual gate-oxide

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990084321A (en) * 1998-05-04 1999-12-06 윤종용 Semiconductor device having an open drain input and output terminal and a manufacturing method therefor
KR20000025228A (en) * 1998-10-09 2000-05-06 김영환 Method for forming gate insulator of semiconductor devices
JP2000164726A (en) 1998-11-25 2000-06-16 Ricoh Co Ltd Manufacture of semiconductor device
KR20020051283A (en) * 2000-12-22 2002-06-28 박종섭 Method for fabricating dual gate-oxide

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