KR100278681B1 - Method of making trench isolation - Google Patents

Abstract

The present invention relates to a method of manufacturing trench isolation to prevent dent phenomenon of the nitride film liner generated at the edge portion of the upper region of the trench isolation, wherein the pad oxide film and the nitride film sequentially formed on the semiconductor substrate are partially etched to form the trench formation region. A mask pattern to be defined is formed, and a portion of the semiconductor substrate is etched using the mask pattern to form a trench. A thermal oxide film is formed on the bottom surface and both side walls of the trench, and a nitride film liner is formed on the thermal oxide film. The nitride film liner is formed of a nitride film having an etching rate smaller than that of the mask pattern. A trench isolation layer is formed on the nitride film liner to completely fill the trench, and the trench isolation layer is planarized and etched until the upper surface of the mask pattern on both sides of the trench is exposed. Subsequently, the mask pattern is removed. By such a method of manufacturing trench isolation, it is possible to prevent the occurrence of nitride film liner dent caused by overetching of the nitride film liner at the edge portion of the upper region of the trench isolation, thereby preventing leakage current caused by the dent, This prevention of leakage current can improve the refresh characteristics of DRAM devices. In addition, it is possible to prevent an electrical short between devices caused by the remaining of the conductive material stringer in the nitride film liner dent, and to reduce the line width distribution of the active region, thereby improving the electrical characteristics of the semiconductor device.

Description

A METHOD OF FABRICATING A TRENCH ISOLATION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing trench isolation, which prevents the occurrence of nitride film liner dents occurring in the trench isolation upper region.

Several techniques have been studied to replace semi-recessed isolation in order to simultaneously achieve the two goals of improving device integration and ensuring effective device isolation. When device isolation is formed using LOCOS (local oxidation of silicon) technology, which is a typical semi-recessed isolation, the inevitable bird's beak phenomenon makes it difficult to accurately define an active region. In addition, LOCOS isolation also suffers from the disadvantage of degrading the narrow channel effect and the tail characteristics of the transistor. This appears as a double hump in the Ids-Vgs curve.

In order to solve the above-described problems of LOCOS isolation, latch up, and parasitic transistor generation, new technology to replace the LOCOS isolation has been required. This technique is trench isolation, which can improve the density of devices per unit area and is a suitable alternative to overcome the problems of the conventional device isolation techniques described above. However, trench isolation also has some drawbacks, one of which is the dent caused by overetching of the nitride liner formed in the trench.

1A-1D are flow diagrams sequentially illustrating a method of making trench isolation in accordance with conventional embodiments.

Referring to FIG. 1A, in the trench isolation manufacturing method of a conventional semiconductor device, a pad oxide film 11 and a nitride film 12 are sequentially formed on a semiconductor substrate 10 first. In general, the nitride film 12 is deposited by LP-CVD, and the etch rate for the high temperature phosphoric acid (H ₃ PO ₄ ) is about 50 μs / min. A photoresist pattern is formed on the nitride film 12 to define an active region. (Not shown) The photoresist pattern is used as a mask to partially etch the nitride film 12 and the pad oxide film 11. Thus, mask patterns 11 and 12 defining the trench formation regions are formed. The mask patterns 11 and 12 are used as masks to partially etch the semiconductor substrate 10 to form the trenches 14.

Referring to FIG. 1B, a thermal oxidation process is performed to eliminate substrate defects and stresses generated during trench etching. Due to this thermal oxidation process, a thin thermal oxide film 16 is formed on both side walls and the bottom surface of the trench 14. The thermal oxidation process rounds the upper and lower corner portions 15 of the trench, thereby reducing the stress concentrated on the upper and corner portions 15. Next, a nitride liner 17 is formed on the entire surface of the semiconductor substrate 10 including the thermal oxide layer 16. The nitride film liner 17 is an oxygen diffusion barrier layer that prevents the semiconductor substrate, ie, the silicon substrate, formed on both sidewalls and the bottom of the trench 14 from being oxidized during the subsequent trench isolation layer 18 forming process. In other words, the nitride film liner 17 prevents oxygen from reaching the trench 14 sidewalls in a subsequent oxidation process. A trench isolation layer 18 is then deposited on the nitride liner 17 to fill the trench 14 with an insulating material.

Referring to FIG. 1C, the trench isolation layer 18 including the trench 14 thickly formed on the semiconductor substrate is planarized by a chemical mechanical polishing (CMP) process until the upper surfaces of the mask patterns 11 and 12 are exposed. Etched. In this case, the nitride film 12 of the mask pattern serves as an etch stop layer.

Referring to FIG. 1D, the nitride layer 12 of the mask pattern is removed by a phosphoric acid solution. In general, since the etching rate of the nitride layer in the phosphoric acid solution is very low, overetching is performed at a high temperature for complete removal. ) The process is carried out. In this over-etching process, part of the nitride film liner 17 in the trench upper region is etched to generate dents of the nitride film liner (reference numeral '19'). The nitride liner dent 19 is further enlarged by a subsequent oxide etch back process to extend the liner dent at the edge of the trench isolation top region.

As is generally known, the liner dent 19 provides a leakage current path to degrade the refresh characteristics of the DRAM, whereby the charge stored in the capacitor causes the liner dent 19 Is leaking through). In severe cases, the stored data may be erased. In the subsequent transistor forming process, the conductive material is not completely removed but remains in the liner dent 19 to generate a stringer, and an electrical short between adjacent gate electrodes may be generated by the stringer. have.

The breakdown voltage may be lowered due to the leakage current caused by the liner dent 19, and the gate oxide film is incompletely formed by the liner dent 19, and the electric field is applied to the gate oxide film. If functioning, Fowler-Nordheim tunneling may occur. This FN tunneling increases the probability of injection of electrons from the bulk into the conduction band of the gate oxide (S. Wolf, Silicon Processing Vol. 3 1995, pp 435-436). This results in undesired currents, which adversely affect the transistor's reliability by changing the overall device characteristics such as threshold voltage and channel current.

The present invention has been proposed to solve the above-described problems, to provide a method for manufacturing trench isolation that can prevent the nitride liner dent caused by overetching the liner of the nitride film at the edge portion of the upper region of the trench isolation. The purpose is.

1A-1D are flow diagrams sequentially illustrating a method of making trench isolation according to a conventional embodiment;

2A-2D are flow diagrams sequentially illustrating a method of making trench isolation in accordance with an embodiment of the present invention;

3 is a graph showing the respective etching rates for phosphoric acid of LP-CVD SiN film and HDP CVD SiN film;

4 is a graph showing the line width distribution of each of the active regions when the LP-CVD SiN film and the HDP CVD SiN film are used as masks, respectively;

5 is a graph showing respective removal rates for CMP planarization etching of LP-CVD SiN film and HDP CVD SiN film.

* Explanation of symbols for the main parts of the drawings

10, 100: semiconductor substrate 11, 110: pad oxide film

12, 120: nitride film 14, 140: trench

16, 160: thermal oxide film 17, 170: nitride film liner

18, 180: trench isolation

(Configuration)

According to the present invention for achieving the above object, a method of manufacturing a trench isolation comprises the steps of partially etching a nitride film and a pad oxide film sequentially formed on a semiconductor substrate to form a mask pattern defining a trench formation region; Etching a portion of the semiconductor substrate using the mask pattern to form a trench; Forming a thermal oxide film on the bottom surface and both sidewalls of the trench; Forming a nitride film liner on the thermal oxide film, wherein the nitride film liner is formed of a nitride film having an etch rate smaller than that of the mask pattern; Forming a trench isolation to completely fill the trench on the nitride liner; Planar etching the trench isolation layer until the upper surface of the mask pattern on both sides of the trench is exposed; And, removing the mask pattern.

2D and 5, according to the trench isolation manufacturing method of the novel semiconductor device according to the embodiment of the present invention, a trench isolation layer is formed to completely fill the trench on the mask pattern and the nitride film liner. The trench isolations are planarized etched until the top surface is exposed. The mask pattern is then removed. In this case, the nitride film of the mask pattern is removed about two times faster than the nitride film liner. By such a method of manufacturing trench isolation, it is possible to prevent the liner dent phenomenon occurring at the edge portion of the trench isolation upper region, thereby preventing leakage current caused by the dent. Prevention of this leakage current can improve the refresh characteristics of the DRAM device. In addition, it is possible to prevent the electrical short between the device caused by the remaining stringer of the conductive material in the dent, and to reduce the line width distribution of the active region can improve the electrical characteristics of the semiconductor device.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2D.

2A-2D are cross-sectional views sequentially illustrating a method of making trench isolation in accordance with an embodiment of the present invention.

Referring to FIG. 2A, in the novel trench isolation method according to the exemplary embodiment of the present invention, a pad oxide film 110 and a nitride film 120 are sequentially formed on a semiconductor substrate 100. The nitride film 120 is formed of HDP high density plasma chemical vapor deposition (HDP CVD) SiN having a thickness in the range of about 1500 kPa to 1600 kPa. Conventionally, the nitride film 120 is formed of LP-CVD SiN. The etch rate of the LP-CVD SiN is about 50 mW / min, whereas the etch rate of the HDP CVD SiN 120 is about 126 mW / min.

FIG. 3 is a graph showing the etch rate for each of the phosphoric acid of the LP-CVD SiN film and the HDP CVD SiN film.

Referring to FIG. 3, it can be seen that the etch rate of LP-CVD SiN is relatively smaller than that of HDP CVD SiN.

The HDP CVD SiN 120 is deposited using SiH ₄ and N ₂ gases at source power in the range of about 1000 Watts to 2000 Watts. In this case, the SiH ₄ and N ₂ gases have a flow rate of about 20 sccm to 100 sccm and a flow rate of about 100 sccm to 500 sccm, respectively. The nitride film 120 serves as an etch stopping layer in a subsequent CMP process.

A photoresist pattern is formed on the nitride layer 120 to define a trench forming region that separates an active region from an inactive region. (Not shown) The photoresist pattern is used as a mask to form the nitride layer 120 and the pad. The oxide layer 110 is etched to form mask patterns 110 and 120. The mask patterns 110 and 120 are used as masks to etch the semiconductor substrate 100 to form trenches 140.

The use of HDP CVD SiN as the nitride film 120 of the mask pattern has been shown to be more effective for the linewidth distribution of the active region than the use of LP-CVD SiN.

FIG. 4 is a graph showing contrast of line width distribution of each active region when the LP-CVD SiN film and the HDP CVD SiN film are used as masks, respectively.

Referring to FIG. 4, it can be seen that, as described above, when the HDP CVD SiN film is used, the line width distribution of the active region is improved.

Referring to FIG. 2B, a thermal oxidation process is performed to solve surface defects and stresses generated during trench etching, and thermal oxidation layers 160 are formed on both sidewalls and bottom surfaces of the trench 140. The formation of the thermal oxide layer 160 causes the corners 150 of the inlet and the bottom of the trench to be rounded, thereby reducing stress on the corners.

Subsequently, the nitride film liner 170 is formed on the entire surface of the semiconductor substrate including the thermal oxide film. The nitride film liner 170 is formed of an LP-CVD SiN film having an etching rate smaller than that of the nitride film 120 of the mask pattern, which is an HDP CVD SiN film. As mentioned above, the etching rate of the HDP CVD SiN film is about 126 mW / min, and the etching rate of the LP-CVD SiN film is about 50 mW / min. The nitride film liner 170 is a diffusion barrier layer to prevent the silicon of both sidewalls and the bottom of the trench from being oxidized during the subsequent trench isolation layer 180 forming process. In general, when the nitride film liner 170 is formed to have a thickness of about 50 GPa or less, it may not serve as a diffusion barrier layer. On the contrary, when too thick, the size of the dent increases, so that the nitride film liner 170 is preferably formed to have a thickness in the range of about 50 kPa to 70 kPa.

Another function of the nitride film liner 170 is a mobile impurity ion, such as sodium (Na) or potassium (K) ion, which is introduced from a slurry, a wet cleaning process, or the like during a subsequent CMP process. Are prevented from moving to silicon bulk and gate oxide. As the impurity ions such as sodium and potassium ions move to the gate oxide, the threshold voltage changes, which is well described in S. M. Sze, Physics of Semiconductors, 2nd edition, Wiley 1981, pp 372-396.

If the nitride film liner 170 is partially thin or absent, the silicon on both sidewalls of the trench may oxidize to form a vertical bird's beak when forming the subsequent trench isolation layer 180. This is well described in "U. S. P 4,631,803, 1986". Vertical Bird Vic can lose the benefits of trench isolation and create new leakage current paths by stressing silicon bulk.

After the nitride film liner 170 is formed, a process of forming the trench isolation layer 180 using USG (undopped silicate glass) on the semiconductor substrate including the trench is performed. In this case, the trench isolation layer 180 is formed to a thickness of 2000 kPa to 10000 kPa. In addition to USG, the trench isolation layer 180 may include phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethylorthosilicate glass (PE-TEOS), ozone tetraethylorthosilicate glass (O3-TEOS), borophospho-tetraethylorthosilicate glass (BP-TEOS), or the like. Polysilicon or the like.

Subsequently, a densification process is performed at a temperature of 1150 ° C. in an N ₂ gas atmosphere. The densification process is for gettering and removing impurities such as sodium and potassium introduced into the trench isolation layer 180. Another purpose of the densification process is to increase the etch resistance of the trench isolation to the etchant used in subsequent cleaning processes to reduce the extent to which the trench isolation is etched.

The densification process may be carried out in a wet oxidation process at a lower temperature, such as about 800 ° C., in addition to the above-described method. The advantage of this method is that it proceeds at low temperatures, thereby preventing unwanted drive-in effects of impurities and effectively performing impurity gettering in a shorter time. This is well described in "U. S. P 5,447,884, 1995".

Referring to FIG. 2C, the trench isolation layer 180 is planarized and etched until the upper surfaces of the mask patterns 110 and 120 on both sides of the trench 140 are exposed. The planarization etching process is performed by a CMP process. In this case, a part of the nitride film 120 of the mask pattern is etched. Mobile impurity ions, such as sodium and potassium ions, introduced during the CMP process cause deterioration of the gate oxide film and adversely affect the reliability of the semiconductor device.

Referring to FIG. 2D, the nitride layer 120 of the mask pattern is removed by a wet etching process. At this time, the wet etching process is performed using a hot phosphoric acid solution, the temperature of the phosphoric acid solution is about 165 ℃. In general, the etch rate of the nitride film to the phosphoric acid solution is very low, so a significant overetch process must be performed to completely remove the nitride film. Referring to FIG. 1D, since the nitride film 12 of the mask pattern is formed of LP-CVD SiN of the same material as the nitride film liner 17 in the conventional trench isolation manufacturing method, the nitride film 12 of the mask pattern is removed. The nitride film liner 17 is also etched together to generate the liner dent 19. However, in the present invention, since the nitride film 120 of the mask pattern is formed of HDP CVD SiN having a larger etching rate than the LP-CVD SiN, which is the nitride film liner 170, the nitride film 120 of the mask pattern is formed. The over-etching process time to completely remove the can be reduced. In other words, the dipping time in the hot phosphoric acid solution can be reduced. This means that the nitride film liner 170 may be prevented from being etched in an over-etching process for completely removing the nitride film 120 of the mask pattern.

5 is a graph showing respective removal rates for CMP planarization etching of the LP-CVD SiN film and the HDP CVD SiN film.

Referring to FIG. 5, it can be seen that the HDP CVD SiN is removed more than about 2 times by a CMP process as compared to LP-CVD SiN.

The present invention has the effect of improving the refresh characteristics of the DRAM by reducing the leakage current by the liner dent occurs in the upper edge portion of the trench isolation in the trench isolation manufacturing method of the conventional semiconductor device. In addition, it is possible to solve the problem of short-circuit generation between devices due to remaining of the conductive layer stringer in the dent, and to reduce the line width distribution of the active region, thereby improving the electrical characteristics of the semiconductor device.

Claims (5)

Partially etching a pad oxide film and a nitride film sequentially formed on the semiconductor substrate to form a mask pattern defining a trench formation region; Etching a portion of the semiconductor substrate using the mask pattern to form a trench; Forming a thermal oxide film on the bottom surface and both side walls of the trench; Forming a nitride film liner on the thermal oxide film, wherein the nitride film liner is formed of a nitride film having an etching rate smaller than that of the mask pattern; Forming a trench isolation to completely fill the trench on the nitride liner; Planar etching the trench isolation layer until the upper surface of the mask pattern on both sides of the trench is exposed; And, Removing the mask pattern. The method of claim 1, The nitride film of the mask pattern is formed of HDP CVD SiN, the nitride film liner is formed of LP-CVD SiN. The method of claim 2, Wherein the etch rate of the HDP CVD SiN is at least 100 μs / min and the etch rate of the LP-CVD SiN is about 50 μs / min. The method of claim 2, And the HDP CVD SiN film is formed in SiH ₄ and N ₂ gas atmosphere and source power in the range of 1000 Watts to 2000 Watts. The method of claim 4, wherein The flow rate of the SiH ₄ and N ₂ gas is 20sccm to 100sccm, and 100sccm to 500sccm manufacturing method of the trench isolation.