TW522558B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW522558B
TW522558B TW090119678A TW90119678A TW522558B TW 522558 B TW522558 B TW 522558B TW 090119678 A TW090119678 A TW 090119678A TW 90119678 A TW90119678 A TW 90119678A TW 522558 B TW522558 B TW 522558B
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Taiwan
Prior art keywords
source
semiconductor
drain
semiconductor memory
voltage
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TW090119678A
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Chinese (zh)
Inventor
Kazuo Yano
Tomoyuki Ishii
Taro Osabe
Takashi Kobayashi
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Hitachi Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491—Virtual ground arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887—Programmable transistors with more than two possible different levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/06—Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

For providing a cheap semiconductor memory device with improved reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

Description

522558 A7 B7 五、發明説明（1) 本發明係關於半導體記憶格及半導體裝置。 (請先閲讀背面之注意事項再填寫本頁) 近年來高速閱讀用途之快閃記憶器以被引進到很多攜 帶式機器。一般而言，高速閱讀用途係使用，將記憶格並 聯，對並聯之每兩個格子配設1個資料線接點，藉此將雜 散電阻抑制成最小，以便進行高速閱讀之記憶格陣列。此 記憶格陣列從早期便爲眾所周知，舉一例如：久米，應用 物理，P. 1114(1996)。 對快閃記憶器來講，確保該記憶格之可靠性很重要。 爲了確保此記憶格之可罪性’在製造過程已做過很多技術 改革，但至今並未開發出根本之技術。目前廣泛使用的是 ，作出几長之記憶格’而以電氣電路方式替換不良格子之 E C C技術。 經濟部智慧財產局員工消費合作社印製 由於多媒體之普遍化及以PDA、數位相機、行動電 話爲首之攜帶式機器之發達，今後大容量非揮發性記憶器 會愈來愈重要。尤其是，從小型化、擷取之高速性、耐撞 擊性之觀點，以快閃記憶器爲代表之半導體非揮發性記憶 器受到重視。然而，由於大容量化之進展，雖橫方向之格 子尺寸隨著加工技術之趨勢而縮小，但另一方之縱方向， 亦即，膜厚度方向之尺度卻幾乎沒有進展。這是因爲低電 場漏洩爲首之可靠性之問題，因此已被認爲在最近之將來 ，短通道效果十分確實會顯現化。同時因無法將使用電壓 低電壓化，因此周邊電路之尺寸無法縮小，對晶片之記憶 格之面積佔有率降低，推動細微化也無法減小晶片面積， 因此成本會上昇。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -4- 522558 A7 B7 五、發明説明（2) -- (請先閲讀背面之注意事項再填寫本頁) 在這種問題之中，從寫入電壓之觀點有各種方式之提 案。相關技術可以舉出，注入2次電子所用之J. D. Bude et al., IEEE International Electron Device Meeting 1995，p989- 991 ，1995及利用台階差注 入源極一汲極間電場所用之 S. Oguraetal.， IEEE I international Electron Device Meeting 1 998, p9 8 7 -9 9 0，1 9 9 8 ° 經濟部智慧財產局員工消費合作社印製 同時，半導體非揮發性記憶器之其他課題有價格之問 題。目前與硬碟或光磁碟、DVD等比較，單位容量之價 格貴上數倍以上。因此低價格化很重要，但使單位格子所 記憶之資訊爲2位元之所謂多値記憶技術已實用化。這種 技術是控制注入記憶節點（浮置節點）內之電子數以準備 多數層次者。多値記憶之傳統技術例可舉出，T. Jung et a I., IEEE International Solid-State Circuit Conference 1996 ，p32 — 33 ，1996。同時，不是多數層 次，而是將1個格子之浮置閘分割爲2以記憶獨立之資訊 之技術有，IEEE Transaction on Components, packaging, and Manufacturing Technology Part A, Vol.2 0， 1 9 9 7 ° E C C技術可以降低對記憶格單體之可靠度之要求， 但相對的中間夾著電子電路，因此會犧牲掉讀出、寫入及 抹除之時間。因此，特別會被要求要有高速之閱讀速度之 應用領域，便無法使用此E C C技術，因而有格子之可靠 度立即影響到記憶器之成本之課題。 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -5- 522558 A7 B7 五、發明説明（3) (請先閱讀背面之注意事項再填寫本頁) 快閃記憶格係藉由在其浮置閘儲存電荷而記憶資訊， 但該浮置閘只要有一個地方有漏洩，該記憶格便成爲不良 品，因此，內含該記憶格之記憶裝置整體會變成不良品。 亦即，浮置閘之一個地方之漏洩使整個記憶格變成不良品 ，因此有，記憶格本身之製造成本變成高價格之課題。 因此，本發明之目的在提供，一方面保持高速讀出， 同時可以將製造成本壓低之半導體記憶裝置及其控制方法 0 如上述，從變更注入電荷方法之觀點有各種方式之提 案，而均能夠在較通常之快閃記憶器爲低電壓下注入電子 (寫入），但在放出電子（讀出）時使用電壓不變。同時 ，對短通道效果卻並位解決課題。 經濟部智慧財產局員工消費合作社印製 其次，說明在多値記憶時使用多數層次之課題如下。 首先是必須使格子之啓始電壓分布寬度較記憶單1位元時 狹窄，會變成爲了對齊寫入或抹除特性，讀出或寫入時返 覆進行在施加脈衝後讀出之證實（verify )動作。因此需要 較平均之注入電荷（放出）時間長數倍至數十倍之時間， 而招致晶片性能之降低。同時，在讀出動作時，也是在幾 次讀出動作後進行運算，輸出結果，因此性能會較通常之 單1位元記憶時降低。而且，由於準備之啓始電壓分布之 間隔狹窄，在記憶之可靠性存有課題。 同時，在分割浮置閘之技術，有較使用單一浮置閘準 備多數層次時，寫入讀出可以高速化之優點，但有加工困 難，單位格子構造變大，降低成本之效果不彰之課題。而 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -6 - 522558 A7 B7 五、發明説明（4) (請先閲讀背面之注意事項再填寫本頁) ，汲極端側注入電荷時會在汲極加上大電壓，使汲極端產 生熱電子。這種方式因爲注入浮置閘之電流對汲極電流之 比例很小，因此需要很大之汲極電流。因此，由於周邊電 路之電流驅動能力之限制，能夠同時寫入之格子數有限， 因而也有不適合大容量記憶之課題。 從以上各點，本發明之目的在提供，一方面可確保可 靠性，同時可實現縱方向之定標之格子構造。同時是在提 供，可以避免格子性能之大幅降低，而可增加每一格子之 記憶資訊之方法。而且是在提供，藉由如此之格子實現大 容量記憶裝置之方法。 本發明並非使用傳統之由單一電荷儲存領域構成之記 憶格，而是建議使用，在對應源極領域、汲極領域或源極 領域及汲極領域之位置，從主動領域介由絕緣層排列之多 數獨立之電荷儲存小領域形成之電荷儲存領域所構成之半 導體記憶格，藉此解決上述問題點。 本發明之具體架構、目的及特徵可以從以下之實施形 態獲得進一步之瞭解。 經濟部智慧財產局員工消費合作社印製 茲說明本發明之具體實施例之半導體格子、半導體裝 置及其製造方法如下。 (實施例1 ) 實施例1之半導體裝置之布置示於第1圖。在第1圖 之I I - I I位置向箭頭方向所視之從最小記憶單位之領 域J 6至鄰接之資料線接點J 5之範圍之截面示於第2圖 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -7- 522558 A7 B7 五、發明説明（5) (請先閲讀背面之注意事項再填寫本頁) 。而在第1圖之I I I - I I I位置向箭頭方向所視之最 小記憶單位之領域J 6之範圍之截面示於第3圖。實際上 是構成更大規模之陣列，但第1圖係爲了說明上之方便表 示3 X 4之小規模格子陣列。有設在p型矽基板之格子分離 領域J 1 7及電荷可以移動之主動領域J 1。垂直於此主 動領域J 1設有聚矽構成之字線J 2，及平行於此字線 J 2之鎢構成之源極線J 3。同時，垂直於此源極線J 3 設有鎢構成之資料線J 4。在主動領域J 1上，由字線 J 2所夾之領域設有用以連接資料線J 4與主動領域J 1 上之汲極J 8之資料線接點J 5。以一點虛線所示之領域 J 6是最小記憶單位。第1圖已表示幾乎所有之構成要素 之參照記號，因此在接下之圖式之不標示記號也能夠瞭解 者，擬適宜省略。 經濟部智慧財產局員工消費合作社印製 在第2圖，有設在p型矽基板之η型之源極領域J 7 、汲極領域J 8，在主動領域J 1上介由厚度1 1 n m之 絕緣膜J 9排列多數具備電荷儲存領域J 1 2、J 1 3之 功能之矽之平均粒徑1 3 n m之微小結晶粒J 1 〇。設有 控制電荷儲存領域之電位之η型多晶矽之字線J 2，矽微 小結晶粒J 1 0與字線J 2之間係從下依序爲厚度4 n m 之S i〇2、厚度8nm之S isN4、厚度4nm之 S i〇2之所謂〇N〇構造之絕緣膜J 1 1。J 1 4 -J 1 6係絕緣層。 在第3圖，構成電荷儲存領域之矽微小結晶粒分別係 獨立之半導體之電荷儲存小領域，因此在格子分離領域 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -8- 522558 A 7 B7 五、發明説明（6) (請先閲讀背面之注意事項再填寫本頁) J 1 7上殘留有電荷儲存領域J 1 8時，記憶器動作上不 會有問題。也可以藉由乾鈾刻、濕蝕刻或其組合，去除此 格子分離領域上之電荷儲存領域J 1 8。 在第4圖表示實施例1所用之記憶格單體在電路圖上 之標記，在相對應之部分標示相同之參照記號。 第5圖表示實施例1之等效電路。實際上是構成更大 規模之陣列，但爲說明方便，僅表示2 X 2之小規模之陣列 〇 其次說明實施例1之動作。本發明係同時在字線J 2 及資料線j 4施加電壓，令其產生熱電子，藉此將電子注 入電荷儲存領域J 1 2、J 1 3。 首先說明寫入動作。在此係令注入較多電荷之條件對 應資訊“ 1 ” ，令注入較少電荷之條件對應資訊“ 0 ” 。 經濟部智慧財產局員工消費合作社印製 以第5圖之以J 2 0表示之記憶格作爲選擇記憶格，僅在 此記憶格J 2 0寫入資訊“ 1 ”時之情形爲例子，說明如 下。將資料線J 2 6之電壓設定成可以形成足夠產生熱電 子之充分強之電場（例如5 V )。源極線J 3之電位設定 在0V。而且，將字線J 2 4之電壓設定成可以將產生之 熱電子引進電荷儲存領域（以下，有時稱作電荷儲存節點 )(例如11V)。這時，在格子內熱電子幾乎全是在資 料線J 2 6側產生，因此集中儲存在第2圖之電荷儲存領 域J 1 2之部分。 這時，關於非選擇記憶格J 2 1，可將字線J 2 5之 電位設定在格子內不會有電流流通之値（例如〇 V )。同 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -9 - 522558 A7 ____B7 五、發明説明（1) 時’非選擇記憶格J 2 2則將資料線J 2 7之電位設定在 格子內不會有電流流通之値（例如〇 V )。這時，非選擇 記憶格J 2 3也是將字線J 2 5電位、資料線j 2 7電位 、源極線J 3電位設定成格子內不會有電流流通之値（例 如Ο V )。因此，對選擇記憶格j 2 〇寫入資訊“ 1，，時 ’不會破壞非選擇記憶格J 2 1、j 2 2、J 2 3之資訊 。在此’將作爲具體例子之寫入電壓之關係整理成表1。 —Frll·---♦! (請先閲讀背面之注意事項再填寫本頁)522558 A7 B7 V. Description of the invention (1) The present invention relates to semiconductor memory cells and semiconductor devices. (Please read the notes on the back before filling out this page.) In recent years, flash memory for high-speed reading has been introduced to many portable devices. Generally speaking, high-speed reading is a memory cell array in which memory cells are connected in parallel, and one data line contact is provided for each two cells in parallel, thereby stray resistance is minimized for high-speed reading. This memory grid array has been well known since its early days, for example: Kume, Applied Physics, P. 1114 (1996). For flash memory, it is important to ensure the reliability of the memory cell. In order to ensure the guilt of this memory cell, many technical reforms have been made in the manufacturing process, but no fundamental technology has been developed so far. Currently widely used is the E C C technology that makes several long memory cells and replaces the bad cells with electrical circuits. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Due to the popularity of multimedia and the development of portable devices such as PDAs, digital cameras, and mobile phones, large-capacity non-volatile memories will become increasingly important in the future. In particular, from the viewpoints of miniaturization, high-speed retrieval, and impact resistance, semiconductor non-volatile memories typified by flash memories have been valued. However, due to the progress in large-capacity, although the grid size in the horizontal direction has decreased with the trend of processing technology, the longitudinal direction of the other side, that is, the scale in the film thickness direction has hardly progressed. This is because of the reliability problem caused by low electric field leakage, so it has been considered that in the near future, the short channel effect will indeed manifest itself. At the same time, because the operating voltage cannot be reduced, the size of the peripheral circuits cannot be reduced, and the area occupancy of the memory cells of the chip is reduced. The promotion of miniaturization cannot reduce the chip area, so the cost will increase. This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) -4- 522558 A7 B7 V. Description of invention (2)-(Please read the precautions on the back before filling this page) In this kind of problem There are various proposals from the viewpoint of a write voltage. Related technologies include JD Bude et al., IEEE International Electron Device Meeting 1995, p989-991, 1995, and S. Oguraetal. IEEE I international Electron Device Meeting 1 998, p9 8 7 -9 9 0, 19 9 8 ° Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. At the same time, other issues of semiconductor non-volatile memory have price issues. Compared with hard disks, optical disks, DVDs, etc., the price per unit capacity is several times more expensive. Therefore, low price is very important, but the so-called multi-bit memory technology that makes the information stored in a unit grid into two bits has been put into practical use. This technique is to control the number of electrons injected into the memory nodes (floating nodes) to prepare for most levels. Examples of traditional techniques for multi-memory memory include T. Jung et a I., IEEE International Solid-State Circuit Conference 1996, p32-33, 1996. At the same time, not at most levels, but the technology of dividing the floating gate of one grid into two to memorize independent information. There are IEEE Transaction on Components, packaging, and Manufacturing Technology Part A, Vol. 2 0, 1 9 9 7 ° ECC technology can reduce the requirement for the reliability of the single memory cell, but the electronic circuit is sandwiched in the middle, so the time of reading, writing and erasing will be sacrificed. Therefore, especially in applications where high-speed reading speed is required, this E C C technology cannot be used, so the reliability of the grid immediately affects the cost of the memory. This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) -5- 522558 A7 B7 V. Description of the invention (3) (Please read the precautions on the back before filling this page) Flash memory is borrowed Information is stored by storing charge in its floating gate, but as long as there is a leak in the floating gate, the memory cell becomes defective, so the entire memory device containing the memory cell becomes defective. That is, the leakage of one place of the floating gate makes the entire memory cell become defective, so there is a problem that the manufacturing cost of the memory cell itself becomes a high price. Therefore, an object of the present invention is to provide a semiconductor memory device and a control method thereof that can maintain high-speed readout while reducing manufacturing costs. As described above, various methods have been proposed from the viewpoint of changing the charge injection method, and all of them The electrons are injected (written) at a lower voltage than the usual flash memory, but the voltage is not changed when the electrons are emitted (read). At the same time, the effect of the short channel is solved in parallel. Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Next, we will explain the issues of using most levels in the case of multiple memories. The first is that the initial voltage distribution width of the grid must be narrower than that when the memory single bit is 1 bit, which will become aligned with the writing or erasing characteristics. When reading or writing, the verification will be performed after the pulse is read. )action. Therefore, it takes several times to dozens of times longer than the average charge injection (discharge) time, which results in a decrease in chip performance. At the same time, in the read operation, the calculation is performed after several read operations and the result is output, so the performance will be lower than that in the normal single-bit memory. In addition, since the interval between the initial voltage distributions for preparation is narrow, there is a problem in the reliability of the memory. At the same time, in the technology of dividing the floating gate, compared with the use of a single floating gate to prepare most levels, the write and read can be speeded up, but there are processing difficulties, the unit lattice structure becomes larger, and the effect of reducing costs is not outstanding Topic. And this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -6-522558 A7 B7 V. Description of the invention (4) (Please read the precautions on the back before filling this page), and inject the charge on the extreme side At the time, a large voltage is applied to the drain electrode, which causes a hot electron to be generated at the drain electrode. This method requires a very large drain current because the ratio of the current injected into the floating gate to the drain current is small. Therefore, due to the limitation of the current drive capability of the peripheral circuit, the number of grids that can be written simultaneously is limited, so there is a problem that it is not suitable for large-capacity memory. From the above points, an object of the present invention is to provide a grid structure that can ensure reliability on the one hand and achieve vertical calibration. At the same time, it is providing a method that can avoid a significant decrease in the performance of the grid and increase the memory information of each grid. Furthermore, a method for realizing a large-capacity memory device by using such a grid is provided. The present invention does not use a traditional memory cell composed of a single charge storage field, but rather proposes to use it in a position corresponding to the source field, the drain field, or the source field and the drain field. The semiconductor memory cell formed by the charge storage field formed by most independent small charge storage fields solves the above problems. The specific structure, purpose, and characteristics of the present invention can be further understood from the following implementation forms. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economics The semiconductor grid, semiconductor device and manufacturing method thereof according to specific embodiments of the present invention are described below. (Embodiment 1) The layout of the semiconductor device of Embodiment 1 is shown in FIG. The cross section of the range from the smallest memory unit J 6 to the adjacent data line joint J 5 viewed from the direction of the arrow at the positions II-II in Fig. 1 is shown in Fig. 2. The paper dimensions are applicable to the Chinese national standard (CNS ) A4 specification (210X297 mm) -7- 522558 A7 B7 V. Description of the invention (5) (Please read the precautions on the back before filling this page). The cross section of the range of the smallest memory unit J 6 viewed from the position of I I I-I I I in the direction of the arrow in Fig. 1 is shown in Fig. 3. It actually constitutes a larger-scale array, but Figure 1 shows a 3 × 4 small-scale grid array for convenience of explanation. There are a grid separation area J 1 7 located on a p-type silicon substrate and an active area J 1 where charges can move. A word line J 2 made of polysilicon and a source line J 3 made of tungsten parallel to this word line J 2 are provided perpendicular to this active area J 1. At the same time, a data line J 4 made of tungsten is provided perpendicular to the source line J 3. On the active area J1, the area sandwiched by the word line J2 is provided with a data line contact J5 for connecting the data line J4 to the drain J8 on the active area J1. The area indicated by a dotted line J 6 is the smallest unit of memory. Figure 1 already shows the reference signs of almost all the constituent elements. Therefore, those who do not mark the following figures can also be understood, and it is appropriate to omit them. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed in Figure 2. There are n-type source areas J 7 and drain areas J 8 located on p-type silicon substrates. In the active area J 1, the thickness is 1 1 nm. Most of the insulating film J 9 arrays have minute crystal grains J 1 0 having an average particle diameter of 13 nm and silicon having functions of charge storage fields J 1 2 and J 1 3. An η-type polycrystalline silicon word line J 2 for controlling the potential in the charge storage area is provided. The silicon micro-crystal grains J 1 0 and the word line J 2 are in order from below with a thickness of 4 nm and a thickness of 8 nm. S is N4, an insulating film J 1 1 with a so-called 〇NO structure with a thickness of 4 nm and SiO2. J 1 4 -J 1 6 series insulation layer. In Figure 3, the silicon micro-crystal grains forming the charge storage field are small charge storage fields of independent semiconductors. Therefore, in the field of grid separation, this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -8- 522558 A 7 B7 V. Description of the invention (6) (Please read the precautions on the back before filling this page) When there is a charge storage area on J 1 7 and J 1 8, there will be no problem in memory operation. The charge storage area J 1 8 in the lattice separation area can also be removed by dry uranium etching, wet etching, or a combination thereof. Fig. 4 shows the circuit diagram marks of the memory cells used in the first embodiment, and the corresponding reference signs are marked in the corresponding parts. Fig. 5 shows an equivalent circuit of the first embodiment. Actually, it constitutes a larger-scale array, but for convenience of explanation, only a small-scale array of 2 × 2 is shown. Next, the operation of the first embodiment will be described. In the present invention, a voltage is applied to the word line J 2 and the data line j 4 at the same time to cause them to generate hot electrons, thereby injecting electrons into the charge storage field J 1 2 and J 1 3. First, the writing operation will be described. Here, the condition for making more charge injection corresponds to the information "1", and the condition for making less charge injection corresponds to the information "0". The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed the memory cell represented by J 2 0 in Figure 5 as the selected memory cell. Only the case where the information "1" is written in this memory cell J 2 0 is taken as an example, as follows: . The voltage of the data line J 2 6 is set so as to form a sufficiently strong electric field (for example, 5 V) sufficient to generate thermoelectrons. The potential of the source line J 3 is set to 0V. Further, the voltage of the word line J 2 4 is set so that the generated hot electrons can be introduced into a charge storage field (hereinafter, sometimes referred to as a charge storage node) (for example, 11V). At this time, since almost all the hot electrons are generated in the grid on the data line J 2 6 side, they are concentratedly stored in the charge storage area J 1 2 in Fig. 2. At this time, regarding the non-selective memory cell J 2 1, the potential of the word line J 2 5 can be set in the cell where no current can flow (for example, 0 V). The same paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -9-522558 A7 ____B7 V. Description of the invention (1) When 'non-selected memory cell J 2 2' is set the potential of the data line J 2 7 There will be no current flowing in the grid (such as 0V). At this time, the non-selected memory cell J 2 3 also sets the potential of the word line J 2 5, the potential of the data line j 2 7, and the potential of the source line J 3 so that no current can flow in the cell (for example, 0 V). Therefore, writing information “1,” to the selected memory cell j 2 〇 will not destroy the information of the non-selected memory cell J 2 1, j 2 2, J 2 3. Here, the writing voltage will be used as a specific example The relationship is arranged in Table 1. —Frll · --- ♦! (Please read the precautions on the back before filling this page)

〔表1〕 選擇字線 非選擇字 選擇資料線 非選擇資料 源極線 電壓 線電壓 電壓 線電壓 電壓 1 1 V 0V 5V 0V 0V 訂 -•T. 經濟部智慧財產局員工消費合作社印製 這時，電荷儲存領域由單一半導體構成之傳統之快閃 記憶器在非選擇記憶格J 2 1 ，字線與資料線之間有高電 壓，只要在電荷儲存領域與資料線之間形成有1處漏洩路 徑，儲存之資訊便會在記憶格單位被完全破壞掉。因此， 字線與資料線間之絕緣耐壓之品質管理非常重要，甚至於 招致記憶裝置整體成本之增加。然而，實施例1之構成電 荷儲存領域之矽之微小結晶粒是分別獨立之半導體之電荷 儲存小領域，因此僅是連接在漏洩路徑之一部分微小結晶 粒之電荷會損失，儲存之資訊不會以記憶格單位被完全破 壞掉，因此可以穩定記憶資訊，降低製造成本。 本紙張尺度適用中囪國家標準^阳丨从規格。10、〆29%^^) •10- 522558 A7 B7 五、發明説明（8) (請先閲讀背面之注意事項再填寫本頁) 對非選擇記憶格J 2 2也同樣。因改寫應力使隧道氧 化膜發生劣化，在低電場下，只要在電荷儲存領域發生有 一處之漏洩，儲存之資訊便被完全破壞。因此，隧道氧化 膜施加有應力時絕緣耐壓之品質管理非常重要，甚至於招 致記憶裝置整體成本之增加。在此也與非選擇記憶格 J 2 1時完全一樣，實施例1係僅是連接在漏洩路徑之一 部分微小結晶粒之電荷會損失，因此可以防止儲存之資訊 以記憶格單位被完全破壞掉，可以穩定記憶資訊，降低製 造成本。 經濟部智慧財產局員工消費合作社印製 同時，在寫入動作時施加負之基板偏壓（例如-2 V )，而相對降低字線J 2 5之電壓（例如9 V )之方法很 有效。基板之負偏壓可以藉引進3重井構造而達成。這時 ，由相鄰之數個記憶格（例如J 2 1、J 2 2、J 2 3 ) 共用P井。因爲能夠降低所使用之字線電壓之絕對値，除 了電壓產生電路變單純之優點以外，另有容易在汲極領域 J 8產生電場之集中，電子之注入效率可以提高之特徵。 茲將使用基板偏壓進行寫入時之電壓關係之具體例子整理 成表2。 〔表2〕[Table 1] Selected word line Non-selected word Selected data line Non-selected data source line voltage line voltage voltage line voltage voltage 1 1 V 0V 5V 0V 0V Order- • T. At this time, printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, The traditional flash memory composed of a single semiconductor in the field of charge storage has a non-selective memory cell J 2 1 and there is a high voltage between the word line and the data line. As long as a leak path is formed between the charge storage field and the data line , The stored information will be completely destroyed in the memory cell unit. Therefore, the quality management of the insulation and withstand voltage between the word line and the data line is very important, even causing an increase in the overall cost of the memory device. However, the small crystal grains of silicon constituting the charge storage field of Example 1 are small fields of charge storage of separate semiconductors, so only the charge of the small crystal grains connected to a part of the leakage path will be lost, and the stored information will not be lost. The memory cell unit is completely destroyed, so it can stably memorize information and reduce manufacturing costs. This paper size applies to the national standard ^ Yang 丨 from the specifications. 10. 〆29% ^^) • 10- 522558 A7 B7 V. Description of the invention (8) (Please read the notes on the back before filling this page) The same is true for non-selected memory cells J 2 2. The oxide film of the tunnel is degraded due to the rewriting stress. Under a low electric field, as long as there is a leak in the charge storage field, the stored information is completely destroyed. Therefore, the quality management of the insulation withstand voltage when the tunnel oxide film is stressed is very important, and even causes an increase in the overall cost of the memory device. This is also exactly the same as when the non-selective memory cell J 2 1 is used. In Example 1, only the charge of the tiny crystal particles connected to a part of the leakage path will be lost, so the stored information can be prevented from being completely destroyed by the memory cell unit. Can stably memorize information and reduce manufacturing costs. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs At the same time, a negative substrate bias voltage (for example, -2 V) is applied during the write operation, and the method of relatively reducing the voltage of the word line J 2 5 (for example, 9 V) is effective. The negative bias of the substrate can be achieved by introducing a triple-well structure. At this time, P wells are shared by several adjacent memory cells (for example, J 2 1, J 2 2, J 2 3). Because the absolute voltage of the zigzag line voltage can be reduced, in addition to the advantages of the simple voltage generating circuit, it is also easy to generate a concentration of an electric field in the drain region J 8, and the electron injection efficiency can be improved. Specific examples of the voltage relationship when writing using the substrate bias are summarized in Table 2. 〔Table 2〕

選擇字線 非選擇字 選擇資料 非選擇資 源極線 基板電壓 電壓 線電壓 線電壓 料線電壓 電壓 9V 0V 5V 0V 0V -2V 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -11 - 522558 A7 B7 五、發明説明（9) (請先閱讀背面之注意事項再填寫本頁) 再說明資訊之抹除動作。關於資訊之抹除係對同一字 線驅動之格子整批進行抹除。在此擬說明第5圖中之同一 字線J 2 4所驅動之選擇記憶格J 2 0、J 2 2之抹除動 作。在字線J 2 4施加負電壓（例如-2 1 V )。而例如 使源極線J 3、資料線J 2 6、J 2 7之電位爲Ο V。這 時，因高電場，注入之電子被放出到基板側。再者，這時 也可以將井電位設定成較Ο V爲高之電位（例如5 V )， 相對地將施加於字線J 2 4之電壓之絕對値設定成較小（ 例如-1 6 V )。使用電壓之絕對値變小，可以簡化電壓 產生電路。 經濟部智慧財產局員工消費合作社印製 在抹除動作，對具有單一電荷儲存領域之傳統技術， 本發明之優位性也是與寫入動作相同。在傳統技術，施加 改寫應力後，只要有一處發生隧道氧化膜之絕緣耐壓劣化 ，便有可能會發生抹除速度極端快之記憶格之不良事故。 抹除速度極端快之記憶格會成爲平常導通狀態，讀出資料 時引起誤動作。但具有由多數個分別獨立之半導體之電荷 儲存小領域構成之電荷儲存領域之實施例1，則與寫入時 完全相同，僅是連接在漏洩路徑之一部分微小結晶粒之電 荷會損失，因此可以穩定記憶資訊，降低製造成本。 再說明資訊之讀出動作。以選擇記憶格J 2 0之資訊 之讀出爲例說明如下。例如，資料線J 2 6之電壓設定成 2 V，源極線J 4之電壓設定成Ο V，在字線J 2 4施加 2 V之讀出脈衝。因注入電荷儲存領域之電荷量之大小， 啓始電壓會不相同，因此記憶“ 0 ”之資料線J 2 6之電 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -12- 522558 A7 B7 五、發明説明（ 流較記憶“ 1 ”之資料線J 2 6之電流大’因此可以讀出 資訊。 其次說明實施例1之製造過程。形成元件分離領域 J 17、3重井構造後，爲了調整啓始電壓’在P井上之 記憶格形成領域打入硼離子。將基板表面氧化’形成厚度 10nm之隧道氧化膜J9後，藉CVD ( Chemical Vapor Deposition)形成矽微小結晶粒J 1 0。試作時’以 平均7nm，1平方公分5X1011個之密度形成。從下方 依序形成厚度4nm之S i〇2、厚度8nm之S i 3Ν4 、厚度4 n m之S i〇2之〇N ◦構造之層間絕緣膜J 1 1 。在這個階段，使用抗蝕劑罩進行相當於周邊電路部分閘 極之部分之〇N〇膜之乾蝕刻，矽微結晶之乾蝕刻’打入 調整啓始用之雜質，再進行氧化。矽微結晶之鈾刻也可以 用濕蝕刻，或乾蝕刻與濕蝕刻之組合。亦可重覆0 N 0膜 乾蝕刻至氧化之處理程序兩次以上，而在周邊電路使用兩 種以上之閘極氧化膜。 爲了形成周邊電路部分之閘電極與記憶格字線J 2 ’ 堆積2 0 0 nm之η型多晶矽，再堆積3 0 0 nm之 S i ◦ 2。以抗蝕劑罩對記憶格部及周邊電路部分進行 S i〇2之乾蝕刻。此結果，在記憶格部分將如J 1 4會殘 留S i〇2。再進行多晶矽之乾蝕刻。在此，僅對記憶格以 抗蝕劑罩開口，對Ο N 0膜進行乾蝕刻。以這種狀態打入 砷、硼之雜質，進行活性化退火。因此，記憶格部源極領 域J 7、汲極領域J 8在這個階段係由砷所成之部分 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ί厂卜——Φ—, (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 -13- 522558 A7 B7 五、發明説明（1) J 7A、J 8A及由硼所成之部分J 7B、J 8B所構成 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 。周邊電路部分也同樣藉由打入雜質形成源極領域、汲極 領域。此後，堆積S i 3 N 4，再堆積s i〇2。進行平坦 化，再堆積S i 0 2。在此，以抗蝕劑罩將記憶格部資料線 接點，及源極線開口。以乾鈾刻去除開口部分之S i〇2。 未被去除之S i〇2會如J 1 6殘留下來。這時，因底材是 S i 3N4，因此由於S i〇2及S i 3N4在乾蝕刻時之選 擇性，縱使記憶格部資料線接點、源極線之抗鈾劑圖案多 少有偏移時，仍會以自行匹配方式開口於正確之汲極領域 、源極領域。而且，由於蝕刻底材之S i 3 N 4，可使基板 之源極領域、汲極領域開口。由於此S i 3 N 4之飽刻，而 形成由S i 3 N 4構成之側壁J 1 5。在此，爲了加強接點 之軔性，而打入磷之雜質，進行活性化退火。磷會擴散至 J 8 C之部分。此後，也可以堆積S i〇2之薄膜，再進行 退蝕刻，以防止資料線接點J 5間之短路。然後，周邊電 路部分也以抗蝕劑罩開口，進行鈾刻，爲了加強接點之軔 性，同樣打入雜質，進行活性化退火。此後，堆積鎢，進 行平坦化。平坦化後，堆積S i ◦ 2，以抗蝕劑罩蝕刻記憶 格汲極接點部分而予以開口。然後，再度堆積鎢。以抗蝕 劑罩蝕刻此鎢，形成資料線J 4。以下返覆同樣之製程， 進行配線製程。 (實施例2 ) 說明第2實施例。記憶格布置、截面圖、等效電路與 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） _ -14- 522558 A7 ___B7 五、發明説明（0 (請先閲讀背面之注意事項再填寫本頁) 實施例1相同。以下說明實施例2之動作。在實施例2， 係藉由改變電荷儲存之處所，以進行每一格子2 b i t以 上之記憶。 首先說明資訊之寫入。茲以將電荷注入第5圖之選擇 記憶格J 2 0之資料線J 2 6側之電荷儲存領域J 1 3， 藉此寫入資訊“ 〇 1 ”爲例子說明如下。將資料線J 2 6 之電壓設定成可以形成足夠產生熱電子之充分強之電場（ 例如5 V )。源極線J 3之電位設定在Ο V。而且，將字 線J 2 4之電壓設定成可以將產生之熱電子引進電荷儲存 領域（例如1 1 V )。這時，在選擇格子J 2 0內，熱電 子幾乎全是產生在連接在資料線J 2 6側之電荷儲存領域 ，因此集中儲存在第2圖之電荷儲存領域J13之部分。 這時，連接在源極線J 3側之電荷儲存領域幾乎不會產生 熱電子，因此不會發生破壞連接在源極線〗3側之電荷儲 存領域J 1 2之資訊之情事。若希望藉由將電荷注入連接 在源極線J 3側之電荷儲存領域J 1 2，以寫入資訊“ 經濟部智慧財產局員工消費合作社印製 10” ，將上述設定之資料線J 2 6與源極線J 3之電壓 對調即可。 而在冩入動作時，施加負之基板偏壓（例如- 2 V ) ，相對降低字線J 2 4之電壓（例如9 V )之方法有效， 係與實施例1相同。 再說明資訊之抹除動作。關於資訊之抹除係由同一字 線驅動之格子整批進行抹除。在此擬說明第5圖中之同一 字線J 2 4所驅動之選擇記憶格J 2 〇、J 2 2之抹除動 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -15- 522558 A7 ___B7_ 五、發明説明（ (請先閱讀背面之注意事項再填寫本頁) 作。在字線J 2 4施加負電壓（例如-2 1 V )。而例如 使源極線J 3、資料線J 2 6、J 2 7之電位爲〇 V。這 時，因高電場，注入之電子被放出到基板側。再者，這時 也可以將井電位設定成較Ο V爲高之電位（例如5 V )， 相對地將施加於字線J 2 4之電壓之絕對値設定成較小（ 例如-1 6 V )。使用電壓之絕對値變小，可以簡化電壓 產生電路。 經濟部智慧財產局員工消費合作社印製 參照第6圖說明讀出動作如下。在此，擬以從選擇記 憶格J 2 0讀出資訊爲例子進行說明。令構成選擇記憶格 J 2 0之電晶體在飽和領域動作。要讀出儲存在源極線 J 3側之電荷儲存領域J 1 2之資訊時，在資料線J 2 6 施加2 V，在源極線J 3施加Ο V，在字線J 2 4施加 2V。這時會形成通道J30，但字線J24直下方之連 接在基板表面附近中之資料線J 2 6之一側成夾斷（pinch off)之狀態，因此不會形成通道。其結果，僅源極線J 3 側之電荷儲存領域J 1 2會對啓始電壓產生影響，可去除 資料線J 2 6側之電荷儲存領域J 1 3之儲存電荷之影響 。若源極線J 3側之電荷儲存領域J 1 2之儲存電荷多， 啓始電壓會高，少則啓始電壓會低，因此，選擇記憶格 J 2 0之電導會依儲存電荷量而異。此電導之差異使流通 之電流不相同，而因資料線之電壓不相同，從資料線之電 壓之差異可以讀出資訊。要讀出資料線J 2 6側之電荷儲 存領域J 1 3之資訊時，將資料線J 2 6與資料線J 3之 設定電壓對調即可。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -16- 522558 A7 B7 五、發明説明（u (請先閱讀背面之注意事項再填寫本頁) 上述寫入動作、讀出動作係單純替換源極、汲極之設 定電壓便可以切換。因此，較之藉由注入單一浮置閘中之 電荷量作成4個層次之方式，寫入動作、讀出動作所需要 之步驟較少，可以高速度動作。同時，在電荷儲存領域之 兩端會成爲資訊是“ 0 ”或“ 1 ”之兩個層次之動作，因 此動作邊際也會增加。 在傳統之寫入動作，若使用多層次時，有必要高度抑 制啓始電壓之格子間分布之擴大。因此是進行，施加寫入 脈衝後進行讀出，未達一定之啓始電壓時再度施加寫入脈 衝之返覆動作之所謂證實（verify)動作，而成爲總寫入量 降低之主因。因此實施例2之高速化之效果在寫入動作時 特別顯著。除此之外，實施例2係構成電荷儲存領域之矽 之微小結晶粒很多，所以進行平均化。其結果，格子間之 參差不齊減低，不作證實動作也有可能進行每一格子記憶 2位元之動作。寫入平均化對起因於隧道絕緣膜之缺陷等 ，而在某格子寫入會異常高速進行之不良事故很有效。 經濟部智慧財產局員工消費合作社印製 其次說明包含周邊電路之記憶裝置整體之驅動方法。 首先參照第7圖說明寫入動作。依照從外部輸入之位址產 生指示是要進行源極端寫入或汲極端寫入之信號 WSERECT J 40。對應產生之信號 WSERECT J 40將源極線J41之電壓切換至 VW S S或VW S D之任一方。輸入資料係先儲存在閃鎖 J 4 2。在此係令電壓h i g h對應“ 1 ” ，電壓1 〇 w 對應“ 0 ” 。在格子J 4 3之源極端寫入動作時，係在源 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -17- 522558 Α7 Β7 五、發明説明（1$ (請先閲讀背面之注意事項再填寫本頁) 極線J 4 1施加V w S S (例如ο V )，欲寫入之資訊是 “ 〇 ”時，將資料線j 4 4之電壓設定在V W D L (例如 Ο V )，欲寫入之資訊是“ 1 ”時’將資料線J 4 4之電 壓設定在較高之電壓VWDH (例如5V)，將高電壓Selected word line Non-selected word Selection data Non-selected resource electrode line substrate voltage voltage line voltage line voltage line voltage 9V 0V 5V 0V 0V -2V This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) -11 -522558 A7 B7 V. Description of the invention (9) (Please read the precautions on the back before filling this page) Then explain the erasing action of the information. The erasure of information is to erase the entire batch of grids driven by the same word line. Here, the erasing operation of the selection memory cells J 2 0 and J 2 2 driven by the same word line J 2 4 in FIG. 5 will be described. A negative voltage (for example, -2 1 V) is applied to the word line J 2 4. For example, the potentials of the source lines J 3 and the data lines J 2 6 and J 2 7 are set to 0 V. At this time, due to the high electric field, the injected electrons are released to the substrate side. Furthermore, at this time, the well potential can also be set to a potential higher than 0 V (for example, 5 V), and the absolute value of the voltage applied to the word line J 2 4 can be set to be relatively small (for example, -1 6 V). . The absolute value of the applied voltage becomes smaller, which can simplify the voltage generating circuit. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. In the erasing action, for the traditional technology with a single charge storage field, the superiority of the present invention is also the same as the writing action. In the conventional technology, after the rewriting stress is applied, as long as the insulation withstand voltage of the tunnel oxide film is deteriorated, a bad accident of erasing the memory cell with extremely fast speed may occur. The memory cell with extremely fast erasing speed will become the normal conduction state, which will cause malfunction when reading data. However, Embodiment 1 having a charge storage field composed of a plurality of independent semiconductor small charge storage fields is exactly the same as that at the time of writing, except that the charge of the small crystal grains connected to a part of the leakage path is lost, so Stably memorize information and reduce manufacturing costs. The operation of reading information will be described again. Take the reading of the information in the selected memory cell J 2 0 as an example. For example, the voltage of the data line J 2 6 is set to 2 V, the voltage of the source line J 4 is set to 0 V, and a read pulse of 2 V is applied to the word line J 2 4. Due to the amount of charge injected into the field of charge storage, the initial voltage will be different, so the data line J 2 6 with the memory of "0" is printed in accordance with China National Standard (CNS) A4 (210X297 mm) -12 -522558 A7 B7 V. Description of the invention (the current is larger than that of the data line J 2 6 with memory "1", so the information can be read out. Next, the manufacturing process of Example 1 will be described. Formation of component separation field J 17, 3 heavy well structure Later, in order to adjust the starting voltage, boron ions were implanted in the memory cell formation area on the well P. The substrate surface was oxidized to form a tunnel oxide film J9 with a thickness of 10 nm, and then silicon microcrystalline particles J 1 were formed by CVD (Chemical Vapor Deposition). 0. At the time of trial production, it was formed at an average density of 7nm and 5X1011 pieces per square centimeter. From the bottom, S i〇2 with a thickness of 4 nm, S i 3N4 with a thickness of 8 nm, and SnO2 with a thickness of 4 nm were sequentially formed. Structured interlayer insulation film J 1 1. At this stage, dry etching of the OON film equivalent to the gate portion of the peripheral circuit portion using a resist mask, and dry etching of silicon microcrystals are used to start adjustment. Impurities Oxidation is then performed. The uranium engraving of silicon microcrystals can also be performed by wet etching, or a combination of dry etching and wet etching. It can also repeat the 0 N 0 film dry etching to oxidation process more than two times, and use two in peripheral circuits. In order to form the gate electrode of the peripheral circuit portion and the memory grid word line J 2 ′, η-type polycrystalline silicon at 200 nm is deposited, and Si i at 300 nm is deposited. 2. With a resist The cover performs dry etching on the memory grid portion and the peripheral circuit portion. As a result, the memory grid portion will leave S i02 as J 1 4. Then, dry etching of polycrystalline silicon is performed. Here, only the memory is etched. The grid is opened with a resist cover, and the 0 N 0 film is dry-etched. In this state, impurities such as arsenic and boron are inserted, and activation annealing is performed. Therefore, the memory cell source region J 7 and the drain region J 8 At this stage, part of the paper is made of arsenic. The size of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm). Ί Factory Bu — Φ — (Please read the precautions on the back before filling this page.) Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau-13- 522558 A7 B 7 V. Description of the invention (1) J 7A, J 8A and J 7B, J 8B made of boron (please read the notes on the back before filling this page) Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs The peripheral circuit part also forms a source region and a drain region by injecting impurities. Thereafter, S i 3 N 4 is deposited, and then SiO 2 is deposited. The planarization is performed, and S i 0 2 is deposited. Here, the The resist cover opens the data line contacts of the memory grid and the source line. Sio2 at the opening was removed with dry uranium engraving. Unremoved S i02 will remain as J 1 6. At this time, because the substrate is Si 3N4, due to the selectivity of Si 102 and Si 3N4 during dry etching, even if the uranium-resistance pattern of the data line contacts and source lines of the memory cell is somewhat offset, , It will still open in the correct drain and source fields by self-matching. In addition, the Si 3 N 4 of the etching substrate can open the source region and the drain region of the substrate. Due to the saturation of this S i 3 N 4, a side wall J 1 5 composed of S i 3 N 4 is formed. Here, in order to strengthen the contact property, an impurity of phosphorus is injected and an activation annealing is performed. Phosphorus will diffuse to the part of J 8 C. After that, a thin film of Si02 can also be deposited and then etched back to prevent a short circuit between the data line contacts J5. Then, the peripheral circuit portion is also opened with a resist cover and etched with uranium. In order to enhance the contact resistance, impurities are similarly injected and activated annealing is performed. Thereafter, tungsten is deposited and planarized. After the planarization, S i ◦ 2 was deposited, and the memory cell drain contact portion was etched with a resist cover to be opened. Then, tungsten was accumulated again. This tungsten is etched with a resist mask to form a data line J4. The same process is repeated below to perform the wiring process. (Embodiment 2) A second embodiment will be described. The layout of the memory cells, cross-sections, equivalent circuits, and dimensions of this paper are applicable to the Chinese National Standard (CNS) A4 (210X297 mm) _ -14- 522558 A7 ___B7 V. Description of the invention (0 (Please read the precautions on the back before (Fill in this page) The same as in Example 1. The operation of Example 2 will be described below. In Example 2, the charge storage location is changed to perform memory of more than 2 bits per grid. First, the writing of information will be described. Take the charge storage area J 1 3 on the data line J 2 6 side of the selected memory cell J 2 0 in FIG. 5 to write the information “〇 1” as an example. The data line J 2 6 The voltage is set to form a sufficiently strong electric field (for example, 5 V) sufficient to generate hot electrons. The potential of the source line J 3 is set to 0 V. Moreover, the voltage of the word line J 2 4 is set to set the generated hot electrons. Introduce a charge storage field (for example, 1 1 V). At this time, in the selection grid J 2 0, the hot electrons are almost all generated in the charge storage field connected to the data line J 2 6 side, so the charges are concentratedly stored in Figure 2 Part of storage area J13 At this time, there is almost no generation of hot electrons in the charge storage area connected to the source line J 3 side, so there is no possibility of destroying the information in the charge storage area J 1 2 connected to the source line 3 side. Charge is injected into the charge storage area J 1 2 connected to the source line J 3 side to write the information “Printed by the Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy 10”, and the data line J 2 6 set above and the source line The voltage of J 3 can be reversed. In the insertion operation, a method of applying a negative substrate bias voltage (for example,-2 V) and relatively reducing the voltage of the word line J 2 4 (for example, 9 V) is effective. 1 is the same. The erasing action of information will be explained again. The erasing of information is erased in a batch by grids driven by the same word line. Here we will explain the selection memory driven by the same word line J 2 4 in Figure 5. The erasure of J 2 〇, J 2 2 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -15- 522558 A7 ___B7_ V. Description of the invention ((Please read the notes on the back before filling On this page). Apply negative voltage to word line J 2 4 ( For example, -2 1 V). For example, the potential of the source line J3, the data lines J2 6, and J2 7 is 0V. At this time, the injected electrons are released to the substrate side due to the high electric field. Furthermore, at this time The potential of the well can also be set higher than 0 V (for example, 5 V), and the absolute value of the voltage applied to the word line J 2 4 can be set to be relatively small (for example,-16 V). The absolute chirp becomes smaller, which can simplify the voltage generation circuit. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, referring to Figure 6, the reading operation is as follows. Here, the description will be made by taking information read from the selection memory J 2 0 as an example. The transistor constituting the selective memory cell J 2 0 is caused to operate in the saturation field. To read the information stored in the charge storage area J 1 2 on the source line J 3 side, apply 2 V to the data line J 2 6, apply 0 V to the source line J 3, and apply 2 V to the word line J 2 4 . At this time, the channel J30 is formed, but one side of the data line J 2 6 connected directly below the word line J24 in the vicinity of the substrate surface is pinched off, so no channel is formed. As a result, only the charge storage area J 1 2 on the source line J 3 side will affect the initial voltage, and the influence of the stored charge in the charge storage area J 1 3 on the data line J 2 6 side can be removed. If there is more stored charge in the charge storage area J 1 2 on the source line J 3 side, the starting voltage will be higher, at least the starting voltage will be lower. Therefore, the conductance of the selected memory cell J 2 0 will vary depending on the stored charge amount. . This difference in conductance makes the current flowing different, and because the voltage of the data lines is different, the information can be read from the difference in voltage of the data lines. To read out the information of the charge storage area J 1 3 on the data line J 2 6 side, the data line J 2 6 and the data line J 3 set voltage can be reversed. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -16- 522558 A7 B7 V. Description of the invention (u (Please read the precautions on the back before filling this page) The above writing and reading actions It can be switched by simply replacing the set voltage of the source and the drain. Therefore, compared with the method of making four levels by injecting the amount of charge into a single floating gate, fewer steps are required for the write operation and the read operation. , Can operate at high speed. At the same time, the two ends of the charge storage field will become two levels of information "0" or "1", so the margin of action will increase. In the traditional writing action, if you use more It is necessary to suppress the expansion of the inter-lattice distribution of the starting voltage to a high degree at the time of gradation. Therefore, it is to perform the so-called verification that the writing pulse is read again after the writing pulse is applied. (Verify) operation, which is the main cause of the decrease in the total write amount. Therefore, the effect of the high-speed operation of Example 2 is particularly significant during the write operation. In addition, Example 2 constitutes a charge storage. There are many small crystal grains of silicon in the field, so the averaging is performed. As a result, the unevenness between the grids is reduced, and it is possible to perform a 2-bit memory operation for each grid without confirming the operation. The write averaging is caused by the tunnel insulation. Defects such as membranes, and the bad accidents where writing at a certain grid can be performed at an extremely high speed are very effective. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Next, the driving method of the entire memory device including peripheral circuits will be explained. Write action. According to the address input from the external input, the signal WSERECT J 40 is used to write to the source terminal or the sink terminal. The corresponding signal WSERECT J 40 switches the voltage of the source line J41 to VW SS or Either VW SD. The input data is stored in the flash lock J 4 2. The voltage high corresponds to "1" and the voltage 1 0w corresponds to "0". When the source extreme of grid J 4 3 is written It is based on the Chinese paper standard (CNS) A4 specification (210X297 mm) at the source paper size. -17- 522558 Α7 Β7 5. Description of the invention (1 $ (please read the back first) Note that this page is to be filled in again.) When the polar line J 4 1 is applied with V w SS (for example ο V) and the information to be written is “〇”, the voltage of the data line j 4 4 is set to VWDL (for example 0 V). When the information to be written is "1", the voltage of the data line J 4 4 is set to a higher voltage VWDH (for example, 5V), and the high voltage

V W W (例如1 2 V )之脈衝供給字線J 4 5。設定在 VWD L時幾乎不會產生熱電子，因此注入記憶節點之電 荷很少，設定在VWDH時注入之電荷量較大。這時，對 以同一字線驅動之其他格子，若同樣對應欲寫入之資料將 連接之資料線之電壓設定成VWD L或VWD Η，便可以 同時寫入資訊。在此，“ 0 ”寫入時不會注入電荷，相當 於未寫入，因此可以僅在同一字線驅動之格子之一部分寫 入資訊。而其他之字線若設定在較VWW低之電壓VWO (例如0 V )便不會有寫入。 其次說明在汲極端之寫入動作。在源極線J 4 1加上 經濟部智慧財產局員工消費合作社印製 V W S D (例如5 V )，而資料線J 4 4之電壓則與源極 端寫入時一樣，資訊是“ 〇 ”時設定在V W D L (例如 0V)，資訊是“1”時設定在VWDH (例如5V)。 然後，對字線J 4 5施加高電壓V W W (例如1 2 V )之 脈衝，便可以寫入。在此，源極端寫入時資料線V w D Η 是電荷注入條件，但汲極端寫入時資料線V W D L爲電荷 注入條件，因此，其特徵是，所記憶之資訊與啓始電壓之 高低對應關係在源極端與汲極端會逆轉。 資訊之抹除動力係對同一字線驅動之格子以整批進行 ，同時抹除源極端與汲極端之資訊。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -18- 522558 A7 B7 五、發明説明（1自 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 接著再參照第8圖說明資訊讀出動作。首先’對應從 外部施加之欲讀出之記憶格之位址’產生指示是要進行源 極_讚出或汲極端讀出之信號RSERECT J 50 。從此位址產生選擇信號R S E R E C T之電路可以與寫 入時之選擇信號產生電路共用。對產生之信號 R S E R E C T J 5 0，如以下所說明，切換源極線 J 5 1電壓、預充電電壓及參考電壓。要讀出格子5 5之 源極端資訊時，將源極線J 5 1設定在V R S S (例如 0 V )，將資料線J 5 2預充電至較VRSS高之電壓 v P C S (例如3 V )後，將電壓v W R (例如2 V )之 讀出脈衝施加在字線。這時，若源極端之電壓較高時，不 太會有電流流通，資料線J 5 2電位在V P C S不會有什 麼變動，但源極端之啓始電壓低時會有很大之電流，資料 線J 5 2之電位會從VP C S大幅度下降。差動放大型之 感測放大器J 5 4之一端連接在資料線，在另一端J 5 5 則施加較V P C S小之電壓V R E F S (例如2 . 4 V ) 作爲參照電壓。令感測放大器J 5 4以一定之定時動作， 藉此在源極端之啓始電壓高時放大至高電位，低時以放大 至低電位。此感測放大器起動定時在啓始電壓低時，也是 設定成記憶格可在飽和領域動作之資料線電壓在高電壓之 狀態較佳。亦即，源極端之啓始電壓低時之啓始電壓爲 V t h，而以資料線電壓較V W R - V t h高之狀態起動 感測放大器較佳。因爲是比較不會受到汲極端之記憶資訊 之影響，可以進行穩定之動作。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29*7公釐） ~' -19- 522558 A7 _ B7 五、發明説明（ 汲極端資訊讀出時設定電壓不同。將源極線J 5 1設 定在較VRSS高之電壓VRSD (例如3V)，將資料 線了52預充電至較从尺80低之電壓¥?€0(例如 〇 V )後在字線施加電壓V W R (例如2 V )之讀出脈衝 。這時，若汲極端之啓始電壓高時，不太會有電流流通， 資料線J 52電位在VPCD (0V)不會有什麼變動， 但汲極端之啓始電壓低時會有很大之電流，資料線J 5 2 之電位會從V P C D ( 〇 V )大幅度上昇。供給感測放大 器之參照電壓係供給較VP CD (0V)大之電壓 V R E F D ( 0 · 6 V )。令感測放大器J 5 4以一定之 定時動作，藉此在汲極端之啓始電壓高時放大至低電位， 低時放大至高電位。因此，在此放大結果與各端之啓始電 壓之大小關係在源極端與汲極端逆轉，與以上說明之寫入 方法一起成爲正確之動作。將上述寫入、讀出動作整合成 表3 〇 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 〔表3〕 從外部輸入之 寫入時資料 格子啓始電 讀出放大後資 輸出至外部 資訊 線設定 壓値 料線電壓 之資訊 源極端記憶 “0”(L) VWDL(L) (L)(源極端) (L) “0”(L) Ί”(Η) VWDH(H) (Η)(源極端) (Η) “r(H) 汲極端記憶 M0”(L) VWDL(L) (Η)(汲極端) (L) *O”(L) “1，，(H) VWDH(H、 (L)(汲極端) (Η) “Γ(Η) 本紙張尺度適用中國國家標準（CNS ) A4規格（2i〇x 297公釐） -20- 522558 A7 B7 五、發明説明（1令 (實施例3 ) (請先閲讀背面之注意事項再填寫本頁) 第9圖係實施例2之半導體裝置之布置圖。實際上是 構成更大規模之陣列’但爲了方便說明表示2 X 5之小規模 格子陣列。在p型矽基板備有，格子分離領域j 1 〇 〇、 平行於此格子分離領域之區域源極線之η型擴散層領域 J 1 0 1及區域資料線之η型擴散層領域J 1 〇 3。在此 擴散層領域J 1 0 1成垂直設有由η型多晶矽構成之字線 J 104。同時，在η型擴散層領域J 1〇1、J 1〇3 所夾，不是字線J 1 0 4之直下方之部分有Ρ型擴散層 J 1 0 2。J 1 0 5係最小記憶單位。實際上是構成更大 規模之陣列，但爲了方便說明表示2 X 5之小規模格子陣列 〇 經濟部智慧財度局員工消費合作社印製 第1 0圖係表示在第9圖之X- X位置向箭頭方向所 視，以最小記憶單位之領域J 1 0 5爲中心至兩側之字線 J 104之範圍之截面。同時，第1 1圖表示在XI -X I位置之向箭頭方向所視，以規劃最小記憶單位 J 1 0 5範圍之格子分離領域J 1 〇 〇爲中心之截面。有 設在ρ型矽基板之η型之區域源極線J 1 〇 1、區域源極 線J 1 03，在主動層J 1 1 7上排列有多數介由厚度 8 n m之絕緣膜J 1 〇 6形成爲電荷儲存領域之矽之平均 徑1 2 n m之微小結晶粒j 1 〇 7。以J 1 1 1代表電荷 儲存領域。設有控制電荷儲存領域之電位之η型多晶矽之 字線J 1 0 4，矽微小結晶粒J 1 〇 7與字線J 1 〇 4之 間係從下方依序形成厚度5 nm之S i〇2、厚度8 nm之 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -21 - 經濟部智慧財產局員工消費合作社印製 522558 A7 B7________ 五、發明説明（1令 s i 3N4、厚度5 nm之S i〇2之〇N〇構造之絕緣膜 J 108。J 1 16係絕緣層。與實施例1同樣’在格子 分離領域J 1 0 0上殘留有電荷儲存領域J 1 1 0也沒有 關係。可以用乾蝕刻、用濕蝕刻，或乾蝕刻與濕鈾刻之組 合去除格子分離領域上之電荷儲存領域J 1 1 〇 °同時’ 區域源極線J 1 0 1與區域源極線J 1 〇 3係由p型擴散 領域J 1 0 2加以分離。 本實施例所用之記憶格單體之電路圖上之表記與第4 圖所示之實施例1相同。 第1 2圖表示實施例3之等效電路。實際上是構成更 大規模之陣列，但爲了方便說明表示2 X 5之小規模格子陣 列。多數記憶格在擴散層以區域源極線J 1 0 1、區域源 極線J 1 0 3相互配線。此區域源極線J 1 0 1係經由選 擇電晶體S T 1連接在全面性源極線j 1 2 0，區域源極 線J 1 0 3也是經由選擇電晶體s T 2連接在全面性資料 線 J 1 2 1。 在實施例1 ，在每兩個並聯之記憶格，配設有金屬之 資料線接點、源極線，但本實施例之特徵是多數記憶格在 擴散層共用資料線接點、源極線。因爲資料線接點大幅度 減少’因而能夠高密度安裝記憶格，對削減成本有很大之 效果。但其反面，讀出時之雜散電阻變大，讀出速度降低 ’但可將資料線、源極線層次化而將速度降低抑制在最低 限度。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)A pulse of V W W (for example, 12 V) is supplied to the word line J 4 5. When VWD L is set, almost no hot electrons are generated, so the charge injected into the memory node is small, and when VWDH is set, the amount of charge injected is large. At this time, for other grids driven by the same word line, if the voltage of the connected data line is also set to VWD L or VWD 对应 corresponding to the data to be written, information can be written at the same time. Here, no charge is injected when "0" is written, which is equivalent to no writing, so information can be written only in a part of the grid driven by the same word line. However, if the other zigzag lines are set to a voltage VWO (for example, 0 V) lower than VWW, there will be no writing. The write operation at the drain terminal will be described next. The source line J 4 1 is printed with VWSD (for example, 5 V) by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the voltage of the data line J 4 4 is the same as when the source terminal is written. The information is set when the information is “〇” In VWDL (for example 0V), it is set to VWDH (for example 5V) when the information is "1". Then, a pulse of high voltage V W W (for example, 12 V) is applied to the word line J 4 5, and writing can be performed. Here, the data line V w D Η is the charge injection condition when the source terminal is written, but the data line VWDL is the charge injection condition when the drain terminal is written. Therefore, the characteristic is that the memorized information corresponds to the level of the starting voltage. The relationship is reversed at the source and drain. The erasing power of information is performed in batches on the grids driven by the same word line, while erasing the source extreme and drain extreme information. This paper size applies to China National Standard (CNS) A4 specification (210 × 297 mm) -18- 522558 A7 B7 V. Description of the invention (1 from (Please read the precautions on the back before filling this page) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Cooperative printed and then explained the information reading operation with reference to Fig. 8. First, "correspond to the address of the memory cell to be read from the outside" to generate an instruction to read the source_like or drain signal RSERECT J 50. The circuit that generates the selection signal RSERECT from this address can be shared with the selection signal generation circuit at the time of writing. For the generated signal RSERECTJ 5 0, as explained below, switch the source line J 5 1 voltage, precharge voltage and Reference voltage. To read the source extreme information of the grid 5 5, set the source line J 5 1 to VRSS (for example, 0 V), and precharge the data line J 5 2 to a voltage higher than VRSS v PCS (for example, 3 V), a read pulse of voltage v WR (for example, 2 V) is applied to the word line. At this time, if the source extreme voltage is high, no current will flow, and the potential of data line J 5 2 will not be at VPCS. have what However, when the starting voltage of the source terminal is low, there will be a large current, and the potential of the data line J 5 2 will drop significantly from VP CS. One end of the differential amplifier type sense amplifier J 5 4 is connected to the data line. At the other end, J 5 5 applies a voltage VREFS (for example, 2.4 V) which is smaller than VPCS as the reference voltage. The sense amplifier J 5 4 is operated at a certain timing, so that when the starting voltage of the source terminal is high, Amplify to a high potential, and when it is low to amplify to a low potential. When the start-up timing of this sense amplifier is low, the data line voltage set to a memory cell that can operate in the saturated field is also in a high voltage state. That is, When the starting voltage of the source terminal is low, the starting voltage is V th, and it is better to start the sense amplifier with the data line voltage higher than VWR-V th. Because it is less affected by the memory information of the drain terminal, Stable operation is possible. This paper size applies Chinese National Standard (CNS) A4 specification (210X29 * 7mm) ~ '-19- 522558 A7 _ B7 V. Description of the invention (the set voltage is different when reading the extreme information. Source line J 5 1 Set VRSD at a higher voltage than VRSS (for example, 3V), pre-charge the data line 52 to a voltage lower than the ruler from ¥ 80 (for example, 0V), and then apply a voltage VWR (for example, 2 V) to the word line. ) Read pulse. At this time, if the starting voltage of the drain terminal is high, no current will flow, and the potential of the data line J 52 will not change at VPCD (0V), but when the starting voltage of the drain terminal is low. There will be a large current, and the potential of the data line J 5 2 will rise sharply from VPCD (0V). The reference voltage supplied to the sense amplifier is a voltage V R E F D (0 · 6 V) greater than VP CD (0V). The sense amplifier J 5 4 is caused to operate at a certain timing, thereby amplifying to a low potential when the starting voltage of the drain terminal is high, and amplifying to a high potential when it is low. Therefore, the relationship between the magnification result and the starting voltage of each terminal is reversed at the source and drain terminals, and becomes the correct action together with the writing method described above. Integrate the above writing and reading operations into Table 3 〇 (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [Table 3] The data grid is opened when writing from the outside After the power is read and amplified, the information is output to the external information line. The information source extreme memory of the set voltage line voltage is “0” (L) VWDL (L) (L) (source extreme) (L) “0” (L) Ί "(Η) VWDH (H) (Η) (source extreme) (Η)" r (H) drain extreme memory M0 "(L) VWDL (L) (Η) (drain extreme) (L) * O" (L ) "1, (H) VWDH (H, (L) (Drain) (Η)" Γ (Η) This paper size is applicable to China National Standard (CNS) A4 (2i0x 297 mm) -20- 522558 A7 B7 V. Description of the invention (1 order (Embodiment 3) (Please read the precautions on the back before filling out this page) Figure 9 is the layout of the semiconductor device of Embodiment 2. In fact, it constitutes a larger scale Array ', but for the sake of explanation, it shows a small-scale grid array of 2 × 5. On a p-type silicon substrate, there is a grid separation area j 1 〇, n-type diffusion parallel to the source lines of the area of the grid separation area. The area J 1 0 1 and the area data line of the n-type diffusion layer area J 1 〇3. In this diffusion layer area J 1 0 1, a zigzag line J 104 composed of n-type polycrystalline silicon is provided vertically. At the same time, in the n-type diffusion The layer area J 1101, J 1 03 is sandwiched, and not directly below the word line J 1 0 4 has a P-type diffusion layer J 1 0 2. J 1 0 5 is the smallest memory unit. Large-scale array, but for the convenience of illustration, it shows a small-scale grid array of 2 X 5. Printed by the Consumer Consumption Cooperative of the Ministry of Economic Affairs and the Financial Affairs Bureau. Figure 10 shows the view in the direction of the arrow at the X-X position of Figure 9. A cross section with the minimum memory unit field J 1 0 5 as the center to the zigzag line J 104 on both sides. At the same time, Figure 11 shows the direction of the arrow at the XI -XI position to plan the minimum memory unit. The grid separation area in the range of J 1 0 5 is a cross section centered on the center. There are n-type regional source lines J 1 〇1, regional source lines J 1 03 on the p-type silicon substrate, and the active layer J The average diameter of most silicon formed in the charge storage field via an insulating film J 1 〇6 with a thickness of 8 nm is arranged on 1 1 7 1 2 n m crystal grains j 1 〇7. The charge storage field is represented by J 1 1 1. There are η-type polycrystalline silicon zigzag lines J 1 0 4 and silicon micro crystal grains J 1 〇7 and characters. Lines J 1 〇4 are sequentially formed from below with a thickness of 5 nm S i〇2, a thickness of 8 nm of this paper size is applicable to China National Standard (CNS) A4 specifications (210X297 mm) -21-Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives 522558 A7 B7________ V. Description of the invention (1 ream si 3N4, thickness 5 nm, Si 〇2 〇N〇 structure insulation film J 108. J 1 16 series insulation layer. It is the same as in Example 1 and it does not matter whether the charge storage region J 1 1 0 remains in the lattice separation region J 1 0 0. You can use dry etching, wet etching, or a combination of dry etching and wet uranium etching to remove the charge storage area J 1 1 0 ° in the grid separation area. At the same time, the regional source line J 1 0 1 and the regional source line J 1 〇 The 3 series is separated by the p-type diffusion field J 1 0 2. The entries on the circuit diagram of the memory cell unit used in this embodiment are the same as those in Embodiment 1 shown in FIG. 4. Fig. 12 shows an equivalent circuit of the third embodiment. It actually constitutes a larger-scale array, but for convenience of explanation, a 2 × 5 small-scale grid array is shown. Most memory cells are interconnected in the diffusion layer with a regional source line J 1 0 1 and a regional source line J 1 0 3. The regional source line J 1 0 1 is connected to the comprehensive source line j 1 2 0 via the selection transistor ST 1, and the regional source line J 1 0 3 is also connected to the comprehensive data line via the selection transistor s T 2 J 1 2 1. In Embodiment 1, metal data line contacts and source lines are provided in every two parallel memory cells, but this embodiment is characterized in that most memory cells share data line contacts and source lines in the diffusion layer. . Because the data line contacts are greatly reduced ’, memory cells can be installed at high density, which has a great effect on reducing costs. On the other hand, the stray resistance during reading becomes larger and the reading speed decreases. However, the data line and the source line can be layered to reduce the speed reduction to a minimum. This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page)

-22- 522558 A7 B7 五、發明説明（2() (實施例4 ) (請先閲讀背面之注意事項再填寫本頁) 再說明實施例4。實施例4之動作原理與實施例2相 同，其基本架構與實施例3相同。第1 3圖表示等效電路 。在此爲了說明上之方便表示較小之記憶格，但實際上在 行方向、列方向均排列有多數之格子。第1 3圖之以虛線 所圍之部分J 1 3 1便是單位陣列構造。多數記憶格之源 極領域J 1 3 2、汲極領域J 1 3 3在擴散層相互連結在 一起，以形成區域源極線J 1 3 2、J 1 3 3。區域源極 線J 1 3 2係經由選擇電晶體S T 3 - S T 6連接在源極 線J 1 3 4、J 1 3 5，全面性源極線J 1 3 6之任一方 。在選擇電晶體驅動用信號線J 1 3 7、J 1 3 8輸入互 爲反轉之信號，因此選擇電晶體ST3、ST4導通時， 可以將區域資料線J 1 3 3當作源極領域使用，將區域資 料線J 1 3 2當作汲極領域使用，選擇電晶體S T 5、 S T 6導通時，可以將區域資料線J 1 3 2當作源極領域 使用，將區域資料線J 1 3 3當作汲極領域使用。若將輸 入選擇電晶體驅動用信號線J 1 3 7、J 1 3 8之信號分 經濟部智慧財產局員工消費合作社印製 別反轉，便有相反之功能。 較之實施例2之驅動方法，雖另需要選擇電晶體，但 有源極端及汲極端讀出時源極線j 1 3 4、J 1 3 5及全 面性資料線J 1 3 6之設定電壓相同，可以固定源極線 J 1 3 4、J 1 3 5之電位來使用，因而可以省略源極線 驅動用電壓切換電路等之優點。同時，如果是實施例4之 陣列架構，由同一區域資料線j 1 3 2、J 1 3 3驅動之 本紙張尺度適财關家標準（CNS ) A4規格（21GX297公釐) " -23- 522558 A7 B7 五、發明説明（2) 多數格子可以共同配設此等選擇電晶體’因此不會增加太 多面積。 (請先閲讀背面之注意事項再填寫本頁) 實施例1之連結源極J 7與汲極J 8之電流方向與字 線J 2之方向係在相互垂直之關係，但實施例4之陣列架 構則是在平行之方向。若使用實施例4之製作方法，便可 以如第9圖所示很容易製作連結源極領域J 1 〇 1、汲極 領域J 1 0 3之方向與字線J 1 04之方向成平行之構造 (實施例5 ) 以下再說明一部分之構造與上述實施例不相同之半導 體格子及半導體裝置。 經濟部智慧財產局員工消費合作社印製 第1 4圖係從第1 6圖之X I V- X I V位置向箭頭 方向所視之實施例5之半導體記憶格之截面構造圖。在P 型矽基板M7 7 a設有η型之井領域M7 7 b，並在其中 設有P型之井M77c，具有所謂3重井構造。P型之井 內有η型之源極M6 9、汲極M7 0領域’在主動領域之 一部分Μ7 6、Μ7 7上，介由厚度8 nm之隧道氧化膜 M7 2排列有多數成爲電荷儲存領域之矽之平均徑1 5 n m之微小結晶粒Μ 7 1。設有用以控制主動領域之一部 分Μ 7 7及電荷儲存領域之電位之η型多晶矽之第1閘電 極Μ 7 4，矽微小結晶粒Μ 7 1與閘電極Μ 7 4之間從下 方依序形成有厚度4nm之S i 〇2、厚度8nm之 S i 3N4、厚度4 nm之S i〇2之〇N〇構造之絕緣膜 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ： ' -24- 522558 Α7 Β7 五、發明説明（2$ (請先閲讀背面之注意事項再填寫本頁) M7 3。並有控制主動領域之一部分M7 6之電位之第2 閘電極M7 5構造。再者’第1 4圖係表示3重井構造’ 但其他實施例則因爲要避免煩雜而省略。 第15圖表系對應第14圖之電路圖。第1閘電極 Μ7 4、第2鬧電極Μ7 5、源極Μ6 9、汲極Μ7 0、 電荷儲存領域Μ 7 1分別標示對應之參照記號。將基板偏 壓用來控制記憶格時’爲了要將不同的Ρ型井間設定成不 同之電位，3重井構造很有效。但若使用η型基板，記憶 格部分用2重井構造便已足夠。 其次說明實施例5之動作。實施例5係將第2閘電極 Μ 7 5當作補助電極使用，藉此以高效率將熱電子注入電 荷儲存領域Μ 7 1。 經濟部智慧財產局員工消費合作社印製 首先說明寫入動作。依欲寫入之資訊設定汲極領域 Μ 7 0之電壓。在此係令注入較多電荷之條件對應資訊“ 1 ” ，電荷較少之狀態對應資訊“ 0 ” 。寫入資訊“ 1 ” 時設定成足夠產生熱電子之充分大之電場（例如5 V)。 源極領域Μ 6 9設定成Ο V。寫入資訊“ 〇 ”時，將源極 汲極間電位差設定成較小（例如Ο V )。將第2閘電極 Μ75設定在一定之電壓（例如2V)。在第1閘電極 Μ7 4施加較第2閘電極Μ7 5高之高電壓（例如1 2V )之寫入脈衝。這時，第2閘電極Μ 7 5下之主動領域 Μ7 6之電阻，較第1閘電極Μ7 4下之主動領域Μ7 7 之電阻大.。因此，源極、汲極間電壓幾乎全加在第2閘電 極Μ7 5下之Μ7 6。同時，在第2閘電極Μ7 5下之主 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -25- 522558 A7 B7 五、發明説明（2$ (請先閱讀背面之注意事項再填寫本頁) 動領域Μ 7 6，也是接近汲極領域Μ 7 0側之一方之電位 較筒，有效之閛極電壓會降低，因此成爲高電阻。因此， 在較靠近第2閘電極Μ7 5下之Μ7 6之汲極Μ7 0之一 端產生較多之熱電子。產生之熱電子因第1閘電極Μ 7 4 之電場而向電荷儲存領域Μ7 1之方向加速，而發生注入 。注入處所集中在近第1閘電極Μ7 4下之第2閘電極 Μ 7 5之領域Μ 7 8。這時在源極汲極間流動之電流因第 2閘電極Μ7 5下之主動領域Μ7 6之電阻較高，因此較 不具補助閘極之構造者少，因之可以有高效率之注入，電 流小很好。由於每單位格子之寫入電流小，因此可以設定 較多之每一次寫入動作能夠寫入之格子數，可以提高記憶 晶片之總寫入資訊量。尤其是適合以較大之資料單位與外 部進行資訊之送受之大容量記憶。寫入“ 〇 ”時因源極汲 極間電壓小，因此不產生熱電子，不會注入電荷。 經濟部智慧財產局員工消費合作社印製 其次說明讀出動作。例如將汲極電壓設定爲2 V，源 極電壓設定爲0V，第2閘電極Μ7 5之電壓設定爲 3 · 5 V，並在第1閘電極Μ 7 4加上2 V之讀出脈衝。 因爲依注入電荷儲存領域Μ 7 3之電荷量之大小啓始電壓 會不一樣，因“ 0 “記憶之汲極電流較“ 1 ”記憶之汲極 電流大，而得進行讀出。 再者，實施例5與不具第2閘電極構造之格子構造比 較，因下述理由在讀出動作時也較有利。亦即，不具第2 閘電極構造之格子構造時，熱電子會被注入汲極附近之記 憶領域，但在高啓始電壓値狀態下電晶體成爲飽和領域之 本紙張尺度適用中國國家標準（CNS ) Α4規格（21〇Χ；297公釐） -26- 522558 A7 B7 五、發明説明（24 (請先閲讀背面之注意事項再填寫本頁) 動作，通道會在汲極附近夾斷（Pinch off)，因此注入電 荷之影響變小。其結果，雖然有注入充分之電荷，表面上 電壓移位變小，動作邊際減少。迴避之手段是，如習知之 M〇S電晶體之熱載子評估’以對調源極、汲極之電壓設 定進行讀出較有效，但會伴隨著產生記憶器之動作速度下 降，周邊電路之複雜化等之負面效果。本發明係在源極汲 極之中間注入電荷，因此可以有效讀出注入之電荷之影響 〇 經濟部智慧財產局員工消費合作社印製 實施例5可以非揮發性記憶’切斷電源後還可以保持 記憶。特別是因爲記憶節點係由很多獨立之半導體之微小 粒子Μ 7 1構成，因此，由於改寫應力使絕緣膜劣化’在 低電場下發生漏洩時，也僅是連接在部分漏洩路徑部分之 微小粒子之電荷會損失，因此可以穩定保持。另一方面， 通常之快閃記憶器會因漏洩路徑使記憶節點之電荷一個接 一個漏失，因此影響很大。快閃記憶器之隧道絕緣膜厚度 係由返覆此改寫後之漏洩電流加以規律。實施例5可以將 隧道絕緣膜加厚相當於提高可靠性之份量，在整個格子之 縱方向之定標上也較快閃記憶器優異。 抹除資訊時，在第1閘電極Μ 7 4加上負電壓即可。 例如，使源極Μ 6 9、汲極Μ 7 0均成Ο V，使第1閘電 極Μ74成爲-18V。這時，因高電場而注入之電子被 放出到基板側。抹除動作係源極端、汲極端整批爲之。再 者，這時也可以將井Μ7 7 c之電位設定在較0V爲高之 電位（例如5 V )，相對地將第1閘電極Μ 7 4之電位之 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） -27- 522558 A7 一__B7_ 五、發明説明（2$ 絕對値設定成較小（例如-1 3 V )。使用電壓之絕對値 變小，電壓產生電路變簡單。 (請先閱讀背面之注意事項再填寫本頁) 其次再參照第1 4圖、第1 6圖說明實施例5之製造 製程。形成活性領域Μ 9 3 經濟部智慧財產局員工消費合作社印製 及3重井構造後，在ρ型井Μ 7 7 c上之記憶格形成 領域，爲了調整啓始電壓而摻入雜質Β (硼）離子。將基 板表面氧化形成厚度1 0 nm之隧道氧化膜Μ7 2後，藉 C V D形成矽微小結晶粒Μ 7 1。試作時，係以平均徑7 nm，每1平方公分5χ1 011個之密度形成。從下方依序 形成厚度4nm之S i〇2、厚度8nm之S i 3N4、厚 度4 nm之S i〇2之〇N〇構造之絕緣膜M7 3後，爲了 形成第1閘電極而堆積η型之多晶矽，再堆積S i 3 N 4膜 。以抗蝕劑膜作爲光罩，依序蝕刻S i 3 N 4膜、多晶矽膜 、〇N 0膜、S i〇2膜。在此製程時形成第1閘電極 Μ 7 4。以第1閘電極作爲掩罩打入雜質，調整第2閘電 極下之雜質濃度。洗淨後，氧化基板表面，再堆積 C V D - S i〇2膜。爲了形成第2閘電極堆積多晶矽膜， 進行平坦化。在此，使多晶矽膜之厚度較加工第1閘電極 而成之台階差高度爲厚。平坦化是在第1閘電極之蓋體之 S i 3 N 4出現時停止，藉此僅使形成第2閘電極用之多晶 矽膜之上面露出，第1閘電極表面仍被S i3N4覆蓋。再 使用第2閘電極加工用之掩罩圖案Μ 9 4進行多晶矽膜之 加工。以第1、第2閘電極作爲掩罩打入A s (砷）離子 ，經過活性化而形成源極Μ 6 9、汲極Μ 7 0領域。並且 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -28- 522558 Α7 Β7 五、發明説明（2自 ，在形成層間膜、平坦化後，進行接點、配線製程。 (請先閲讀背面之注意事項再填寫本頁) (實施例6 ) 第1 7圖係實施例6之記憶裝置之截面構造圖。係以 由同一字線Μ 1 〇 0驅動之相鄰之兩個記憶格Μ 1 〇 3及 Ml 0 4爲主體之截面圖。第1 8圖係說明實施例6之記 憶格陣列之連接關係之電路圖。實際上是構成更大規模之 陣列，但爲了說明上之方便表示4 X 4之小規模之格子陣列 。格子之基本架構與實施例5相同，格子單體之動作也一 樣，但依格子之連接關係，其截面構造或製作方法有異， 另外其驅動方法有特徵。 經濟部智慧財產局員工消費合作社印製 第1閘電極Μ 1 0 0兼有字線之功能，第2閘電極 Μ 9 5作爲補助控制線與字線Μ 1 〇 〇成垂直配線。源極 領域Μ 9 7、汲極領域Μ 9 8在擴散層配線而向平行於補 助控制線Μ 9 5之方向延伸，將記憶格加以並聯。此記憶 格Μ 1 〇 3之汲極領域Μ 9 8兼相鄰之記憶格Μ 1 〇 4之 源極領域Μ 9 7。通常之如此由多數格子共用源極、汲極 領域，而成並聯之架構，其格子之汲極領域與相鄰格子之 源極領域在格子分離領域是成絕緣狀態，但實施例6不作 物理式之分離，而成共同之擴散層。因此可以縮小格子分 離領域之面積，對低成本化有效果。 在動作時有一特徵是，對由同一字線驅動之格子係每 隔一個寫入、讀出。例如，對記憶格Μ 1 〇 3進行寫入或 讀出動作時，使兩側之相鄰接格子之補助控制線Μ 9 6、 本紙張尺度適用中國國家標準（〇^)八4規格（210、/297公釐） -29- 522558 A7 B7 五、發明説明（2$ (請先閱讀背面之注意事項再填寫本頁) Μ 1 0 5成低電壓，使控制線下之矽表面成高電阻，藉此 防止由同一字線驅動之格子間之短路。亦即，使用補助控 制線以電氣方式進行格子分離。對記憶格Μ 1 〇 4進行寫 入或讀出動作時，使鄰接之格子之補助控制線Μ 9 5成爲 低電壓即可。本實施例係以4 X 4之小規模格子陣列表示， 但實際上構成更大規模之格子陣列時，擴散層配線之電阻 很高，電壓效果有問題。因此以適當之間隔打接點，以金 屬線打裏較有效。同時，也可以採，在與金屬線之接觸孔 之間設開關，以擴散層配線作爲區域資料線，以金屬線作 爲全面性資料線之層次化架構。採層次化架構時，動作時 不需要之部分之區域資料線不必充放電，因此對低消耗電 力化、局速化有效。 經濟部智慧財產局員工消費合作社印製 參照第1 9圖就其製造方法與實施例5之差異爲中心 說明如下。在爲了周邊電路而形成格子分離領域、井構造 ’導入調節第2閘電極下之啓始電壓値用之雜質後，氧化 基板表面形成厚度8 nm之隧道氧化膜Μ7 2後，堆積形 成第2閘電極用之多晶矽膜、S i〇2膜後，進行加工以形 成第2閘電極M9 5、M9 6。再以此圖案作爲掩罩，如 圖上之箭頭所示，斜方向打入A s離子，而形成源極、汲 極領域之擴散層M9 7、M9 8及M9 9。這時也導入調 節第1閘電極下之啓始用之雜質。將基板表面氧化形成厚 度8 n m之隧道氧化膜μ 7 2後，藉C V D形成矽微小結 晶粒ΜΙ 0 1及Ml 〇 2。再從下方依序形成厚度4 nm 之S i〇2、厚度8nm之S i3N4、厚度4nm之 本紙張尺度適用中國國家標準（CNS )M規格（21〇χ297公董） -30- 522558 A7 B7 五、發明説明（2$ (請先閱讀背面之注意事項再填寫本頁) S i〇2之Ο N 0構造之層間絕緣膜Μ 7 3後，爲了形成第 1閘電極而堆積η型之多晶矽，進行平坦化。再堆積W ( 鎢）、S i 0 2膜，以抗蝕劑膜作爲掩罩，依序蝕刻 S i〇2膜、W、η型多晶矽膜，形成第1閘電極兼字線 Μ 1 〇 〇。再形成層間膜，平坦化後，進行接點製程、配 線製程。使用本製作方法時，補助閘上也會留下矽微小結 晶粒。這可能是由於以如快閃記憶之連續之多晶矽膜形成 記憶領域時，因格子間之記憶領域之短路，或與補助電極 之電容藕合等造成之特性惡化，而且，由於存在有起因於 補助電極之台階差，因此也很難去除。在實施例6則不去 除，其電氣特性上也不會有問題，因而具有製作過程簡單 之特徵。 (實施例7 ) 第2 0圖表示實施例7之記憶格之截面構造圖。 經濟部智慧財產局員工消費合作社印製 有設在Ρ型井Mila之η型之源極Ml、汲極M2 ，控制通道之η型多晶矽之閘電極Μ 3。閘電極Μ 3與基 板之間排列有多數平均徑1 2 n m之微小結晶粒Μ 4。在 閘電極Μ 3之兩側面有ρ型之多結晶矽構成之側壁構造 Μ 7、Μ 8，與閘電極Μ 3之間存在有絕緣膜Μ 1 3。同 時，側壁構造Μ 7、Μ 8與基板之間也存在有絕緣膜 Μ14。在通常之LDD構造，側壁構造Μ7、Μ8構造 直下之基板表面Ml 1、Ml 2係高濃度之η型，但本實 施例則是Ρ型或低濃度η型。而且，源極Μ 1、汲極Μ 2 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） " -31 - 522558 A7 B7_ 五、發明説明（2令 領域與側壁構造係經由鎢層Μ 9、Μ 1 0連接在一起。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 其次說明實施例7之動作。實施例7係藉改變儲存電 荷之處所在每一記憶格記憶2位元以上。再者，在實施例 7，係對調源極及汲極動作，因此電子不一定從源極流至 汲極，但爲了防止稱呼變複雜，對領域之名稱擬固定場所 而使用此等之名稱。首先參照第2 1圖（a )，說明將電 荷注入接近源極領域Μ 1之記憶節點Μ 1 5之情形。將源 極設定在Ο V，將汲極設定在4 V，在閘電極施加1 2 V 之脈衝。這時，汲極端之側壁Μ 8之電位也是設定成爲 4V，因此其下之基板表面Ml 2會反轉成η型。另一方 面，源極端側壁Μ 7之電壓很低（Ο V )，其下之基板表 面Ml 1之電子濃度低。其結果，施加之汲極電壓之大部 分加在源極端側壁下之Μ 1 1。此部分之電場強，因此產 生熱電子。產生之熱電子被施加在閘電極Μ 3之電壓形成 之電場吸引，注入到接近源極Μ 1之記憶節點Μ 1 5。此 熱電子之注入效率較通常之熱電子注入效率高，不必流動 很大之汲極電流也可以寫入資訊。因此，可以同時在多數 格子進行寫入，可以做大容量記憶。同時，在這個時候， 在汲極端之側壁Μ8下之基板表面Ml 2中，接近汲極之 領域Ml 8之電場也會變強，但因附近不存在有電荷儲存 領域之微小結晶粒Μ 4，同時與閘電極Μ 3之距離也大， 因此不會發生汲極端寫入。要在汲極端之記憶節點Μ 1 6 進行寫入時，對調源極電壓與汲極電壓即可。 同時，在寫入動作時，在ρ型井Ml 1 a施加負之基 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -32- 522558 A7 B7___ 五、發明説明（3() (請先閲讀背面之注意事項再填寫本頁) 板偏壓（例如-2 V )，而相對降低閘極電壓（例如使成 爲1 0 V )之方法比較有效。因爲可以降低使用之閘極電 壓之絕對値，除了有電壓產生電路變簡單之優點之外’因 啓始電壓會上昇，另有容易產生側壁下之電場集中之特徵 。這時若在側壁下使用低濃度η型，將可以使讀出電流比 使用Ρ型時大。 經濟部智慧財產局員工消費合作社印製 其次，參照第2 1圖（b )說明讀出動作如下。爲了 讀出資訊，令由源極、汲極、閘極構成之電晶體在飽和領 域動作。要讀出注入在源極端記憶節點Μ 1 5之電荷時， 使汲極電壓爲2 V，使源極電壓爲Ο V，使閘極電壓爲 2 V。這時會形成通道Μ 1 7，閘極電極下之基板表面中 之接近汲極端處會成夾斷之狀態，因此不會形成通道。其 結果，僅源極端記憶節點Μ 1 5之儲存電荷會對啓始電壓 產生影響，可去除汲極端記憶節點Μ 1 6之儲存電荷之影 響。若源極端記憶節點Μ 1 5之儲存電荷量多，啓始電壓 會高，少則啓始電壓低，因此，源極、汲極間之電導會因 儲存電荷量而異。依據此電導之差異造成之電壓之差異， 可以讀出資訊。要讀出汲極端記憶節點Μ 1 6之儲存電荷 時，對調源極與汲極之設定電壓即可。在此係使讀出源極 端資訊時之源極領域設定電壓爲0 V，但設定成較寫入時 之源極領域設定電壓低之一定之電壓（例如-1 V )，反 轉源極端下之表面加以低電阻化以增加讀出電流之方法很 有效。這時，應對應此將閘極電壓、汲極電壓之設定例如 降低成IV、IV。再者，也可在ρ型井Ml la施加正 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）" -33- 522558 Α7 Β7 五、發明説明（3令 電壓（例如-1 V )而進行同樣之設定。 (請先閲讀背面之注意事項再填寫本頁) 再者’寫入時使用上述負之基板偏壓時，讀出時使用 相對高之基板偏壓（例如〇 V )之動作方法較有效。寫λ 時之基板偏壓使側壁下成高電阻，容易產生熱電子，可以 確保充分大之讀出電流。其結果，可以使高速之寫入與高 速之讀出兩立。 上述寫入方法、讀出方法可單純地對調源極、汲極之 設定電壓即可。因此，較之藉注入單一浮置閘中之電荷量 作成4個層次之方式，寫入動作、讀出動作所需要之步驟 較少’因此可以高速動作。同時，在兩端係分別成爲是資 訊“ 1 ” 、 “ 0 ”之兩層次之動作，因此動作邊際也會增 經濟部智慧財產局員工消費合作社印製 加。在寫入動作時，若是使用多層次，必須高度抑制啓始 電壓之格子間分布擴展。因此實施在施加寫入脈衝後進行 讀出’未達一定之啓始電壓時再度施加寫入脈衝之返覆動 作之所謂證實動作，而成爲總寫入量之降低之主因。因此 ，實施例7之高速化之效果在寫入時特別顯著。加上因實 施例7有很多獨立之構成記憶節點之矽微小結晶粒，因此 寫入可以平均化。其結果，格子間之參差不齊減少，不做 證實動作仍可進行每記憶格記憶2位元之動作。寫入平均 化對起因於隧道絕緣膜之缺陷等，使某些格子之寫入以異 常之高速進行之不良事故，也很有效。 資訊之抹除，係在閘電極Μ 3加上負電壓爲之。例如 ，使源極Μ 1、汲極Μ 2均成Ο V，使閘極Μ 3成爲 -1 2 V。這時，因電場使注入之電子會被放出到基板側 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -34- 522558 A7 ___.__B7_ 五、發明説明（3会 。抹除動作係源極端、汲極端整批爲之。再者，這時也可 以將井電位設定在較〇 V爲高之電位（例如5 V )，相對 地將閘極Μ 3之電位之絕對値設定成較小（例如-7 V ) 。使用電壓之絕對値變小，電壓產生電路變簡單。 第2 2圖表示實施例7之等效電路圖。使用表示源極 端記憶節點Μ 1 5及汲極端記憶節點Μ 1 5之記號。在第 2 2圖（a )係表示，以源極端側壁Μ 7作爲閘電極，其 下之基板表面Ml 1作爲通道而形成之場效應電晶體 Μ 1 9，及以汲極端側壁Μ 8作爲閘電極，其下之基板表 面Μ 1 2作爲通道而形成之場效應電晶體Μ 2 0。但對應 Ρ型井Ml 1 a之基板偏壓端子則省略未圖示。爲避免圖 式變複雜，在以下所示之記憶裝置之等效電路係使用簡化 之第2 2圖（b)之表示方法。 其次說明實施例7之製造製程。形成格子分離領域、 3重井構造後，在ρ型 井上之記憶格形成領域摻入電壓調整用之雜質B (硼 )離子。將基板表面氧化，形成厚度1 0 nm之隧道氧化 膜Μ 5後，藉C V D形成矽微小結晶粒Μ 4。試作時，係 以平均徑1 2 nm，每1平方公分4χ1 011個之密度形成 。形成厚度1 2 n m之層間絕緣膜Μ 6後，堆積形成閘電 極用之η型多晶矽，再堆積S i 0 2膜。以抗蝕劑膜作爲掩 罩，依序鈾刻S i〇2膜、多晶矽膜，形成閘電極。以相同 掩罩再進一步蝕刻S i 0 2膜，結晶粒也去除掉。 去除抗蝕刻劑後，形成犧牲氧化膜，注入雜質，調整 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） "~ -35- i J- -1»! L-l. — - i -. m ϋ (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 522558 A7 B7 五、發明説明（3$ (請先閲讀背面之注意事項再填寫本頁) 側壁下之雜質濃度。此後進行氧化，氧化基板表面及閘電 極側面。此則成爲側壁Μ 7、Μ 8構造及閘電極Μ 3間之 絕緣膜Μ 1 3。這個時候，因雜質之增速氧化使閘極側面 之氧化較基板表面之氧化快，絕緣膜較厚。接著堆積η型 多晶矽，退蝕刻此膜厚度分以形成側壁構造Μ 7、Μ 8。 此後，以抗蝕劑爲掩罩去除側壁多晶矽中不希望其短路之 部分。去除方法是以等方的乾鈾刻、濕蝕刻或組合兩者來 進行。以閘極Μ 3、側壁Μ 7、Μ 8作爲掩罩注入A s， 形成源極Μ 1、Μ 2。並以濕鈾刻使基板表面露出，而僅 在矽上選擇性堆積鎢（W )。 此源極領域Μ 1與源極側側壁構造Μ 7、汲極領域 Μ 2與汲極側側壁構造Μ 8之距離很短，堆積鎢則可以將 其連接在一起。較之對側壁構造Μ 7、Μ 8形成接點，以 配線連接擴散層Μ 1、Μ 2之格子構造，格子面積有顯著 之縮小，處理程序簡單。此後進行層間絕緣膜之堆積、平 坦化、接點製程後配線。 經濟部智慧財產局員工消費合作社印製 實施例7係以多晶矽構成閘電極Μ 3，但也可以使成 與矽化物或金屬之多層構造，以達成低電阻化。這時，閘 電極Μ 3與側壁Μ 7、Μ 8間之絕緣膜不要以氧化而是以 堆積形成較佳。而記憶節點係以矽之微小結晶形成，但也 可以用其他半導體或金屬形成。這時，重要的是各節點要 各自獨立。其形成方法，實施例7係在隧道絕緣膜上以 C V D形成，但也可以使用其他堆積方法。而且，也可以 形成隧道絕緣膜以上之膜厚度之絕緣膜後，打入S i、 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -36- 522558 A7 B7 五、發明説明（34 (請先閲讀背面之注意事項再填寫本頁) G e等之離子，再加熱，藉此使其在絕緣膜中析出多數微 小結晶，以形成記憶節點。記憶節點可以使用，例如 S i 3 N 4膜之多陷阱之膜。 (實施例8) 經濟部智慧財產局員工消費合作社印製 第2 3圖至第2 8圖表現示本發明之第8實施例。係 以實施例7所說明之記憶格子作爲基本構造之記憶格陣列 構造，第2 3圖係等效電路圖，第2 4圖係對應第2 3圖 之布置圖，第2 5圖係從箭頭方向所視之在第2 4圖之 X X V - X X V位置相鄰接之字線Μ 2 5、Μ 2 9與接點 M2 2之範圍之截面之構造圖，第2 6圖係從箭頭方向所 視之在第2 4圖之XXV I - XXV I位置相鄰接之格子 分離領域Μ 2 6之範圍之截面構造圖。而第2 3圖之虛線 所圍之部分Μ 2 3對應單位格子。第2 3圖係以4行2列 ，計8格子記憶1 6位元。實際上係使行、列數更多以構 成大規模之格子陣列，但爲了方便以這種規模進行說明。 再者，圖上係對同一構件或具有同一功能者標示相同之記 號。 閘電極相互以字線Μ 2 5連接。本實施例之字線 Μ 2 5係具有閘電極之功能之構造。汲極領域Μ 2 7與鄰 接格子共用，經由對此配設之接觸孔Μ 2 2連接至資料線 Μ 2 4。共用字線之相鄰接格子係由格子分離領域Μ 2 6 加以分離。源極領域以擴散層配線形成源極線Μ 2 1 ，與 字線成平行。在實施例8，擴散層表面由砂化物或金屬覆 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） ' ~ -37- 522558 Α7 Β7 五、發明説明（3含 (請先閱讀背面之注意事項再填寫本頁) 蓋，因此是低電阻，擴散層配線也充分具實用性。當然可 以在各處設接觸孔，以金屬線打裏則可以進一步低電阻化 。同時，本實施例之製作過程係與實施例5相同，這時會 在格子分離領域上殘留記憶節點之微小結晶領域Μ 2 8。 如果是像快閃記憶器之連接膜浮置閘時，會成爲鄰接格子 間之浮置閘之短路而不動作，但實施例8之記憶節點間漏 洩很少，可以動作。因此可以省略切斷快閃記憶器之鄰接 浮置閘之製程，可以簡化製程。 其次說明實施例8之驅動方法。首先說明第2 7圖之 寫入動作。依照從外部輸入之位址，產生指示是要進行源、 極端Μ 3 0寫入或汲極端Μ 3 1寫入之信號 WSERECTM36。對應產生之信號Μ36切換源極 線Μ 2 1之電壓。輸入資料係先儲存在閂鎖Μ 3 4。在此 係令電壓h i g h對應“ 1 ” ，電壓1 〇 w對應“ 〇 ” 。 經濟部智慧財產局員工消費合作社印製 格子Μ 2 3之源極端Μ 3 0寫入動作時，係在源極線 Μ 2 1施加V R S S (例如〇 V )，欲寫入之資訊是“ 〇 ”時，將資料線Μ 2 4之電壓設定在V W D L (例如〇 V )，欲寫入之資訊是“ 1 ”時，將資料線Μ 2 4之電壓設 定在V W D Η (例如5 V )，將高電壓V W W (例如 1 2V)之脈衝供給字線M2 5。設定在VWDL時幾乎 不會產生熱電子，因此注入記憶節點之電荷很少，設定在 V W D Η時注入之電荷量較大。這時，對以同一字線驅動 之其他格子，若同樣對應欲寫入之資料將連接之資料線之 電壓設定成VWDL或VWDH，便可以同時寫入資訊。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -38- 522558 Α7 Β7 五、發明説明（3令 (請先閲讀背面之注意事項再填寫本頁) 在此，“〇”寫入時不會注入電荷，因此相當於未寫入， 因此可以僅在同一字線驅動之格子之一部分寫入資訊。而 其他之字線若設定在較V W W低之電壓V W 0 (例如0 V )便不會有寫入。其次說明在汲極端M3 1之寫入動作。 將源極線Μ 2 1設定成V W D Η (例如5 V )，而資料線 Μ 2 4之電壓則與源極端Μ 3 0寫入時一樣，資訊是“ 〇 ”時設定在V W D L (例如〇 V )，資訊是“ 1 ”時設定 在V W D Η (例如5 V )。然後，對字線Μ 2 5施加高電 壓V W W (例如1 2 V )之脈衝，便可以寫入。在此，源 極端Μ 3 0寫入時，資料線V W D Η是電荷注入條件，但 汲極端Μ 3 1寫入時資料線V W D L爲電荷注入條件，因 此，其特徵是，所記憶之資訊與啓始電壓之高低對應關係 在源極端與汲極端會逆轉。 經濟部智慧財產局員工消費合作社印製 接著再參照第2 8圖說明資訊讀出動作。首先，對應 從外部施加之欲讀出之資料之位址，產生指示是要進行源 極端Μ 3 0讀出或汲極端Μ 3 1讀出之信號 RSERECT Μ 35。從此位址產生選擇信號 R S E R E C Τ之電路可以與寫入時之選擇信號產生電路 共用。對產生之信號RSERECT Μ 35，如以下 所說明，切換源極線M2 1電壓、預充電電壓及參考電壓 。要讀出源極端Μ 3 0之資訊時，將源極線Μ 2 1設定在 V R S S (例如0 V )，將資料線Μ 2 4預充電至較 VRSS高之電壓VPCS(例如3V)後，將電壓 V W R (例如2 V )之讀出脈衝施加在字線。這時，若源 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ：297公釐） -39- 522558 Α7 Β7 五、發明説明（3》 (請先閲讀背面之注意事項再填寫本頁) 極端M3 0之啓始電壓較高時，不太會有電流流通，資料 線Μ 2 4電位在V P C S不會有什麼變動，但源極端 M3 〇之啓始電壓低時會有很大之電流，資料線m2 4之 電位會從V P C S大幅度下降。差動放大型之感測放大器 Μ 3 3之一端連接在資料線，在另一端Μ 3 2則施加較 VPCS小之電壓VREFS (例如2 · 4V)作爲參照 電壓。令感測放大器Μ 3 3以一定之定時動作，藉此在源 極端M3 0之啓始電壓高時放大至高電位，低時以放大至 低電位。此感測放大器起動定時在啓始電壓低時，也是設 定成記憶格可在飽和領域動作之資料線電壓在高電壓之狀 態較佳。亦即，源極端之啓始電壓低時之啓始電壓爲 V t h，而以資料線電壓較V W R - V t h高之狀態起動 感測放大器較佳。因爲是比較不會受到汲極端Μ 3 1之記 憶資訊之影響，可以進行穩定之動作。 經濟部智慧財產局員工消費合作社印製 汲極端Μ 3 1之資訊讀出時設定電壓不同。將源極線 Μ2 1設定在較VRSS高之電壓VRSD (例如3V) ，將資料線M2 4預充電至較VRSD低之電壓VP CD (例如Ο V )後，在字線施加電壓V W R (例如2 V )之 讀出脈衝。這時，若汲極端M3 1之啓始電壓較高時，不 太會有電流流通，資料線Μ 2 4電位在V P C D ( Ο V ) 不會有什麼變動，但汲極端之啓始電壓低時會有很大之電 流，資料線Μ 2 4之電位會從V P C D ( 〇 V )大幅度上 昇。供給感測放大器之參照電壓係供給較V P C D ( 〇 V )大之電壓VREFD (例如〇 · 6V)。令感測放大器 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ；297公釐） -40- 522558 A7 __B7 五、發明説明（湳 (請先閲讀背面之注意事項再填寫本頁) M3 3以一定之定時動作，藉此在汲極端M3 1之啓始電 壓高時放大至低電位，低時放大至高電位。因此，放大結 果與各端之啓始電壓之大小關係在源極端與汲極端再度成 爲逆轉，與以上說明之寫入方法一倂成爲正確之動作。將 上述寫入、讀出動作整理成表4。 〔表4〕 從外部輸入 寫入時資料 格子啓始電 讀出放大後 輸出至外部 之資訊 線設定 壓値 資料線電壓 之資訊 源極端記憶 “0，，(L) VWDL(L) (L)(源極端) (L) “0”(L) “γ(η) VWDH(H) (Η)(源極端) (Η) “Γ(Η) 汲極端記憶 “0”(L) VWDL(L) (Η)(汲極端) (L) “0”(L) “r(H) VWDH(H) (L)(汲極端） (Η) “Γ(Η) 資訊之抹除動作係對同一字線驅動之格子以整批進行 ，同時抹除源極端與汲極端之資訊。 經濟部智慧財產局員工消費合作社印製 (實施例9 ) 第2 9圖至第3 6圖表示本發明之第9實施例。第 2 9圖表示本實施例之記憶格子之截面構造。 本實施例之基本架構、動作原理與實施例7相同，但 製作方法不同。同時，起因於製作方法不同，容易構成之 格子陣列構造也不同。首先說明基本架構。圖中之基板之 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -41 · 522558 Α7 Β7 五、發明説明（必 (請先閲讀背面之注意事項再填寫本頁) P井省略。在設於格子分離領域M4 4之ρ型砂基板設有 η型之源極M3 7、汲極M3 8，並有控制通道，兼作字 線之鎢之閘電極Μ 3 9。閘電極Μ 3 9與基板之間排列有 多數平均徑8 n m之微小結晶粒Μ 4 0。在閘電極側面有 Ρ型之多結晶矽構成之側壁構造Μ 4 6、Μ 4 7，與閘電 極Μ 3 9之間存在有絕緣膜Μ 4 8。同時，側壁構造 Μ 4 6、Μ 4 7與基板之間存在有絕緣膜Μ 4 9。側壁構 造直下之基板表面Μ4 1、Μ4 2與通常之L DD構造不 同，其極性與源極Μ 3 7、汲極Μ 3 8領域不同，是ρ型 。而且，源極Μ 3 7、汲極Μ 3 8領域與側壁構造係經由 鎢層Μ 5 0連接在一起。 第3 0圖係使用實施例9之記憶格子構成之記憶裝置 之記憶格陣列部分之等效電路圖。 經濟部智慧財產局員工消費合作社印製 第3 1圖第34圖表示依照製造製程之布置圖。在表 示最終布置之第3 4圖，以虛線所圍之在1個記憶格領域 之XX I X - XX I X位置向箭頭方向所示之截面對應第 2 9圖。在此爲了說明上之.方便表示較小之記憶格，但實 際上在行方向、列方向均排列有多數之格子。第3 0圖之 以虛線所圍之部分Μ 5 7便是單位陣列構造。多數記憶格 之源極領域Μ 3 7、汲極領域Μ 3 8在擴散層相互連結在 一起，以形成區域源極線Μ 3 7、Μ 3 8。區域源極線 Μ 3 7係經由選擇電晶體S Τ 7 - S Τ 9連接在源極線 Μ 5 5，全面性源極線Μ 5 6之任一方，區域源極線 Μ 3 8係經由選擇電晶體S Τ 8 - S Τ 1 0連接在源極線 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） -42- 522558 A7 B7 五、發明説明（4b (請先閱讀背面之注意事項再填寫本頁) Μ 5 2 2，全面性源極線Μ 5 6之任一方。在選擇電晶體 ST7、ST8驅動用信號線Μ5 4輸入互爲反轉之信號 ，因此可以將區域資料線之一方當作源極，另一方當作汲 極領域使用。若將信號線Μ 5 3、Μ 5 4之輸入信號分別 反轉，便有相反之功能。較之實施例8之驅動方法，雖另 需要選擇電晶體’但因源極端及汲極端讀出時源極線 Μ 5 2、Μ 5 5及全面性資料線Μ 5 6之設定電壓相同， 可以固定源極線Μ5 2、Μ5 5之電位使用，因而有可以 省略源極線驅動用電壓切換電路等之優點。同時，如果是 實施例9之陣列架構，此等選擇電晶體在由同一區域資料 線Μ 3 7、Μ 3 8驅動之多數格子可以共同配設’因此不 會增加太多面積。 經濟部智慧財產局員工消費合作社印製 實施例8之連結源極Μ 3 0與汲極Μ 3 1之電流方向 及字線Μ 2 5之方向係在互相垂直之關係，但實施例9之 陣列架構則是在平行之方向。若使用實施例9之製作方法 ，便可以如第2 9圖所示，很容易製作連結源極領域 M3 7、汲極領域M3 8之方向與字線M3 9之方向成平 行之構造。 其次說明實施例9之製造過程。如第3 5圖（a )所 示，形成格子分離領域Μ 4 4、3重井構造後’在p井上 之記憶格形成領域打入調整啓始電壓用之B (硼）離子。 第3 1圖表示形成記憶格陣列之格子分離領域用掩罩圖案 M5 8。將基板表面犧牲氧化後，堆積厚度1 5 0 nm2 S i 3 N 4膜，以抗蝕劑作爲掩罩蝕刻S i 3 N 4膜’而形成 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -43 - 522558 A7 B7 五、發明説明（4)1 (請先閱讀背面之注意事項再填寫本頁) 虛擬之閘電極M5 1。以虛擬閘電極M5 1作爲掩罩進行 雜質之打入，調整側壁下之啓始電壓後，去除基板表面之 氧化膜而再度氧化，並再堆積絕緣膜Μ 5 1 a而形成側壁 M4 6、M4 7下之成爲絕緣膜M4 9之部分。接著，堆 積厚度1 〇 〇 nm之P型多晶矽，退蝕刻1 2 0 nm分以 形成側壁。這時，使用抗蝕劑掩罩，同時形成選擇電晶體 閘極M59 (第32圖）。此後，以抗鈾劑圖案M63爲 經濟部智慧財產局員工消費合作社印製 掩罩，以等方的方式進行蝕刻，去除多餘之側壁。如第 3 5圖（b )所示，以虛擬閘極及側壁、選擇電晶體閘極 Μ 5 9爲掩罩，打入砷離子形成η型擴散層後，以抗鈾劑 作爲掩罩藉由乾蝕刻及濕蝕刻，使格子之擴散層部分之基 板表面露出。這時，選擇電晶體之擴散層要將絕緣膜留下 來。此後，如第3 6圖（a )所示，將擴散層表面及側壁 之多晶矽表面矽化物化。格子部分之擴散層表面及側壁係 以電氣方式連接在一起，但在選擇電晶體部分不連接。然 後堆積絕緣膜，進行C Μ P，藉此使虛擬閘極之上面露出 。接著，如第3 6圖（b )所示，以抗蝕劑圖案Μ 6 4作 爲掩罩，藉濕鈾刻去除格子部分之S i 3 Ν 4，爲了形成隧 道絕緣膜而進行厚度7 n m之氧化。 接著，再以C V D法形成矽微小結晶粒。堆積在溝之 底面之微小結晶成爲記憶節點。形成在溝側面之部分並不 需要，但因不影響格子之啓始電壓，因此可以不去除。形 成厚度1 2 n m之作爲層間絕緣膜Μ 4 5 2CVD-S i 〇2/CVD - S isN4/CVD - S i 〇2 之〇N〇 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -44- 522558 Α7 Β7 五、發明説明（ (請先閲讀背面之注意事項再填寫本頁) 構造膜後，爲了形成閘電極而堆積鎢膜，平坦化後則以埋 入溝部分之形態形成閘電極。接著，形成對選擇電晶體閘 極M5 9之接觸孔M6 3及連接源極線及擴散層用之接觸 孔Μ 6 4，再堆積W膜後，以配線圖案抗蝕劑作爲掩罩， 對鎢膜進行加工，形成字線Μ 3 9、源極線Μ 5 2、 Μ55、選擇電晶體控制線Μ53、Μ54。這時之鎢蝕 刻係刻進到深部之先前形成之閘電極，以防止鄰接字線之 短路。並且堆積層間絕緣膜，進行平坦化，形成全面性資 料線及擴散層連接用接觸孔Μ 6 2。堆積金屬材料後，進 行全面性資料線Μ 5 6之加工。 (實施例1 0 ) 經濟部智慧財產局員工消費合作社印製 第3 7圖、第3 8圖表示第1 0實施例。單位記憶格 子構造與實施例9相同，但格子陣列架構不相同。第3 7 圖係等效電路圖、第3 8圖係布置圖。與實施例9之差異 是擴散層配線Μ 3 7僅連接在源極線Μ 6 8，擴散層配線 Μ 3 8僅連接在全面性資料線Μ 5 6。而與實施例8之連 接關係不相同的是，經由選擇電晶體Μ 6 5連接在全面性 資料線Μ 5 6。實施例1 〇之特徵是，組合如實施例9之 利用擴散層之共同構造Μ 3 7、Μ 3 8以減少接點數之效 果，以及如實施例8之藉由驅動源極線便可以不必準備很 多選擇電晶體之效果，以實現小面積。配設選擇電晶體之 目的是在，從全面性資料線電氣方式切離與動作無關之陣 列之區域資料線，藉此減低雜散電容，將寫入、讀出動作 本紙張尺度適用^國國家標準（CNS ) Α4規格（210X297公廣)' ~~ -45- 522558 A7 B7 五、發明説明（旄 高速化。 (請先閲讀背面之注意事項再填寫本頁) (實施例1 1 ) 第39圖、第40圖表示第1 1實施例。第39圖係 記憶格之截面構造，第4 0圖係陣列構造之等效電路圖。 實施例1 1之格子構造與實施例1 0不相同。具有源極 M79、汲極M80、主動領域M8 1、主動領域附近之 多數獨立之半導體之電荷儲存小領域構成之電荷儲存領域 Μ 8 7、用以控制主動領域Μ 8 1及電荷儲存領域Μ 8 7 之電位之控制電極Μ 8 4、設在控制電極兩側壁而以控制 電極及絕緣膜Μ 9 0、Μ 9 1絕緣之側壁電極Μ 8 5、 經濟部智慧財產局員工消費合作社印製 Μ 8 6則相同。不同的是源極領域Μ 7 9、汲極領域 Μ 8 0不連接在側壁電極Μ 8 5、Μ 8 6，側壁電極電位 係與源極Μ 7 9、汲極Μ 8 0分開獨立供給。因爲需要有 至側壁電極之接續製程，因而需要較多之面積，製程也複 雜化，但電壓之自由度增加，可以提昇記憶器性能。尤其 是在讀出動作，在源極側位元讀出動作時，可對源極領域 Μ7 9之電壓，在源極側側壁電極Μ8 5施加正之電壓， 藉此使源極側側壁電極下之領域Μ 8 2低電阻化，因此讀 出電流會增加。其結果，可以將讀出動作高速化。汲極側 位元讀出動作時也可以使汲極側側壁電極Μ 8 6電位變化 ，因此是相同。關於格子架構也僅是側壁電極之控制線增 加，其他可以使用上述實施例之連接關係。考量要獨立在 源極側電荷儲存領域Μ 8 7 Α及汲極側電荷儲存領域 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -46 - 522558 Α7 Β7 五、發明説明（4)4 M8 7 B寫入資訊，將實施例1 1之等效電路標記成如第 4 〇圖。 (請先閲讀背面之注意事項再填寫本頁) (實施例1 2 ) . 第4 1圖、第42圖表示第1 2實施例。第4 1圖係 記憶格陣列之截面構造，第4 2圖係陣列構造之等效電路 圖。第4 1圖相當於第4 2圖中以虛線所示之長橢圓部分 Μ 1 1 7之平行於字線之截面。單位格子之構造及每一格 子記憶2 b i t以上之動作原理與實施例1 1相同。連接 關係與實施例6相同，在鄰接格子間共用擴散層。與實施 例6不同的是，在兼字線之閘電極之兩側壁設有補助電極 ’每一格子可以記憶2 b i t以上。在同一字線驅動之每 隔一個格子進行寫入、讀出動作這一點也與實施例6相同 。在第4 2圖以虛線表示之短橢圓部分之Μ 1 1 8之格子 經濟部智慧財產局員工消費合作社印製 進行寫入時，兩側之格子使用補助電極使其成非導通狀態 。這時，各格子分別具有兩個補助電極，但可以使一方成 低電壓以實現非導通狀態，也可以使雙方均成低電壓。這 時，至少要饋入資料之擴散層側之補助電極固定在低電壓 較佳。例如在Μ 1 1 8之格子之補助電極Μ 1 1 2側寫入 資訊時，寫入資料係饋入擴散層Μ 1 1 9，但這時之鄰接 格子之補助電極Μ 1 1 4將其電位固定在低電壓較佳。因 爲，饋入資料側擴散層電位會有很大之變動，但若將靠近 之補助電極電位固定在較低電位，便可以抑制鄰接格子之 電荷保持領域附近之電位變動，可以有更穩定之記憶保持 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ：297公釐） -47- 522558 A7 B7 五、發明説明（旎 。本實施例也與實施例6同樣，爲了擴散層配線之低電阻 化，以金屬線打裏或層次化資料線構造較有效。 (請先閲讀背面之注意事項再填寫本頁) 製造過程與實施例5相類似，因此僅說明其槪要。與 實施例5不同’在記憶格子領域不做鄰接擴散層配線間之 格子分離。因爲要使用補助電極以電氣方式分離。形成井 領域、形成虛擬閘電極後堆積導電性材料、藉退蝕刻形成 高度較虛擬閘極低之側壁。以虛擬閘極、側壁爲掩罩打入 '雜質，形成擴散層。再者，形成側壁後堆積薄絕緣膜，在 打入雜質後進行退蝕刻使基板表面露出，進行矽化物化製 程，則可以在不與側壁短路之情況下完成矽化物化。堆積 絕緣膜後進行平坦化，使虛擬電極上端露出表面。選擇性 去除虛擬電極後進行氧化，形成隧道氧化膜，以金屬或半 導體之微小粒子形成多數個之記憶領域。形成〇N〇膜之 層間膜後堆積字線材料，以抗蝕劑圖案做爲掩罩進行蝕刻 ，藉此形成字線。 經濟部智慧財產局員工消費合作社印製 第4 3圖表示實施例1 2之別的形態。相當於由鄰接 格子共用側壁閘極Μ 1 1 9之構造。但並非要形成側壁， 因此製作方法不同。較之上述構造，因爲補助閘極可以有 較大之寬度’接點製程較容易。而且，較之獨立驅動側壁 之兩側時，配線數可以較少，因此可以不必太介意配線間 距，很容易以金屬線打裏。在本實施例，若將補助電極 Ml 1 9設定在低電壓，相鄰接之兩個格子均成爲非導通 。因此，使3條中之1條補助電極成爲低電阻，由同一字 線驅動之格子則可以使相鄰接之3個格子中之1個格子動 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） _ ^ — -48- 522558 A7 ______^_B7____ 五、發明説明（‘ (請先閲讀背面之注意事項再填寫本頁) 作。製造過程則在實施例1 2之第4 1圖之架構之製作過 程途中，打入形成擴散層用之雜質後，去除側壁，將補助 閘電極材料埋入溝後，進行退蝕刻形成補助閘電極。此後 ，將絕緣材料埋入溝內，平坦化後則再度與第4 1圖製作 過程相同。 (實施例1 3 ) 第44圖至第47圖表示第13實施例。第44圖係 記憶格陣列之截面構造，第4 5圖係小規模陣列構造之等 效電路圖，第4 6圖及第4 7圖係對應於第4 5圖之布置 圖。第4 4圖係第4 5圖中以虛線所示之橢圓Μ 1 3 0部 分之垂直於字線方向之截面圖。在此也同樣以較實際之陣 列架構爲小規模者來進行說明。與先前之實施例不同，實 施例1 3之特徵是記憶格成串聯連接。同時，在如第4 4 圖之電流流通之截面，串聯連接之記憶格間不存在有擴散 層這一點也是其特徵。本架構之串聯連接之分電阻較高， 但有格子面積小之特徵。 經濟部智慧財產局員工消費合作社印製 在由字線Μ 1 2 1驅動之格子之一端Μ 1 2 8寫入資 料時，首先依欲寫入之資訊將第1資料線Μ 1 3 1設定在 高電壓（例如5 V )或低電壓（例如Ο V )。第2資料線 Ml 3 2設定在0V。而且，將欲寫入之格子之字線 Μ 1 2 1及該格子之欲寫入側之補助電極Μ 1 2 0以外之 字線Μ123、Μ136、補助電極Μ122、Μ135 設定在一定之高電位（例如6 · 5 V )，使電極下成爲低 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐）~' -49 - 522558 A7 _B7 五、發明説明（4> (請先閱讀背面之注意事項再填寫本頁) 電阻狀態。寫入之補助電極Μ 1 2 0設定在較低電位（例 如2V)，使其下面之基板表面Ml 2 4成爲較高之電阻 狀態。使格子之字線Μ 1 2 1較其他之字線在高電位（例 如1 2 V )時，若第1資料線Μ 1 3 1設定在高電壓（例 如5 V )時，在補助電極與字線間之基板表面產生熱電子 ，注入到附近之電荷儲存領域Μ 1 2 8。第1資料線 Ml 3 1設定在低電壓時幾乎不會注入電荷。對另一端 Μ 1 2 9之電荷注入使用同一字線Μ 1 2 1及相反側之補 助電極Μ 1 2 2。這一次是將資料饋入第2資料線 Μ 1 3 2，第1資料線Μ 1 3 1成爲Ο V。除了電流之方 向相反以外，以同樣之動作將資訊寫入電荷儲存領域 Μ 1 2 9。 經濟部智慧財產局員工消費合作社印製 在讀出動作時，讀出寫入時將寫入資訊饋入第1資料 線Μ 1 3 1之一側之資料時，將第1資料線Μ 1 3 1，讀 出寫入時將寫入資料饋入第2資料線Μ 1 3 2之一側之資 料時，將第2資料線Μ 1 3 2預充電至正之電位（例如 2V)。在各個場合，另一端是在0V。將驅動欲讀出之 格子之字線Μ 1 2 1以外之字線Μ 1 2 3、Μ 1 3 6，補 助電極Ml 2 0、Ml 2 2及Ml 3 5設定在高電位（例 如6 · 5 V )，並且向該字線Μ 1 2 1供應一定之讀出電 壓（例如3 V )。例如預充電第1資料線Μ 1 3 1之讀出 動作時，字線Μ 1 2 1下之領域Μ 1 2 5中，連接在較低 電位之第2資料線Μ 1 3 2之一側形成通道，第1資料線 Μ 1 3 1側則夾斷，因此會受到第2資料線Μ 1 3 2側之 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） "' -50- 522558 Α7 Β7 五、發明説明（4 影響較多’亦即，受到較多之Μ 1 2 8所保持之資訊之影 響，因此可以讀出。 實施例1 3係使用準備兩條資料線而對調電壓設定之 方式’但也可以採其他之實施形態，例如第4 8圖所示， 使成使用資料線Μ138、源極線Μ139之連接關係， 在資料線側之寫入時，可以使用提高源極線電位之與實施 例8同樣之驅動方法。使用這種連接關係時，對一列之串 聯格子陣列各準備一條資料線即可，較第4 5圖之連接關 係資料線間隔會較小，因此可以實現小記憶格，對低成本 化有效果。 連同第4 6圖、第4 7圖之記憶格陣列部分布置圖一 倂說明實施例1 3之製造過程。進行格子分離，定義主動 領域Μ 1 3 7後，堆積隧道絕緣膜、矽微小結晶、Ο Ν〇 層間膜、字線電極材料、覆體絕緣膜。以抗蝕劑作爲掩罩 蝕刻蓋體絕緣膜、字線材料、層間膜、矽微小結晶，形成 字線Μ 1 3 6、Μ 1 2 3及Μ 1 2 1。表面氧化後堆積絕 緣膜，再堆積能夠塡埋由字線作成之溝之厚度之補助閘電 極材料。一倂使用周邊部分用之抗蝕劑掩罩將補助閘電極 材料退蝕刻，絕緣鄰接補助閘電極間而形成記憶格。此後 以字線、補助電極作爲掩罩，在主動領域Μ 1 3 7之兩端 部打入η型雜質，予以活性化。形成層間絕緣膜後，在主 動領域Μ 1 3 7兩端部分別穿設接觸孔Μ 1 3 3、 Μ 1 3 4，形成第1資料線Μ 1 3 1及第2資料線Μ 1 3 2。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） ί n«l ml !w m : ϋ.^ m ml n (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 ;τ: -51 - 522558 A7 ___ __ B7 五、發明説明（也 (實施例1 4 ) (請先閲讀背面之注意事項再填寫本頁) 第49圖、第5 0圖表示第1 4實施例。第49圖係 截面圖，第5 0圖係表示格子陣列之連接關係之等效電路 圖。第5 0圖所示之縱長之虛線之橢圓Ml 4 8之部分截 面圖對應第4 9圖。很類似實施例1 3，但不存在有補助 電極，成爲補助電極之部分全部是記憶格這一點不相同。 電荷儲存領域Ml 4 4存在於整體。實施例1 4之每一記 憶格之面積很小。因此，不進行源極側、汲極側之兩端寫 入，作爲低成本架構仍然有效。若與每一格子之多値記憶 組合，便可以達成大大凌駕目前之快閃記憶器之低成本化 。同時，實施例1 4係如第5 0圖所示進行兩端寫入使每 一格子爲2b i t ，但也可以使注入電荷之處所爲同一處 所’以電荷量作成多層次，也可以藉由電荷量及兩端寫入 實現更高密度之記憶。同時，陣列之架構係與實施例1 3 之其他實施形態（第4 8圖）相同，但也可以是與第4 5 圖同樣之連接關係。 經濟部智慧財產局員工消費合作社印製 驅動方法也是與實施例1 3之其他實施形態（第4 8 圖）相同，但要寫入以字線Μ 1 4 1驅動之格子之紙面左 側時，與實施例1 3之補助電極Μ 1 2 0同樣使用左側之 字線Μ 1 4 0。讀出時也一樣。不同的是，在實施例1 3 成爲補助電極之部分也成爲記憶格，而可以使用鄰接記憶 格之字線作爲補助電極進行記憶、讀出動作這一點。具體 上，其特徵是，驅動字線Μ 1 4 1之記憶格時，將兩端之 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） ' _ -52- 522558 Α7 Β7 五、發明説明（5b 字線Μ 1 4 0、Μ 1 4 1當作補助電極使用，驅動字線 Μ 1 4 2之記憶格時，將兩端之字線Μ 1 4 1 、Μ 1 4 3 當作補助電極使用。第5 0圖係將串聯連接格子之兩端 Μ 1 4 7表示爲普通之電晶體，但架構是可以與記憶格相 同。因爲只有一側有補助電極，無法進行兩端寫入，但一 側可以寫入，也可以當作記憶格使用。 再說明實施例1 4之製造過程。以不同之製程製造鄰 接字線爲其特徵。進行格子分離，定義主動領域Μ 1 3 7 後，堆積隧道絕緣膜、矽微小結晶Μ 1 4 4、〇Ν〇層間 膜Μ 1 4 8、字線電極材料用之η型多晶矽、蓋體絕緣膜 。以抗蝕劑作爲掩罩蝕刻蓋體絕緣膜、字線材料，形成字 線Μ 1 4 Ο、Μ 1 4 2。與實施例1 3不同，層間膜、矽 微小結晶不蝕刻。在這時進行輕度之氧化。η型多晶矽表 面會被氧化，但矽微小結晶或基板由〇 Ν〇層間膜 M1 4 8保護，事實上不被氧化。也可以使用CVD絕緣 膜取代氧化，但由字線驅動之格子之特性會有因事後作成 之字線較層間絕緣膜厚之份量之變動，需要注意。而且， 堆積足夠完全塡埋由字線Ml 4 〇、M1 4 2作成之溝之 厚度之字線材料，一倂使用周邊部分用之抗鈾劑掩罩對字 線材料進行退蝕刻，形成字線Μ 1 4 1、Μ 1 4 3。此後 則與實施例1 3。 (實施例1 5 ) 第5 1圖至第54圖表示第1 5實施例。第5 1圖係 本紙張尺度適用中國國家榡準（CNs ) Α4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 -53- 522558 Α7 Β7 五、發明説明（5)1 (請先閱讀背面之注意事項再填寫本頁) 在垂直於資料線，平行於字線芝之面之截面圖。第5 2圖 係單位構造之等效電路圖，第5 3圖係表示格子間之連接 關係之等效電路圖。第5 4圖係表示格子間之連接關係、 布置之布置圖，第5 4圖中之L I - L I位置向箭頭方向 所視之截面對應第5 1圖。從電路圖看，第5 3圖中以虛 線所示之橢圓Μ 1 6 6之領域之截面對應第5 1圖。記憶 格係形成在絕緣膜上，例如形成在格子分離用之塡埋絕緣 膜上。由於是積層化構造，由η型多晶矽構成之源極（源 極線）Μ 1 4 9、汲極（汲極線）Μ 1 5 0互成上下之位 置關係，其間有絕緣膜Μ 1 5 8。源極Μ 1 4 9、汲極 Ml 5 0間係由半導體之通道層薄膜Ml 5 3、Ml 6 4 連接，電流係垂直流向基板。通道層薄膜側面設有介由隧 道絕緣膜Μ 1 5 6相互獨立之多數半導體結晶粒構成之電 荷儲存領域Μ 1 5 4、Μ 1 5 5，復介由層間絕緣膜 Μ 1 5 7，在資料線之側面配設補助電極Μ 1 5 2、 經濟部智慧財產局員工消費合作社印製 Μ 1 6 4及字線Μ 1 5 1 ，以控制各通道層薄膜之一部分 。本構造因利用立體構造，格子面積變小，對低成本化有 很大效果。 實施例1 5之架構可以藉一條資料線Μ 1 5 0驅動兩 處之電荷儲存領域Μ 1 5 4、Μ 1 5 5。亦即，將資料寫 入一方之電荷儲存領域，例如Μ 1 5 4，讀出時使相反側 之補助電極Μ 1 6 3成低電壓，使此領域近邊之通道層薄 膜Μ 1 6 4成爲非導通狀態。可以將寫入側之補助電極 Μ 1 5 2呈作寫入動作之補助電極，完成商效率之熱電子 本紙張尺度適财關家縣（CNS ) Α4規格（21GX297公董) ~ ' -54- 522558 Α7 _ Β7 五、發明説明（金 注入。 (請先閲讀背面之注意事項再填寫本頁) 實施例1 5係將補助電極Ml 4 9僅當作寫入、讀出 之補助電極使用，但也可以對調字線與補助電極之功能進 行驅動。例如將補助電極Μ 1 5 2當作字線使用時，首先 將資料饋入（例如寫入“ 1 ”時設定在〇 V ,寫入“ 〇 ” 時設定在5 V )兩側之資料線Μ 1 6 7、Μ 1 5 0，將源 極線設定在高電壓（例如5 V )，將兩側之補助電極 Ml 6 8、M1 5 2設定在低電壓（例如〇ν)。再將字 線Μ 1 5 1設定在比較低電壓（例如2 V )，在補助電極 Μ 1 5 2施加高電壓（例如1 1 V )，便可以在補助電極 Ml 5 2兩端之電荷保持用之微小點Ml 6 9、Ml 5 4 中，補助電極橫側且靠近字線Μ 1 5 1之部分寫入資訊。 讀出時則將字線Μ 1 5 1設定在高電壓（例如4 V )，使 字線Μ 1 5 1橫側成低電阻，將補助電極Μ 1 5 2設定在 一定之讀出電壓（例如2 · 5 V )即可。 經濟部智慧財產局員工消費合作社印製 此項對調動作係如更單純示於第5 5圖，閘電極以微 小之間隔並排時方有可能。在Ρ型矽基板Μ 1 7 0上形成 隧道絕緣膜Μ 1 7 7、微小粒記憶節點、層間膜Μ 1 7 8 ，在其上形成第1閘電極Μ 1 7 1及第2閘電極Μ 1 7 2 。可以藉η型之擴散層Ml 7 3、Ml 7 4從兩端取出電 極。要將資訊寫入第1閘電極Μ 1 7 1下之記憶領域 Μ 1 7 5時，將第2閘電極Μ 1 7 2當作補助閘極使用。 反之，要將資訊寫入第2閘電極Μ 1 7 2下之記憶領域 Μ 1 7 6時，將第1閘電極Μ 1 7 1當作補助閘極使用。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -55- 522558 Α7 Β7 i、發明説明（sh (請先閱讀背面之注意事項再填寫本頁) 要讀出第1閘電極Μ 1 7 1下之記憶領域Μ 1 7 5之資訊 時，將第2閘電極Ml 7 2設定成高電壓，而不論寫入第 2閘電極Μ 1 7 2下之記憶領域Μ 1 7 6之資訊如何，使 第2閘電極Μ 1 7 2之基板表面成爲低電阻，並使第丨聞 電極Ml 7 1成爲一定之讀出電壓，而以電阻之差異看出 啓始電壓位移。要讀出第2閘電極Μ 1 7 2下之記憶領域 時，將第1聞電極Ml 7 1設定成高電壓，使第2聞電極 Ml 7 2成爲一定之讀出電壓。 以此架構作爲基本，採與實施例2同樣之陣列架構也 可以。對應第1 7圖之圖式係第5 6圖。除了與實施例2 相同之記憶動作外，也可以在其他補助電極Μ 9 5、 Μ 9 6下寫入資訊，記憶密度可以提高。 經濟部智慧財產局員工消費合作社印製 在實施例1 5，資料線上Μ 1 5 9及源極線間 Μ 1 6 0殘留有通道之半導體材料。當然加進去除製程也 無妨，但不去除動作上並沒有問題。亦即，源極線因設定 共同電位，因此源極線間Μ 1 6 0漏洩不會成爲問題，資 料線上Μ 1 5 9則只是連接相同資料線之不同側面而已。 實施例1 5係以η型多晶矽形成源極線、資料線，這與金 屬線比較時電阻太高。在適當之長度設接點，以金屬之資 料線打裏之架構之方法較有效。另外，在適當之長度切斷 多晶矽資料線Μ 1 5 0，經由開關取接點，而連接到金屬 之全面性資料線之層次化資料線構造也很有效。也可以用 金屬形成源極線、資料線，設法將其低電阻化。這時，通 道層薄膜Μ153、Μ164及Μ149Μ150間不能 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） •56- 522558 A7 B7 五、發明説明（5^ Γ碕先閱讀背面之注意事唄再填寫本頁} PN接合，但使通道層薄膜Ml 5 3、Ml 6 4充分空乏 化，便可以將截止時之漏洩抑制得很低。再者，實施例 1 5係採源極、絕緣膜、汲極之縱型構造，但也可以鈾刻 矽基板表面，作成與上述資料線同樣之縱型構造。 經濟部智慧財產局員工消費合作社印製 其次說明實施例1 5之製造過程。在格子分離領域上 依序堆積η型多晶矽、S i〇2、η型多晶矽、S i〇2， 以抗蝕刻劑作爲掩罩整批加工，形成資料線Μ 1 5 0、源 極線Ml 4 9。堆積本質的（intrinsic)或弱ρ型之厚度8 n m之非晶矽薄膜，再堆積隧道絕緣膜Μ 1 5 6。以這項 熱製程藉C V D進行非晶矽薄膜之結晶化。形成矽結晶粒 ，再堆積層間絕緣膜Μ 1 5 7，在其上面以埋溝之形態堆 積補助電極材料之η型多晶矽。進行退鈾刻，在溝底形成 補助電極Μ 1 5 2、Μ 1 6 3。在此氧化表面或堆積絕緣 膜，再以將字線材料埋入溝內之形態進行堆積。進行平坦 化，以抗蝕刻劑作爲掩罩加工字線材料，形成字線 Μ 1 5 1。在此，資料線側面中之沒有字線之領域也存在 有通道層薄膜，但將啓始電壓設定在較高電壓，使成正常 時截止，便不會有問題。將啓始電壓設定成較低時，若以 字線作爲掩罩進一步進行層間膜、隧道膜、通道層薄膜之 加工，便可以防止沒有字線部分之漏洩。同時，也可以在 形成補助電極前先進行通道層薄膜蝕刻。 (使用虛擬格子產生讀出時之參照電位之方法） 在上述各實施例欲產生讀出時之參照電位，以使用虛 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） -57- 522558 A7 B7 五、發明説明（ώ (請先閲讀背面之注意事項再填寫本頁) 擬格子之方法較有效。第5 7圖成單純化表示使用虛擬格 子時之施加讀出字線電壓後之資料線之電位變化。第5 7 圖（a )係源極端讀出，（b )係汲極端讀出。如圖所示 ’源極端讀出之特性不受汲極端讀出之影響爲理想，但實 際上是會稍受影響。汲極端讀出時也一樣。使用虛擬格子 便可以實質上迴避這種影響。因此虛擬格子之寫入時兩端 均使用進行輕度之寫入之格子較佳。輕度寫入有將寫入時 之電壓設定在較低電壓之方法，縮短供給字線之寫入脈衝 寬度之方法’將資料線電壓設定成較小之方法等，使用那 一種方法都可以。 (記憶圖） 再說明記憶圖。在此將由同一字線驅動之整個格子稱 作傘形區（sector)。 經濟部智慧財產局員工消費合作社印製 第5 8圖表示實施例8之記憶圖。由同一字線驅動之 格子有8 1 9 2格子，具有1 6 3 8 4條之字線，可實現 2 5 6 M b之記憶容量。實際上是除了這些外，另外每字 線具有錯誤更正等用之控制資訊數十位元組（byte )，但 在圖中省略未表示。又如實施例7所述，改變井電位進行 抹除動作時，以多數傘形區作爲一組之區塊（block)單位 共用井。不同區塊之井則電氣方式分離可個別驅動。因此 是進行區塊單位之抹除。 其結果，應驅動之井數減少，端至端之雜散電阻也降 低，因此能以高速進行穩定之動作。圖中左側之位址係傘 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -58- 522558 A7 B7___ 五、發明説明（sb (請先閲讀背面之注意事項再填寫本頁) 形區位址。一個格子有源極端記憶及汲極端記憶’因此同 一字線驅動之格子分配有兩個傘形區。實施例8係僅在源 極端依序分配傘形區位址，汲極端之傘形區位址係離開源 極端位址。寫入時，在傘形區位置成連續之領域依序寫入 。因此，寫入動作中不必變更源極線電位，可以高速寫入 。依相同理由，讀出也可以高速。另一方面，不同檔案之 資訊會記憶在同一格子內。 經濟部智慧財產局員工消費合作社印製 實施例8係在兩端同時進行抹除動作，無法選擇性僅 抹除一方之檔案。因此須先將儲存有欲抹除之檔案之記憶 領域之另一端之部分讀出外部，保持在R A Μ等。然後抹 除該領域，再將保持在外部之資訊及欲改寫之資訊寫入。 採用上述區塊抹除法時，此項迴避讀出動作之單位是區塊 。不改變井電位而進行抹除之方式時可以作傘形區單位之 抹除，因此也可以進行以下所述之其他方法。亦即，讀出 欲改寫之傘形區之另一端資訊，儲存在暫存器後抹除傘形 區，然後寫回另一端資訊。欲改寫之資訊之寫入則在此後 進行。若準備每一資料線兩個暫存器，便可以同時將此迴 避資訊與改寫資訊保持在暫存器，因此，動作程序之自由 度可以增加。另一方面’一般之抹除動作需要讀出動作之 數倍之時間，因此有返覆抹除動作會使動作較上述之迴避 到外部之方式慢之課題。 第5 9圖表示實施例8之其他記憶圖之例子。本架構 係將不同源極線驅動之兩傘形區作爲一組，當作區塊。例 如由相鄰接之字線Μ 2 5、Μ 2 9驅動之傘形區形成區塊 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公董） -59 - 522558 Α7 Β7 五、發明説明（έτ (請先閲讀背面之注意事項再填寫本頁) 。傘形區位址之分配要避免相同字線之源極端與汲極端成 連續狀，而以此順序寫入。其結果，在進行一方之字線（ 例如Μ 2 9 )之汲極端之寫入之期間，可以將由下一次寫 入之另一方之字線（例如Μ 2 5 )驅動之格子之源極線（ 例如M2 1 )之電壓設定切換成源極端寫入用之電壓，電 壓切換之速度之負面影響較少。較之第5 8圖所示之方法 ，源極線切換之頻繁度較高，電力消耗會較大，但可以構 成較小之區塊，以此單位抹除時，不須要上述迴避動作。 再者，在此說明者係使用兩端記憶之格子之記憶器之 資訊儲存處所之管理方法，例如說明傘形區位址之寫入順 序者。因此，傘形區、區塊、位址等之分配當然不一定要 如此。同時，分配方法使用以軟體等之分配管理，在使用 途中改變分配方法也可以。 而實施例4係在同一區塊內之源極端依序分配傘形區 號碼後，連續分配給汲極端（參照第5 8圖）。在實施例 4，係以驅動單位區域資料線之多數字線作爲一組，將由 此等一組之字線驅動之格子整體稱作區塊。 經濟部智慧財產局員工消費合作社印製 寫入順序也照此順序時，可以將連續之資料儲存在同 一區塊之源極端、汲極端，因此，不作抹除區塊時之迴避 動作也可以。寫入動作中會有源極端、汲極端之切換動作 ，但因實施例4較實施例8之切換快速，因此這種驅動有 用。另外，採用連續進行同一字線驅動之源極端與汲極端 之寫入之驅動方法也可以。區域源極線之充放電部分之消 耗電力會增加，時間也因切換動作而變慢，但因可以進行 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） -60- 522558 A7 B7 五、發明説明（由 字線單位之抹除、寫入，因此在處理之資料之規模較小時 特別有效。 (請先閲讀背面之注意事項再填寫本頁) 而且，在實施例9，係以驅動單位區域資料線之多數 字線作爲一組，將由此等一組之字線驅動之格子整體稱作 區塊。實施例9係在同一區塊內之源極端依序分配傘形區 號碼後，連續分配給汲極端（參照第6 0圖）。寫入順序 也照此順序時，可以將連續之資料儲存在同一區塊之源極 端、汲極端，因此，不作抹除區塊時之迴避動作也可以。 寫入動作中會有源極端、汲極端之切換動作，但因本實施 例較實施例8之切換快速，因此很適合這種驅動。另外， 採用連續進行同一字線驅動之源極端與汲極端之寫入之驅 動方法也可以。區域源極線之充放電部分之消耗電力會增 加，時間也因切換動作而變慢，但因可以進行字線單位之 抹除、寫入，因此在處理之資料單位之規模較小時特別有 效。 經濟部智慧財產局員工消費合作社印製 同時，實施例1 0也具有區域資料線構造，因此區塊 之定義與實施例9相同。實施例1 0之格子驅動方法與實 施例8類似，但使連接在不含成爲寫入、讀出之目標格子 之區域資料線之選擇電晶體成截止狀態之部分不相同。同 時，在使用本實施例之記憶格之記憶器，以下說明之記憶 處所之管理方法也與實施例8不相同。本方法特別適用於 以數位照像機之攝影等單位檔案大小在1 〇 〇 K B程度以 上之規模，且檔案大小大體上整齊時之用途。 首先從外部輸入指定單位檔案大小之信號。寫入檔案 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ' 522558 A7 B7 五、發明説明（sb (請先閲讀背面之注意事項再填寫本頁) 時’不對調各記憶器焊接區之源極端或汲極端，而使用多 數區塊進行寫入。例如僅進行源極端寫入。此多數區塊數 ’係能夠以源極端、汲極端雙方加起來之容量儲存先前輸 入之檔案大小之數目。然後將模式切換至另一端寫入用， 進行剩餘之寫入。其結果，抹除檔案時只要抹除上述多數 區塊即可，與實施例9同樣有不需要迴避動作之特徵。 依據本發明時，能夠廉價供給被要求能高速讀出之半 導體記憶裝置。或者提供，一方面可確保可靠性，同時可 以實現縱方向之定標之格子構造。同時，可以提供能增加 每一格子之記憶資訊而不會使格子性能大幅度下降之方法 。而且，可以提供藉由這種格子實現大容量記憶裝置之方 法。 圖式之簡單說明 第1圖係實施例1之半導體裝置之布置圖。 第2圖係從第1圖之I I - I I位置向箭頭方向所視 之半導體裝置之截面圖。 經濟部智慧財產局員工消費合作社印製 第3圖係從第1圖之I I I - I I I位置向箭頭方向 所視之半導體裝置之截面圖。 第4圖係表示實施例1之記憶格在對應之電路圖上之 標記之圖。 第5圖係實施例1之半導體裝置之等效電路圖。 第6圖係表示實施例2之每一格2 b i t以上之記憶 方式之讀出原理之圖。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -62- 522558 A7 B7 五、發明説明（6b 第7圖係包含周邊電路之驅動一倂表示之實施例2之 寫入動作之圖。 (請先閲讀背面之注意事項再填寫本頁) 第8圖係包含周邊電路之驅動一倂表示之實施例2之 讀出動作之圖。 第9圖係實施例2之半導體裝置之布置圖。 第1 0圖係從第9圖之X - X位置向箭頭方向所視之 半導體記憶裝置之截面圖。 第11圖係從第9圖之XI-XI位置向箭頭方向所 視之半導體記憶裝置之截面圖。 第1 2圖係實施例3之記憶器陣列之等效電路圖。 第1 3圖係實施例4之記憶器陣列之等效電路圖。 第1 4圖係從第1 6圖之X I V- X I V位置向箭頭 方向所視之實施例5之半導體記憶格之截面構造圖。 第1 5圖係對應實施例5之半導體記憶格之等效電路 圖。 第1 6圖係實施例5之半導體記憶格之布置圖。 經濟部智慧財產局員工消費合作社印製 第1 7圖係實施例6之半導體裝置之記憶格部分之字 線平行面之截面構造圖。 第1 8圖係說明實施例6之半導體裝置之記憶格部分 之連接關係之等效電路圖。 第1 9圖係說明實施例6之半導體裝置之記憶格部分 之製造過程之字線平行面之截面構造圖。 第2 0圖係實施例7之半導體記憶格之截面構造圖。 第2 1圖（a ) 、（ b )係說明實施例7之半導體記 本紙張尺度適用中國國家標準（CNS ) A4規格（210、〆297公釐） -63- 522558 A7 B7-22- 522558 A7 B7 V. Description of the invention (2 () (Embodiment 4) (Please read the precautions on the back before filling out this page) Then explain Embodiment 4. The operation principle of Embodiment 4 is the same as that of Embodiment 2. Its basic structure is the same as that of Embodiment 3. Figure 13 shows the equivalent circuit. Here, small memory cells are shown for convenience of explanation, but in practice, there are a large number of cells arranged in the row direction and the column direction. The dotted area J 1 3 1 in Figure 3 is the unit array structure. The source region J 1 3 of most memory cells and the drain region J 1 3 3 are connected to each other in the diffusion layer to form a regional source. The polar lines J 1 3 2, J 1 3 3. The regional source lines J 1 3 2 are connected to the source lines J 1 3 4 and J 1 3 5 via selection transistors ST 3-ST 6, which are comprehensive source lines. Either J 1 3 6. When the signal line for driving the transistor J 1 3 7, J 1 3 8 is selected, the signals are mutually inverted. Therefore, when the transistors ST3 and ST4 are selected to be on, the regional data line J 1 can be used. 3 3 is used as the source field, and the area data line J 1 3 2 is used as the drain field. When the transistors ST 5 and ST 6 are selected to be on The regional data line J 1 3 2 can be used as the source area, and the regional data line J 1 3 3 can be used as the drain area. If the input selects the transistor drive signal line J 1 3 7, J 1 3 8 The signal is divided into the consumer property cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and it has the opposite function. Compared with the driving method of Example 2, although the transistor needs to be selected, the source and source of the readout time are read out. The set voltages of the polar lines j 1 3 4, J 1 3 5 and the comprehensive data line J 1 3 6 are the same. The potentials of the source lines J 1 3 4 and J 1 3 5 can be fixed for use, so the source lines can be omitted. Advantages of driving voltage switching circuit, etc. At the same time, if it is the array structure of embodiment 4, the paper size standard (CNS) A4 specification driven by the same area data line j 1 3 2, J 1 3 3 ( 21GX297mm) " -23- 522558 A7 B7 V. Description of the invention (2) Most grids can be equipped with these selection transistors' so it will not increase too much area. (Please read the precautions on the back before filling in this (Page) The current direction of the source J 7 and the drain J 8 connected in Example 1 and The direction of the word line J 2 is perpendicular to each other, but the array structure of the fourth embodiment is in a parallel direction. If the manufacturing method of the fourth embodiment is used, the connected source can be easily produced as shown in FIG. 9. Field J 1 〇1, Drain field J 1 0 3 and the word line J 1 04 are parallel to each other (Embodiment 5) The following will describe a part of the semiconductor grid and semiconductor device whose structure is different from the above embodiment . Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 14 is a cross-sectional structure view of the semiconductor memory cell of Example 5 viewed from the position of X I V-X I V in Figure 16 to the direction of the arrow. A P-type silicon substrate M7 7 a is provided with an n-type well region M7 7 b, and a P-type well M77c is provided therein, which has a so-called triple well structure. In the P-type well, there are n-type source M6 9, drain M7 0 field. On the M7 6, M7 7 part of the active field, most of the tunnel oxide film M7 2 with a thickness of 8 nm is arranged as a charge storage field. The fine crystal grains M 7 1 of silicon having an average diameter of 15 nm. The first gate electrode M 7 4 of η-type polycrystalline silicon for controlling the potential of a part M 7 7 in the active field and the potential in the charge storage field is provided, and the silicon fine crystal grains M 7 1 and the gate electrode M 7 4 are sequentially formed from below. There are S i 〇2 thickness of 4nm, S i 3N4 thickness of 8nm, and SiO2 structure of 4nm thickness. The paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm): '-24- 522558 Α7 Β7 V. Description of the invention (2 $ (please read the precautions on the back before filling this page) M7 3. It also has the structure of the second gate electrode M7 5 which controls the potential of M7 6 which is part of the active area. In addition, "Figure 14 shows the triple-well structure", but other embodiments are omitted because of the need to avoid confusion. Figure 15 is a circuit diagram corresponding to Figure 14. The first gate electrode M7 4, the second alarm electrode M7 5, The source M6 9, the drain M7 0, and the charge storage area M 7 1 are respectively marked with corresponding reference signs. When the substrate bias is used to control the memory cell, 'in order to set different P-wells to different potentials, 3 The heavy well structure is very effective. However, if an η-type substrate is used, the memory cell is partially used. A double-well structure is sufficient. Next, the operation of Example 5 will be described. Example 5 uses the second gate electrode M 75 as an auxiliary electrode, thereby injecting hot electrons into the charge storage area M 71 with high efficiency. Economy Printed by the Consumer Cooperative of the Ministry of Intellectual Property Bureau. Firstly, the writing operation is described. The voltage of the drain field M 70 is set according to the information to be written. Here, the condition for injecting more charge corresponds to the information “1”, and the charge is less. The state corresponds to the information "0". When the information "1" is written, it is set to a sufficiently large electric field (for example, 5 V) to generate hot electrons. The source region M 6 9 is set to 0 V. When the information "0" is written , Set the potential difference between the source and the drain to be small (for example, 0 V). Set the second gate electrode M75 to a certain voltage (for example, 2 V). Apply the first gate electrode M7 4 higher than the second gate electrode M7 5 High-voltage (for example, 12V) write pulse. At this time, the resistance of the active area M7 6 under the second gate electrode M7 5 is larger than the resistance of the active area M7 7 under the first gate electrode M7 4. . Therefore, the voltage between the source and the drain is almost all applied to M7 6 under the second gate M7 5. At the same time, the main paper size under the second gate electrode M7 5 applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) -25- 522558 A7 B7 V. Description of the invention (2 $ (Please read the precautions on the back first) (Fill in this page again) The potential in the moving field M 7 6 is also close to the one on the side of the drain region M 7 0. The effective field voltage will decrease, so it will become a high resistance. Therefore, it is closer to the second gate electrode M7. There are more hot electrons at one end of the drain M7 0 of M7 6 under 5. The generated hot electrons are accelerated toward the charge storage area M7 1 by the electric field of the first gate electrode M 7 4, and injection occurs. Focused on the area M 7 8 of the second gate electrode M 7 5 under the first gate electrode M 7 4. At this time, the current flowing between the source and drain electrodes is lower than the resistance of the active field M 7 6 under the second gate electrode M 7 5. High, so there are fewer structures without auxiliary gates, so it can be injected with high efficiency, and the current is small. Because the write current per unit grid is small, more write operations can be set per write operation. The number of grids can increase the number of memory chips The total amount of written information. It is especially suitable for large-capacity memory to send and receive information with a large data unit. When writing "0", the voltage between the source and the drain is small, so no hot electrons are generated and no injection is performed. The charge is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, followed by a description of the readout action. For example, the drain voltage is set to 2 V, the source voltage is set to 0 V, and the voltage of the second gate electrode M7 5 is set to 3 · 5 V. And a read pulse of 2 V is added to the first gate electrode M 7 4. Because the initial voltage varies according to the amount of charge injected into the charge storage area M 7 3, because "0" the drain current of the memory is higher than " 1 ”The drain current of the memory is large and reading can be performed. In addition, compared with the lattice structure without the second gate electrode structure in Example 5, it is also advantageous in the reading operation for the following reasons. That is, there is no In the grid structure of the second gate electrode structure, the hot electrons will be injected into the memory area near the drain, but the transistor becomes saturated in the high initial voltage state. The paper size of this paper applies the Chinese National Standard (CNS) Α4 specification ( 21〇Χ; 297 mm) -26- 522558 A7 B7 V. Description of the invention (24 (Please read the precautions on the back before filling this page) Action, the channel will be pinched off near the drain (Pinch off), so the effect of the injected charge will change As a result, although sufficient charge is injected, the voltage shift on the surface becomes smaller, and the operating margin is reduced. The means to avoid this is to adjust the source and drain of the MOS transistor, as is known in the art. The voltage setting is more effective for reading, but it will be accompanied by the negative effects of a reduction in the operating speed of the memory and the complication of peripheral circuits. The invention injects charge in the middle of the source and drain, so it can effectively read and inject The effect of the electric charge 0 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Example 5 Non-volatile memory can be retained after the power is turned off. In particular, since the memory node is composed of many small particles M 71 of independent semiconductors, the insulation film is deteriorated due to rewriting stress. When a leak occurs under a low electric field, it is only a small particle connected to a part of the leakage path. The charge is lost, so it can be stably maintained. On the other hand, the flash memory usually loses the charge of the memory nodes one by one due to the leakage path, so it has a great impact. The thickness of the tunnel insulation film of the flash memory is determined by rewriting the leakage current after rewriting. Embodiment 5 can increase the thickness of the tunnel insulation film, which is equivalent to improving the reliability. It is also superior to the flash memory in the longitudinal calibration of the entire grid. When erasing information, a negative voltage may be applied to the first gate electrode M 7 4. For example, the source M 69 and the drain M 70 are both set to 0 V, and the first gate electrode M 74 is set to -18 V. At this time, electrons injected due to the high electric field are released to the substrate side. The erasing action is the source of the extreme, and the entire batch is absorbed. Moreover, at this time, the potential of the well M7 7 c can also be set to a potential higher than 0V (for example, 5 V), and the paper size of the potential of the first gate electrode M 7 4 is relatively applicable to the Chinese National Standard (CNS) Α4 specifications (210X297 mm) -27- 522558 A7 __B7_ V. Description of the invention (2 $ Absolute 値 is set to a small value (for example -1 3 V). The absolute 値 of the voltage used is reduced, and the voltage generation circuit is simplified. (Please read the precautions on the back before filling out this page.) Next, refer to Figures 14 and 16 to explain the manufacturing process of Example 5. Form an active area M 9 3 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and After the triple-well structure, in the memory cell formation area on the p-type well M 7 7 c, impurities B (boron) ions are doped to adjust the starting voltage. The substrate surface is oxidized to form a tunnel oxide film M 7 2 with a thickness of 10 nm. Then, silicon microcrystalline particles M 71 were formed by CVD. In the trial, they were formed at a density of 5 x 1 011 per square centimeter at an average diameter of 7 nm. S i 02 with a thickness of 4 nm and a thickness of 8 nm were sequentially formed from below. S i 3N4, 4 nm thickness S i〇2〇〇〇 The absolute structure After the edge film M7 3, in order to form a first gate electrode, η-type polycrystalline silicon is deposited, and then a S i 3 N 4 film is deposited. Using the resist film as a photomask, the S i 3 N 4 film, the polycrystalline silicon film, 〇N 0 film, Si 02 film. During this process, the first gate electrode M 74 is formed. The first gate electrode is used as a mask to inject impurities, and the impurity concentration under the second gate electrode is adjusted. After washing, The surface of the substrate is oxidized, and then a CVD-Sio2 film is deposited. In order to form a second gate electrode, a polycrystalline silicon film is deposited and planarized. Here, the thickness of the polycrystalline silicon film is thicker than the step height formed by processing the first gate electrode. The planarization is stopped when S i 3 N 4 of the cover of the first gate electrode appears, whereby only the upper surface of the polycrystalline silicon film for forming the second gate electrode is exposed, and the surface of the first gate electrode is still covered by S i3N4. Then, the mask pattern M 9 4 for processing the second gate electrode is used to process the polycrystalline silicon film. As and arsenic ions are implanted with the first and second gate electrodes as a mask to activate the source M 6. 9, drain pole M 7 0 field. And this paper size applies to Chinese National Standard (CNS) A4 specifications (210 × 297) (Central) -28- 522558 Α7 Β7 5. Description of the invention (2 since, after forming an interlayer film, flattening, contact and wiring process. (Please read the precautions on the back before filling out this page) (Example 6) Fig. 17 is a cross-sectional structure view of the memory device of Example 6. It is a cross-sectional view with two adjacent memory cells M 1 0 and M 104 driven by the same word line M 100 as the main body. Fig. 18 is a circuit diagram illustrating the connection relationship of the memory array of the sixth embodiment. It actually constitutes a larger-scale array, but for the convenience of explanation, a small-scale grid array of 4 × 4 is shown. The basic structure of the grid is the same as that of the fifth embodiment, and the operation of the grid is also the same. However, depending on the connection relationship of the grid, its cross-sectional structure or manufacturing method is different, and its driving method has characteristics. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The first gate electrode M 100 has the function of a word line, and the second gate electrode M 95 is used as a supplementary control line to form a vertical wiring with the word line M 100. The source region M 9 7 and the drain region M 9 8 are wired in the diffusion layer to extend in a direction parallel to the auxiliary control line M 9 5, and the memory cells are connected in parallel. The drain region M 98 of this memory cell M 103 and the source region M 97 of the adjacent memory cell M 104. Usually, the grids share the source and drain domains in a parallel structure. The grid's drain domain and the adjacent grid's source domains are insulated in the grid separation domain. However, Embodiment 6 does not use a physical formula. Separation, forming a common diffusion layer. Therefore, the area of the grid separation area can be reduced, which is effective for reducing the cost. One characteristic of the operation is that writing and reading are performed every other grid system driven by the same word line. For example, when writing or reading the memory cell M 1 〇3, the auxiliary control line M 9 of the adjacent grids on both sides shall be used. 6. This paper size is applicable to the Chinese National Standard (〇 ^) 8 4 specifications (210 、 / 297mm) -29- 522558 A7 B7 V. Description of the invention (2 $ (Please read the precautions on the back before filling in this page) Μ 1 0 50% low voltage, making the silicon surface under the control line high resistance This prevents short-circuits between the grids driven by the same word line. That is, grids are separated electrically using an auxiliary control line. When performing a write or read operation on the memory grid M 104, the adjacent grids are separated. The auxiliary control line M 95 can be a low voltage. This embodiment is represented by a small-scale grid array of 4 × 4, but when a larger-scale grid array is actually formed, the resistance of the diffusion layer wiring is high, and the voltage effect is effective. Problem. Therefore, it is more effective to make contacts at appropriate intervals and metal lines. At the same time, it is also possible to set a switch between the contact hole with the metal lines, use the diffusion layer wiring as the regional data line, and the metal line as Hierarchical data lines Structure. When adopting a hierarchical structure, the area data lines that are not needed during operation do not need to be charged and discharged, so it is effective for low power consumption and speeding up. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The difference between the manufacturing method and Example 5 is mainly explained below. After forming the grid separation area for the peripheral circuit, and the well structure 'introduces impurities used to adjust the starting voltage under the second gate electrode, the thickness of the surface of the oxidized substrate is 8 After the tunnel oxide film M72 of nm, a polycrystalline silicon film and a Sio2 film for the second gate electrode are deposited, and then processed to form the second gate electrodes M9 5, M9 6. Then use this pattern as a mask, such as As shown by the arrows in the figure, the As ions are driven obliquely to form the diffusion layers M9 7, M9 8 and M9 9 in the source and drain regions. At this time, the impurities used to adjust the initial use under the first gate electrode are also introduced. After the surface of the substrate is oxidized to form a tunnel oxide film μ 72 with a thickness of 8 nm, the silicon microcrystalline particles M 0 1 and M 102 are formed by CVD. Then, S i 02 with a thickness of 4 nm is sequentially formed from below. S i3N4, thickness 4nm This paper size applies to Chinese National Standard (CNS) M specification (21〇χ297 public director) -30- 522558 A7 B7 V. Description of the invention (2 $ (Please read the notes on the back before filling this page) S i〇2 of After the interlayer insulating film M 7 3 with a structure of 0 N 0, n-type polycrystalline silicon is deposited and formed in order to form a first gate electrode, and then planarized. Then, W (tungsten) and Si 0 2 films are deposited, and a resist film is used as a mask. The cover is sequentially etched with a Si 102 film, a W, n-type polycrystalline silicon film to form a first gate electrode and word line M 100. An interlayer film is formed again, and after planarization, a contact process and a wiring process are performed. When using this manufacturing method, silicon micro-junction grains also remain on the auxiliary gate. This may be due to the deterioration of characteristics caused by a short circuit in the memory field between the grids or the capacitance of the auxiliary electrode when the memory field is formed by a continuous polycrystalline silicon film such as flash memory, and because of the existence of the subsidy The step of the electrode is poor, so it is difficult to remove. In the sixth embodiment, it is not removed, and there is no problem in electrical characteristics, so it has a feature that the manufacturing process is simple. (Embodiment 7) Fig. 20 is a sectional structural view of a memory cell of Embodiment 7. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed a gate electrode M 3 of n-type polysilicon and a gate electrode M 2 of the n-type in the P-type well Mila and a control channel. Between the gate electrode M 3 and the substrate, a plurality of fine crystal grains M 4 having an average diameter of 12 nm are arranged. On both sides of the gate electrode M 3, there are sidewall structures M 7 and M 8 made of polycrystalline silicon of p-type, and an insulating film M 1 3 is present between the gate electrode M 3 and the gate electrode M 3. At the same time, there is also an insulating film M14 between the side wall structures M7, M8 and the substrate. In a normal LDD structure, the side wall structures M7 and M8 structures directly below the substrate surface Ml 1, Ml 2 are high-concentration n-types, but this embodiment is a P-type or low-concentration n-type. In addition, the source M1 and drain M2 are in accordance with the Chinese National Standard (CNS) A4 specification (210X 297 mm) " -31-522558 A7 B7_ V. Description of the invention The tungsten layers M 9 and M 10 are connected together. (Please read the precautions on the back before filling out this page.) The Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs prints out the operation of Example 7. Example 7 is by changing storage Where the charge is located, each memory cell memorizes more than 2 bits. Furthermore, in Embodiment 7, the source and drain are adjusted, so the electron does not necessarily flow from the source to the drain, but in order to prevent the name from becoming complicated, The names of the domains are intended to be fixed and these names are used. First, referring to Figure 21 (a), the description will be given of the situation where charges are injected into the memory node M 1 near the source domain M 1. Set the source to 0 V The drain electrode is set to 4 V, and a pulse of 1 2 V is applied to the gate electrode. At this time, the potential of the sidewall M 8 of the drain electrode is also set to 4 V, so the substrate surface Ml 2 below it is inverted to an n-type. On the one hand, The voltage is very low (0 V), and the electron concentration on the substrate surface Ml 1 below is low. As a result, most of the applied drain voltage is added to M 1 1 under the source extreme side wall. The electric field in this part is strong, so Hot electrons. The generated hot electrons are attracted by the electric field formed by the voltage applied to the gate electrode M 3 and injected into the memory node M 1 close to the source M 1. The injection efficiency of this hot electron is higher than the ordinary hot electron injection efficiency. Information can be written without flowing a large drain current. Therefore, writing can be performed in most cells at the same time, and large-capacity memory can be made. At the same time, at this time, in the substrate surface M12 under the sidewall M8 of the drain terminal The electric field in the field Ml 8 near the drain electrode will also become stronger, but since there are no micro crystal grains M 4 in the charge storage field nearby, and the distance from the gate electrode M 3 is also large, no write in the drain terminal will occur. When writing to the memory node M 1 6 at the drain terminal, it is only necessary to adjust the source voltage and the drain voltage. At the same time, during the write operation, a negative basic paper size is applied to the ρ-type well M 1 1 a, which is applicable to China. country Standard (CNS) A4 specification (210X297 mm) -32- 522558 A7 B7___ 5. Description of the invention (3 () (Please read the precautions on the back before filling this page) Board bias (eg -2 V), and relative The method of reducing the gate voltage (for example, to make it 10 V) is more effective. Because the absolute voltage of the gate voltage used can be reduced, in addition to the advantages of a simplified voltage generation circuit, 'the starting voltage will rise, and The characteristic of electric field concentration under the side wall is easy to occur. At this time, if a low-concentration n-type is used under the side wall, the read current can be made larger than that when the P-type is used. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Next, referring to FIG. 21 (b), the reading operation is described as follows. In order to read the information, the transistor composed of the source, the drain, and the gate is operated in the saturation field. To read out the charge injected into the memory node M 1 5 of the source terminal, the drain voltage is 2 V, the source voltage is 0 V, and the gate voltage is 2 V. At this time, a channel M 1 7 will be formed, and the substrate surface under the gate electrode will be pinched off near the drain terminal, so no channel will be formed. As a result, only the stored charge of the source extreme memory node M 1 5 will affect the starting voltage, and the influence of the stored charge of the extreme memory node M 1 6 can be removed. If the source extreme memory node M 1 5 has a large amount of stored charge, the starting voltage will be high, at least the starting voltage will be low. Therefore, the conductance between the source and the drain will vary depending on the amount of stored charge. Based on the difference in voltage caused by this difference in conductance, information can be read. To read the stored charge of the memory node M 1 6 at the drain terminal, it is sufficient to adjust the set voltages of the source and the drain. In this case, the source voltage is set to 0 V when the source extreme information is read, but it is set to a certain voltage (for example, -1 V) lower than the set voltage of the source region when writing. It is effective to reduce the resistance of the surface to increase the read current. In this case, reduce the settings of the gate voltage and drain voltage to IV and IV, for example. In addition, the original paper size can also be applied to the ρ-type well Ml la. Applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) " -33- 522558 Α7 Β7 5. Description of the invention (3 order voltage (for example, -1 V ) And perform the same setting. (Please read the precautions on the back before filling in this page.) Furthermore, when using the above negative substrate bias when writing, use a relatively high substrate bias when reading (eg 0V). The operation method is more effective. The substrate bias when writing λ makes the resistance under the side wall high, and it is easy to generate hot electrons, which can ensure a sufficient read current. As a result, high-speed writing and high-speed reading can be achieved. The above-mentioned writing method and reading method can simply adjust the set voltage of the source and the drain. Therefore, compared with the method of making four levels by injecting the amount of charge injected into a single floating gate, the writing operation and reading There are fewer steps required to perform the action, so it can move at high speed. At the same time, the two ends of the action are two-level actions of information "1" and "0", so the margin of action will also increase the consumption of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. Close In the writing operation, if multi-level is used, it is necessary to highly suppress the spread of the inter-lattice distribution of the starting voltage. Therefore, after the writing pulse is applied, it is read and applied again when the starting voltage is not reached. The so-called verification operation of the write-back pulse operation becomes the main cause of the decrease in the total write amount. Therefore, the effect of the high-speed operation of the seventh embodiment is particularly significant during the writing. In addition, the seventh embodiment has many independent features. The silicon micro crystal grains constituting the memory node can be averaged. As a result, the unevenness between the grids can be reduced, and the operation of 2 bits per memory cell can be performed without confirming the operation. The averaging of writes is related to the cause. Defects in the tunnel insulation film, etc., are also effective in causing some grids to write at abnormally high speeds. The erasure of information is caused by applying a negative voltage to the gate electrode M 3. For example, the source Both the pole M1 and the drain M2 become 0 V, making the gate M 3 -1 2 V. At this time, the injected electrons will be released to the substrate side due to the electric field. The paper size applies the Chinese National Standard (CNS) A4 specification. 210Χ297 mm) -34- 522558 A7 ___. __B7_ V. Explanation of the invention (3 sessions. The erasing action is the source and drain terminals of the whole batch. Furthermore, at this time, the well potential can also be set to a higher potential than 0V (for example, 5 V). The absolute value of the potential of the gate M 3 is set to be small (for example, -7 V). The absolute value of the use voltage is reduced, and the voltage generating circuit is simplified. Fig. 22 shows an equivalent circuit diagram of the seventh embodiment. The marks of the extreme memory node M 1 5 and the extreme memory node M 1 5 are shown in Fig. 22 (a). The source extreme side wall M 7 is used as the gate electrode, and the substrate surface M 11 below it is formed as a channel. Field-effect transistor M 1 9 and a field-effect transistor M 2 0 formed by using the drain side wall M 8 as the gate electrode and the substrate surface M 1 2 below as a channel. However, it corresponds to the substrate of the P-well M 1 1 a The bias terminal is omitted and not shown. In order to avoid complication of the diagram, the equivalent circuit of the memory device shown below uses a simplified representation method of FIG. 22 (b). Next, the manufacturing process of the seventh embodiment will be described. After forming the lattice separation area and triple-well structure, The memory cell formation area of the well is doped with impurity B (boron) ions for voltage adjustment. The substrate surface is oxidized to form a tunnel oxide film M 5 with a thickness of 10 nm, and then silicon microcrystalline particles M 4 are formed by CVD. It is formed at a density of 12 x average diameter of 4 x 1 011 per square centimeter. After forming an interlayer insulating film M 6 having a thickness of 12 nm, n-type polycrystalline silicon for gate electrodes is deposited, and a Si 0 2 film is deposited. With the resist film as a mask, the SiO 2 film and the polycrystalline silicon film were sequentially etched to form a gate electrode. The Si 0 2 film was further etched with the same mask, and the crystal grains were also removed. After removing the anti-etchant , Forming a sacrificial oxide film, injecting impurities, adjusting the size of this paper to apply the Chinese National Standard (CNS) A4 specification (210X297 mm) " ~ -35- i J- -1 »! Ll.  —-I-.  m ϋ (Please read the precautions on the back before filling out this page) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives printed 522558 A7 B7 V. Description of the invention (3 $ (Please read the precautions on the back before filling out this page) The impurity concentration below. After this, oxidation is performed to oxidize the surface of the substrate and the side of the gate electrode. This becomes the insulating film M 1 3 between the side wall M 7 and M 8 structure and the gate electrode M 3. The oxidation on the side of the gate is faster than the oxidation on the substrate surface, and the insulating film is thicker. Then η-type polycrystalline silicon is deposited, and the thickness of this film is etched back to form the sidewall structures M 7, M 8. After that, the sidewall is removed with a resist as a mask The part of polycrystalline silicon that is not expected to be short-circuited. The removal method is performed by equal dry uranium etching, wet etching, or a combination of both. Gates M3, sidewalls M7, and M8 are used as masks to inject As to form a source Poles M1, M2. The substrate surface is exposed with wet uranium engraving, and tungsten (W) is selectively deposited only on silicon. This source region M1 and the source side wall structure M7, and the drain region M2 Distance from drain side wall structure M 8 Short, stacked tungsten can be connected together. Compared with the grid structure of M7, M8, which forms a contact, and the grid structure of the diffusion layers M1, M2 is connected by wiring, the grid area is significantly reduced, and the processing procedure is simple. After that, the interlayer insulation film is deposited, planarized, and wiring is made after the contact manufacturing process. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Example 7 The gate electrode M 3 is made of polycrystalline silicon. It has a multilayer structure to achieve low resistance. At this time, the insulating film between the gate electrode M 3 and the sidewalls M 7 and M 8 is preferably formed by stacking instead of oxidation. The memory node is formed by microcrystalline silicon, but It can also be formed with other semiconductors or metals. At this time, it is important that each node be independent. For the formation method, the seventh embodiment is formed by CVD on the tunnel insulating film, but other deposition methods can also be used. Also, it can be formed After the insulation film with a thickness of more than the tunnel insulation film is inserted into Si, the paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) -36- 522558 A7 B7 V. Description of the invention (34 (Please read the precautions on the back before filling out this page) Ge and other ions, and then heat, so that it will precipitate a lot of tiny crystals in the insulating film to form a memory node. Memory node A film with multiple traps such as Si 3 N 4 film can be used. (Embodiment 8) Figures 23 to 28 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs show the eighth embodiment of the present invention. The memory grid array structure using the memory grid described in Example 7 as the basic structure. Figure 23 is an equivalent circuit diagram, Figure 24 is a layout diagram corresponding to Figure 23, and Figure 25 is from the arrow direction. The structure diagram of the cross section of the range of the word lines M 2 5, M 2 9 and the contact M2 2 adjacent to each other at positions XXV-XXV in Fig. 24. Fig. 26 is viewed from the direction of the arrow. A cross-sectional structure diagram of the range of the grid separation area M 2 6 adjacent to the positions XXV I-XXV I in FIG. 24. The part M 2 3 enclosed by the dotted line in Fig. 23 corresponds to the unit grid. Figure 23 is based on 4 rows and 2 columns, with 8 grid memories and 16 bits. Actually, the number of rows and columns is increased to form a large-scale grid array, but for the sake of convenience, the description will be made on this scale. In addition, the same symbols are assigned to the same components or persons having the same function. The gate electrodes are connected to each other by a word line M 2 5. The zigzag line M 2 5 of this embodiment has a function of a gate electrode. The drain region M 2 7 is shared with the adjacent grid, and is connected to the data line M 2 4 through the contact hole M 2 2 provided for this purpose. Adjacent grids of a common word line are separated by a grid separation area M 2 6. In the source region, the source line M 2 1 is formed by a diffusion layer wiring, and is parallel to the word line. In Example 8, the surface of the diffusion layer is covered with sand or metal. The paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) '~ -37- 522558 Α7 Β7 V. Description of the invention (3 including (please read first Note on the back, fill in this page again) cover, so it has low resistance, and the diffusion layer wiring is also fully practical. Of course, contact holes can be provided everywhere, and metal resistance can be used to further reduce the resistance. At the same time, this implementation The manufacturing process of the example is the same as that of Example 5. At this time, the micro crystal area M 2 8 of the memory node will remain on the grid separation area. If it is a floating gate like a flash memory connection film, it will become a space between adjacent grids. The short circuit of the floating gate does not operate, but the leakage between the memory nodes in Embodiment 8 is small and can be operated. Therefore, the process of cutting off the adjacent floating gate of the flash memory can be omitted, and the manufacturing process can be simplified. Next, the embodiment 8 will be explained. The driving method. Firstly, the writing operation in Fig. 27 will be described. According to the address input from the outside, a signal indicating whether to write to the source, the extreme M 3 0, or the drain M 3 1 is generated. SERECTM36. Corresponds to the generated signal M36 switches the voltage of the source line M 2 1. The input data is stored in the latch M 3 4. Here, the voltage high corresponds to "1", and the voltage 1 0w corresponds to "0". Economy The Ministry of Intellectual Property Bureau employee consumer cooperative prints the source extreme M 3 0 of the grid M 2 3 when the writing action is applied to the source line M 2 1 when VRSS (for example, 0V) is applied. When the information to be written is “〇” , Set the voltage of the data line M 2 4 to VWDL (for example 0V), when the information to be written is "1", set the voltage of the data line M 2 4 to VWD 例如 (for example 5 V), and set the high voltage A pulse of VWW (for example, 12V) is supplied to the word line M2 5. When VWDL is set, hot electrons are hardly generated, so the charge injected into the memory node is very small, and when VWD is set, the amount of charge injected is large. For other grids driven by the same word line, if the voltage of the connected data line is also set to VWDL or VWDH corresponding to the data to be written, the information can be written at the same time. This paper size applies the Chinese National Standard (CNS) Α4 specification (210 × 297) Mm) -38- 522558 Α 7 Β7 V. Description of the invention (3 orders (please read the precautions on the back before filling in this page) Here, "0" will not inject charge when writing, so it is equivalent to not writing, so it can only be on the same word line Part of the driven grid writes information. If the other zigzag lines are set at a voltage VW 0 (for example, 0 V) lower than VWW, there will be no write. Secondly, the write action at the drain terminal M3 1 will be explained. Source The polar line M 2 1 is set to VWD Η (for example, 5 V), and the voltage of the data line M 2 4 is the same as when the source terminal M 3 0 is written. When the information is “0”, it is set to VWDL (for example, 0 V). When the information is "1", set to VWD Η (for example, 5 V). Then, a pulse of a high voltage V W W (e.g., 12 V) is applied to the word line M 2 5 to write. Here, when the source terminal M 3 0 is written, the data line VWD Η is a charge injection condition, but when the drain terminal M 3 1 is written, the data line VWDL is a charge injection condition. Therefore, it is characterized by the memorized information and The corresponding relationship between the starting voltage level and the source voltage side will reverse. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economy First, corresponding to the address of the data to be read from the outside, a signal RSERECT M 35 is generated to indicate whether to read from the source terminal M 30 or to read from the terminal M 3 1. The circuit generating the selection signal R S E R E C T from this address can be shared with the selection signal generating circuit at the time of writing. For the generated signal RERECT M 35, as described below, the source line M2 1 voltage, the precharge voltage, and the reference voltage are switched. To read out the information at the source terminal M 3 0, set the source line M 2 1 to VRSS (for example, 0 V), pre-charge the data line M 2 4 to a higher voltage VPCS (for example, 3 V) than VRSS, and then A read pulse of a voltage VWR (for example, 2 V) is applied to the word line. At this time, if the source paper size is in accordance with the Chinese National Standard (CNS) A4 specifications (210 ×: 297 mm) -39- 522558 Α7 Β7 V. Description of the invention (3) (Please read the precautions on the back before filling this page) Extreme When the initial voltage of M3 0 is high, no current will flow. The potential of the data line M 2 4 will not change much in VPCS, but there will be a large current when the initial voltage of the source terminal M3 〇 is low. The potential of line m2 4 will drop significantly from VPCS. One end of the differential amplifier type sense amplifier M 3 3 is connected to the data line, and the other end M 3 2 is applied with a voltage VREFS (for example, 2 · 4V) that is smaller than VPCS. As a reference voltage, the sense amplifier M 3 3 is caused to operate at a certain timing, thereby amplifying to a high potential when the starting voltage of the source terminal M 3 0 is high, and amplifying to a low potential when it is low. When the starting voltage is low, the voltage of the data line that is set so that the memory cell can operate in the saturation field is better in the high voltage state. That is, the starting voltage when the starting voltage at the source terminal is low is V th, and the data line Higher than VWR-V th The state-start sense amplifier is better. Because it is relatively unaffected by the memory information of the drain terminal M 3 1, it can perform stable operations. The information is read out by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The set voltage is different when the source line M2 1 is set to a higher voltage VRSD (eg 3V) than VRSS, and the data line M2 4 is precharged to a lower voltage VP CD (eg 0V) than VRSD, and then applied to the word line The read pulse of voltage VWR (for example, 2 V). At this time, if the initial voltage of the drain terminal M3 1 is high, there will be no current flowing, and the potential of the data line M 2 4 will not be much at VPCD (0 V). It varies, but when the starting voltage of the drain terminal is low, there will be a large current, and the potential of the data line M 2 4 will rise significantly from VPCD (0V). The reference voltage supplied to the sense amplifier is higher than VPCD (0V ) Large voltage VREFD (such as 0.6V). Make the paper size of the sense amplifier applicable to the Chinese National Standard (CNS) A4 specification (210 ×; 297 mm) -40- 522558 A7 __B7 5. Description of the invention (湳 (please first Read the notes on the back and fill in (Page) M3 3 operates at a certain timing, thereby amplifying to a low potential when the starting voltage of the drain terminal M3 1 is high and to a high potential when it is low. Therefore, the relationship between the amplification result and the starting voltage of each terminal is at the source. The extreme and drain extremes are reversed again, and the correct operation is completed with the above-mentioned writing method. The above-mentioned writing and reading operations are organized into Table 4. [Table 4] The data grid starts to be turned on when external input is input. After reading and zooming out, output to the external information line to set the voltage of the data line. The extremes of the information source voltage “0 ,, (L) VWDL (L) (L) (source extreme) (L)“ 0 ”(L)“ γ (η) VWDH (H) (Η) (Source extreme) (Η) “Γ (Η) Drain extreme memory“ 0 ”(L) VWDL (L) (Η) (Drain extreme) (L)“ 0 ”(L ) "R (H) VWDH (H) (L) (Drain) (Η)" Γ (Η) The erasing action of information is performed in batches on the grids driven by the same word line, while erasing the source and drain Extreme information. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (Embodiment 9) Figures 29 to 36 show a ninth embodiment of the present invention. Figures 29 and 9 show the cross-sectional structure of the memory grid of this embodiment. The basic structure and operation principle of this embodiment are the same as those of Embodiment 7, but the manufacturing method is different. At the same time, the lattice array structure that is easy to construct is different due to different manufacturing methods. The basic architecture is explained first. The paper size of the substrate in the picture applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -41 · 522558 Α7 Β7 V. Description of the invention (required (please read the precautions on the back before filling this page) P well omitted The ρ-type sand substrate provided in the grid separation area M4 4 is provided with an n-type source electrode M3 7 and a drain electrode M3 8 and has a control channel serving as a gate electrode M 3 9 of tungsten serving as a word line. The gate electrode M 3 9 There are many small crystal grains M 4 0 with an average diameter of 8 nm arranged on the substrate. On the side of the gate electrode, there are P-type polycrystalline silicon sidewall structures M 4 6 and M 4 7 and between the gate electrode M 3 9 There is an insulating film M 4 8. At the same time, there is an insulating film M 4 9 between the side wall structure M 4 6 and M 4 7 and the substrate. The substrate surfaces M 4 1 and M 4 2 directly below the side wall structure are different from the ordinary LED structure, Its polarity is different from that of the source M 37 and the drain M 38 domains and is of the p-type. In addition, the source M 37 and the drain M 38 domains and the sidewall structure are connected together by a tungsten layer M 50. Figure 3 0 shows the equivalent power of the memory cell array portion of the memory device using the memory cell of Example 9. Figure. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 31. Figure 34 shows the layout according to the manufacturing process. Figures 3 and 4 showing the final layout are enclosed in dotted lines by XX in a memory cell area. IX-XX The cross section shown in the direction of the arrow at the position of IX corresponds to Figure 29. It is explained here for explanation. It is convenient to represent smaller memory cells, but in reality, there are a large number of cells arranged in the row and column directions. The part M 5 7 enclosed by the dotted line in Fig. 30 is the unit array structure. Source regions M 3 7 and drain regions M 3 8 of most memory cells are connected to each other in a diffusion layer to form regional source lines M 3 7 and M 3 8. The regional source line M 3 7 is connected to one of the source lines M 5 5 and the comprehensive source line M 5 6 via a selection transistor S T 7-S T 9, and the regional source line M 3 8 is selected Transistor S Τ 8-S Τ 1 0 connected to the source line The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) -42- 522558 A7 B7 V. Description of the invention (4b (Please read the back Please fill in this page again) Μ 5 2 2 or any of the comprehensive source lines Μ 5 6. When selecting the transistor ST7, ST8 driving signal line Μ5 4 input mutually inverted signals, so the regional data can be One of the lines is used as the source and the other is used as the drain area. If the input signals of the signal lines M 5 3 and M 5 4 are inverted respectively, they have the opposite function. Compared with the driving method of Embodiment 8, Although a transistor needs to be selected, the source line M 5 2 and M 5 5 and the comprehensive data line M 5 6 have the same set voltage when the source and drain terminals are read out. The source line M 5 2 and M 5 5 can be fixed. It has the advantage of using the potential, so that the voltage switching circuit for driving the source line can be omitted. At the same time, If it is the array structure of Example 9, these selection transistors can be arranged together in most grids driven by the same regional data lines M 3 7 and M 3 8, so it will not increase too much area. Staff of the Intellectual Property Bureau of the Ministry of Economic Affairs The consumer cooperative prints the current direction of the source M 3 0 and the drain M 3 1 and the direction of the word line M 2 5 of Example 8 in a mutually perpendicular relationship, but the array structure of Example 9 is in parallel Orientation. If the manufacturing method of Embodiment 9 is used, as shown in FIG. 29, a structure in which the direction connecting the source region M3 7 and the drain region M3 8 is parallel to the direction of the word line M3 9 can be easily produced. Next, the manufacturing process of Example 9. As shown in Fig. 35 (a), after the formation of the lattice separation area M 4 4 and the triple well structure, the memory cell formation area on the p well is entered to adjust the starting voltage B. (Boron) ions. Figure 31 shows the mask pattern M5 for the grid separation area forming the memory grid array. 8. After sacrificial oxidation of the substrate surface, a 150 nm2 S i 3 N 4 film was deposited with a resist as the resist. Mask to etch Si 3 N 4 film 'to form the paper The dimensions are applicable to Chinese National Standard (CNS) A4 specifications (210X297 mm) -43-522558 A7 B7 V. Description of the invention (4) 1 (Please read the precautions on the back before filling this page) Virtual gate electrode M5 1. Take The dummy gate electrode M5 1 is used as a mask to carry in the impurity. After adjusting the initial voltage under the side wall, the oxide film on the substrate surface is removed and oxidized again, and the insulation film M 5 1 a is stacked to form the side wall M4 6 and M4 7 The next part becomes the insulating film M4 9. Next, a P-type polycrystalline silicon having a thickness of 100 nm was deposited, and then etched back to 120 nm to form a sidewall. At this time, a resist mask is used to simultaneously form a selective transistor gate M59 (Fig. 32). After that, a mask was printed with the anti-uranium agent pattern M63 for the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the etching was performed in an equal manner to remove the excess sidewall. As shown in Figure 35 (b), the dummy gate and sidewalls, and the transistor gate M 59 are used as masks. After arsenic ions are formed to form an n-type diffusion layer, the uranium resist is used as a mask. Dry etching and wet etching expose the substrate surface of the diffusion layer portion of the grid. In this case, choose the diffusion layer of the transistor to leave the insulating film. Thereafter, as shown in FIG. 36 (a), the polycrystalline silicon surface on the surface of the diffusion layer and the sidewall is silicided. The surface of the diffusion layer and the side wall of the lattice part are electrically connected together, but are not connected in the selected transistor part. Then, the insulating film is deposited and CMP is performed to expose the upper surface of the dummy gate. Next, as shown in FIG. 36 (b), the resist pattern M 6 4 is used as a mask to remove S i 3 Ν 4 in the grid portion by wet uranium engraving. In order to form a tunnel insulating film, a thickness of 7 nm is performed. Oxidation. Next, fine silicon crystal grains were formed by the C V D method. The tiny crystals accumulated on the bottom surface of the trench become memory nodes. The portion formed on the side of the trench is not necessary, but it does not need to be removed because it does not affect the initial voltage of the grid. An interlayer insulating film with a thickness of 12 nm is formed as M 4 5 2CVD-S i 〇2 / CVD-S isN4 / CVD-S i 〇2 〇N〇 This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 Mm) -44- 522558 Α7 Β7 V. Description of the invention ((Please read the precautions on the back before filling this page) After the film is constructed, a tungsten film is deposited to form the gate electrode. After planarization, it is buried in the trench portion. The gate electrode is formed in the shape. Next, a contact hole M6 3 for selecting the transistor gate M5 9 and a contact hole M 6 4 for connecting the source line and the diffusion layer are formed. After the W film is deposited, the wiring pattern resist is used as Mask, and process the tungsten film to form word line M 39, source line M 5 2, M55, and select transistor control line M53, M54. At this time, the tungsten etching is etched into the previously formed gate electrode in the deep part, In order to prevent a short circuit between adjacent word lines, an interlayer insulating film is deposited and planarized to form a comprehensive data line and a contact hole M 6 for connection of a diffusion layer. After depositing a metal material, a comprehensive data line M 56 is processed. (Example 10) Employees of Intellectual Property Bureau, Ministry of Economic Affairs Fig. 37 and Fig. 38 printed by Fei Cooperative show the tenth embodiment. The unit memory lattice structure is the same as that of embodiment 9, but the lattice array architecture is different. Fig. 37 is an equivalent circuit diagram and Fig. 38 The layout is different from Example 9. The diffusion layer wiring M 3 7 is connected only to the source line M 6 8, and the diffusion layer wiring M 3 8 is connected only to the comprehensive data line M 56. The connection relationship is different, and it is connected to the comprehensive data line M 5 6 through the selection transistor M 6 5. The characteristic of Example 10 is that the common structures M 3 7 and M 3 are combined using the diffusion layer as in Example 9. 8 in order to reduce the number of contacts, as in Example 8, by driving the source line, there is no need to prepare a lot of effect of selecting a transistor to achieve a small area. The purpose of the selection of the transistor is to comprehensively The data line is electrically cut off from the area data line of the array that has nothing to do with the movement, so as to reduce the stray capacitance, and the writing and reading will be performed. ~ -45- 522558 A7 B7 V. Description of the invention (旄 高(Please read the precautions on the back before filling in this page) (Embodiment 1 1) Figure 39 and Figure 40 show the first embodiment. Figure 39 is the cross-sectional structure of the memory cell, Figure 40 It is an equivalent circuit diagram of the array structure. The grid structure of Example 11 is different from that of Example 10. It has a source M79, a drain M80, an active area M8 1, and a small area of charge storage for most independent semiconductors near the active area. The charge storage area M 8 7, the control electrode M 8 for controlling the potential of the active area M 8 1 and the charge storage area M 8 7, and the control electrode and the insulating film M 90 provided on both side walls of the control electrode, Μ 9 1 Insulated side wall electrode Μ 8 5. It is the same for M 8.6 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The difference is that the source area M 7 9 and the drain area M 80 are not connected to the side wall electrodes M 8 5 and M 86. The side wall electrode potential is supplied separately from the source M 79 and the drain M 80. Because a continuous process to the side wall electrodes is required, more area is required and the process is complicated, but the freedom of the voltage is increased, which can improve the performance of the memory. Especially in the readout operation, in the source-side bit readout operation, a positive voltage can be applied to the voltage in the source region M79 and the source-side sidewall electrode M85, so that the voltage below the source-side sidewall electrode can be reduced. Since the area M 8 2 has a low resistance, the read current increases. As a result, the read operation can be speeded up. The potential of the drain-side sidewall electrode M 86 can also be changed during the bit-side readout operation. Therefore, it is the same. Regarding the lattice structure, only the control lines of the side wall electrodes are added, and the connection relationship of the above embodiment can be used for others. The consideration should be independent in the source-side charge storage area M 8 7 Α and the drain-side charge storage area. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -46-522558 Α7 Β7 V. Description of the invention ( 4) 4 M8 7 B writes information, and marks the equivalent circuit of Example 11 as shown in FIG. 4. (Please read the precautions on the back before filling out this page) (Example 1 2).  Figure 41 and Figure 42 show the twelfth embodiment. Figure 41 is a cross-sectional structure of a memory grid array, and Figure 42 is an equivalent circuit diagram of the array structure. Fig. 41 is equivalent to a cross section parallel to the word line of the oblong portion M 1 1 7 shown by a dotted line in Fig. 42. The structure of the unit grid and the operation principle of the memory above 2 b i t in each grid are the same as those in the embodiment 11. The connection relationship is the same as in Example 6, and the diffusion layer is shared between adjacent cells. The difference from Embodiment 6 is that auxiliary electrodes are provided on both side walls of the gate electrode of the double-word line, and each grid can store 2 b i t or more. The point that writing and reading are performed every other grid driven by the same word line is the same as that of the sixth embodiment. In the grid of M 1 18 in the short ellipse shown by the dashed line in Figure 42. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs for writing. The grids on both sides are made non-conducting using auxiliary electrodes. In this case, each grid has two auxiliary electrodes, but one of them can be brought to a low voltage to achieve a non-conducting state, or both can be brought to a low voltage. In this case, it is better to fix the auxiliary electrode on the diffusion layer side that feeds at least a low voltage. For example, when writing information on the auxiliary electrode M 1 1 2 of the grid of M 1 18, the written data is fed into the diffusion layer M 1 1 9 but at this time, the auxiliary electrode M 1 1 of the adjacent grid fixes its potential. It is better at low voltage. Because the potential of the diffusion layer on the data side changes greatly, but if the potential of the nearby auxiliary electrode is fixed at a lower potential, the potential change near the charge retention area of the adjacent grid can be suppressed, and a more stable memory can be obtained. Keeping this paper standard applicable to Chinese National Standard (CNS) A4 specification (210 ×: 297 mm) -47- 522558 A7 B7 V. Description of the invention (旎. This embodiment is also the same as embodiment 6, for the low resistance of diffusion layer wiring It is more effective to use metal wire for lining or layering the data line structure. (Please read the precautions on the back before filling this page) The manufacturing process is similar to that in Example 5, so only the main points are explained. Different from Example 5. 'In the memory grid area, grid separation between adjacent diffusion layer wirings is not done. Because auxiliary electrodes are used for electrical separation. Form a well area, deposit a conductive material after forming a virtual gate electrode, and etch back to form a lower height than the virtual gate. The side wall is formed by using the dummy gate and the side wall as a mask to inject 'impurities' to form a diffusion layer. Furthermore, a thin insulating film is deposited after the side wall is formed. After etching, the substrate surface is exposed, and the silicide process is performed, and the silicide can be completed without shorting the side wall. After the insulating film is stacked, the silicide is planarized to expose the upper end of the virtual electrode. After the virtual electrode is selectively removed Oxidation is performed to form a tunnel oxide film, and a plurality of memory areas are formed by small particles of metal or semiconductor. After forming an interlayer film of OON film, word line materials are stacked, and a resist pattern is used as a mask to etch, thereby Form a word line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 43 shows the other form of Example 12. It is equivalent to the structure in which the side gates M 1 19 are shared by adjacent grids. However, it is not necessary to form a side wall. Therefore, the manufacturing method is different. Compared with the above structure, because the auxiliary gate can have a larger width, the contact process is easier. Moreover, the number of wiring can be less than that when the two sides of the side wall are independently driven, so it is not necessary to worry too much The wiring pitch can be easily struck by metal wires. In this embodiment, if the auxiliary electrode Ml 19 is set to a low voltage, it is connected adjacently. Each grid becomes non-conducting. Therefore, making one of the three auxiliary electrodes low resistance, and the grid driven by the same word line can make one of the three grids adjacent to each other. The paper size is suitable for China. National Standard (CNS) A4 specification (210X297 mm) _ ^ — -48- 522558 A7 ______ ^ _ B7____ 5. Description of the invention ('(Please read the notes on the back before filling this page). The manufacturing process is in the example During the manufacturing process of the structure shown in Figure 4 of Figure 1, the impurities used to form the diffusion layer were inserted, the side walls were removed, the auxiliary gate electrode material was buried in the trench, and the auxiliary gate electrode was etched back to form the auxiliary gate electrode. Thereafter, the insulating material was formed. It is buried in the trench, and after flattening, it is the same as the manufacturing process of FIG. 41. (Embodiment 1 3) FIGS. 44 to 47 show the thirteenth embodiment. Fig. 44 is a cross-sectional structure of a memory grid array, Fig. 45 is an equivalent circuit diagram of a small-scale array structure, and Figs. 46 and 47 are layout diagrams corresponding to Fig. 45. Fig. 44 is a sectional view perpendicular to the word line direction of the ellipse M 1 30 portion indicated by a dotted line in Fig. 45. Here too, a more practical array structure is used for explanation. Unlike the previous embodiment, the features of embodiment 13 are that the memory cells are connected in series. At the same time, in the cross section of current flow as shown in Fig. 4, there is no diffusion layer between the memory cells connected in series. The series-connected resistors of this structure have a higher resistance, but have the characteristics of a small grid area. When the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints data at one end M 1 2 8 of the grid driven by the word line M 1 2 1, first set the first data line M 1 3 1 at the information to be written. High voltage (for example 5 V) or low voltage (for example 0 V). The second data line Ml 32 is set to 0V. Then, set the word line M 1 2 of the grid to be written and the word lines M 123, M 136, the auxiliary electrodes M 122, and M 135 other than the auxiliary electrodes M 1 2 0 on the write side of the grid to a certain high potential ( For example, 6 · 5 V), make the electrode below the low paper size applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) ~ '-49-522558 A7 _B7 5. Description of the invention (4 > (Please read the Please fill in this page again) Resistance state. The auxiliary electrode M 1 2 0 for writing is set at a lower potential (for example, 2V), so that the substrate surface M 1 2 below it has a higher resistance state. The grid zigzag line When M 1 2 1 is at a higher potential (eg, 12 V) than other word lines, if the first data line M 1 3 1 is set at a high voltage (eg, 5 V), the substrate surface between the auxiliary electrode and the word line Generates hot electrons and injects them into the nearby charge storage area M 1 2 8. The first data line Ml 31 is hardly injected when set to a low voltage. The same word line M 1 is used for charge injection at the other end M 1 2 9 2 1 and the auxiliary electrode M 1 2 2 on the opposite side. This time, the data is fed into the second The data line M 1 3 2 and the first data line M 1 3 1 become 0 V. Except that the direction of the current is reversed, the information is written into the charge storage area M 1 2 by the same operation. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs During the read operation, when the read information is written and the write information is fed to the data on one side of the first data line M 1 3 1, the first data line M 1 3 1 is printed. When writing data to feed the data on one side of the second data line M 1 32, pre-charge the second data line M 1 32 to a positive potential (for example, 2V). In each case, the other end is at 0V. Drive the word lines M 1 2 3 other than the word line M 1 2 3 of the grid to be read out, and the auxiliary electrodes M 1 2 0, M 1 2 2 and M 1 3 5 are set to a high potential (for example, 6 · 5 V ), And a certain read voltage (for example, 3 V) is supplied to the word line M 1 2 1. For example, when the read operation of the first data line M 1 3 1 is precharged, the area M under the word line M 1 2 1 In 1 2 5, a channel is connected to one side of the second data line M 1 3 2 at a lower potential, and the first data line M 1 3 1 side is pinched off, so it will be subject to the second data line M 1 3 2 side. This paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) " '-50- 522558 Α7 Β7 V. Description of the invention (4 has more influence', that is, it is maintained by more M 1 2 8 The effect of information can be read. Embodiment 1 3 uses a method of preparing two data lines to adjust the voltage setting. However, other implementation forms can also be adopted, for example, as shown in FIG. 48, the connection relationship between the data line M138 and the source line M139 is used. When writing on the data line side, the same driving method as that of the eighth embodiment can be used to increase the potential of the source line. When using this connection relationship, it is sufficient to prepare one data line for each row of the serial grid array, which is smaller than the data line interval of the connection relationship in Fig. 45. Therefore, a small memory cell can be realized, which is effective for cost reduction. Together with the layout diagrams of the memory cell arrays in FIGS. 46 and 47, the manufacturing process of Embodiment 13 will be described. After the lattice separation is performed to define the active area M 1 37, the tunnel insulating film, silicon microcrystals, 0 NO interlayer film, word line electrode material, and covering insulating film are stacked. Using the resist as a mask, the cover insulating film, the word line material, the interlayer film, and the silicon microcrystals are etched to form the word lines M 1 36, M 1 2 3, and M 1 2 1. After the surface is oxidized, an insulating film is deposited, and then a supplementary gate electrode material capable of burying a trench formed by word lines is deposited. Once the auxiliary gate electrode material is etched back using a resist mask for the peripheral part, the memory gate is formed by insulatingly adjoining the auxiliary gate electrode. Thereafter, word lines and auxiliary electrodes are used as masks, and n-type impurities are driven into both ends of the active area M 1 37 to be activated. After the interlayer insulating film is formed, contact holes M 1 3 3 and M 1 3 4 are respectively formed at both ends of the active area M 1 3 7 to form a first data line M 1 31 and a second data line M 1 32. The size of this paper applies the Chinese National Standard (CNS) Α4 specification (210 × 297 mm) ί n «l ml! W m: ϋ. ^ m ml n (Please read the notes on the back before filling this page) Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs; τ: -51-522558 A7 ___ __ B7 V. Description of the invention (also (Example 1 4 ) (Please read the precautions on the back before filling in this page) Figure 49 and Figure 50 show the 14th embodiment. Figure 49 is a cross-sectional view and figure 50 is the equivalent of the connection relationship of the grid array Circuit diagram. Partial cross-sectional view of the long dashed ellipse Ml 48 shown in Fig. 50 corresponds to Fig. 49. It is similar to that in Example 13 except that there is no auxiliary electrode. All the parts that become the auxiliary electrode are memories. This point is not the same. The charge storage area M 144 exists in the whole. The area of each memory cell in Example 1 4 is small. Therefore, writing at both ends of the source side and the drain side is not performed as a low cost. The structure is still valid. If combined with the multi-memory of each grid, the cost reduction of the current flash memory can be achieved. At the same time, Example 14 is written at both ends as shown in Figure 50 Make each cell 2b it, but it can also make the injected charge The same place is made of multiple levels based on the amount of charge, and a higher density of memory can also be achieved by the amount of charge and writing at both ends. At the same time, the architecture of the array is the same as the other embodiments of Embodiment 1 (Figure 4-8). ) The same, but it can also have the same connection relationship as in Figure 4 5. The printing and driving method of the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is also the same as the other embodiments of Embodiment 1 (Figure 4 8), but to write When the left side of the paper surface of the grid driven by the word line M 1 41 is used, the left side word line M 1 40 is used in the same manner as the auxiliary electrode M 1 2 0 of Example 13. The same is true when reading. The difference is that Embodiment 13 The part that becomes the auxiliary electrode also becomes a memory cell, and the word line adjacent to the memory cell can be used as an auxiliary electrode for memory and read operations. Specifically, it is characterized by driving the word line M 1 4 1 In the case of memory, the paper size at both ends shall apply the Chinese National Standard (CNS) A4 specification (210 × 297 mm) '_ -52- 522558 Α7 Β7 V. Description of the invention (5b word line Μ 1 4 0, Μ 1 4 1 Use as auxiliary electrode, drive When the memory grid of line M 1 4 2 is used, the word lines M 1 4 1 and M 1 4 3 at both ends are used as auxiliary electrodes. Figure 50 shows the ends M 1 4 7 connected in series to the grid as ordinary Transistor, but the structure can be the same as the memory cell. Because only one side has auxiliary electrodes, two-end writing cannot be performed, but one side can be written, and it can also be used as a memory cell. Manufacturing process. Different adjacent processes are used to manufacture adjacent word lines as its features. After grid separation is performed to define the active area M 1 37, the tunnel insulation film, silicon microcrystals M 1 4 and ONO interlayer film M 1 4 8 are stacked. Η-type polycrystalline silicon and cover insulating film for word line electrode materials. The cover insulating film and the word line material are etched with the resist as a mask to form the word lines M 1 40 and M 1 42. Unlike Example 13, the interlayer film and the silicon microcrystals are not etched. At this time, mild oxidation was performed. The surface of the η-type polycrystalline silicon is oxidized, but the small crystals of silicon or the substrate are protected by the 0 NO interlayer M1 4 8 and are not actually oxidized. It is also possible to use a CVD insulating film instead of oxidation, but the characteristics of the grid driven by the word line may vary due to the amount of thickness of the word line compared to the thickness of the interlayer insulating film, which requires attention. In addition, the word line material having a thickness sufficient to bury the trenches made of the word lines M1 40 and M1 42 is deposited, and the word line material is etched back with an anti-uranium mask for peripheral portions to form the word lines. M 1 4 1, M 1 4 3. Thereafter, it is the same as that in Example 13. (Embodiment 15) FIGS. 51 to 54 show a fifteenth embodiment. Figure 51 is the size of this paper applicable to China National Standards (CNs) Α4 size (210X 297 mm) (Please read the precautions on the back before filling this page) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives -53 -522558 Α7 Β7 V. Description of the invention (5) 1 (Please read the precautions on the back before filling in this page) Sectional view perpendicular to the data line and parallel to the word line. Fig. 52 is an equivalent circuit diagram of a unit structure, and Fig. 53 is an equivalent circuit diagram showing a connection relationship between cells. Fig. 54 is a layout diagram showing the connection relationship and arrangement between the grids. The cross section viewed from the position of L I-L I in the direction of the arrow in Fig. 54 corresponds to Fig. 51. From the circuit diagram, the cross section of the area of the ellipse M 1 66 shown by the dashed line in Fig. 53 corresponds to Fig. 51. The memory grid is formed on the insulating film, for example, on a buried insulating film for grid separation. Due to the layered structure, the source (source line) M 1 4 9 and the drain (drain line) M 1 50 composed of η-type polycrystalline silicon form an up-and-down positional relationship with an insulating film M 1 5 8 in between. . The source M 1 49 and the drain M 150 are connected by the channel layer films M 15 and M 16 of the semiconductor, and the current flows vertically to the substrate. The side of the channel layer film is provided with a charge storage area M 1 5 and M 1 5 composed of a plurality of semiconductor crystal grains independent of each other through a tunnel insulating film M 1 5 6, and an interlayer insulating film M 1 5 7 is interposed. The side of the line is equipped with an auxiliary electrode M 1 2 2. The employee cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints M 1 64 and the word line M 1 5 1 to control a part of each channel layer film. Since this structure uses a three-dimensional structure, the area of the lattice becomes small, which has a great effect on cost reduction. The structure of embodiment 15 can drive two charge storage areas M 1 54 and M 1 5 by one data line M 1 50. That is, write data into one charge storage area, such as M 1 5 4. When reading, the auxiliary electrode M 1 6 3 on the opposite side becomes a low voltage, so that the channel layer film M 1 6 4 near the area becomes Non-conducting state. The auxiliary electrode M 1 5 2 on the writing side can be used as the auxiliary electrode for the writing operation, and the thermal efficiency of the commercial paper can be completed. The paper size is suitable for Guancai County (CNS) A4 specification (21GX297 public director) ~ '-54- 522558 Α7 _ Β7 V. Description of the invention (gold injection. (Please read the precautions on the back before filling out this page) Example 1 5 The auxiliary electrode Ml 49 is used only as an auxiliary electrode for writing and reading, but It is also possible to drive the function of the word line and the auxiliary electrode. For example, when using the auxiliary electrode M 1 5 2 as a word line, the data is first fed in (for example, when “1” is written, it is set to 0V, and “0” is written. The data lines M 1 6 and M 1 50 on both sides are set at 5 V), the source line is set to a high voltage (for example, 5 V), and the auxiliary electrodes M 16 and M 1 5 2 on both sides are set. At a low voltage (for example, ν), the word line M 1 51 is set to a relatively low voltage (for example, 2 V), and a high voltage (for example, 1 1 V) is applied to the auxiliary electrode M 1 5 2 so that the auxiliary electrode can be applied to the auxiliary electrode. In the small dots Ml 6 9 and Ml 5 4 for holding the charges at both ends of Ml 5 2, the auxiliary electrode is laterally adjacent to the word line M 1 5 1 When reading, the word line M 1 51 is set to a high voltage (for example, 4 V), so that the horizontal side of the word line M 1 51 is low resistance, and the auxiliary electrode M 1 5 2 is set to a certain value. The readout voltage (for example, 2.5 V) can be printed. This swapping action is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs as shown more simply in Figure 5-5. It is possible only when the gate electrodes are arranged side by side at a slight interval. A tunnel insulating film M 1 7, a micrograin memory node, and an interlayer film M 1 7 are formed on a P-type silicon substrate M 1 70, and a first gate electrode M 1 71 and a second gate electrode M are formed thereon. 1 7 2. The electrodes can be taken out from both ends by the n-type diffusion layer Ml 3, Ml 7 4. When information is to be written into the memory area M 1 7 under the first gate electrode M 1 7 1, the second 2 The gate electrode M 1 7 2 is used as an auxiliary gate. Conversely, when information is written into the memory area M 1 76 under the second gate electrode M 1 72, the first gate electrode M 1 71 is used as a subsidy. The gate is used. This paper size is applicable to China National Standard (CNS) Α4 specification (210 × 297 mm) -55- 522558 Α7 Β7 i. Description of the invention (sh (please read the back first) Please fill in this page again for attention) To read the information of the memory area M 1 7 5 under the first gate electrode M 1 71, set the second gate electrode M 72 to a high voltage, regardless of writing the second gate electrode What is the information in the memory area M 1 7 under the electrode M 1 72, so that the substrate surface of the second gate electrode M 1 72 becomes a low resistance, and the first electrode M 1 71 becomes a certain readout voltage, and The difference in resistance indicates the initial voltage shift. To read out the memory area under the second gate electrode M 172, the first electrode Ml 71 is set to a high voltage so that the second electrode Ml 72 becomes a constant read voltage. Taking this architecture as a base, it is also possible to adopt the same array architecture as in the second embodiment. The drawing corresponding to Fig. 17 is Fig. 56. In addition to the same memory operation as in Example 2, information can also be written under other auxiliary electrodes M 95, M 96, and the memory density can be increased. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In Example 15, the semiconductor material of the channel M 1 59 and the channel M 1 60 between the source lines remained. Of course, it is okay to add the removal process, but there is no problem in the removal operation. That is, because the source lines set a common potential, leakage of M 1 60 between the source lines will not be a problem, and M 1 59 on the data lines is only connected to different sides of the same data line. Example 15 5 uses n-type polycrystalline silicon to form source lines and data lines. This is too high when compared with metal lines. It is more effective to set up contacts at appropriate lengths, and use the structure of metal data lines for lining. In addition, it is effective to cut the polycrystalline silicon data line M 1 50 at an appropriate length and take a contact via a switch, and the structure of a hierarchical data line connected to a comprehensive data line of metal is also effective. You can also use metal to form the source and data lines and reduce the resistance. At this time, the channel layer films M153, M164, and M149M150 cannot be used in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) at this paper size. 56-522558 A7 B7 V. Description of the invention (5 ^ Γ 碕 Read the notes on the back first填写 Fill in this page again} PN junction, but by fully emptying the channel layer films Ml 5 3 and Ml 6 4, the leakage at the time of cut-off can be suppressed to a very low level. Furthermore, Example 1 5 uses source and insulation The vertical structure of the film and the drain, but the surface of the silicon substrate can also be engraved with uranium to make the same vertical structure as the above data line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the manufacturing process of Example 15 is described next. In the field of lattice separation, n-type polycrystalline silicon, Si 102, n-type polycrystalline silicon, and Si 102 are sequentially stacked, and an etching resist is used as a mask to process the entire batch to form a data line M 1 50 and a source line M 1 4 9 .Intrinsic or weak ρ-type amorphous silicon thin film with a thickness of 8 nm is deposited, and the tunnel insulation film M 1 56 is deposited. This thermal process is used to crystallize the amorphous silicon thin film by CVD. Silicon crystals are formed. Grains, and then stacked interlayer insulation film M 1 57. The n-type polycrystalline silicon of the auxiliary electrode material is deposited in the form of a buried trench on it. The uranium withdrawal is performed to form the auxiliary electrode M 1 5 2 and M 1 6 at the bottom of the trench. An insulating film is deposited on this surface or stacked Then, the word line material is buried in the trench and stacked. The planarization is performed, and the word line material is processed with an anti-etchant as a mask to form the word line M 1 51. Here, there is no word in the side of the data line. There is also a channel layer film in the field of the line, but setting the starting voltage at a higher voltage and turning off when it is normal will not cause any problems. When setting the starting voltage to a lower level, if a word line is used as a mask Further processing of the interlayer film, the tunnel film, and the channel layer film can prevent the leakage of the word line portion. At the same time, the channel layer film can be etched before the auxiliary electrode is formed. Potential method) In each of the above embodiments, it is necessary to generate the reference potential when reading. To use the virtual paper size, apply the Chinese National Standard (CNS) A4 specification (210X 297 mm) -57- 522558 A7 B7 V. Invention Explanation (please read the precautions on the back before filling this page) The method of simulating the grid is more effective. Figure 5 7 shows simplification indicating the potential change of the data line after applying the read word line voltage when using the virtual grid. Figure 5 7 (a) is the source extreme readout, (b) is the drain extreme readout. As shown in the figure, the characteristics of the source extreme readout are not affected by the drain extreme readout, but it is actually slightly Affected. The same is true when the drain terminal is read out. This effect can be substantially avoided by using the virtual grid. Therefore, it is better to use a grid that is lightly written at both ends when the virtual grid is written. For light writing, there are a method of setting the voltage at the time of writing to a lower voltage, a method of shortening the write pulse width supplied to the word line, and a method of setting the data line voltage to a smaller value. Either method can be used. (Memory map) The memory map will be described again. The entire grid driven by the same word line is referred to herein as a sector. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Fig. 58 shows the memory map of the eighth embodiment. The grid driven by the same word line has 8 1 9 2 grids, with 1 6 3 8 4 zigzag lines, which can achieve a memory capacity of 2 5 6 M b. In fact, in addition to these, each word line has tens of bytes of control information used for error correction and the like, but is not shown in the figure. As described in Embodiment 7, when the well potential is changed to perform the erasing operation, a plurality of umbrella regions are used as a group of block units to share the well. Wells in different blocks are electrically separated and can be driven individually. Therefore, the erasure of block units is performed. As a result, the number of wells to be driven is reduced, and the end-to-end stray resistance is also reduced, so that stable operation can be performed at a high speed. The address on the left in the figure is an umbrella. The paper size is applicable to Chinese National Standard (CNS) A4 specifications (210X 297 mm) -58- 522558 A7 B7___ 5. Description of the invention (sb (Please read the precautions on the back before filling this page) ) Shape area address. One grid active extreme memory and drain extreme memory 'so the grid driven by the same word line is assigned two umbrella areas. Embodiment 8 only sequentially allocates umbrella area addresses at the source extreme, The address of the umbrella area is away from the source extreme address. When writing, the writing in the continuous area of the umbrella area is performed sequentially. Therefore, it is not necessary to change the source line potential during writing, and high-speed writing can be performed. For the same reason It can also be read at high speed. On the other hand, the information of different files will be stored in the same grid. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy Delete one party's file. Therefore, the other end of the memory area where the file to be erased is stored must be read out and kept at RAM, etc. Then erase this area and then keep it outside. The information and the information to be rewritten are written. When the above-mentioned block erasing method is adopted, the unit for avoiding the read operation is a block. When the erasing method is not changed, the unit of the umbrella area can be erased. Therefore, other methods described below can also be performed. That is, read the information at the other end of the umbrella area to be rewritten, store it in the scratchpad, erase the umbrella area, and then write back the information at the other end. The writing is performed afterwards. If two registers are prepared for each data line, this avoidance information and rewrite information can be kept in the registers at the same time, so the freedom of the action program can be increased. On the other hand, ' The general erasing action requires several times as long as the reading action, so there is a problem that the repeated erasing action will make the action slower than the above-mentioned way to avoid the outside. Figures 5 and 9 show other memory maps of Embodiment 8. For example, this architecture uses two umbrella regions driven by different source lines as a group as a block. For example, a block paper is formed by the umbrella regions driven by adjacent zigzag lines M 2 5 and M 2 9 Standard applicable to China Standard (CNS) Α4 specification (210 × 297 public directors) -59-522558 Α7 Β7 V. Description of the invention (Please read the notes on the back before filling this page). The allocation of the address of the umbrella area should avoid the source of the same word line The extremes and the drains are written continuously in this order. As a result, during the writing of the drains of one word line (for example, M 2 9), the next word written by the other can be written. The voltage setting of the source line (eg M2 1) of the grid driven by the line (eg M 2 5) is switched to the voltage used for the source extreme writing, and the negative effect of the speed of voltage switching is less than that shown in Figure 5-8. In this method, the frequency of source line switching is high, and the power consumption will be large, but it can constitute a smaller block. When erasing in this unit, the above avoidance action is not required. Furthermore, the explanation here is the management method of the information storage location of the memory using the grids stored at both ends, for example, the explanation of the writing sequence of the address of the umbrella area. Therefore, the allocation of umbrella areas, blocks, addresses, etc. is not necessarily the case. At the same time, the distribution method uses software such as distribution management. It is also possible to change the distribution method during use. In the fourth embodiment, after the source extremes in the same block are sequentially assigned the umbrella area numbers, they are continuously assigned to the drain extremes (refer to Figure 58). In the fourth embodiment, a plurality of digital lines for driving data lines in a unit area are used as a group, and the entire grid driven by these groups of zigzag lines is called a block. Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. When the writing sequence is also in this order, continuous data can be stored at the source and drain ends of the same block. Therefore, the avoidance action when the block is not erased is also acceptable. In the writing operation, the switching action of the active extreme and the drain extreme is performed. However, since the switching in Embodiment 4 is faster than that in Embodiment 8, this driving is useful. Alternatively, a driving method in which source and drain terminals of the same word line are continuously driven may be used. The power consumption of the charging and discharging part of the regional source line will increase, and the time will be slowed by the switching action. However, because this paper can be used, the Chinese National Standard (CNS) A4 specification (210X297 mm) -60- 522558 A7 B7 V. Description of the invention (Erased and written by word line units, so it is particularly effective when the scale of the processed data is small. (Please read the precautions on the back before filling this page). Moreover, in Example 9, it is Take the multiple digital lines that drive the unit area data lines as a group, and the entire grid driven by these groups of zigzag lines is called a block. Embodiment 9 assigns the umbrella region numbers in sequence to the source extremes in the same block. After that, it is continuously assigned to the drain terminal (refer to Figure 60). When the writing sequence is also in this order, continuous data can be stored in the source terminal and drain terminal of the same block. Therefore, it is not necessary to erase the block. The avoidance action is also possible. In the write action, the switching action of the active extreme and the drain extreme is performed, but this embodiment is more suitable for this driving because the switching is faster than that of the embodiment 8. In addition, the same word is continuously used The driving method of the driving source extreme and the drain extreme can also be written. The power consumption of the charge / discharge part of the regional source line will increase, and the time will be slowed by the switching operation. However, because the word line unit can be erased, Write, so it is particularly effective when the size of the data unit processed is small. At the same time as printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, Example 10 also has a regional data line structure, so the block definition is the same as that of Example 9. The grid driving method of Embodiment 10 is similar to that of Embodiment 8, but the portion where the selection transistor connected to the data line of the area that does not include the target grid for writing and reading is turned off is different. At the same time, it is used The memory of the memory cell of this embodiment, the management method of the memory location described below is also different from that of embodiment 8. This method is particularly suitable for files with a unit size of more than 1,000 KB, such as photography with a digital camera. Scale, and the file size is generally neat. First, input the signal of the specified unit file size from the outside. Write to the file. This paper size is applicable. National Standard (CNS) A4 specification (210X297 mm) '522558 A7 B7 V. Invention description (sb (Please read the precautions on the back before filling this page)' Do not reverse the source extremes of each soldering area of the memory or draw Extreme, and use most blocks for writing. For example, only source extremes are written. This majority number of blocks' can store the number of previously entered file sizes with the capacity of the source extremes and drain extremes combined. Then the mode is Switch to the other end for writing and perform the remaining writing. As a result, it is only necessary to erase most of the above-mentioned blocks when erasing the file. Similar to the embodiment 9, there is a feature that no avoidance action is required. According to the present invention, it is possible to A low-cost semiconductor memory device is required that can be read at high speed, or a lattice structure that can ensure reliability and achieve vertical calibration can be provided on the one hand. At the same time, it can provide a method that can increase the memory information of each grid without greatly reducing the performance of the grid. Furthermore, a method for realizing a large-capacity memory device by using such a grid can be provided. Brief Description of the Drawings Fig. 1 is a layout diagram of the semiconductor device of the first embodiment. Fig. 2 is a cross-sectional view of the semiconductor device viewed from the I I-I I position in Fig. 1 in the direction of the arrow. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 3 is a cross-sectional view of the semiconductor device viewed from the I I I-I I I position in Figure 1 in the direction of the arrow. Fig. 4 is a diagram showing the marks of the memory cell of the first embodiment on the corresponding circuit diagram. FIG. 5 is an equivalent circuit diagram of the semiconductor device of the first embodiment. Fig. 6 is a diagram showing a reading principle of a memory method of 2 b i t or more in each grid of the second embodiment. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -62- 522558 A7 B7 V. Description of the invention (6b Figure 7 shows the writing operation of the second embodiment including the driving of the peripheral circuit. Figure. (Please read the precautions on the back before filling out this page) Figure 8 is a diagram of the readout operation of the second embodiment including the driving circuit of the peripheral circuit. Figure 9 is the layout of the semiconductor device of the second embodiment. Fig. 10 is a cross-sectional view of the semiconductor memory device viewed from the X-X position in Fig. 9 to the arrow direction. Fig. 11 is a semiconductor memory viewed from the XI-XI position in Fig. 9 to the arrow direction. Sectional view of the device. Fig. 12 is an equivalent circuit diagram of the memory array of Embodiment 3. Fig. 13 is an equivalent circuit diagram of the memory array of Embodiment 4. Fig. 14 is from Fig. 16 Cross-sectional structure diagram of the semiconductor memory cell of Example 5 viewed from the direction of the XI V-XIV position in the direction of the arrow. Figure 15 is an equivalent circuit diagram of the semiconductor memory cell corresponding to Example 5. Figure 16 is the fifth embodiment Layout drawing of semiconductor memory cell. Member of Intellectual Property Bureau, Ministry of Economic Affairs Figure 17 printed by a consumer cooperative is a cross-sectional structure view of a zigzag parallel plane of a memory cell portion of the semiconductor device of the sixth embodiment. Figure 18 illustrates the connection relationship of the memory cell portion of the semiconductor device of the sixth embodiment. FIG. 19 is a cross-sectional structure diagram of a zigzag parallel plane explaining the manufacturing process of the memory cell portion of the semiconductor device of Embodiment 6. FIG. 20 is a cross-sectional structure diagram of the semiconductor memory cell of Embodiment 7. 2 1 Figures (a) and (b) illustrate the paper size of the semiconductor notebook in Example 7 and apply the Chinese National Standard (CNS) A4 specifications (210, 〆297 mm) -63- 522558 A7 B7

五、發明説明（A 憶格之寫入動作、讀出動作用之截面構造圖。 第2 2圖（a) 、（b)係明不實施例7之半導體言己 (請先閲讀背面之注意事項再填寫本頁) 憶格之側壁形成之電晶體構造之等效電路、其簡圖之等效 電路圖。 第2 3圖係表示使用實施例7之半導體記憶格之記憶 格陣列之連接關係之等效電路圖。 第2 4圖係實施例7之對應第2 3圖之布置圖。 第2 5圖係實施例8之半導體裝置之記憶格之資料線 平行、字線截面方向之相鄰接兩格子之截面圖。 第2 6圖係實施例8之半導體裝置之記憶格之資料線 截面、字線平行方向之格子之截面圖。 第2 7圖係說明實施例8之半導體裝置之寫入動作用 之電路架構圖。 第2 8圖係說明實施例8之半導體裝置之讀出動作用 之電路架構圖。 第2 9圖係從第3 4圖之XX I X - XX I X位置向 箭頭方向所視之實施例9之半導體記憶格之截面構造圖。 經濟部智慧財產局員工消費合作社印製 第3 0圖係表示使用實施例9之半導體記憶格構成之 記憶格陣列之連接關係之等效電路圖。 第3 1圖係說明實施例9之半導體記憶格之製造過程 用之製造途中之記憶格陣列之布置圖。 第3 2圖係說明實施例9之半導體記憶格之製造過程 用之製造途中之記憶格陣列之布置圖。 第3 3圖係說明實施例9之半導體記憶格之製造過程 本紙張尺度適用中國國家標準（cns ) A4規格（2丨〇><297公釐) -64- 522558 A7 B7 五、發明説明（企 用之製造途中之記憶格陣列之布置圖。 (請先閱讀背面之注意事項再填寫本頁) 第3 4圖係說明實施例9之半導體記憶格之製造過程 用之記憶格陣列之布置圖。 第3 5圖係說明實施例9之半導體記憶格之製造過程 之一部分之截面圖。 第3 6圖係說明實施例9之半導體記憶格之製造過程 之接下之一部分之截面圖。 第3 7圖係對應實施例1 0之半導體裝置之記憶格陣 列之架構之等效電路圖。 第3 8圖係表示對應第3 7圖之實施例1 0之半導體 裝置之記憶格陣列之架構之布置圖。 第3 9圖係實施例1 1之半導體記憶格之資料線截面 之截面構造圖。 第4 0圖係對應實施例1 1之半導體記憶格之等效電 路圖。 第4 1圖係實施例1 2之半導體裝置之記憶格陣列部 分之字線平行面之截面構造圖。 經濟部智慧財產局員工消費合作社印製 第4 2圖係說明實施例1 2之半導體裝置之記憶格部 分之連接關係之等效電路圖。 第4 3圖係實施例1 2之其他實施形態之半導體裝置 之記憶格陣列部分之字線平行面之截面構造圖。 第4 4圖係實施例1 3之半導體裝置之記憶格陣列部 分之字線平行面之截面圖。 第4 5圖係說明實施例1 3之半導體裝置之記憶格部 ^紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） ' -65- 522558 A7 _ B7____ 五、發明説明（eb 分之連接關係之等效電路圖。 第4 6圖係說明實施例1 3之半導體裝置之製造過程 (請先閲讀背面之注意事項再填寫本頁) 之一部分之對應第4 5圖部分之布置圖。 第4 7圖係說明實施例1 3之半導體裝置之製造過程 之接下一部分之對應第4 5圖部分之布置圖。 第4 8圖係說明實施例1 3之其他實施形態之半導體 裝置之記憶格陣列部分之連接關係之等效電路圖。 第4 9圖係實施例1 4之半導體裝置之記憶格陣列部 分之讀出電流平行面、字線截面方向之截面構造圖。 第5 0圖係說明實施例1 4之半導體裝置之記憶格陣 列部分之連接關係之等效電路圖。 第5 1圖係實施例1 5之半導體裝置之記憶格陣列部 分之布置之從第5 4圖中之L I - L I位置向箭頭方向所 視之截面構造圖。 第5 2圖係對應實施例1 5之半導體記憶格之等效電 路圖。 經濟部智慧財產局員工消費合作社印製 第5 3圖係說明實施例1 5之半導體裝置之記憶格陣 列部分之連接關係之等效電路圖。 第5 4圖係表示實施例1 5之半導體裝設之記憶格陣 列部分之布置圖。 第5 5圖係實施例1 5之其他實施形態之半導體記憶 格之截面構造圖。 第5 6圖係實施例1 5之其他實施形態之半導體裝置 之記憶格部分之字線平行面、資料線截面方向之截面構造 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -66 - 522558 A7 B7V. Description of the Invention (A cross-section structure diagram of the write operation and read operation of the memory. Figure 22 (a), (b) shows the semiconductor language of the seventh embodiment (please read the note on the back first) Please fill in this page again) The equivalent circuit of the transistor structure formed on the side wall of the memory cell, and the equivalent circuit diagram of its simplified diagram. Figures 2 and 3 show the connection relationship of the memory cell array using the semiconductor memory cell of Example 7. Equivalent circuit diagrams. Fig. 24 is a layout diagram corresponding to Fig. 23 of Embodiment 7. Fig. 25 is a data line of the memory cell of the semiconductor device of Embodiment 8 being parallel and adjacent to each other in the direction of the cross section of the word line. Sectional view of a grid. Figures 2 and 6 are cross-sectional views of the data line and word line parallel to the memory line of the semiconductor device of the eighth embodiment. Figures 27 and 7 illustrate the writing operation of the semiconductor device of the eighth embodiment. The diagram of the circuit structure used. Figures 2 to 8 are diagrams illustrating the readout operation of the semiconductor device of the eighth embodiment. Figures 9 to 9 are viewed from the positions XX IX-XX IX in Figure 3 to the arrow direction Cross-sectional structure of the semiconductor memory cell of Example 9. Printed by the Employees' Cooperative of the Ministry of Economics and Intellectual Property of Japan. Figure 30 is an equivalent circuit diagram showing the connection relationship of a memory cell array using the semiconductor memory cell of Example 9. Figure 31 illustrates the semiconductor memory cell of Example 9. The layout diagram of the memory cell array in the manufacturing process used in the manufacturing process. Figure 3 2 is a layout diagram illustrating the memory cell array in the manufacturing process used in the manufacturing process of the semiconductor memory cell in Embodiment 9. Figure 3 3 illustrates the implementation The manufacturing process of the semiconductor memory cell of Example 9 The paper size is applicable to the Chinese national standard (cns) A4 specification (2 丨 〇 > < 297 mm) -64- 522558 A7 B7 V. Description of the invention (in the manufacturing process of the enterprise Layout of the memory cell array. (Please read the precautions on the back before filling out this page.) Figures 3 and 4 are layouts of the memory cell arrays used to explain the manufacturing process of the semiconductor memory cell of Example 9. Figures 3 and 5 are A cross-sectional view illustrating a part of the manufacturing process of the semiconductor memory cell of Embodiment 9. FIGS. 3 to 6 are cross-sectional views illustrating the next part of the manufacturing process of the semiconductor memory cell of Embodiment 9. Section 3 7 The figure is an equivalent circuit diagram of the structure of the memory cell array corresponding to the semiconductor device of Embodiment 10. Fig. 38 is a layout diagram showing the structure of the memory cell array of the semiconductor device according to Embodiment 10 of Fig. 37. Fig. 39 is a cross-sectional structure diagram of the data line section of the semiconductor memory cell of Embodiment 11. Fig. 40 is an equivalent circuit diagram of the semiconductor memory cell corresponding to Embodiment 11. Fig. 41 is Embodiment 1 2 Cross-section structure diagram of the parallel plane of the word line of the memory cell array portion of the semiconductor device. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 4 2 illustrates the connection relationship of the memory cell portion of the semiconductor device of Example 12 Effective circuit diagram. Fig. 43 is a cross-sectional structure view of the word line parallel plane of the memory cell array portion of the semiconductor device of the other embodiments of Embodiment 12; Fig. 44 is a cross-sectional view of a parallel plane of a word line of a memory cell array portion of the semiconductor device of Embodiment 13; Figures 4 and 5 illustrate the memory cells of the semiconductor device of Example 1 ^ The paper size applies the Chinese National Standard (CNS) A4 specification (210 × 297 mm) '-65- 522558 A7 _ B7____ V. Description of the invention (in eb points) The equivalent circuit diagram of the connection relationship. Figures 4 and 6 are layout diagrams corresponding to Figures 4 and 5 as part of the semiconductor device manufacturing process of Example 13 (please read the precautions on the back before filling this page). Fig. 4 is a layout diagram corresponding to the next part of Fig. 4 for explaining the manufacturing process of the semiconductor device of Embodiment 1 3. Fig. 4 is a diagram illustrating a memory cell of the semiconductor device of the other embodiments of Embodiment 1 3 The equivalent circuit diagram of the connection relationship of the array part. Figures 4 and 9 are cross-sectional structural diagrams of the read current parallel plane and the word line cross-sectional direction of the memory cell array part of the semiconductor device of Example 14 in Example 14. Figure 50 illustrates the implementation The equivalent circuit diagram of the connection relationship of the memory cell array portion of the semiconductor device of Example 14 is shown in FIG. 51. FIG. 51 is the arrangement of the memory cell array portion of the semiconductor device of Example 15 from LI to LI in FIG. 54. The cross-section structure view viewed from the direction of the arrow. Figure 5 2 is the equivalent circuit diagram of the semiconductor memory cell corresponding to Example 15. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 5 illustrates Example 1 5 The equivalent circuit diagram of the connection relationship of the memory cell array portion of the semiconductor device. Fig. 54 is a layout diagram of the memory cell array portion of the semiconductor device of the embodiment 15. Fig. 55 is the other of the embodiment 15 Cross-section structure diagram of the semiconductor memory cell of the embodiment. Figures 5 and 6 are cross-sectional structures of parallel lines and data line cross-sections of the memory cell portion of the semiconductor device of the other embodiments of Embodiment 15 of this paper. Standard (CNS) A4 size (210X 297 mm) -66-522558 A7 B7

五、發明説明（A 圖。 (請先閲讀背面之注意事項再填寫本頁) 第5 7圖係表示實施例8之半導體裝置之讀出動作時 之電位變化之模型圖。 第5 8圖係表示實施例8之半導體裝置之記憶圖之例 子之圖。 第5 9圖係表示實施例8之半導體裝置之記憶圖之例 子之圖。 第6 0圖係表示實施例9之半導體裝置之記憶圖之例 子之圖。 經濟部智慧財產局員工消費合作社印製 主要元件對照表 J 1 :主動領域 J 2 : η型多晶矽之字線 J 3 :源極線 J 4 :資料線 J 5 :資料線接點 J 6 :最小記憶單位 J 7 : η型之源極領域 J 7 Α〜J 7 C :源極領域之構成要素 J 8 :汲極領域 J 8 A〜J 8 C :汲極領域之構成要素 J 9 :絕緣膜 J 1 0 :微小結晶粒 J 1 1 : Ο N〇構造之絕緣膜 本紙張尺度適用中國國家標準（CNs ) A4規格（210X297公釐） 67- 522558 A7 B7 五、發明説明（全 J12、J13:電荷儲存領域 J 1 4〜J 1 6 :絕緣層 J 1 7 :格子分離領域 J 1 8 :電荷儲存領域 J 2 0 :選擇記憶格 J 2 1、J 2 2、J 2 3 :非選擇記憶格 J 2 4、J 2 5 :字線 J 4 0 :指示是要進行源極端寫入或汲極端寫入之信號 W S E R E C T J 4 1 :源極線 VWSS、VWSD :源極線J 4 1之電壓 J 4 2 :閂鎖 J 4 3 ··格子 J 4 4 :資料線 J 4 5 :字線 VWDL、VWDH、VWW、VWO :有關寫入動作之 電壓 J 5 0 :指示是要進行源極端讀出或汲極端讀出之信號V. Description of the invention (Figure A. (Please read the precautions on the back before filling out this page) Figures 5 and 7 are model diagrams showing potential changes during the read operation of the semiconductor device of Example 8. Figure 5 and 8 Fig. 5 is a diagram showing an example of a memory map of the semiconductor device of the eighth embodiment. Figs. 5 to 9 are diagrams showing an example of a memory map of the semiconductor device of the eighth embodiment. Fig. 60 is a memory diagram of the semiconductor device of the ninth embodiment. An example of the diagram. The comparison table of the main components printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs J 1: Active field J 2: η-type polycrystalline silicon zigzag line J 3: Source line J 4: Data line J 5: Data line connection Point J 6: Minimum memory unit J 7: η-type source field J 7 Α ~ J 7 C: Source field components J 8: Drain field J 8 A ~ J 8 C: Drain field J 9: Insulating film J 1 0: Fine crystal grains J 1 1: 〇 N〇 Insulating film of structure This paper is applicable to Chinese National Standards (CNs) A4 specification (210X297 mm) 67- 522558 A7 B7 V. Description of the invention ( All J12, J13: charge storage area J 1 4 to J 1 6: insulation layer J 1 7: grid division Off field J 1 8: charge storage field J 2 0: selected memory cell J 2 1, J 2 2, J 2 3: non-selected memory cell J 2 4, J 2 5: word line J 4 0: indication is to be performed Source terminal write signal or sink terminal write signal WSERECTJ 4 1: source line VWSS, VWSD: source line J 4 1 voltage J 4 2: latch J 4 3 · grid J 4 4: data line J 4 5: Word lines VWDL, VWDH, VWW, VWO: Voltages related to the write operation J 5 0: Signals indicating that source or drain readout is to be performed

R S E R E C T VRSS、VESD :源極線J41之電壓 J 5 1 :源極線 J 5 2 :資料線 VPCS、VRSD、VWR :有關讀出動作之電壓 J 5 4 :差動放大型之感測放大器 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ]r[—— (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 -68- 522558 A7 B7 五、發明説明（也J 5 5 :感測放大器之其他輸入線 V R E F S、V R E F D :感測放大器之參照電位 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） -69-RSERECT VRSS, VESD: Voltage of source line J41 J 5 1: Source line J 5 2: Data line VPCS, VRSD, VWR: Voltage of readout operation J 5 4: Differential amplifier type sense amplifier This paper Standards are applicable to China National Standard (CNS) A4 specifications (210X297 mm)] r [—— (Please read the notes on the back before filling out this page) Order printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economics-68- 522558 A7 B7 V. Description of the invention (also J 5 5: Other input lines of the sense amplifier VREFS, VREFD: Reference potential of the sense amplifier (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 specification (210 × 297 mm) -69-

Claims (1)

522558 A8 B8 C8 D8 六、申請專利範圍 ….522558 A8 B8 C8 D8 6. Scope of patent application ... 附件1:第901 1 9678號專利申請案丨%^月 中文申請專利範圍修正本 ~ (請先閲讀背面之注意事項再填寫本頁) 民國91年10月16日修正 1·一種半導體記憶裝置， 係具有源極領域、汲極領域， 上述源極領域及汲極領域由半導體構成之通道領域連 接在一起， 並備有控制上述通道領域之電位之金屬或半導體構成 之聞電極， 而在上述通道領域近旁，將備有多數電荷儲存領域之 半導體記憶元件排成陣列狀之記憶格陣列，其特徵在於’ 第1半導體記憶元件與鄰接之第2格子（c e 1 1 ) 共用源極領域。 2.—種半導體記憶裝置， 係具有源極領域、汲極領域， 經濟部智慧財產局員工消費合作社印製 上述源極領域及汲極領域由半導體構成之通道領域連 接在一起， 並備有控制上述通道領域之電位之金屬或半導體構成 之閘電極， 而在上述通道領域近旁，將備有多數電荷儲存領域之 半導體記憶元件排成陣列狀之記憶格陣列’其特徵在於’ 第1半導體記憶元件與鄰接之第2格子共用源極領域 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 522558 A8 B8 C8 D8____ 六、申請專利範圍 第2半導體記憶元件與鄰接之第3格子共用汲極領域 〇 3.—種半導體記憶裝置， 係具有源極領域、汲極領域， 上述源極領域及汲極領域由半導體構成之通道領域連 接在一起， 並備有控制上述通道領域之電位之金屬或半導體構成 之閘電極， 而在上述通道領域近旁，將備有多數電荷儲存領域之 半導體記憶元件排成陣列狀，其特徵在於， 上述記憶格陣列之元件分離領域之布置實質上呈相互 平行排列之長方形， 連接上述半導體記憶元件之閘電極之字線之布置實質 上呈相互平行排列之長方形， 上述半導體記憶元件具有僅與相鄰接之1個格子共用 源極領域之擴散層之架構， . 上述半導體記憶元件之源極線係由擴散層配線或金屬 配線將3格子以上相互連接在一起， 上述相互平行排列之長方形之元件分離領域，及上述 相互平行排列之長方形之擴散層實質上成平行，且上述相 互平行排列之長方形之元件分離領域，及上述相互平行排 列之字線實質上成相互垂直之位置關係。 4 . 一種半導體記憶裝置， 係具有源極領域、汲極領域， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） —：—一-----Φ------ir------Awl (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -2- 522558 A8 Β8 C8 D8 々、申請專利範圍 上述源極領域及汲極領域由半導體構成之通道領域連 接在一起， 並備有控制上述通道領域之電位之金屬或半導體構成 之閘電極， 而在上述通道領域近旁，將備有多數電荷儲存領域之 半導體記憶元件排成陣列狀，其特徵在於， 上述記憶格陣列之元件分離領域之布置實質上呈相互 平行排列之長方形， 連接上述半導體記憶元件之閘電極之字線實質上呈相 互平行排列之長方形， 上述半導體記憶元件具有多數源極領域經由擴散層相 互連接在一起之架構， 連接上述多數源極領域之擴散層之布置實質上呈相互 平行排列之長方形， · 上述相互平行排列之長方形之元件分離領域，及上述 相互平行排列之長方形之擴散層實質上成平行，且上述相 互平行排列之長方形之元件分離領域，及上述相互平行排 列之字線實質上成相互垂直之位置關係。 5 . —種半導體記憶元件，其特徵在於， 具有由半導體構成之通道領域， 在上述通道領域近旁有多數電荷儲存領域， 具有用以控制上述通道領域及上述多數電荷儲存領域 之電位之金屬或半導體構成之第1閘電極， 並具有用以控制與半導體表面之上述通道領域不同^ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I I >1 —1. I i I I ... _ (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 522558 A8 Β8 C8 D8 六、申請專利範圍 分之電位之金屬或半導體構成之第2閘電極。 6 . —種半導體記憶元件，其特徵在於， (請先閲讀背面之注意事項再填寫本頁) 具有源極領域、汲極領域， 上述源極領域及汲極領域由半導體構成之通道領域連 接在一起， 在上述通道領域近旁備有多數電荷儲存領域， 具有用以控制上述通道領域之一部分及上述多數電荷 儲存領域之電位之金屬或半導體構成之第1閘電極， 並具有用以控制與上述通道領域之一部分不相同之通 道領域之一部分之電位之金屬或半導體構成之第2閘電極 0 7 . —種半導體記憶元件，其特徵在於， 具有源極領域、汲極領域， 上述源極領域及汲極領域由半導體構成之通道領域連· 接在一起， 具有用以控制上述通道領域之電位之金屬或半導體構 成之閘電極， 經濟部智慧財產局員工消費合作社印製 在上述通道領域近旁備有多數電荷儲存領域， 在上述閘極領域之兩側之側面有半導體或金屬構成之 側壁構造， 在上述側壁構造與上述閘電極之間有絕緣膜' 8 .如申請專利範圍第7項之半導體記憶元件’其中 ，上述閘電極兩側之側壁構造中，近源極領域之一方連接 在源極領域，近汲極領域之一方連接在汲極。 I紙張尺度適用中國國家標準（CNS ) A4規格(210X297公釐） -4 - 522558 A8 B8 C8 D8__ 六、申請專利範圍 (請先閲讀背面之注意事項再填寫本頁) 9 ·如申請專利範圍第8項之半導體記憶元件，其中 ，上述側壁構造與源極領域或汲極領域，由選擇性堆積在 側壁構造及源極領域或汲極領域上之金屬或半導體連接在 一起。 1 〇 · —種半導體記憶裝置，其特徵在於， 在排列多個申請專利範圍第5項至第9項中任一項之 半導體記憶元件， 由資料線及字線驅動之記憶格陣列， 多數半導體記憶元件之汲極領域連接在同一資料線， 上述汲極領域連接在同一資料線之多數半導體記憶元 件之第2閘電極相互連接在一起， 上述源極領域連接在同一資料線之多數半導體記憶元 件之第1閘電極連接在互異之字線。 1 1 . 一種半導體記憶裝置，其特徵在於， 在排列多個申請專利範圍第5項之半導體記憶元件之 記憶格陣列， 經濟部智慧財產局員工消費合作社印製 第1半導體記憶元件與第2半導體記憶元件被連接成 通道電流串聯流通， 在第1半導體記憶元件之第1閘電極之兩側中， 第2半導體記憶元件之第2閘電極配置在與第1半導 體記憶元件之第2閘電極相反之一側。 1 2 · —種半導體記憶裝置，其特徵在於， 具有由半導體構成之通道領域， 在上述通道領域近旁有多數電荷儲存領域， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） " 522558 A8 B8 C8 D8 六、申請專利範圍 具有用以控制上述通道領域及上述多數電荷儲存領域 之電位之金屬或半導體構成之第1閘電極， 並具有用以控制與半導體表面之上述通道領域不相同 部分之電位之金屬或半導體構成之第2閘電極， 包含，鄰接於半導體表面之上述通道領域，用以控制 與上述第2閘電極相反側部分之電位之金屬或半導體構成 之第3閘電極之構造。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） -6-Attachment 1: Patent Application No. 901 1 9678 丨% ^ Chinese version of the revised patent application scope ~ (Please read the precautions on the back before filling out this page) October 16, 1991 Amendment 1. A semiconductor memory device, It has a source field and a drain field. The source field and the drain field are connected together by a channel field composed of a semiconductor, and are provided with a smell electrode composed of a metal or a semiconductor that controls the potential of the channel field. Near the field, a memory cell array in which semiconductor memory elements having most charge storage fields are arranged in an array is characterized in that the first semiconductor memory element and an adjacent second cell (ce 1 1) share a source region. 2. A kind of semiconductor memory device, which has a source field and a drain field, printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the source field and the drain field are composed of semiconductor channels, and are controlled. A gate electrode composed of a metal or a semiconductor having a potential in the above-mentioned channel field, and in the vicinity of the above-mentioned channel field, a memory cell array in which a plurality of semiconductor memory elements in the charge storage field are arranged in an array is characterized by a first semiconductor memory element Share the source area with the adjacent second grid. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 522558 A8 B8 C8 D8____ VI. Patent application scope The second semiconductor memory element and the adjacent third grid share the same data. Electrode field 03. A semiconductor memory device having a source field and a drain field, the source field and the channel field composed of semiconductors are connected together, and a metal controlling the potential of the channel field is provided. Or semiconductor-made gate electrodes, and near the channel area, The semiconductor memory elements provided in most charge storage fields are arranged in an array, and are characterized in that the arrangement of the element separation fields of the memory cell array is substantially rectangular parallel to each other, and the word lines connecting the gate electrodes of the semiconductor memory elements are arranged. The arrangement is substantially rectangular parallel to each other. The above-mentioned semiconductor memory element has a structure in which a diffusion layer in the source region is shared with only one adjacent grid. The source lines of the above-mentioned semiconductor memory element are formed by diffusion layer wiring or metal. The wiring connects more than 3 grids to each other, the rectangular element separation areas arranged in parallel with each other, and the rectangular diffusion layers arranged in parallel with each other are substantially parallel, and the rectangular element separation areas arranged in parallel with each other, and the above The zigzag lines arranged in parallel to each other are substantially in a mutually perpendicular positional relationship. 4. A semiconductor memory device, which has a source field and a drain field. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) —: — 一 ----- Φ ------ ir ------ Awl (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-2-522558 A8 Β8 C8 D8 The pole areas are connected together by channel areas made of semiconductors, and gate electrodes made of metals or semiconductors that control the potential of the above-mentioned channel areas are provided. Near the above-mentioned channel areas, semiconductor memory elements with most charge storage areas are arranged. The array is characterized in that the arrangement of the element separation areas of the memory cell array is substantially rectangular parallel to each other, and the word lines connecting the gate electrodes of the semiconductor memory element are substantially rectangular parallel to each other. It has a structure in which most of the source domains are connected to each other through a diffusion layer. Arranging the rectangles arranged substantially parallel to each other, the above-mentioned parallel element separation areas arranged in parallel with each other, and the above-mentioned parallel parallel diffusion layers arranged substantially parallel, and the above-mentioned parallel element separation areas arranged in parallel, and The zigzag lines arranged in parallel with each other are substantially in a mutually perpendicular positional relationship. 5. A semiconductor memory element, characterized in that it has a channel field composed of a semiconductor, most of the charge storage fields are near the above channel field, and a metal or semiconductor is used to control the potential of the above channel field and most of the charge storage fields. The first gate electrode is formed and has a different control from the above-mentioned channel area of the semiconductor surface. ^ This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) II > 1-1. I i II .. _ (Please read the precautions on the back before filling out this page) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives to print 522558 A8 B8 C8 D8 6. The second gate electrode made of a metal or semiconductor with a potential in the scope of the patent application. 6. A semiconductor memory element, characterized in that (Please read the precautions on the back before filling out this page) It has a source area and a drain area. The source area and the drain area are connected by semiconductor channels. Together, there are most charge storage areas near the above-mentioned channel area. The first gate electrode is made of metal or semiconductor for controlling the potential of part of the above-mentioned channel area and most of the above-mentioned charge storage area. A second gate electrode composed of a metal or a semiconductor having a potential in a part of a different channel field. A semiconductor memory element characterized by having a source field and a drain field, and the source field and the drain field. The pole areas are connected and connected together by the channel areas made of semiconductors. They have gate electrodes made of metal or semiconductors to control the potential of the above-mentioned channel areas. The employees ’cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs have printed a large number of them near the above-mentioned channel areas. Charge storage area on both sides of the gate area There is a side wall structure made of semiconductor or metal on the side, and there is an insulating film '8 between the side wall structure and the gate electrode. 8 As for the semiconductor memory element in the scope of patent application item 7,' wherein, in the side wall structure on both sides of the gate electrode, One of the near-source domains is connected to the source domain, and one of the near-drain domains is connected to the drain. I Paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) -4-522558 A8 B8 C8 D8__ VI. Scope of patent application (please read the precautions on the back before filling this page) 9 The semiconductor memory element according to item 8, wherein the sidewall structure and the source region or the drain region are connected by a metal or a semiconductor selectively deposited on the sidewall structure and the source region or the drain region. 10. A semiconductor memory device characterized by arranging a plurality of semiconductor memory elements in any one of claims 5 to 9 of a patent application range, a memory cell array driven by a data line and a word line, and most of the semiconductors The drain fields of the memory elements are connected to the same data line, the second gate electrodes of most semiconductor memory elements connected to the same data line in the drain field are connected to each other, and most of the semiconductor memory elements are connected to the same data line in the source field. The first gate electrode is connected to a different zigzag line. 1 1. A semiconductor memory device, characterized in that, in a memory cell array in which a plurality of semiconductor memory elements with the scope of patent application No. 5 are arranged, the first semiconductor memory element and the second semiconductor are printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The memory element is connected so that a channel current flows in series. On both sides of the first gate electrode of the first semiconductor memory element, the second gate electrode of the second semiconductor memory element is arranged opposite to the second gate electrode of the first semiconductor memory element. One side. 1 2 · A semiconductor memory device, characterized in that it has a channel field composed of semiconductors, and there are most charge storage fields near the above channel field. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) & quot 522558 A8 B8 C8 D8 6. The scope of the patent application has the first gate electrode made of metal or semiconductor to control the potential of the above-mentioned channel area and most of the above charge storage areas, and has the above-mentioned channel area to control the semiconductor surface. The second gate electrode made of a metal or semiconductor having the same potential as the metal includes a third gate electrode made of metal or semiconductor adjacent to the above-mentioned channel area on the surface of the semiconductor to control the potential of the portion opposite to the second gate electrode. Of the structure. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210X297 mm) -6-
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Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003078045A (en) * 2001-09-03 2003-03-14 Sony Corp Nonvolatile semiconductor memory and its fabricating method
KR100462385B1 (en) * 2002-07-23 2004-12-17 주식회사 엑셀반도체 Flash Memory Pair And Method of Arraying Thereof
JP2004281736A (en) * 2003-03-17 2004-10-07 Nec Electronics Corp Semiconductor memory device
CN100353555C (en) * 2003-11-24 2007-12-05 联华电子股份有限公司 Storing device and manufacturing method therefor
US7569882B2 (en) * 2003-12-23 2009-08-04 Interuniversitair Microelektronica Centrum (Imec) Non-volatile multibit memory cell and method of manufacturing thereof
KR100601943B1 (en) * 2004-03-04 2006-07-14 삼성전자주식회사 Method of manufacturing memory device comprising gate having uniformly distributed silicon nano dots
JP2005347589A (en) * 2004-06-04 2005-12-15 Matsushita Electric Ind Co Ltd Nonvolatile semiconductor memory device and method for manufacturing the same
JP4795660B2 (en) * 2004-09-29 2011-10-19 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4534724B2 (en) * 2004-11-05 2010-09-01 ソニー株式会社 Nonvolatile semiconductor memory device
JP4902196B2 (en) * 2005-02-09 2012-03-21 シャープ株式会社 Nonvolatile semiconductor memory device
JP5047786B2 (en) * 2005-04-27 2012-10-10 スパンション エルエルシー Manufacturing method of semiconductor device
TWI271827B (en) * 2005-11-11 2007-01-21 Powerchip Semiconductor Corp Non-volatile memory and manufacturing method and operating method thereof
US7485528B2 (en) 2006-07-14 2009-02-03 Micron Technology, Inc. Method of forming memory devices by performing halogen ion implantation and diffusion processes
JP5142501B2 (en) * 2006-08-25 2013-02-13 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
WO2008072692A1 (en) 2006-12-15 2008-06-19 Nec Corporation Nonvolatile storage device and method for manufacturing the same
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US7971158B2 (en) * 2008-06-23 2011-06-28 International Business Machines Corporation Spacer fill structure, method and design structure for reducing device variation
JP2008300859A (en) * 2008-07-18 2008-12-11 Renesas Technology Corp Nonvolatile semiconductor memory
JP5193815B2 (en) 2008-11-12 2013-05-08 株式会社東芝 Semiconductor memory device
KR101043410B1 (en) * 2009-02-27 2011-06-22 주식회사 하이닉스반도체 Semiconductor memory device and manufacturing method thereof
US20110001179A1 (en) * 2009-07-03 2011-01-06 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same
US9431400B2 (en) * 2011-02-08 2016-08-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and method for manufacturing the same
FR2996680A1 (en) * 2012-10-10 2014-04-11 St Microelectronics Rousset NON-VOLATILE MEMORY HAVING VERTICAL SELECTION TRANSISTORS
CN104377202B (en) * 2013-08-12 2018-02-16 华邦电子股份有限公司 Embedded memory element and its manufacture method
US9397112B1 (en) * 2015-02-06 2016-07-19 Taiwan Semiconductor Manufacturing Co., Ltd. L-shaped capacitor in thin film storage technology
US9502122B2 (en) * 2015-02-12 2016-11-22 Taiwan Semiconductor Manufacturing Company Limited Systems, devices and methods for memory operations
CN106205715B (en) * 2016-08-04 2019-06-28 芯成半导体（上海）有限公司 The operating method of flash memory
US10014305B2 (en) 2016-11-01 2018-07-03 Micron Technology, Inc. Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors
US9761580B1 (en) * 2016-11-01 2017-09-12 Micron Technology, Inc. Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of vertically opposed capacitors
US10062745B2 (en) 2017-01-09 2018-08-28 Micron Technology, Inc. Methods of forming an array of capacitors, methods of forming an array of memory cells individually comprising a capacitor and a transistor, arrays of capacitors, and arrays of memory cells individually comprising a capacitor and a transistor
US9837420B1 (en) 2017-01-10 2017-12-05 Micron Technology, Inc. Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods of forming a tier of an array of memory cells, and methods of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor
US9842839B1 (en) 2017-01-12 2017-12-12 Micron Technology, Inc. Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array comprising rows of access lines and columns of digit lines, a 2T-1C memory cell, and methods of forming an array of capacitors and access transistors there-above
KR102521278B1 (en) * 2017-09-25 2023-04-14 에스케이하이닉스 주식회사 Semiconductor device and fabrication method thereof
US10388658B1 (en) 2018-04-27 2019-08-20 Micron Technology, Inc. Transistors, arrays of transistors, arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, and methods of forming an array of transistors
CN111863084A (en) * 2019-04-29 2020-10-30 北京兆易创新科技股份有限公司 Method and device for controlling performance of NOR flash memory
KR20210081180A (en) 2019-12-23 2021-07-01 삼성전자주식회사 Electronic device and method of manufacturing the same
US20220140147A1 (en) * 2020-11-04 2022-05-05 Samsung Electronics Co., Ltd. Thin film structure and semiconductor device comprising the same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US109539A (en) * 1870-11-22 Improvement in curtain-fixtures
JP2667444B2 (en) * 1988-06-10 1997-10-27 株式会社東芝 Nonvolatile semiconductor memory device
JP2862434B2 (en) 1991-06-07 1999-03-03 シャープ株式会社 Non-volatile memory
US5452248A (en) * 1991-06-27 1995-09-19 Kabushiki Kaisha Toshiba Method of operating a nonvolatile semiconductor memory device
US5357134A (en) * 1991-10-31 1994-10-18 Rohm Co., Ltd. Nonvolatile semiconductor device having charge trap film containing silicon crystal grains
JPH0637286A (en) 1992-07-14 1994-02-10 Sharp Corp Non-volatile memory and manufacture thereof
JPH0677440A (en) * 1992-08-27 1994-03-18 Mitsubishi Electric Corp Nonvolatile semiconductor memory
US5451475A (en) * 1993-04-28 1995-09-19 Matsushita Electric Industrial Co., Ltd. Nickel positive electrode for alkaline storage battery and sealed nickel-hydrogen storage battery using nickel positive electrode
JP3613594B2 (en) * 1993-08-19 2005-01-26 株式会社ルネサステクノロジ Semiconductor element and semiconductor memory device using the same
JP2848223B2 (en) * 1993-12-01 1999-01-20 日本電気株式会社 Erasing method and manufacturing method for nonvolatile semiconductor memory device
JP3732649B2 (en) * 1997-05-07 2006-01-05 株式会社東芝 Nonvolatile semiconductor memory device
US5824584A (en) * 1997-06-16 1998-10-20 Motorola, Inc. Method of making and accessing split gate memory device
TW437099B (en) * 1997-09-26 2001-05-28 Matsushita Electronics Corp Non-volatile semiconductor memory device and the manufacturing method thereof
JP2000049245A (en) 1998-07-31 2000-02-18 Sony Corp Nonvolatile semiconductor memory cell and data writing control method in the same
US6181597B1 (en) * 1999-02-04 2001-01-30 Tower Semiconductor Ltd. EEPROM array using 2-bit non-volatile memory cells with serial read operations
JP3954245B2 (en) * 1999-07-22 2007-08-08 株式会社東芝 Voltage generation circuit
US6255166B1 (en) * 1999-08-05 2001-07-03 Aalo Lsi Design & Device Technology, Inc. Nonvolatile memory cell, method of programming the same and nonvolatile memory array
JP4058219B2 (en) * 1999-09-17 2008-03-05 株式会社ルネサステクノロジ Semiconductor integrated circuit
US6400610B1 (en) * 2000-07-05 2002-06-04 Motorola, Inc. Memory device including isolated storage elements that utilize hole conduction and method therefor
US6477083B1 (en) * 2000-10-11 2002-11-05 Advanced Micro Devices, Inc. Select transistor architecture for a virtual ground non-volatile memory cell array

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