JPH0637286A - Non-volatile memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a cell array into a virtual ground structure so as to lessen a non-volatile memory in chip size even if such a trouble that the memory is put in an enhancement state when a memory cell section is excessively erased occurs by a method wherein a specific memory cell is provided. CONSTITUTION:A floating gate 4 is arranged on a semiconductor substrate where a field oxide film is formed through the intermediary of a gate insulating film 3, and a selection gate 8 is provided to the side wall of the floating gate 4. A first impurity diffusion region 6a arranged through a self-aligned manner and a second impurity diffusion region 6b arranged in self-alignment with the selection gate 8. Furthermore, a control gate 9 is provided widthwise traversing the channel of the floating gate 4 at a right angle, and a spacer 13 connected to the selection gate 8 is formed on the side wall of the control gate 9. By this setup, a non-volatile memory of this design can be lessened in chip area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory and a manufacturing method thereof, and more particularly to a nonvolatile memory suitable for high integration and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, in a memory cell of a nonvolatile memory having a select gate and injecting hot electrons from the source side, the select gate and the bit line are arranged in parallel as shown in the equivalent circuit of FIG. Is configured.
A memory cell showing such an equivalent circuit will be described with reference to FIG.

As shown in FIG. 7, in this memory cell, a floating gate 14 is formed on a semiconductor substrate 1 with a gate insulating film 3 interposed therebetween.
A control gate 19 is stacked on the insulating film 4 via an insulating film 17. And these floating gates 1
4 and the select gate 18 is arranged on the sidewall of the control gate 19 as a spacer. Adjacent memory cells having the control gate 19 in common are connected by the impurity diffusion regions 6 functioning as bit lines, and the memory cells adjoining the control gate 19 in the vertical direction with respect to the common adjoining direction. The cells are connected by sharing one of the impurity diffusion regions 6. Therefore, the selection gate 18 and the bit line are arranged in parallel with each other.

[0004]

In the memory cell of the non-volatile memory as described above, since the select gate 18 and the bit line are arranged in parallel with each other, the memory cell portion is over-erased, resulting in enhancement. If such a problem occurs, the cell array cannot be configured as a virtual ground, so that there is a problem that the cell array has contacts, the cell array area increases, and the chip size increases.

The present invention has been made in view of the above-mentioned problems. Even when a problem occurs such that the memory cell portion is over-erased and enhanced, the cell array is made into a virtual ground configuration to reduce the chip size. A non-volatile memory and a method for manufacturing the same are provided.

[0006]

According to the present invention, a floating gate is disposed on a semiconductor substrate having a field oxide film formed thereon via a gate insulating film, and a selection is disposed on a sidewall of the floating gate. A gate is formed, and a first impurity diffusion region self-aligned with the floating gate and a second impurity diffusion region self-aligned with the select gate are formed. A control gate on the floating gate, the control gate being orthogonal to the channel width direction of the floating gate, and a sidewall of the control gate via the control gate and an insulating film,
Provided is a non-volatile memory including a memory cell in which a spacer connected to the select gate is formed.

Further, (a) a floating gate is formed on a semiconductor substrate on which a gate insulating film and a field oxide film are formed, and (b) a surface layer of the semiconductor substrate on one end side of the floating gate. A first impurity diffusion region is formed by self-alignment with respect to the gate, (c) A spacer serving as a selection gate is formed on a sidewall of the floating gate, and then a second impurity diffusion region is self-aligned with respect to the selection gate. Forming a region,
(D) A control gate that is orthogonal to the channel width direction of the floating gate is formed on the floating gate via an insulating film, and then connected to the select gate on the sidewall of the control gate via the insulating film. Thus, a method of manufacturing a non-volatile memory including the step of forming a spacer is provided.

As the semiconductor substrate in the present invention, a silicon substrate is usually used, and the silicon substrate is
A field oxide film is formed by a known method such as COS. As the gate insulating film formed on the semiconductor substrate, a SiO ₂ film is usually used. This SiO ₂
The film can be formed by a known method such as thermal oxidation or CVD. The thickness of this SiO ₂ film is 9
About 0 to 110Å is preferable.

As the floating gate formed on the semiconductor substrate, materials such as polysilicon and WSi _x can be used, but polysilicon is preferable. At this time, for example, polysilicon is used by a known method, for example, C
It can be formed by depositing by a VD method or the like and etching into a desired pattern by a photolithography process or the like. The thickness of this polysilicon is 1000
Approximately 2000 Å is preferable, and an impurity of a type different from that of the semiconductor substrate is diffused.

Further, a first impurity diffusion layer serving as a source region is formed in self-alignment with the floating gate. At this time, the drain region is masked with a resist, and the floating gate is used as a mask to self-align with the floating gate, and the source region is doped with impurities such as P or As. For example, about 40 to 80 keV, 1 ×
The first impurity diffusion layer can be formed by implanting at a concentration of about 10 ¹⁴ to 1 × 10 ¹⁶ ions / cm ² .

Further, for example, polysilicon is laminated on the floating gate and etched back by, for example, reactive ion etching to form a spacer serving as a select gate on the sidewall of the floating gate. At this time, it is preferable that polysilicon is stacked in a range of about 4000 to 5000 Å. Then, ion implantation is performed on the entire surface of the semiconductor substrate under the same conditions as described above, and the second impurity diffusion layer to be the drain region is formed in self-alignment with the select gate.

Further, polysilicon is deposited on the floating gate and the select gate via an insulating film,
A control gate is formed on the floating gate by known etching so as to be orthogonal to the channel width direction of the floating gate. As the insulating film, for example, a SiO ₂ film of about 200 to 300 Å, Si
It is preferable to deposit an N film or a laminated film of SiO ₂ / SiN. At this time, polysilicon can be deposited by a known method such as a CVD method.
Further, the film thickness of polysilicon is preferably about 2000 to 4000 Å. As a material for the control gate, WSi _x or the like can be used instead of polysilicon.
Then, a SiN film, which is an insulating film, is deposited on the control gate and etched back by reactive ion etching to form a film having a thickness of 300 on the side wall of the control gate only.
A SiN film of about 500 Å is formed, polysilicon is further deposited on about 4000 ∫ 5,000 Å, and is etched back by reactive ion etching to form a spacer on the sidewall of the control gate and right above the select gate. This spacer is formed so as to connect the select gate.

[0013]

According to the present invention, the floating gate arranged via the gate insulating film and the select gate arranged on the side wall of the floating gate are formed on the semiconductor substrate on which the field oxide film is formed. 1st self-aligned to floating gate
An impurity diffusion region and a second impurity diffusion region arranged in self-alignment with the select gate, and a control gate on the floating gate, the control gate being orthogonal to the channel width direction of the floating gate, Since the memory cell is provided with the spacer connected to the select gate on the side wall of the control gate through the control gate and the insulating film, the select gate and the bit line are made to go straight. As a result, even if over-erasing occurs during erasing, there is no problem. That is, even if the memory cell A shown in FIG. 1 is of the enhancement type, the memory cell A is turned off by turning off the select gate of the memory cell A, which may affect the reading of the memory cell B. Disappear.

[0014]

Embodiments of a non-volatile memory according to the present invention will be described with reference to the drawings. A memory cell of a non-volatile memory that injects hot electrons from the source side is configured by vertically arranging a select gate and a bit line as shown in the equivalent circuit of FIG.

A memory cell showing such an equivalent circuit is
A description will be given based on FIG. As shown in FIG. 5, in this memory cell, a floating gate 4 is formed of polysilicon on a silicon substrate 1 on which a gate insulating film 3 and a SiO ₂ film which is a field oxide film 2 are respectively formed. SiO ₂ film 7 for gate 4
A spacer is formed of polysilicon as the select gate 8 via the. Further, in the surface layer of the silicon substrate 1, a first impurity diffusion region 6a is formed in self alignment with the floating gate 4, and a second impurity diffusion region 6b is formed in self alignment with the selection gate 8. .

SiO ₂ is formed on the floating gate 4.
The control gate 9 is laminated through the film 7,
A SiO ₂ film 10 is formed on the control gate 9, and a spacer 13 made of polysilicon is formed on the sidewalls of the control gate 9 and the SiO ₂ film 10 via a Si ₃ N ₄ film 12. And this spacer 13
As a result, the selection gate 8 formed on the side wall of the floating gate 4 becomes the control gate 9 and the SiO ₂
They are connected by spacers 13 formed on the side walls of the film 10. Adjacent memory cells sharing the control gate 9 are connected by the impurity diffusion region 6 functioning as a bit line, and the memory cells adjoining each other perpendicularly to the adjoining direction sharing the control gate 9. Are connected by making one of the impurity diffusion regions 6 common. Therefore, the selection gate 8 and the bit line are arranged perpendicular to each other.

An embodiment of a method for manufacturing a nonvolatile memory according to the present invention will be described below with reference to the drawings. First, FIG.
As shown in FIG. 1, after the field oxide film 2 is formed on the silicon substrate 1 by the selective oxidation method to separate the elements, the SiO ₂ film 3 and the polysilicon, which are gate oxide films, are formed on the entire surface of the silicon substrate 1 by 100 Å, respectively. And 2000 Å are sequentially deposited. Then, N such as P or As is added to the polysilicon.
⁺ After diffusing the impurity ions, the floating gate 4 is formed by etching into a desired pattern in a photolithography process. Further, the region where the drain region 6b is formed is masked by using the resist 5, and As ions are applied to the side to be the source region 6a at about 40 keV, 1 × 1.
Inject about 0 ¹⁵ ions / cm ² .

Then, the entire surface of the silicon substrate 1 including the floating gate 4 is thermally oxidized to an S of about 400 Å.
An iO ₂ film 7 is formed, and an interlayer insulating film and a gate oxide film of the select gate are formed on the side surface and the upper surface of the floating gate 4, respectively. Further, on the silicon substrate 1 including them, polysilicon of about 4500 Å is deposited, and P, As
After diffusing N ⁺ impurity ions such as the above, anisotropic etching is performed to form a polysilicon spacer to be the select gate 8 on the sidewall of the floating gate 4 (FIG. 3).

Then, in order to form the drain region 6b, As ions are applied to the entire surface of the silicon substrate 1 at about 40 keV,
Inject about 1 × 10 ¹⁵ ions / cm ² . After that, on the selection gate 8, an SiO ₂ film of about 500 Å is formed as an insulating film.
A film (11 in FIG. 4B) is formed. Next, after depositing about 3000 Å polysilicon on the entire surface of the silicon substrate 1 including them, N ⁺ impurity ions such as P and As are diffused, and an about 1000 Å SiO ₂ film 10 is deposited on the polysilicon by the CVD method. Then, the control gate 9 is formed by etching into a desired pattern in a photolithography process. Then, a SiN film 12 of about 400 Å is formed on the silicon substrate 1 including the control gate 9, and then etched back to form an insulating film on the side wall of the control gate 9. At that time, the SiO ₂ film on the spacer formed as the select gate 8 is also removed at the same time (FIG. 4).

Further, 4500 is formed on the entire surface of the silicon substrate 1.
A polysilicon layer 13 having a thickness of about Å is stacked, and a polysilicon spacer 13 is formed on the sidewall of the control gate 9 by anisotropic etching. At this time, the spacer 13 is connected to the select gate 8 by forming the spacer 13 on the spacer which is the select gate 8 formed in the lower layer (FIG. 5).

[0021]

According to the nonvolatile memory and the method of manufacturing the same according to the present invention, a floating gate disposed on a semiconductor substrate on which a field oxide film is formed via a gate insulating film, and a sidewall of the floating gate. And a second impurity diffusion region self-aligned with the floating gate, and a second impurity diffusion region self-aligned with the floating gate. And a control gate orthogonal to the channel width direction of the floating gate, and a sidewall of the control gate connected to the selection gate through the control gate and an insulating film. Since the memory cell is formed with a spacer, By direct and trine, even happening overerasure during erasing, it is possible to the cell array to the bar Teya Le Grand configuration. Therefore, the chip area can be reduced.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing a nonvolatile memory according to the present invention.

FIG. 2 is a schematic plan view and a schematic cross-sectional view showing the manufacturing process of the nonvolatile memory of the present invention.

FIG. 3 is a schematic plan view and a schematic cross-sectional view showing the manufacturing process of the nonvolatile memory of the present invention.

FIG. 4 is a schematic plan view and a schematic cross-sectional view showing the manufacturing process of the nonvolatile memory of the present invention.

FIG. 5 is a schematic plan view and a schematic cross-sectional view showing the manufacturing process of the nonvolatile memory of the present invention.

FIG. 6 is an equivalent circuit diagram showing a conventional nonvolatile memory.

7A and 7B are a schematic plan view and a schematic cross-sectional view of a main part showing a structure of a conventional nonvolatile memory.

[Explanation of symbols]

1 silicon substrate (semiconductor substrate) 2 field oxide film 3 SiO ₂ film (gate insulating film) 4 floating gate 6 impurity diffusion region 8 select gate 9 control gate 12 SiN film (insulating film) 13 spacer

Claims (2)

[Claims] 1. A floating gate disposed via a gate insulating film and a select gate disposed on a sidewall of the floating gate are formed on a semiconductor substrate on which a field oxide film is formed, and the floating gate is formed on the floating gate. On the other hand, a first impurity diffusion region arranged in self-alignment and a second impurity diffusion region arranged in self-alignment with the select gate are formed, and the floating gate of the floating gate is formed on the floating gate. A memory cell having a control gate perpendicular to the channel width direction and a spacer, which is a sidewall of the control gate and is connected to the select gate via an insulating film with the control gate, is provided. Non-volatile memory characterized by. 2. A floating gate is formed on a semiconductor substrate on which (a) a gate insulating film and a field oxide film are formed, and (b) a surface layer of the semiconductor substrate, the floating gate being on one end side of the floating gate. A first impurity diffusion region is formed by self-alignment with respect to the gate, and (c) a spacer serving as a selection gate is formed on a sidewall of the floating gate, and then a second impurity diffusion region is self-aligned with respect to the selection gate. A region is formed, and (d) a control gate is formed on the floating gate, the control gate being orthogonal to the channel width direction of the floating gate via an insulating film, and the insulating film is formed on the sidewall of the control gate via the insulating film. A non-volatile memory including a step of forming a spacer so as to be connected to a select gate. Re manufacturing method.