KR101043410B1 - Semiconductor memory device and manufacturing method thereof - Google Patents

Semiconductor memory device and manufacturing method thereof Download PDF

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KR101043410B1
KR101043410B1 KR1020090016911A KR20090016911A KR101043410B1 KR 101043410 B1 KR101043410 B1 KR 101043410B1 KR 1020090016911 A KR1020090016911 A KR 1020090016911A KR 20090016911 A KR20090016911 A KR 20090016911A KR 101043410 B1 KR101043410 B1 KR 101043410B1
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source
forming
unit cells
registration fee
word line
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KR1020090016911A
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KR20100097988A (en
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황상민
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주식회사 하이닉스반도체
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Abstract

The present invention provides a semiconductor memory device and a method of manufacturing the same that can prevent interference between two neighboring unit cells in a highly integrated semiconductor memory device including a unit cell composed of a floating body transistor, thereby improving operation reliability. A semiconductor memory device according to the present invention includes a plurality of unit cells formed in one active region and an insulating wall bisecting source / drain regions shared by the plurality of unit cells.
Oxide film, bit line contact, interference

Description

Technical Field [0001] The present invention relates to a semiconductor memory device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a unit cell included in a highly integrated semiconductor memory device that does not include a capacitor, and a related device.

As the data storage capacity of a semiconductor memory device increases, the size of many unit cells becomes smaller and the size of various components for reading or writing operations is also decreasing. Therefore, if there are unnecessary overlapping wirings or transistors in the semiconductor memory device, it is important to minimize the area occupied by each element. Reducing the size of a plurality of unit cells included in the semiconductor memory device also greatly affects the degree of integration.

A unit cell in a general semiconductor memory device is composed of one transistor and one capacitor. However, the charge temporarily stored in the storage node SN between the capacitor and the transistor decreases with time due to the leakage current caused by the junction and the leakage current due to the characteristics of the capacitor. For this reason, the DRAM must periodically refresh the unit cells to prevent data from being lost. To overcome this problem, attempts have been made to increase the capacitance value (Cs) of a capacitor so that a large amount of charges can be stored in a storage node (SN) in a unit cell.

As a typical method for increasing the capacitance value Cs of the capacitor, there is a method of reducing the leakage current by changing the oxide film used as the insulating film of the capacitor to a high-dielectric-constant film formed of an insulating material having a large dielectric constant such as a nitrided oxide film, A method of increasing the surface area of both electrodes of a capacitor by forming a capacitor having a two-dimensional planar structure by a three-dimensional cylinder structure or a trench structure has been proposed in order to increase the capacitance value Cs of the capacitor. However, as the design rule is reduced, it is inevitable that the planar area for forming the capacitor is reduced, and it is also difficult to develop a material constituting the insulating film in the capacitor. Accordingly, as the value of the junction resistance of the storage node SN in the unit cell and the turn-on resistance value of the transistor become larger, the normal read and write operations become difficult to perform and the refresh characteristics become worse.

To improve this, a unit cell in the proposed improved semiconductor memory device includes a transistor having a floating body. That is, the semiconductor storage device can store data in a floating body of a transistor in a unit cell without including a capacitor used for storing data conventionally in a unit cell.

1A and 1B are a plan view and a cross-sectional view illustrating a cell array of a general semiconductor memory device constituted by unit cells composed of floating body transistors without a capacitor. Specifically, FIG. 1A is a plan view for explaining a cell array in which two unit cells are formed in each active region, and FIG. 1B is a cross-sectional view taken along the X-X 'axis shown in FIG. 1A.

Referring to FIG. 1A, an active region 110 in the form of an island defined by a device isolation layer (not shown) is defined in a row and a column direction in a cell array. The active regions 110 adjacent to each other in the row direction share a word line 120 crossing the center of each active region 110 and are formed between the active regions 110 adjacent in the vertical direction. A dummy word line 130 is formed. A bit line contact 140 is formed between two neighboring word lines 120 that intersect one active region 110 and a word line 120 and a dummy word line 130 are formed on the active region 110. [ A source line contact 150 is formed.

1B, a cell array is formed on an SOI substrate 100 including a lower silicon layer 102, an insulating layer 104, and an upper silicon layer 106, and the upper silicon layer 106 is active The portion except for the region 110 is etched and embedded in the element isolation film 112. A word line 120 and a dummy word line 130 are formed on each of the active regions 110 and the device isolation film 112. Spacers 128 and 128 are formed on both sidewalls of the word line 120 and the dummy word line 130. [ Is formed. An N type source / drain region is formed on both sides of the word line 120 in the P type active region 110 and a landing plug 160 is formed on the source / drain regions on both sides of the word line 120. A source line contact 150 is formed on the landing plug 160 between the neighboring word lines 120 and on the landing plug 160 formed between the bit line contact 140 and the word line 120 and the dummy word line 130 . A bit line 170 is connected to the bit line contact 140 and a source line 180 is connected to the source line contact 150.

In the case of a unit cell including the above-described floating body transistor, a hot carrier generated in response to a positive voltage (V G > 0, V D > 0) through a word line and a ground voltage (GND, 0 V) the data is stored in the floating body by leaving a hole in the floating body. When the stored data is read, it is determined whether holes remain in the floating body corresponding to the amount and speed of the current flowing from the source line to the bit line when a voltage is applied through the word line.

2A to 2D are cross-sectional views illustrating a method of manufacturing the semiconductor memory device shown in FIG.

Referring to FIG. 2A, an isolation layer 112 is formed on an upper silicon layer 106 of an SOI substrate 100 to define an active region 110. A word line 120 and a dummy word line 130 are then formed on the active region 110 and the device isolation layer 112. Specifically, the word line 120 is composed of a gate lower electrode 122, a gate upper electrode 124, and a gate hard mask film 126, and the structure of the dummy word line 130 is also the same as that of the word line 120 same.

As shown in FIG. 2B, the spacer film 127 is deposited to a constant thickness on the structure including the word line 120 and the dummy word line 130.

Referring to FIG. 2C, the spacer film 127 is etched back to expose the active region 110 such that only the spacers 128 remain on the sidewalls of the word lines 120 and the dummy word lines 130. Thereafter, the exposed active region 110 is subjected to ion implantation to form a source / drain region.

Referring to FIG. 2D, a source / drain region is formed, and then a conductive material is deposited on the source / drain regions to form a landing plug 160.

As described above, two unit cells are formed in one active region in order to increase the degree of integration by minimizing the area occupied by the unit cells when forming the semiconductor memory device using the floating body effect. At this time, two neighboring unit cells share the source / drain region in the active region connected with the bit line contact as well as the bit line. Each unit cell stores a carrier in a floating body located below the word line, and the junction between the source / drain region and the floating body serves to confine the data.

In the operation of the semiconductor memory device, when different data are stored in two adjacent unit cells, a potential difference occurs in a floating body of two adjacent unit cells. This potential difference is caused by a PNP bipolar transistor consisting of a floating body of two unit cells and a source / drain region shared by two unit cells, ie, a shared source / drain region as a base, a floating body of two unit cells This results in the effect that the bias voltage is applied between the emitter and the collector in a PNP bipolar transistor made up of an emitter and a collector. In this case, the potential of the floating body changes due to the potential difference in the floating body of the two unit cells, so that the data of '0' is changed to '1' or the data of '1' is changed to '0'. In order to prevent the potential from being changed, and to prevent data distortion due to the potential difference of the floating body of the two unit cells, the doping concentration of the impurity in the source / drain region must be increased.

On the other hand, as the degree of integration of the semiconductor memory device increases, the size of the unit cell decreases and the width of the word line decreases. If the doping concentration of the impurity in the source / drain region is increased in such an environment, a punch through phenomenon due to a short channel effect may occur.

The reason why the data is distorted due to the potential difference as described above is that two unit cells are formed in one active region in order to increase the degree of integration. Also, a conductive material such as polysilicon is deposited on the source / drain regions formed through the ion implantation process to deposit the landing plug, and the impurity ions included in the source / drain regions are expanded to the floating body region There is a high possibility that a punch through phenomenon occurs in a semiconductor memory device having a high degree of integration.

In order to solve the above-mentioned conventional problems, the present invention provides a semiconductor memory device comprising a unit cell composed of a floating body transistor, a source / drain region shared by two adjacent unit cells formed in one active region, The present invention provides a semiconductor memory device and a method of manufacturing the semiconductor memory device, which can prevent interference between two neighboring unit cells to increase operation reliability.

The present invention provides a semiconductor memory device including a plurality of unit cells formed in one active region and an insulating wall dividing the source / drain regions shared by the plurality of unit cells.

Preferably, the plurality of unit cells are formed on an SOI substrate, and the insulating wall is in contact with an embedded insulating film in the SOI substrate.

Preferably, the active region is defined by a device isolation film which is formed on the silicon layer on the buried insulating film of the SOI substrate, and which is in contact with the buried insulating film.

Preferably, the number of unit cells formed in one active region is two.

Preferably, the semiconductor storage device further includes a contact connected to both sides of the source / drain region divided by the insulating film.

Preferably, the semiconductor storage device further includes a bit line or a source line connected to the contact.

Preferably, the width of the insulating wall is narrower than half the width of the gate pattern of the cell transistor included in the unit cell.

The present invention also provides a method of manufacturing a semiconductor device, comprising: forming a word line included in a plurality of unit cells formed in one active region and forming an insulating wall to divide a first source / drain region shared by the plurality of unit cells The present invention also provides a method of manufacturing a semiconductor memory device.

Advantageously, the step of forming the word line includes forming an isolation layer defining the active region on the SOI substrate and forming a gate pattern comprised of a plurality of gate electrodes on the active region.

Preferably, dividing the first source / drain region shared by the plurality of unit cells by forming the insulating wall comprises depositing a spacer film over the structure including the word line, Forming a mask pattern for exposing a region and forming the insulating wall in the first source / drain region.

Preferably, the step of forming the mask pattern includes etching the spacer film to expose an upper portion of the word line, depositing a mask film on the spacer film and the word line, and patterning the mask film to form the first And exposing the source / drain regions.

Preferably, the step of forming the insulating wall further comprises: a step of further etching the spacer film to expose a portion of the first source / drain region; a step of etching a part of the exposed first source / And burying a portion of one of the first source / drain regions etched by oxidizing the exposed silicon with an insulating material.

Preferably, the width of the insulating wall is narrower than 1/2 of the width of the word line.

Preferably, the manufacturing method of the semiconductor memory device further comprises forming a source line or a bit line connected to both sides of the first source / drain region divided into two.

Preferably, the manufacturing method of the semiconductor memory device includes: etching a spacer film on a sidewall of the word line to expose a first source / drain region and a second source / drain region that is not shared by the plurality of unit cells And performing ion implantation in the exposed first and second source / drain regions.

Preferably, the method of manufacturing the semiconductor memory device further comprises forming a contact on the first and second source / drain regions after the ion implantation step.

An insulating wall is formed between two neighboring unit cells formed on one active region in the course of manufacturing a highly integrated semiconductor memory device, thereby preventing interference between neighboring unit cells It is possible to increase the operational reliability of the semiconductor memory device.

Also, in the semiconductor memory device including the floating body unit cell, even if two or more unit cells are formed in one active region, the potential difference between the source and drain regions formed by the source / It is possible to prevent the data from being distorted by the semiconductor memory device and to increase the degree of integration of the semiconductor memory device.

In a highly integrated semiconductor memory device including a cell array composed of unit cells including a floating body transistor, the present invention prevents data interference between a plurality of unit cells formed in one active region, thereby enhancing operational reliability. To this end, the present invention is characterized in that insulating walls are formed in the source / drain regions shared by neighboring unit cells. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

3A, an active region 310 is defined on an upper silicon layer 306 of an SOI substrate 300 including a lower silicon layer 302, an immersion isolation layer 304 and an upper silicon layer 306 Thereby forming an element isolation film 312. Then, a word line 320 and a dummy word line 330 are formed on the active region 310 and the device isolation film 312. Specifically, the word line 320 is composed of a gate lower electrode 322, a gate upper electrode 324 and a gate hard mask film 326, and the structure of the dummy word line 330 is also the same as that of the word line 320 same. A spacer film 327 is deposited to a constant thickness on the structure including the word line 320 and the dummy word line 330. At this time, the spacer film 327 to be deposited is deposited thicker than the conventional spacer film 127. In one example, the spacer film 327 is deposited by a thickness that is close to one-half of the spacing between adjacent word lines 330 so that the space between neighboring word lines 330 is nearly filled.

As shown in FIG. 3B, a portion of the spacer film 327 is etched to expose the tops of the word lines 320 and the dummy word lines 330. At this time, the etching depth of the spacer film 327 is controlled so that the active region 310 is not exposed to both sides of the word line 320 and the dummy word line 330 but is protected by the spacer film 327. Particularly, in the present invention, since the thickness of the spacer film 327 is thickened, the active region 310 is not exposed unless the depth is deepened in the etching process.

Referring to FIG. 3C, a hard mask film (not shown) is deposited on the word line 320, the dummy word line 330 and the spacer film 327 and patterned through an exposure process so that the source line The spacer film 327 remaining between the neighboring word lines 320 covering the spacer film 327 left in the active region 310 to be connected (i.e., the region between the word line 320 and the dummy word line 330) Thereby forming an exposed mask pattern 338. [ At this time, in the process of removing the hard mask layer between the neighboring word lines 320, the spacer film 327 left in the lower portion is further etched to expose a part of the active region 310, (310). At this time, the exposed region in the active region 310 is completely removed to expose the embedded insulating film 304.

The width of the etched region in the active region 310, which is determined according to the deposited thickness of the spacer film 327, is very narrow, ranging from several angstroms to several tens of angstroms, It is enough. For example, as shown in FIG. 3C, the width of the word line 320 or the interval between the out-of-word lines 320 is smaller than 1/2.

3D, after removing the mask pattern 338, the exposed silicon is locally oxidized through the area to be etched in the active area 310 to form the insulating wall 348. [ Here, the insulating wall 348 divides one active region 310 into two, thereby preventing charge from moving between unit cells formed on both sides.

Referring to FIG. 3E, the spacer film 327 is further etched through an etch-back process so that the spacers 328 are left only on the sidewalls of the word lines 320 and the dummy word lines 330, and source / drain regions are formed Thereby exposing the active region 310. Thereafter, the exposed active region 310 is subjected to ion implantation.

Although not shown, after a source / drain region is formed, a conductive material is deposited on the source / drain region to form a landing plug (not shown), and then a source line (not shown) and a bit line do. In an embodiment of the present invention shown in FIGS. 3A through 3E, an insulating wall 348 is formed in a source / drain region to which a bit line is connected. In another embodiment, a source / A wall 348 may be formed.

As described above, the method of manufacturing the semiconductor memory device according to an embodiment of the present invention includes forming word lines 320 included in a plurality of unit cells formed in one active region 310, (348) to divide the source / drain regions shared by the plurality of unit cells. At this time, insulating walls need not be formed in the source / drain regions that are not shared by the plurality of unit cells.

Referring to FIG. 3E, unlike the related art, two neighboring unit cells are isolated from each other due to the insulating wall 348, so that the movement of charges can be blocked even if the potentials of the neighboring unit cells are different from each other. The method of fabricating a semiconductor memory device according to an embodiment of the present invention further includes the step of further etching the spacer film 338 to the sidewall of the word line 320 after the formation of the insulating wall 348, Drain region is exposed, and ion implantation is performed on the exposed source / drain region to complete the unit cell.

The semiconductor memory device manufactured by the above method includes a plurality of unit cells formed in one active region and an insulating wall bisecting the source / drain regions shared by the plurality of unit cells. At this time, insulating walls are not formed in the source / drain regions that are not shared by the plurality of unit cells. The semiconductor memory device having such a structure can prevent data interference which may occur due to a potential difference between floating bodies during reading / writing operations for reading data written in different unit cells or storing different data in adjacent unit cells . In particular, even if a cell transistor for storing two bits or more of data in one active region is formed, an insulating wall can be formed between the cell transistors to prevent the data interference phenomenon. Therefore, the integration degree of the semiconductor memory device can be improved have.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

FIGS. 1A and 1B are a plan view and a cross-sectional view illustrating a cell array of a general semiconductor memory device constituted of unit cells composed of floating body transistors without a capacitor. FIG.

FIGS. 2A to 2D are cross-sectional views illustrating a method of manufacturing the semiconductor memory device shown in FIG. 1; FIGS.

FIGS. 3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention; FIGS.

Claims (16)

  1. A plurality of unit cells formed in one active region; And
    An insulating wall that bisects a source / drain region shared by the plurality of unit cells;
    And a semiconductor memory device.
  2. Claim 2 has been abandoned due to the setting registration fee.
    The method according to claim 1,
    Wherein the plurality of unit cells are formed on an SOI substrate, and the insulating wall is in contact with an embedded insulating film in the SOI substrate.
  3. Claim 3 has been abandoned due to the setting registration fee.
    3. The method of claim 2,
    Wherein the active region is defined by a device isolation film formed on the silicon layer on the buried insulating film of the SOI substrate and in contact with the buried insulating film.
  4. Claim 4 has been abandoned due to the setting registration fee.
    The method according to claim 1,
    And the unit cell formed in the one active region has two unit cells.
  5. Claim 5 has been abandoned due to the setting registration fee.
    The method according to claim 1,
    And a contact connected to both sides of the source / drain region divided by the insulating wall.
  6. Claim 6 has been abandoned due to the setting registration fee.
    6. The method of claim 5,
    And a bit line or a source line connected to the contact.
  7. Claim 7 has been abandoned due to the setting registration fee.
    The method according to claim 1,
    Wherein a width of the insulating wall is narrower than a half of a width of a gate pattern of a cell transistor included in the unit cell.
  8. Forming a word line included in a plurality of unit cells formed in one active region; And
    Forming an insulating wall to separate the first source / drain regions shared by the plurality of unit cells
    And forming a gate insulating film on the semiconductor substrate.
  9. Claim 9 has been abandoned due to the setting registration fee.
    9. The method of claim 8,
    The step of forming the word line
    Forming an isolation layer on the SOI substrate to define the active region; And
    And forming a gate insulating film on the semiconductor substrate.
  10. Claim 10 has been abandoned due to the setting registration fee.
    9. The method of claim 8,
    And dividing the first source / drain region shared by the plurality of unit cells by forming the insulating wall
    Depositing a spacer film over the structure including the word line;
    Forming a mask pattern to expose the first source / drain regions; And
    Forming an isolation wall in the first source / drain region
    And forming a gate insulating film on the semiconductor substrate.
  11. Claim 11 has been abandoned due to the set registration fee.
    11. The method of claim 10,
    The step of forming the mask pattern
    Etching the spacer film to expose an upper portion of the word line;
    Depositing a mask film on the spacer film and the word line; And
    Exposing the first source / drain region by patterning the mask layer
    And forming a gate insulating film on the semiconductor substrate.
  12. Claim 12 is abandoned in setting registration fee.
    The step of forming the insulating wall
    Further etching the spacer film to expose a portion of the first source / drain region;
    Exposing an embedded insulating film by etching a portion of one of the exposed first source / drain regions; And
    Implanting a portion of one of the first source / drain regions etched away with an insulating material by oxidizing the exposed silicon
    And forming a gate insulating film on the semiconductor substrate.
  13. Claim 13 has been abandoned due to the set registration fee.
    13. The method of claim 12,
    Wherein a width of the insulating wall is narrower than a half of a width of the word line.
  14. Claim 14 has been abandoned due to the setting registration fee.
    9. The method of claim 8,
    And forming a source line or bit line connected to both sides of the first source / drain region to be divided.
  15. Claim 15 is abandoned in the setting registration fee payment.
    9. The method of claim 8,
    Etching a spacer film on a sidewall of the word line to expose a first source / drain region and a second source / drain region that is not shared by the plurality of unit cells; And
    And performing ion implantation in the exposed first and second source / drain regions.
  16. Claim 16 has been abandoned due to the setting registration fee.
    16. The method of claim 15,
    Further comprising forming a contact on the first and second source / drain regions after performing the ion implantation. ≪ Desc / Clms Page number 22 >
KR1020090016911A 2009-02-27 2009-02-27 Semiconductor memory device and manufacturing method thereof KR101043410B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05121756A (en) * 1991-10-24 1993-05-18 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
KR970077218A (en) * 1996-05-28 1997-12-12 김광호 Contact formation method to improve the refresh characteristics
KR20020046139A (en) * 2000-12-11 2002-06-20 가나이 쓰토무 Semiconductor device
KR20050010260A (en) * 2003-07-18 2005-01-27 주식회사 하이닉스반도체 Method of manufacturing NAND flash memory device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05121756A (en) * 1991-10-24 1993-05-18 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
KR970077218A (en) * 1996-05-28 1997-12-12 김광호 Contact formation method to improve the refresh characteristics
KR20020046139A (en) * 2000-12-11 2002-06-20 가나이 쓰토무 Semiconductor device
KR20050010260A (en) * 2003-07-18 2005-01-27 주식회사 하이닉스반도체 Method of manufacturing NAND flash memory device

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