JP4919549B2 - Nonvolatile memory and semiconductor device - Google Patents

Description

【００８３】
【表２】

【００８４】
本願発明の多値不揮発性メモリは、様々なＥＥＰＲＯＭに応用することが可能である。メモリ素子ごとのデータ消去が可能なフル機能ＥＥＰＲＯＭ、およびブロック毎に一括消去を行うフラッシュメモリのどちらのタイプのＥＥＰＲＯＭに対しても適用することができる。フラッシュメモリに適用する場合には、さらにＮＯＲ型、ＮＡＮＤ型、あるいは他の公知の型に対応する回路構成を採用することが可能である。ただし、本願発明においては、ピニング線と呼ばれる多値を制御する配線を有する点において従来の回路構成とは異なっている（実施例３、５参照）。
【００８５】
また、本実施例ではスタック型のメモリトランジスタについて述べたが、本願発明はスプリットゲート構造のメモリトランジスタに対しても適用することが可能である（実施例２参照）。
【００８６】
さらに、本願発明のメモリトランジスタは、ホットエレクトロン書き込みを行うことも可能である。具体的には、書き込みを行うチャネル形成領域を挟む２つのピニング領域に電圧を印加することによって、選択したチャネル形成領域のみにおいてインパクトイオン化を発生させればよい。例えばｎチャネル型の場合に、ドレイン領域のチャネル長方向の方向電界を大きくするためには、２つのピニング領域の電位を他のピニング領域の電位よりも高くするとよい。
【００８７】
この他、フローティングゲート電極とソース領域あるいはドレイン領域とのオーバーラップ領域を形成することにより、ソース側あるいはドレイン側からのトンネル電流による電子の注入や放出を行うことも可能である。
【００８８】
また、本願発明において、メモリトランジスタと一体形成される駆動回路および他の周辺回路を構成するトランジスタ、あるいは半導体装置においてメモリ部と一体形成される他の回路を構成するトランジスタに対しても、ピニング領域を設けることは有効である。これにより、メモリセル以外の回路においても、短チャネル効果の抑制およびその他のピニング領域による効果を得ることが可能となる。
【００８９】
（実施例１）
本実施例では、本願発明の不揮発性メモリの作製方法について述べる。本願発明のピニング型メモリトランジスタは、ピニング領域を除けば、基本的にはソース領域、ドレイン領域、チャネル形成領域、フローティングゲート電極、コントロールゲート電極によって構成されているので、微細加工が可能な範囲で、公知の作製方法を用いることができる。
【００９０】
特に、従来のメモリトランジスタの作製方法と同様に、第１のゲート絶縁膜は熱酸化工程によって良質の膜を形成することが好ましく、また、層間膜としてＳｉＯ₂／ＳｉＮ／ＳｉＯ₂で表される様な積層膜（ＯＮＯ膜と呼ばれる）を用いることが望ましい。勿論、他の絶縁膜を用いることも可能である。
【００９１】
作製方法の観点から見た場合、本願発明のピニング型メモリトランジスタの特徴は、ピニング領域と呼ばれる不純物領域を形成する点と、素子サイズが極めて小さいメモリトランジスタを対象にしているという点にある。例えば、ピニング領域に関して言えば、フローティングゲート電極と第１のゲート絶縁膜を介して一部重なる構造とすることや、ソース領域およびドレイン領域を横切る構造とすることなどに特徴がある。また、素子サイズに関して言えば、フローティングゲート電極、ピニング領域およびチャネル形成領域の加工寸法として典型的には、０．０１〜１μｍのサイズで形成しなくてはならない。フローティングゲート電極とピニング領域との間のオーバーラップ構造はさらに微細な構造が必要である。
【００９２】
このような極微細な構造を作製するためには、一般的にはセルフアライン方式が非常に有効である。本願発明のピニング型メモリトランジスタにおいても、ピニング領域、オーバーラップ領域、ソース領域およびドレイン領域の形成にはセルフアライン方式を用いることが望ましい。具体的にはまず、ピニング領域の形成は、まずフローティングゲート電極の極微細加工を行い、これをマスクとして、イオンインプランテーション法によってセルフアライン方式で形成する。特に、フローティングゲート電極とピニング領域との間にオーバーラップ領域を形成する場合には、イオンインプランテーション法による斜め打ち込みを行えばよい。
【００９３】
なお、フローティングゲート電極の極微細加工は、０．１５μｍ程度までのパターンに関してはステッパーやスキャン露光装置によってレジストによるマスクパターンを形成することができる。一方、パターンサイズが０．１５μｍ以下になると、電子描画法によるマスクパターンの形成が必要となる。マスクパターンの形成後はＩＣＰ等によるドライエッチングを行うことが好ましい。
【００９４】
なお、ピニング領域への不純物の打ち込みは、基板に対して垂直方向への高エネルギー打ち込みと斜め方向への低エネルギー打ち込みに分けてもよいし、基板に対して斜め方向への高エネルギー打ち込みを一度で行う方法でも良い。
【００９５】
ピニング領域に添加した不純物元素はファーネスアニール、レーザーアニール、ランプアニール等で活性化を行うことが好ましい。特に、不純物の拡散を最小限に抑えるためには、ＲＴＡ法による活性化が好ましい。
【００９６】
次に、ソース領域、ドレイン領域およびピニング領域から配線を引き出す領域におけるピニング領域の形成について述べる。ピニング領域がドレイン領域を横切る場合の断面構造の一例は、図３に示されており、実施の形態において説明した。ピニング領域は微細な構造であるからやはりセルフアライン方式によって作製するのが好ましい。従って、最初にソース領域、ドレイン領域等、活性領域以外でピニング領域を形成する必要のある領域においても、フローティングゲート電極を適切な形に微細加工する。そして、フローティングゲート電極をマスクとして、イオンインプランテーション法によって、活性領域内のピニング領域と同時に形成することが好ましい。
【００９７】
最終的には、活性領域以外フローティングゲート電極は取り除かれる。レジストをマスクとしてもよいし、コントロールゲート電極をマスクとして取り除くこともできる。
【００９８】
また、ソース領域およびドレイン領域への不純物ドープはコントロールゲート電極をマスクとするセルフアライン方式によって行われる。このとき、ソース・ドレイン領域への打ち込み深さは、ピニング領域の深さよりも浅くなるように調節する。また、ソース・ドレイン領域がピニング領域によって分断されないように、ソース・ドレイン領域の不純物濃度はピニング領域の不純物濃度よりも濃くする必要がある。このようにして、図３に示した断面構造が形成される。なお、ソース・ドレイン領域への打ち込み深さを、ピニング領域の深さよりも浅くすることは、ドレイン領域の空乏層の広がりを効果的に抑える目的においても重要である。
【００９９】
なお、ソース領域およびドレイン領域がピニング領域によって分断される場合には、コンタクトホール形成後に、まずソース・ドレイン領域と同じ導電型の不純物（代表的には、ｎ型ならば、リン、ｐ型ならばボロン）を含むポリシリコンを成膜したのちに、アルミニウム等の金属膜を成膜することによって、ソース領域およびドレイン領域コンタクトを取ることができる。
【０１００】
本実施例では、本願発明のピニング型メモリトランジスタの作製方法において、特に、ピニング領域の作製方法と、極微細加工に関して述べた。これらのプロセスを公知のメモリトランジスタ作製プロセスに適切に組み込むことによって、本願発明の不揮発成メモリを作製することが可能となる。勿論、実施の形態で説明したピニング型メモリトランジスタの構造、あるいは実施例３、５で説明する回路構造を作製する方法であれば、どのような作製方法であっても構わない。
【０１０１】
（実施例２）
本実施例では、実施の形態で示したピニング型メモリトランジスタの構成（図１参照）とは異なる例として、スプリットゲート構造を有するピニング型メモリトランジスタの構成例を、図６を用いて説明する。
【０１０２】
なお、フローティングゲート電極およびコントロールゲート電極の構造を除いた領域に関しては、図１に示したスタックゲート型メモリトランジスタと同じ構造であり、図１の説明に用いた符号を利用する。即ち、図６において図１と同じ符号のついた部分は図１の説明を参照すれば良い。本実施例では、特にフローティングゲート電極およびコントロールゲート電極についての説明を行う。
【０１０３】
スプリットゲート構造とは、図６に示す通り、コントロールゲート電極６１０の一部が活性領域上に第１のゲート絶縁膜を介して直接積層されている構造をいう。従って、チャネル形成領域は、第１のゲート絶縁膜を介してフローティングゲート電極６０８が形成されている領域と、コントロールゲート電極が形成されている領域とに分けられる。
【０１０４】
図１４に、図６に示したスプリットゲート構造のピニング型メモリトランジスタの等価回路を示す。スプリットゲート構造のピニング型メモリトランジスタの動作方法は、スタック構造のピニング型メモリトランジスタの動作方法と同様で良い。スプリットゲート構造を用いる利点は、チャネル形成領域上にコントロールゲート電極が形成されている領域が選択トランジスタとして機能する点にある。つまり、ピニング型メモリトランジスタの選択性を高める働きと、読み出し時において、非選択セルが過消去状態であってもオフの状態を保つ働きとがある。
【０１０５】
なお、スプリットゲート構造のピニング型メモリトランジスタは、基本的にはスタック構造のピニング型メモリトランジスタと同じ工程でもって作製できる。つまり、実施例１に示したプロセスを用いて作製することが可能である。
【０１０６】
（実施例３）
本実施例では、本願発明の多値メモリトランジスタを、ＮＡＮＤ型フラッシュメモリに応用した回路の説明を行う。ただし、本願発明では、ピニング線と呼ばれる多値を制御する配線を有する点、これに伴い書き込み、消去、読み出しの方式が異なる点、等において、従来のＮＡＮＤ型フラッシュメモリとは異なる。
【０１０７】
図７は、メモリセルが縦８×横ｎ個（ｎは１以上の整数）のマトリクス状に配列されたＮＡＮＤ型のメモリセルアレイの回路図である。各メモリセルはそれぞれ、四角の破線で囲まれた一つのピニング型メモリトランジスタによって構成されている。
【０１０８】
本実施例では、各ピニング型メモリトランジスタが３つのフローティングゲート電極を有する場合について説明を行うが、一般にｋ個（ｋは１以上の整数）のフローティングゲート電極を有する場合についても、本実施例を適用することは容易である。また、本実施例では、縦８個×横ｎ個のメモリセルアレイについて説明を行うが、この構成に限定する必要はない。なお、メモリトランジスタ（１，１）〜（ｎ，ｍ）はｎチャネル型またはｐチャネル型のいずれの導電型トランジスタでも良いが、本実施例では、ｎチャネル型トランジスタとする。
【０１０９】
図７において、同じ列に配置されたピニング型メモリトランジスタ（例えば第１列の（１，１）〜（１，８））は直列に接続されている。また、同じ行に配置されたピニング型メモリトランジスタ（例えば、第１行の（１，１）〜（ｎ，１））、は、それぞれのコントロールゲート電極が一つのワード線Ｗ１に接続されている。
【０１１０】
なお、ピニング型メモリトランジスタを直列に接続するとは、ピニング型メモリトランジスタを構成するサブメモリトランジスタおよびピニング領域を、それぞれ直列に接続することを意味する。また、ピニング型メモリトランジスタのコントロールゲート電極は、ピニング型メモリトランジスタを構成するサブメモリトランジスタ全てに共通である。
【０１１１】
直列に接続された８つのピニング型メモリトランジスタ（例えば第１列の（１，１）〜（１，８））の両端には、選択用トランジスタ（１，０）及び（１，９）が直列に接続されている。つまり、第１行目のメモリセルの上には、選択用トランジスタ（１，０）〜（ｎ，０）が、第８行目のメモリセルの下には、選択用トランジスタ（１，９）〜（ｎ，９）がそれぞれ配置されている。選択用トランジスタ（１，０）〜（ｎ，０）のソース電極及びドレイン電極の残る一方にはビット線Ｂ１〜Ｂｎが接続されており、ゲート電極には選択用ゲート線Ｓ１が接続されている。また、選択用トランジスタ（１，９）〜（ｎ，９）のソース電極及びドレイン電極の残る一方には共通のソース電位Ｖｓが与えられており、ゲート電極には選択用ゲート線Ｓ２が接続されている。
【０１１２】
そして、直列に接続された８つのピニング型メモリトランジスタ（例えば第１列の（１，１）〜（１，８））が有する４つのピニング領域は、それぞれピニング線Ｐ（１；０)、Ｐ（１；１)、Ｐ（１；２)、Ｐ（１；３)に接続されている。
【０１１３】
このように構成された本願発明の不揮発性メモリの動作方法について述べる。本願発明では、実施の形態で説明したように、書き込みと消去はフローティングゲート電極とピニング領域間のトンネル電流によって行い、読み出し方法は１値／ＦＧ方式または１ビット／ＦＧ方式を用いることができる。１値／ＦＧ方式の場合、本実施例の不揮発性メモリは各メモリセルに４値、つまり２ビットのデータを格納することができるので、８×ｎ×２ビットの記憶容量を有する。また、１ビット／ＦＧ方式の場合、本実施例の不揮発性メモリは各メモリセルに３ビットを格納することができるので、８×ｎ×３ビットの記憶容量を有する。なお、書き込みと消去は、一行同時書き込みと一括消去について説明する。
【０１１４】
なお、従来のＮＡＮＤ型フラッシュメモリでは、書き込み方法と消去方法はフローティングゲート電極とチャネル形成領域全面（ウェル）間のトンネル電流によって行われるが、本願発明ではそのようなウェル電位を制御する必要はない。また、トンネル電流はオーバーラップ領域を用いるため、チャネル領域全面を用いる従来方法と比較してカップリング比を大きく取ることが可能であり、低い動作電圧を実現することができる。
【０１１５】
本実施例において、”０”の状態とはメモリトランジスタのフローティングゲート電極に電荷が蓄積されている状態を指し、”１”の状態とはメモリトランジスタのフローティングゲート電極に電荷が蓄積されていない状態を指す。また、”０”の状態のメモリトランジスタのしきい値電圧は０．５Ｖ〜３Ｖであるとし、”１”の状態のメモリトランジスタのしきい値電圧は−１Ｖ以下であるとする。
【０１１６】
まず、一行同時書き込みについて述べる。具体例として、一行目のピニング型メモリトランジスタ（１，１）〜（ｎ，１）を取り上げ、メモリトランジスタ（１，１）を構成するサブメモリトランジスタ（１，１；１）に”０”を、他のサブメモリトランジスタ（１，１；２）および（１，１；３）に”１”を、またメモリトランジスタ（２，１）〜（ｎ，１）を構成する全てのサブメモリトランジスタに”１”を書き込む場合を説明する。なお、書き込む直前は全て”１”の状態とする。
【０１１７】
まず、ピニング線Ｐ（１；１）とソース電位ＶｓをＧＮＤに落し、ピニング線Ｐ（１；０），Ｐ（１；２），Ｐ（１；３）を７Ｖとする。また、選択用ゲート線Ｓ１、Ｓ２にそれぞれ０Ｖを印加し、選択用トランジスタ（１，０）〜（ｎ，０）および（１，９）〜（ｎ，９）をオフの状態にする。そしてワード線Ｗ１に１５Ｖ、ワード線Ｗ２〜Ｗ８に７Ｖを印加すると共に、ビット線Ｂ１〜Ｂｎに０Ｖを印加する。
【０１１８】
その結果、メモリトランジスタ（１，１）においては、サブメモリトランジスタ（１，１；１）のフローティングゲート−ピニング領域間にのみ高電圧（約１５Ｖ）が印加され、トンネル電流によるフローティングゲートへの電荷注入が行われ、”０”が書き込まれる。サブメモリトランジスタ（１，１；２）、（１，１；３）および、メモリトランジスタ（２，１）〜（ｎ，１）を構成するピニング領域とフローティングゲート間には高々８Ｖの電位差が生じるだけであり、フローティングゲートへの電荷注入は行われない。つまり、サブメモリトランジスタ（１，１；２）、（１，１；３）およびメモリトランジスタ（２，１）〜（ｎ，１）は”１”の状態のままとなる。また、一行目以外のメモリトランジスタについても、フローティングゲート−ピニング領域間に高々７Ｖの電位差が生じるだけであり、フローティングゲートへの電荷注入は行われない。このようにして、一行同時書き込みが行われる。
【０１１９】
次に、メモリトランジスタ（１，１）からの１値／ＦＧ方式の読み出しについて説明する。まず、ピニング線Ｐ（１；０）〜Ｐ（１；３）をＧＮＤに落し、ワード線Ｗ１に０Ｖ、ワード線Ｗ２〜Ｗ８に５Ｖを印加する。これにより、２行目から８行目のメモリトランジスタは全てオンの状態となる。また、１行目のメモリトランジスタは、”１”の状態のサブメモリトランジスタがオンの状態となり、”０”の状態のサブメモリトランジスタがオフの状態となる。つまり、直列に接続された８つのメモリトランジスタの電流量は、１行目のメモリトランジスタ（１，１）を構成する”１”の状態のサブメモリトランジスタの数よって決まることになる。そして、選択用ゲート線Ｓ１、Ｓ２に５Ｖを印加し、選択用トランジスタをオンの状態とすると共に、ソース電位ＶｓをＧＮＤに落すことにより、ビット線Ｂ１を通して、メモリトランジスタ（１，１）に格納された４値のデータの読み出すことが可能となる。
【０１２０】
次に、メモリトランジスタ（１，１）からの１ビット／ＦＧ方式の読み出しについて説明する。最初に、サブメモリトランジスタ（１，１；１）から選択的に１ビットの情報を読み出す方法を述べる。まず、ピニング線Ｐ（１；０）、Ｐ（１；１）をＧＮＤに落し、ピニング線Ｐ（１；２）、Ｐ（１；３）に−５Ｖ、ワード線Ｗ１に０Ｖを印加する。これにより、１行目のメモリトランジスタにおいて、サブメモリトランジスタ（１，１；１）以外は全てオフの状態となる。また、サブメモリトランジスタ（１，１；１）は、”１”の状態であればオンの状態となり、”０”の状態であればオフの状態となる。一方、ワード線Ｗ２〜Ｗ８には５Ｖを印加する。これにより、２行目から８行目のメモリトランジスタにおいて、サブメモリトランジスタ（１，１；１）と直列に接続するサブメモリトランジスタは全てオンの状態となる。その結果、直列に接続された８つのメモリトランジスタの導通、非導通は、サブメモリトランジスタ（１，１；１）の状態で決まることになる。そして、選択用ゲート線Ｓ１、Ｓ２に５Ｖを印加し、選択用トランジスタをオンの状態とすると共に、ソース電位ＶｓをＧＮＤに落すことにより、ビット線Ｂ１を通して、サブメモリトランジスタ（１，１；１）のデータを読み出すことが可能となる。全く同様にして、サブメモリトランジスタ（１，１；２）、（１，１；３）からも、１ビットの情報を読み出すことが可能であり、メモリトランジスタ（１；１）から３ビットの情報を読み出すことが可能となる。
【０１２１】
一括消去を行う場合は、全てのワード線Ｗ１〜Ｗ８を０Ｖとし、全てのピニング線Ｐ（１；ｉ）〜Ｐ（ｎ；ｉ）（ｉ＝０〜３）を１５Ｖとする。その結果、フローティングゲート電極−ピニング領域間に高電位差が生じ、トンネル電流による消去が行われる。なお、選択用ゲート線Ｓ１、Ｓ２の電位は選択トランジスタがオフの状態となるように決める。
【０１２２】
勿論、上述した動作電圧の値は、一例であって、その値に限られるわけではない。実際に、メモリトランジスタに印加される電圧は、メモリトランジスタの半導体活性層の膜厚やコントロールゲート電極とフローティングゲート電極との間の容量等に依存する。そしてメモリトランジスタの動作電圧もそれに従って変化する。
【０１２３】
なお、メモリトランジスタへの書き込み時および読み出し時において、同じ列や行のメモリセルに電圧が印加されることによって、誤消去や誤書き込みが発生する場合がある。動作電圧は、このような書き込みストレスや読み出しストレスを最小限に抑え、誤消去や誤書き込みが発生しないように設定することが必要である。
【０１２４】
なお、本実施例の回路構成は、実施例１に示したプロセスを用いて作製することが可能である。特に、選択トランジスタに関しては他のサブメモリトランジスタと同様にフローティングゲート電極を加工して、セルフアラインによってピニング領域を形成した後に、フローティングゲート電極をエッチングで取り除けばよい。
【０１２５】
（実施例４）
本実施例では、本願発明のピニング領域を用いた不揮発性メモリを構成するメモリセルの上面構造について説明する。図８には、実施例３に示したＮＡＮＤ型フラッシュメモリを構成するメモリセルアレイの上面図の一例が示されている。
【０１２６】
図８に示した上面図は、２つのピニング型の選択トランジスタ８１０と８つのピニング型メモリトランジスタ８１１（３つだけ表示）を直列してなるメモリセルアレイの上面図であり、領域８０１はフィールド酸化膜、領域８０８がピニング領域である。図８において、それぞれのピニング型メモリトランジスタ８１１は、フローティングゲート電極８０５を３つ有しており、３つのサブメモリトランジスタ８１２によって構成されている。また、メモリトランジスタ８１１のコントロールゲート電極はワード線８０４を兼ねており、選択トランジスタ８１０のゲート電極は選択線８０３を兼ねている。選択線トランジスタのドレイン領域と配線（ビット線）８０９はコンタクトホール８０７を介して電気的に接続されている。
【０１２７】
なお、本実施例は実施の形態におけるメモリセルの上面図の一例である。勿論、実施例３において説明した回路構成と合致すれば、他のどのような上面図であっても構わない。
【０１２８】
（実施例５）
本実施例では、本願発明の多値メモリトランジスタを、ＮＯＲ型フラッシュメモリに応用した回路の説明を行う。ただし、本願発明では、ピニング線と呼ばれる多値を制御する配線を有する点、これに伴い書き込み、消去、読み出しの方式が異なる点、等において、従来のＮＯＲ型フラッシュメモリとは異なる。
【０１２９】
図９は、メモリセルがｍ行ｎ列（ｍ、ｎはそれぞれ１以上の整数）のマトリクス状に配列されたＮＯＲ型のメモリセルアレイの回路図である。各メモリセルはそれぞれ、四角の破線で囲まれた一つのピニング型メモリトランジスタによって構成されている。
【０１３０】
本実施例では、各ピニング型メモリトランジスタが３つのフローティングゲート電極を有する場合について説明を行うが、一般にｋ個（ｋは１以上の整数）のフローティングゲート電極を有する場合についても、本実施例を適用することは容易である。また、メモリトランジスタ（１、１）〜（ｎ、ｍ）はｎチャネル型またはｐチャネル型のいずれの導電型トランジスタでも良いが、本実施の形態では、ｎチャネル型トランジスタとする。
【０１３１】
図９において、ｉ番目の列（ｉは１以上ｎ以下の整数）に配置されているｍ個のメモリセルを構成するピニング型メモリトランジスタ（ｉ，１）、（ｉ，２）〜（ｉ，ｍ）は、ドレイン電極にビット線Ｂｉが接続され、ソース電極にはソース電位Ｖｓが与えられている。また４つのピニング領域には、それぞれピニング線Ｐ（ｉ；０）、Ｐ（ｉ；１）、Ｐ（ｉ；２）、Ｐ（ｉ；３）が接続されている。また、ｊ番目の行（ｊは１以上ｍ以下の整数）に配置されているｎ個のメモリセルを構成するメモリトランジスタ（１，ｊ）、（２，ｊ）〜（ｎ，ｊ）は、コントロールゲート電極にワード線Ｗｊが接続されている。
【０１３２】
このように構成された本願発明の不揮発性メモリの動作方法について述べる。本願発明では、実施の形態で説明したように、書き込みと消去はフローティングゲート電極とピニング領域間のトンネル電流によって行い、読み出し方法は１値／ＦＧ方式または１ビット／ＦＧ方式を用いることができる。１値／ＦＧ方式の場合、本実施例の不揮発性メモリは各メモリセルに４値、つまり２ビットのデータを格納することができるので、ｍ×ｎ×２ビットの記憶容量を有する。また、１ビット／ＦＧ方式の場合、本実施例の不揮発性メモリは各メモリセルに３ビットを格納することができるので、ｍ×ｎ×３ビットの記憶容量を有する。
【０１３３】
なお、本願発明の不揮発性メモリでは、トンネル電流による書き込みを行うため、ホットエレクトロン注入を行う従来のＮＯＲ型フラッシュメモリと比して、書き込みに必要な電流量は小さくてすむ。そのため、昇圧が容易であると共に、同時書き込みによる書き込みの高速化が可能となる。
【０１３４】
具体例として、図９におけるピニング型メモリトランジスタ（１，１）への書き込み、読み出し、およびメモリ全体の一括消去について説明する。
【０１３５】
まず、ピニング型メモリトランジスタ（１，１）を構成するサブメモリトランジスタ（１，１；１）への書き込みを行う場合は、ソース電位Ｖｓ、ビット線Ｂ１〜ＢｎをＧＮＤに落し、ワード線Ｗ１に正電圧（例えば６Ｖ）、ピニング線Ｐ（１；１）に負電圧（例えば−６Ｖ）を印加する。また、Ｐ（１；１）以外のピニング線には０Ｖを印加する。その結果、サブメモリトランジスタ（１，１；１）のフローティングゲート−ピニング領域間にのみ高い電位差（約１２Ｖ）が生じ、トンネル電流によるフローティングゲートへの電荷注入（つまり書き込み）が行われる。ピニング型メモリトランジスタ（１，１）を構成する他のサブメモリトランジスタ（１，１；２）、（１，１；３）への書き込みも全く同様に行うことができる。
【０１３６】
次に、メモリトランジスタ（１，１）からの１値／ＦＧ方式の読み出しについて説明する。まず、ソース電位Ｖｓおよびピニング線Ｐ（１；０）〜Ｐ（１；３）をＧＮＤに落し、ワード線Ｗ１に所定の電位を印加する。その結果、メモリトランジスタ（１，１）において、フローティングゲート電極に電荷が蓄積されていないサブメモリトランジスタがオンの状態となり、フローティングゲート電極に電荷が蓄積されているサブメモリトランジスタがオフの状態となる。つまり、メモリトランジスタ（１、１）において形成されるチャネル幅の総和は、電荷が蓄積されていないフローティングゲート電極の数に比例する。このようにして、メモリトランジスタ（１、１）に格納された４値のデータをビット線Ｂ１から読み出す。
【０１３７】
次に、メモリトランジスタ（１，１）からの１ビット／ＦＧ方式の読み出しについて説明する。最初に、サブメモリトランジスタ（１，１；１）から選択的に１ビットの情報を読み出す方法を述べる。まず、ソース電位Ｖｓおよびピニング線Ｐ（１；０）、Ｐ（１；１）をＧＮＤに落し、ピニング線Ｐ（１；２）、Ｐ（１；３）に−５Ｖ、ワード線Ｗ１に所定の電位を印加する。その結果、１行目のメモリトランジスタにおいて、サブメモリトランジスタ（１，１；１）以外は全てオフの状態となる。また、サブメモリトランジスタ（１，１；１）は、フローティングゲート電極に電荷が蓄積されていなければオンの状態となり、フローティングゲート電極に電荷が蓄積されていればオフの状態となる。従って、サブメモリトランジスタ（１，１；１）に格納された１ビットのデータをビット線Ｂ１から読み出すことが可能となる。全く同様にして、サブメモリトランジスタ（１，１；２）、（１，１；３）からも、１ビットの情報を読み出すことが可能であり、メモリトランジスタ（１；１）から３ビットの情報を読み出すことが可能となる。
【０１３８】
なお、所定の電圧は、消去された状態（フローティングゲート電極に電子が蓄積されていない状態）におけるしきい値電圧と書き込まれた状態（フローティングゲート電極に電子が蓄積された状態）におけるしきい値電圧の間に設定すればよい。例えば、消去された状態のメモリトランジスタが０．５Ｖ以上３．５Ｖ以下のしきい値電圧を有し、書き込まれた状態のメモリトランジスタが、６．５Ｖ以上のしきい値電圧を有する場合には、所定の電圧として例えば５Ｖを用いることができる。
【０１３９】
なお、書き込み時および読み出し時において選択されていない信号線Ｂ２〜Ｂｎ、Ｗ２〜Ｗｍ、Ｐ（２；ｉ）〜Ｐ（ｎ；ｉ）（ｉ＝０〜３）の電位は全て０Ｖであるとする。
【０１４０】
メモリ全体の一括消去を行う場合、ソース電位Ｖｓ、ビット線Ｂ１〜Ｂｎおよびワード線Ｗ１〜ＷｍをＧＮＤに落す。そして、ピニング線Ｐ（１；１）〜Ｐ（ｎ；３）に正電圧（例えば１２Ｖ）を印加すると、全てのメモリトランジスタにおいて、フローティングゲート電極に蓄積されている電子がトンネル電流によってピニング領域へ注入され、記憶されていたデータが消去される。
【０１４１】
勿論、上述した動作電圧の値は、一例であって、その値に限られるわけではない。実際に、メモリトランジスタ（１，１）に印加される電圧は、メモリトランジスタの半導体活性層の膜厚やコントロールゲート電極とフローティングゲート電極との間の容量等に依存する。そしてメモリトランジスタ（１，１）の動作電圧もそれに従って変化する。
【０１４２】
なお、メモリトランジスタ（１，１）への書き込み時および読み出し時において、同じ列や行のメモリセルに電圧が印加されることによって、誤消去や誤書き込みが発生する場合がある。動作電圧は、このような書き込みストレスや読み出しストレスを最小限に抑え、誤消去や誤書き込みが発生しないように設定することが必要である。
【０１４３】
なお、本実施例の回路構成は、実施例１に示したプロセスを用いて作製することが可能である。また、実施例２に示したスプリットゲート構造のメモリトランジスタを用いることも可能である。
【０１４４】
（実施例６）
本実施例では、本願発明のピニング領域を用いた不揮発性メモリを構成するメモリセルの上面構造について説明する。図１０（Ａ）には、実施の形態に示したＮＯＲ型フラッシュメモリを構成するメモリセルアレイの上面図の一例が示されている。
【０１４５】
図１０（Ａ）に示した上面図は、実施例５に示したＮＯＲ型フラッシュメモリにおける２つの並列するピニング型メモリトランジスタを含む上面図であり、領域１００１はフィールド酸化膜、領域１００７がピニング領域である。図１０（Ａ）において、それぞれのピニング型メモリトランジスタ１００９は、フローティングゲート電極１００５を３つ有しており、３つのサブメモリトランジスタ１０１０によって構成されている。領域１０１１はソース領域、１０１２はドレイン領域であり、ドレイン領域１０１２と配線（ビット線）１００８とはコンタクトホール１００６を介して電気的に接続されている。また、メモリトランジスタ１００９のコントロールゲート電極はワード線１００４を兼ねている。
【０１４６】
なお、図１０（Ａ）において、実施例５に示した回路構造と合致するためには、２つのメモリトランジスタ間において、ピニング領域が電気的に接続されると同時に、ソース・ドレイン領域は電気的に非接続の状態である必要がある。このような構成とするためには、領域１００３に不純物を添加しないで実質的に真性な領域を形成するか、さらに好ましくは、酸素等の不純物を添加して電子と正孔の両方にとって非導電性の不純物領域を形成するとよい。特に、酸素を添加した場合ついて、線分ＢＢ’に関する断面図を図１０（Ｂ）に示す。図１０（Ｂ）において、領域１００７はピニング領域、領域１００３は酸素を添加した不純物領域である。
【０１４７】
なお、本実施例は実施の形態におけるメモリセルの上面図の一例である。勿論、実施例５において説明した回路構成と合致すれば、他のどのような上面図であっても構わない。
【０１４８】
（実施例７）
本実施例では本願発明の不揮発性メモリをワンチップ上に集積化されたＲＩＳＣプロセッサ、ＡＳＩＣプロセッサ等のマイクロプロセッサに適用した場合の例について説明する。
【０１４９】
図１１に示すのは、マイクロプロセッサの一例である。マイクロプロセッサは典型的にはＣＰＵコア１１０１、キャッシュメモリ１１０２（ＲＡＭでも良い）、クロックコントローラ１１０３、フラッシュメモリ１１０４、キャッシュコントローラ１１０５、シリアルインターフェース１１０６、Ｉ／Ｏポート１１０７等から構成される。
【０１５０】
勿論、図１１に示すマイクロプロセッサは簡略化した一例であり、実際のマイクロプロセッサはその用途によって多種多様な回路設計が行われる。
【０１５１】
図１１に示すマイクロプロセッサではＣＰＵコア１１０１、クロックコントローラ１１０３、キャッシュコントローラ１１０５、シリアルインターフェース１１０６、Ｉ／Ｏポート１１０７をＣＭＯＳ回路で構成している。
【０１５２】
また、フラッシュメモリ１１０４には本願発明の不揮発性メモリが利用され、ピニング型メモリトランジスタを用いた多値フラッシュメモリが用いられている。フラッシュメモリ１１０４の回路構成としては、実施例３または５に示した回路構成を用いることができるし、他の回路構成を用いることもできる。なお、キャッシュメモリ１１０２に本願発明の不揮発性メモリを利用することも可能である。
【０１５３】
なお、ＣＰＵコア１１０１、クロックコントローラ１１０３、キャッシュコントローラ１１０５、シリアルインターフェース１１０６、Ｉ／Ｏポート１１０７を構成するＣＭＯＳ回路に対して、本願発明で用いたピニング領域を設けることも有効である。ＣＭＯＳ回路を含むトランジスタにピニング領域を適用する場合の詳細については、例えば、特開平１０−６５１６２号公報を参照することができる。
【０１５４】
この様に、ピニング領域は回路設計の段階で必要箇所に設けることが可能であり、回路全体に利用するか、その一部に利用するかは実施者が適宜決定すれば良い。様々な性能が複合化されたハイブリッドＩＣに本願発明を適用する場合においては、この様な回路設計の自由度が非常に有効である。
【０１５５】
（実施例８）
本願発明の不揮発性メモリはデータの記憶・読み出しを行う記録媒体として、あらゆる分野の電子機器に組み込むことが可能である。本実施例では、その様な電子機器について説明する。
【０１５６】
本願発明の不揮発性メモリを利用しうる電子機器としては、ビデオカメラ、デジタルカメラ、プロジェクター（リア型またはフロント型）、ヘッドマウントディスプレイ、ゴーグル型ディスプレイ、ゲーム機、カーナビゲーション、パーソナルコンピュータ、携帯情報端末（モバイルコンピュータ、携帯電話または電子書籍等）などが挙げられる。それらの一例を図１２、１３に示す。
【０１５７】
図１２（Ａ）はディスプレイであり、筐体２００１、支持台２００２、表示部２００３等を含む。
本願発明は表示部２００３やその他の信号制御回路に接続され、画像信号の補正や処理データの記憶に利用される。
【０１５８】
図１２（Ｂ）はビデオカメラであり、本体２１０１、表示部２１０２、音声入力部２１０３、操作スイッチ２１０４、バッテリー２１０５、受像部２１０６で構成される。本願発明は内蔵のＬＳＩ基板に組み込まれ、画像データの記憶などの機能に利用される。
【０１５９】
図１２（Ｃ）はヘッドマウントディスプレイの一部（右片側）であり、本体２２０１、信号ケーブル２２０２、頭部固定バンド２２０３、表示部２２０４、光学系２２０５、表示装置２２０６等を含む。本願発明は表示装置２２０６やその他の信号制御回路に接続され、画像信号の補正や処理データの記憶に利用される。
【０１６０】
図１２（Ｄ）は記録媒体を備えた画像再生装置（具体的にはＤＶＤ再生装置）であり、本体２３０１、記録媒体２３０２、操作スイッチ２３０３、表示部（ａ）２３０４、表示部（ｂ）２３０５等で構成される。なお、この装置は記録媒体としてＤＶＤ（Digital Versatile Disc）、ＣＤ等を用い、音楽鑑賞や映画鑑賞やゲームやインターネットを行うことができる。本願発明は内蔵のＬＳＩ基板に組み込まれ、画像データや処理データの記憶などの機能に利用される。
【０１６１】
図１２（Ｅ）はゴーグル型ディスプレイであり、本体２４０１、表示部２４０２、アーム部２４０３を含む。本願発明は表示部２４０２やその他の信号制御回路に接続され、画像信号の補正や処理データの記憶に利用される。
【０１６２】
図１２（Ｆ）はパーソナルコンピュータであり、本体２５０１、筐体２５０２、表示部２５０３、キーボード２５０４等で構成される。本願発明は内蔵のＬＳＩ基板に組み込まれ、処理データや画像データの記憶に利用される。
【０１６３】
図１３（Ａ）は携帯電話であり、本体２６０１、音声出力部２６０２、音声入力部２６０３、表示部２６０４、操作スイッチ２６０５、アンテナ２６０６を含む。本願発明は内蔵のＬＳＩ基板に組み込まれ、電話番号を記録するアドレス機能などを付加するために利用される。
【０１６４】
図１３（Ｂ）は音響再生装置、具体的にはカーオーディオであり、本体２７０１、表示部２７０２、操作スイッチ２７０３、２７０４を含む。本願発明は内蔵のＬＳＩ基板に組み込まれ、画像データや処理データの記憶などの機能に利用される。また、本実施例では車載用オーディオを示すが、携帯型や家庭用の音響再生装置に用いても良い。
【０１６５】
以上の様に、本願発明の適用範囲は極めて広く、あらゆる分野の電子機器に適用することが可能である。また、本実施例の電子機器は実施例１〜６のどのような組み合わせからなる構成を用いても実現することができる。
【０１６６】
【発明の効果】
本願発明を利用することで、短チャネル効果などに代表される微細効果の影響を最小限に抑え、不揮発性メモリのさらなる微細化を進めることができる。
【０１６７】
また、本願発明によると、フローティングゲート電極の電荷蓄積量を制御する従来方式による多値技術とは全く異なる方式によってセルの多値化を行うことが可能であり、従来以上に多値化を進めることが可能となる。
【０１６８】
その結果、極めて集積密度の高い不揮発性メモリを実現することが可能となる。
【０１６９】
さらに、本願発明の集積密度の高い不揮発性メモリを搭載することによって、高機能、多機能化が可能な半導体装置を提供することができる。
【図面の簡単な説明】
【図１】 本願発明の不揮発性メモリの全体構成を示す図。
【図２】 本願発明の不揮発性メモリの部分構成を説明する上面図。
【図３】 本願発明の不揮発性メモリの部分構成を説明する断面図。
【図４】 エネルギーバンドの変化を説明するための図。
【図５】 本願発明の不揮発性メモリの等価回路を示す図。
【図６】 本願発明の不揮発性メモリの全体構成を示す図。
【図７】 本願発明の不揮発性メモリの回路構成を示す図。
【図８】 本願発明の不揮発性メモリの上面図。
【図９】 本願発明の不揮発性メモリの回路構成を示す図。
【図１０】 本願発明の不揮発性メモリの上面図。
【図１１】 本願発明の不揮発性メモリを用いた半導体回路を示す図。
【図１２】 本願発明の不揮発性メモリを用いた電子機器を示す図。
【図１３】 本願発明の不揮発性メモリを用いた電子機器を示す図。
【図１４】 本願発明の不揮発性メモリの等価回路を示す図。
【符号の説明】
１０１ シリコン基板
１０２ フィールド酸化膜
１０３ ソース領域
１０４ ドレイン領域
１０５ ピニング領域
１０６ チャネル形成領域
１０７ 第１のゲート絶縁膜
１０８ フローティングゲート電極
１０９ 第２のゲート絶縁膜
１１０ コントロールゲート電極
１１１ 層間膜
１１２ 配線[0001]
[Technical field to which the invention belongs]
The present invention relates to a semiconductor nonvolatile memory. In particular, the present invention relates to an electrically writable and erasable semiconductor non-volatile memory (hereinafter referred to as EEPROM or Electrically Erasable and Programmable Read Only Memory). In particular, the present invention relates to a semiconductor nonvolatile memory using a multi-value technology. The present invention is effective for a semiconductor nonvolatile memory having a channel length of 0.01 to 1 μm (preferably 0.01 to 0.5 μm). The present invention also relates to a semiconductor device having a semiconductor nonvolatile memory.
[0002]
In this specification, an electrically writable and erasable semiconductor non-volatile memory (EEPROM) literally refers to an entire semiconductor non-volatile memory capable of electrical writing and erasing, for example, a full-function EEPROM, Includes flash memory in its category. Unless otherwise specified, the nonvolatile memory and the semiconductor nonvolatile memory are used synonymously with the EEPROM. A semiconductor device refers to all devices that function by utilizing semiconductor characteristics. For example, an electro-optical device typified by a microprocessor, a liquid crystal display device, and an EL display device, and a microprocessor or an electro-optical device are mounted. In its category.
[0003]
[Prior art]
An electrically writable and erasable semiconductor non-volatile memory (EEPROM) is known as a memory representative of a semiconductor non-volatile memory. Since EEPROM is a non-volatile memory, unlike DRAM (Dynamic Random Access Memory) and SRAM (Static RAM), which represent other semiconductor memories, data is not lost even when the power is turned off. Further, when compared with a magnetic disk representing another nonvolatile memory, it has excellent characteristics in terms of integration density, impact resistance, power consumption, writing / reading speed, and the like. Because of these features, there has been an increasing trend to use EEPROM as a substitute for various memories such as a magnetic disk or DRAM.
[0004]
In particular, the integration density of EEPROM has been remarkably improved, and development is progressing at a very fast pace of about twice a year. Mass production of EEPROMs with gigabit capacity is expected to be realized soon, and there is also a tendency to pursue DRAMs in terms of integration. Technologies that support such an increase in integration density include circuit configuration improvement, miniaturization technology, and multi-value technology.
[0005]
First, in the circuit configuration, from a full-function EEPROM having a configuration of 2 transistors / cell to a flash memory having a configuration of 1 transistor / cell, and a cell area of 10F. ² From NOR type flash memory which requires (F is the minimum processing dimension), cell area 5F ² The integration density has been improved to a NAND flash memory that realizes the above.
[0006]
The miniaturization technology is the most important technology that promotes high integration, miniaturization, and cost reduction in almost all semiconductors such as IC, LSI, VLSI, and ULSI. As with other ICs and the like, the EEPROM is always developed with a miniaturization technique and is being developed along the scaling law.
[0007]
Furthermore, multi-value technology has been attracting attention in recent years as a method for improving the degree of memory integration. The multi-value technique is a technique for holding data of three or more values in one memory cell. As a conventional method, a method of controlling the charge accumulation amount of the floating gate and distinguishing between three or more states has been developed, and a quaternary flash memory has already been commercialized.
[0008]
[Problems to be solved by the invention]
As described above, the EEPROM has realized a dramatic increase in integration density by a circuit configuration, a miniaturization technique, and a multi-value technique. In order to further improve the degree of integration in the future, miniaturization technology and multi-value technology are considered to be increasingly important. However, there are many problems facing miniaturization technology and multi-value technology.
[0009]
Regarding the miniaturization, 0.12 to 0.15 μm is considered as the scaling limit of the EEPROM. There are several factors that determine the scaling limit. Typical examples include the fine processing limit, the short channel effect, and the reliability of the tunnel oxide film. In particular, in an EEPROM that requires an operating voltage higher than that of a normal transistor, the short channel effect is an important problem. Even if microfabrication is possible, the short channel effect does not function as a memory. Can happen.
[0010]
The short channel effect is a general term for various phenomena that occur when the channel length of a transistor is shortened, such as a punch-through phenomenon, deterioration of subthreshold characteristics (increase in S value), reduction in threshold voltage, etc. It has been known. Many of the short channel effects are caused by the depletion layer region extending from the drain region, and how to suppress the spread of the depletion layer region is a problem.
[0011]
In addition, in the case of multilevel, when using the conventional method for controlling the charge accumulation amount of the floating gate electrode, it is difficult to control the variation in the charge accumulation amount, good charge retention characteristics, and good read characteristics. It has been. Although a four-value flash memory is realized by the conventional method, it is considered that development of a multi-value technology different from the conventional method is necessary in order to further increase the number of values.
[0012]
The present invention has been made in view of the above problems. In the present invention, the short channel effect generated with miniaturization is effectively suppressed, and the multi-level cell is made different from the multi-level technology based on the conventional method for controlling the charge accumulation amount of the floating gate electrode. Do. Another object is to provide a non-volatile memory with extremely high integration density.
[0013]
[Means for Solving the Problems]
In the present invention, first, as a method for suppressing the short channel effect accompanying miniaturization, a plurality of local impurity regions are formed in an active region of a memory transistor. Specifically, impurity regions are formed in a stripe shape in the channel length direction. For the impurity region provided in a stripe shape, an impurity having a conductivity type opposite to that of the impurity used for the source region and the drain region is used.
[0014]
Note that in this specification, a region surrounded by a source region, a drain region, and an element isolation region is referred to as an active region, and the active region is further distinguished into an impurity region provided in a stripe shape and a channel formation region.
[0015]
It should be noted that the present invention is applied to an extremely fine nonvolatile memory. Specifically, the channel length is 0.01 to 1 μm (preferably 0.01 to 0.5 μm), the width of the impurity region is 0.01 to 1 μm (preferably 0.01 to 0.5 μm), and the channel formation region Is effective for a semiconductor nonvolatile memory having a width of 0.01 to 1 μm (preferably 0.01 to 0.5 μm).
[0016]
In a fine transistor, a technique for providing a local impurity region in an active region is disclosed in Japanese Patent Laid-Open No. 10-65162. The gazette states that the provision of a local impurity region in the active region suppresses the spread of the depletion layer from the drain region and suppresses the short channel effect while maintaining a high on-current. Has been.
[0017]
In this publication, the term “pinning” is defined in the sense of “suppression” because the effect of suppressing the depletion layer can be understood as if the depletion layer is pinned. An impurity region that pins the depletion layer is called a pinning region.
[0018]
In the present invention, as a more important point, a multi-value memory transistor is realized by applying a memory transistor using a pinning region. The present invention pays attention to the fact that the transistor structure using the pinning region has a plurality of channel formation regions, and realizes multi-valued memory transistors by assigning 1-value or 1-bit data to each channel formation region. To do.
[0019]
Note that in this specification, a memory transistor using a pinning region is particularly referred to as a pinning memory transistor when distinguished from a conventional memory transistor. In obvious cases, the pinning type memory transistor may be simply written as a memory transistor.
[0020]
The pinning type memory transistor of the present invention is characterized in that a floating gate electrode is provided on each of a plurality of channel formation regions via a first gate insulating film, and a potential is independently applied to the plurality of pinning regions. The point made into the structure which can be mentioned. With such a structure, it is possible to store single-value or single-bit data for each floating gate electrode (and thus each channel formation region).
[0021]
Here, an operation method of the pinning memory transistor will be briefly described. Multi-value data is written and erased by a tunnel current between the floating gate electrode and the pinning region. When the memory transistor is an n-channel type, electrons are injected into the selected floating gate electrode, and electrons are emitted from all the floating gate electrodes. When the memory transistor is a p-channel type, electrons are emitted from the selected floating gate electrode, and electrons are injected into all the floating gate electrodes.
[0022]
As a reading method, a case where 1-value data is assigned to each floating gate electrode (referred to as 1-value / FG method) and a case where 1-bit data is assigned (referred to as 1-bit / FG method) can be used. . The 1-value / FG method is a method of reading a current value proportional to the number of formed channels by applying an appropriate potential to the control gate electrode. When k floating gate electrodes (k is an integer of 1 or more) are provided, (k + 1) value data can be stored in one memory transistor. On the other hand, in the 1-bit / FG method, at the time of reading, an appropriate potential is applied to the control gate electrode, and at the same time, an appropriate potential difference is applied between the two pinning regions sandwiching the selected channel formation region and the other pinning regions. As a result, a current value reflecting the state of the selected floating gate electrode can be read, and 1-bit information can be stored per floating gate electrode.
[0023]
Note that the 1-bit / FG method uses a characteristic that the threshold voltage of the selected channel formation region shifts when a voltage is applied to the pinning region sandwiching the channel formation region. This characteristic is effective when the channel width is very narrow, and the width of the channel formation region is desirably 0.01 to 1 μm (preferably 0.01 to 0.5 μm).
[0024]
The configuration of the present invention is shown below.
[0025]
A nonvolatile memory including a memory transistor having at least a source region, a drain region, and an active region formed using a single crystal semiconductor,
The active region is composed of a plurality of impurity regions provided in stripes in the channel length direction and a plurality of intrinsic or substantially intrinsic channel forming regions sandwiched between the plurality of impurity regions,
A non-volatile memory is provided in which the memory transistor stores data of three or more values.
[0026]
A source region, a drain region, and an active region formed using a single crystal semiconductor, and a first gate insulating film, a plurality of floating gate electrodes, and a second gate insulating film on the active region; A non-volatile memory including a memory transistor formed by stacking a control gate electrode,
The active region is composed of a plurality of impurity regions provided in stripes in the channel length direction and a plurality of intrinsic or substantially intrinsic channel forming regions sandwiched between the plurality of impurity regions,
The plurality of floating gate electrodes are provided one on each of the plurality of channel formation regions via the first gate insulating film,
The control gate electrode is provided to overlap the plurality of floating gate electrodes via the second gate insulating film,
A non-volatile memory is provided in which the memory transistor stores data of three or more values.
[0027]
A source region, a drain region, and an active region formed using a single crystal semiconductor, and a first gate insulating film, a plurality of floating gate electrodes, and a second gate insulating film on the active region; A non-volatile memory including a memory transistor formed by stacking a control gate electrode,
The active region is composed of a plurality of impurity regions provided in stripes in the channel length direction and a plurality of intrinsic or substantially intrinsic channel forming regions sandwiched between the plurality of impurity regions,
The plurality of floating gate electrodes are provided one on each of the plurality of channel formation regions via the first gate insulating film,
The control gate electrode is provided to overlap the plurality of floating gate electrodes via the second gate insulating film,
The plurality of impurity regions can independently control the potential,
A non-volatile memory is provided in which the memory transistor stores data of three or more values.
[0028]
Each of the plurality of floating gate electrodes may partially overlap with one of the plurality of impurity regions through the first gate insulating film.
[0029]
The plurality of impurity regions provided in the active region may be continuously formed in one or both of the source region and the drain region.
[0030]
The plurality of impurity regions are preferably formed of an element selected from Group 13 or Group 15.
[0031]
Preferably, the plurality of impurity regions are made of an element selected from Group 13 or Group 15, and a depletion layer extending from the drain region toward the source region is suppressed by the plurality of impurity regions.
[0032]
The concentration of the element contained in the plurality of impurity regions is 1 × 10 ¹⁷ ~ 5x10 ²⁰ atoms / cm ^Three It is preferable that
[0033]
The channel length of the memory transistor is preferably 0.01 to 1 μm.
[0034]
The width of the plurality of impurity regions is preferably 0.01 to 1 μm.
[0035]
The width of the plurality of channel formation regions is preferably 0.01 to 1 μm.
[0036]
A semiconductor device using the nonvolatile memory as a recording medium is provided.
[0037]
A microprocessor is provided as the semiconductor device.
[0038]
As the semiconductor device, a display, a video camera, a head mounted display, a DVD player, a head mounted display, a personal computer, a mobile phone, and a car audio are provided.
[0039]
DETAILED DESCRIPTION OF THE INVENTION
In this embodiment, first, a typical element structure of the pinning memory transistor of the present invention is described, and then various effects (such as suppression of the short channel effect) by the pinning region and multi-valued pinning memory transistors are described. Give an explanation.
[0040]
First, a typical element structure of the pinning type memory transistor of the present invention will be described with reference to FIGS. FIG. 1 shows a top view and a cross-sectional view of a pinned memory transistor having a stack structure. FIG. 2 is a part of the top view shown in FIG. 1 and shows a source region, a drain region, and an active region.
[0041]
First, refer to FIG. In FIG. 1, a substrate 101 is a single crystal silicon substrate, and 102 is a field oxide film formed by the LOCOS method. Of course, the STI method and other element isolation methods may be used. Region 103 and region 104 are a source region and a drain region, respectively. When the memory transistor is an n-channel type, an element selected from group 15 (typically arsenic or phosphorus) is used. An element selected from (typically boron, gallium or indium) is added at a high concentration. Region 105 and region 106 are a pinning region and a channel formation region, respectively.
[0042]
Pinning region 105 is an impurity region having a conductivity type opposite to that of source region 103 and drain region 104. That is, an n-channel memory transistor is formed by adding an element selected from group 13 (typically boron, gallium, or indium). In particular, indium with low diffusion is preferable. A p-channel memory transistor is formed by adding an element selected from Group 15 (typically arsenic or phosphorus). In particular, arsenic with little diffusion is preferable. In the present invention, the concentration of these impurity elements is set to 1 × 10. ¹⁷ ~ 5x10 ²⁰ atoms / cm ^Three (Preferably 1 × 10 ¹⁸ ~ 5x10 ¹⁹ atoms / cm ^Three ) Adjust within the range.
[0043]
The implantation depth of the pinning region 105 is desirably deeper than at least the junction depth of the source region 103 and the drain region 104 in order to effectively suppress the short channel effect described later (see FIG. 1C). What is necessary is just to adjust the implantation depth of the pinning area | region 105 so that it may become 0.05-0.5 micrometer (preferably 0.2-0.3 micrometer).
[0044]
To describe the pinning region 105 and the channel forming region 106, which are key points of the present invention, in more detail, reference is made to FIG. The same symbols are used for regions corresponding to FIG. Further, the region 201 is a region sandwiched between the source region and the drain region, and the region 201 is referred to as an active region in this specification.
[0045]
Here, some terms are defined. First, the distance (corresponding to the length of the active region 201) between the source region 103 and the drain region 104 is the channel length (L), the width of the pinning region 105 is the pinning width (v), and the width of the channel formation region 106 Is defined as the channel width (w). The width of the active region 201 is defined as the total channel width (Wtotal). The total channel width is equal to the sum of the pinning width and the channel width. A direction along the channel length is referred to as a channel length direction, and a direction perpendicular to the channel length direction is referred to as a channel width direction.
[0046]
As shown in FIG. 2, one pinning region 105 is typically formed linearly in the channel length direction. A plurality of such pinning regions 105 are provided in a stripe shape. At this time, the two pinning regions located at both ends are preferably formed so as to include a side end portion of the active region 201 (an end portion where the active region and the field oxide film are in contact). A channel formation region is defined as a region surrounded by a source region, a drain region, and a pinning region (or field oxide film). The active region 201 includes a pinning region and a channel formation region.
[0047]
In the multilevel memory transistor according to the present invention, at least two channel formation regions are required in order to assign one-value or one-bit data to one channel formation region. In addition, providing a pinning region at the side end of the active region (the end where the active region and the field oxide film are in contact) has the effect of reducing the leakage current transmitted through the side end.
[0048]
In FIG. 2, the pinning regions are formed not only in the active region 201 but also in the source region 103 and the drain region 104. This is because it is necessary to draw out wiring from each pinning region 105 in the multi-value nonvolatile memory of the present invention. In the present invention, the pinning region crosses the source region 103 or the drain region 104 to lead out the wiring from each pinning region 105. However, the pinning region 105 may have a structure in which a potential is applied independently. Any structure may be used.
[0049]
An example of a cross-sectional structure of the drain region where the pinning region is formed is shown in FIG. The cross-sectional view shown in FIG. 3 is a cross-section regarding the line segment CC ′ of the memory transistor shown in FIG. 1A, and the same symbols are used for regions corresponding to FIG. In FIG. 3, the impurity concentration of the drain region 104 is formed higher than the impurity concentration of the pinning region 105, and the junction depth of the drain region 104 is shallower than the junction depth of the pinning region 105. With such a structure, the structure in which the pinning region 105 crosses the drain region 104 is realized without the drain region 104 being divided by the pinning region 105. Note that the same structure can be used when crossing the source region 103.
[0050]
With reference to FIG. 1 again, the description of the element structure of the memory transistor will be continued.
[0051]
In FIG. 1, a first gate insulating film 107, a floating gate electrode 108, a second gate insulating film 109, a control gate electrode 110, an interlayer film 111, and a wiring 112 are sequentially stacked on the active region described above. It has a structure.
[0052]
One floating gate electrode 108 is provided so as to overlap each channel formation region 106 with the first gate insulating film 107 interposed therebetween. The control gate electrode 110 is common to all the floating gate electrodes 108 and is provided so as to overlap with the second gate insulating film 109. That is, a plurality of memory transistors sharing the source region 103, the drain region 104, and the control gate electrode 110 are incorporated in one memory transistor. In this specification, a memory transistor incorporated in parallel with the pinning type memory transistor of the present invention is referred to as a sub-memory transistor.
[0053]
Each floating gate electrode 108 also has a structure overlapping with a part of the pinning region 105 with the first gate insulating film 107 interposed therebetween. Further, the structure is such that two or more floating gate electrodes do not overlap at the same time with respect to one pinning region. A region where the floating gate electrode and the pinning region overlap is called an overlap region.
[0054]
Note that the thickness of the first gate insulating film 107 is preferably 6 to 20 nm. The floating gate electrode 108 and the control gate electrode 110 are preferably made of a polycrystalline silicon layer. Of course, it is also possible to use a conductive layer such as a metal film instead of the polycrystalline silicon layer. SiO as interlayer film ₂ / SiN / SiO ₂ It is also effective to use a laminated film (referred to as ONO film) represented by
[0055]
The pinning type memory transistor shown in FIG. 1 has a structure having three floating gate electrodes, in other words, a structure having three sub memory transistors, but the present invention is not limited to this structure. In general, a structure having k floating gate electrodes (or sub-memory transistors) (k is an integer of 1 or more) may be used.
[0056]
The non-volatile memory of the present invention mainly has two excellent features by using the memory transistor having the element structure as described above. One is that a multi-valued memory transistor can be realized, which is extremely effective for high integration of a nonvolatile memory. The other one contributes to the performance improvement as a transistor, and of course, also contributes to the performance improvement in the memory transistor. In particular, the effect of suppressing the short channel effect is indispensable for further miniaturization, and is very important for high integration of nonvolatile memories.
[0057]
Therefore, the present invention is effective for a memory transistor having a very small size. Specifically, it is effective when the channel length (L) is 0.01 to 1 μm (preferably 0.01 to 0.5 μm). The pinning width may be 0.01 to 1 μm (preferably 0.01 to 0.3 μm). The channel width can correspond to any case, but in the present invention, since it is not necessary to flow a particularly large current, it may be 0.01 to 1 μm (preferably 0.01 to 0.5 μm).
[0058]
Before describing the effect of the pinning region, first, the energy band of the active region including the pinning region is considered. 4A and 4B schematically show energy band diagrams in the channel width direction of active regions in n-channel and p-channel pinning memory transistors, respectively. 4A and 4B, regions 401 and 403 represent pinning regions, and regions 402 and 404 represent channel formation regions, respectively.
[0059]
First, the channel formation regions 402 and 404 are intrinsic or substantially intrinsic. Therefore, the Fermi level Ef is located approximately at the center of the energy gap Eg.
[0060]
Note that the intrinsic region refers to a region to which an impurity element imparting N-type or P-type and an impurity element such as carbon, nitrogen, or oxygen is not intentionally added. For example, when an I-type silicon substrate (intrinsic silicon substrate) is produced by an advanced purification technique and used, an intrinsic channel formation region can be obtained. A substantially intrinsic region basically refers to an undoped single crystal semiconductor region. In addition, a region in which the conductivity type is intentionally offset by adding an impurity element of a reverse conductivity type and a region having one conductivity type in a range in which the threshold voltage can be controlled are included. For example, the dopant concentration is 5 × 10 ¹⁶ atoms / cm ^Three The following (preferably 5 × 10 ¹⁵ atoms / cm ^Three And the concentration of carbon, nitrogen and oxygen contained is 2 × 10 ¹⁸ atoms / cm ^Three The following (preferably 5 × 10 ¹⁷ atoms / cm ^Three It can be said that the single crystal silicon which is the following is substantially intrinsic. In this sense, a silicon wafer generally used in an IC is substantially intrinsic unless impurities are intentionally added during the process.
[0061]
On the other hand, the pinning regions 401 and 403 are formed by an element selected from group 13 in the n-channel type memory transistor and by an element selected from group 15 in the p-channel type memory transistor, respectively. An element selected from group 13 supplies an electron acceptor level, and an element selected from group 15 supplies an electron donor level. Therefore, in an n-channel memory transistor, the energy band of the pinning region 401 is a conduction band. In the p-channel memory transistor, the energy band of the pinning region 403 is shifted to the valence band side. As a result, a schematic diagram of the energy band as shown in FIG. 4 is obtained.
[0062]
As can be seen from FIG. 4, in both cases of the n-channel type and the p-channel type, the pinning region forms an energy barrier for majority carriers (electrons in the n-channel type and holes in the p-channel type) and vice versa. In addition, an energy stable region is formed for minority carriers (holes in the n-channel type and electrons in the p-channel type). Note that the energy barrier height ΔE varies depending on the concentration of the impurity element added. In the present invention, the concentration of the impurity element is set to 1 × 10. ¹⁷ ~ 5x10 ²⁰ atoms / cm ^Three (Preferably 1 × 10 ¹⁸ ~ 5x10 ¹⁹ atoms / cm ^Three ) Adjust within the range.
[0063]
Since the pinning region forms an energy barrier for majority carriers, the majority carriers move preferentially in the respective channel formation regions. As a result, when a striped pinning region is provided from the source region to the drain region, an effect is obtained in which a majority carrier moving path is defined by the pinning region. In the multi-value memory transistor, 1-value or 1-bit data is assigned to the plurality of movement paths.
[0064]
First, the effect of the memory transistor as a transistor will be briefly described as an effect of the pinning region. Note that a method of providing a pinning region in a transistor is disclosed in Japanese Patent Laid-Open No. 10-65162, and the same gazette can be referred to for details.
[0065]
First, the pinning region acts as a stopper for the depletion layer spreading from the drain side, and effectively suppresses the spread of the depletion layer. Therefore, the punch-through phenomenon due to the spread of the depletion layer is prevented. In addition, since an increase in depletion layer charge due to the spread of the depletion layer is suppressed, the subthreshold characteristics are improved, and a decrease in threshold voltage can be avoided.
[0066]
Second, the threshold voltage can be increased by reducing the channel width. As already mentioned, the pinning region forms an energy barrier for majority carriers. When the channel width is narrowed, the penetration of this energy barrier into the channel formation region cannot be ignored, and the threshold voltage increases. This is a phenomenon known as one of the narrow channel effects. The narrow channel effect becomes more prominent as the channel width becomes narrower.
[0067]
As described above, in the present invention, the short channel effect is suppressed, the intensity of the narrow channel effect is controlled by freely designing the impurity concentration and the channel width added to the pinning region, and the threshold voltage is adjusted. Is possible.
[0068]
Thirdly, in the present invention, there is an advantage that the channel formation region is formed of a substantially intrinsic region. Since the region in which carriers move is substantially intrinsic, the decrease in mobility due to impurity scattering is extremely small, and high carrier mobility can be obtained. As a result, in the nonvolatile memory according to the present invention, in particular, the reading time is significantly shortened.
[0069]
Fourth, the pinning region has a role of preventing parasitic bipolar conduction due to impact ionization (impact ionization). This is because the pinning region forms an energy stable region for minority carriers, and minority carriers generated by impact ionization immediately move into the pinning region and are extracted to the wiring. Therefore, unlike the conventional case, the parasitic potential is not turned on by changing the potential of the substrate, and the source-drain breakdown voltage is not lowered.
[0070]
Thus, by forming the pinning region, various excellent effects including suppression of the short channel effect can be obtained.
[0071]
Next, multi-valued pinning memory transistors, which is a key point of the present invention, will be described. The memory transistor of the present invention is a multi-value memory transistor that applies a plurality of channel formation regions formed by pinning regions.
[0072]
Its features include a structure in which a potential can be applied independently by pulling out wiring from each pinning region, and a region in which each floating gate electrode partially overlaps with the pinning region via the first gate insulating film (over (Wrap area) is formed (see FIG. 1).
[0073]
Therefore, the pinning type memory transistor shown in FIG. 1 can be expressed by an equivalent circuit as shown in FIG. In FIG. 5, PT is a pinning memory transistor, and ST1, ST2, and ST3 are sub-memory transistors. Vd is a drain voltage, Vs is a source voltage, Vcg is a control gate voltage, and Vp0, Vp1, Vp2 and Vp3 are potentials of a pinning region (hereinafter referred to as pinning potential).
[0074]
The pinning type memory transistor shown in FIG. 5 includes three sub memory transistors, but the present invention is not limited to this structure. In general, a structure having k sub-memory transistors (k is an integer of 1 or more) may be used.
[0075]
Next, the operation method of the multilevel memory transistor of the present invention will be described with reference to FIG. In the multilevel memory transistor of the present invention, data is written and erased by a tunnel current. As a reading method, a method of assigning 1 value to one floating gate electrode (1 value / FG method) and a method of assigning 1 bit (1 bit / FG method) will be described. The 1-bit / FG method is advantageous in the degree of integration. On the other hand, the 1-value / FG method is excellent in reading margin and reliability.
[0076]
In the multilevel memory transistor of the present invention, electrons are injected into and discharged from the floating gate electrode by a tunnel current. When the memory transistor is an n-channel type, electrons are injected into individual floating gates, and electrons are emitted all at once from the floating gate electrode constituting one memory transistor. Specifically, electrons are injected by applying a potential difference between the control gate electrode and a pinning region that partially overlaps the selected floating gate electrode, and electrons are emitted from the control gate electrode and one or more This is done by applying a potential difference to the pinning region. When electrons are emitted, a p-type inversion layer is formed in the channel formation region, so that electrons are emitted from all floating gate electrodes.
[0077]
When the memory transistor is a p-channel type, electrons are emitted from individual floating gates, and electrons are injected into all floating gate electrodes. That is, electrons are emitted by applying a potential difference between the control gate electrode and the pinning region that partially overlaps the selected floating gate electrode, and electron injection is performed between the control gate electrode and one or more pinning regions. By applying a potential difference between the two. At the time of electron injection, since an n-type inversion layer is formed in the channel formation region, electrons are injected into all the floating gate electrodes.
[0078]
As a reading method, two methods are described: one value data is assigned to each floating gate electrode (1 value / FG method) and one bit data is assigned (1 bit / FG method). In the 1 value / FG method, an appropriate potential is applied to the control gate electrode during reading. As a result, a channel is formed in the channel formation region depending on the charge accumulation state of the floating gate electrode, and a current amount proportional to the number of formed channels is read. In the 1-value / FG method, (k + 1) -value data can be stored for k floating gate electrodes (k is an integer of 1 or more).
[0079]
In the 1-bit / FG method, it is necessary to apply an appropriate potential between the two pinning regions sandwiching the selected channel formation region and another pinning region at the same time as applying an appropriate potential to the control gate electrode. This reading method applies the same effect as the change in threshold voltage seen in the narrow channel effect. When a voltage is applied to two pinning regions sandwiching the channel formation region, the threshold value of the channel formation region is obtained. The characteristic that the voltage shifts is used. For example, in the case of an n-channel memory transistor, a negative voltage is applied to a pinning region other than two pinning regions that sandwich the channel formation region to be selected. In the case of a p-channel memory transistor, the channel formation region to be selected is sandwiched. A positive voltage is applied to a pinning region other than the two pinning regions. As a result, it is possible to apply a voltage to the control gate electrode so that all non-selected channel formation regions are turned off, and the selected channel formation region is turned on or off reflecting the charge accumulation state of the floating gate electrode. Thus, 1-bit information can be stored per one floating gate electrode.
[0080]
Note that in the 1-bit / FG method, the channel width is particularly required to be narrow, and the width of the channel formation region is desirably 0.01 to 1 μm (preferably 0.01 μm to 0.5 μm).
[0081]
Based on the equivalent circuit shown in FIG. 5, examples of operating voltages of the n-channel type and p-channel type multilevel memory transistors of the present invention are summarized in Tables 1 and 2, respectively. Tables 1 and 2 show operating voltages of pinning type memory transistors having three floating gate electrodes corresponding to the equivalent circuit shown in FIG. 5. Generally, k (k is an integer of 1 or more). The same operation may be performed when the floating gate electrode is provided. Of course, the operating voltages in Tables 1 and 2 are examples, and the operating voltages need not be limited to the values in Tables 1 and 2.
[0082]
[Table 1]

[0083]
[Table 2]

[0084]
The multi-value nonvolatile memory of the present invention can be applied to various EEPROMs. The present invention can be applied to both types of EEPROMs, which are a full-function EEPROM capable of erasing data for each memory element and a flash memory that performs batch erasure for each block. When applied to a flash memory, it is possible to further adopt a circuit configuration corresponding to a NOR type, a NAND type, or another known type. However, the present invention is different from the conventional circuit configuration in that it has wiring for controlling multiple values called pinning lines (see Examples 3 and 5).
[0085]
Although the stack type memory transistor has been described in this embodiment, the present invention can be applied to a memory transistor having a split gate structure (see Embodiment 2).
[0086]
Further, the memory transistor of the present invention can also perform hot electron writing. Specifically, impact ionization may be generated only in the selected channel formation region by applying a voltage to two pinning regions sandwiching the channel formation region to be written. For example, in the case of the n-channel type, in order to increase the direction electric field in the channel length direction of the drain region, the potentials of the two pinning regions may be higher than the potentials of the other pinning regions.
[0087]
In addition, by forming an overlap region between the floating gate electrode and the source region or the drain region, it is possible to inject and emit electrons by a tunnel current from the source side or the drain side.
[0088]
In the present invention, the pinning region is also applied to a transistor constituting a drive circuit and other peripheral circuits integrally formed with a memory transistor, or a transistor constituting another circuit integrally formed with a memory portion in a semiconductor device. It is effective to provide As a result, even in a circuit other than the memory cell, it is possible to suppress the short channel effect and obtain the effect of other pinning regions.
[0089]
Example 1
In this example, a method for manufacturing a nonvolatile memory of the present invention will be described. The pinning type memory transistor of the present invention is basically composed of a source region, a drain region, a channel formation region, a floating gate electrode, and a control gate electrode, except for the pinning region. A known manufacturing method can be used.
[0090]
In particular, as in the conventional method for manufacturing a memory transistor, it is preferable that the first gate insulating film is a high-quality film formed by a thermal oxidation process. ₂ / SiN / SiO ₂ It is desirable to use a laminated film (referred to as ONO film) represented by Of course, other insulating films can be used.
[0091]
From the viewpoint of the manufacturing method, the pinning type memory transistor of the present invention is characterized in that an impurity region called a pinning region is formed and that a memory transistor having an extremely small element size is targeted. For example, with regard to the pinning region, there are features such as a structure that partially overlaps with the floating gate electrode and the first gate insulating film, and a structure that crosses the source region and the drain region. In terms of the element size, the processing dimensions of the floating gate electrode, the pinning region, and the channel formation region typically have to be 0.01 to 1 μm. The overlap structure between the floating gate electrode and the pinning region requires a finer structure.
[0092]
In general, the self-alignment method is very effective for producing such an extremely fine structure. Also in the pinning type memory transistor of the present invention, it is desirable to use the self-alignment method for forming the pinning region, the overlap region, the source region and the drain region. Specifically, first, the pinning region is formed by first micro-fabricating the floating gate electrode, and using this as a mask, a self-alignment method is formed by an ion implantation method. In particular, when an overlap region is formed between the floating gate electrode and the pinning region, oblique implantation by an ion implantation method may be performed.
[0093]
In the microfabrication of the floating gate electrode, a resist mask pattern can be formed by a stepper or a scanning exposure apparatus for patterns up to about 0.15 μm. On the other hand, when the pattern size is 0.15 μm or less, it is necessary to form a mask pattern by an electronic drawing method. After the mask pattern is formed, dry etching using ICP or the like is preferably performed.
[0094]
The implantation of impurities into the pinning region may be divided into a high energy implantation in a direction perpendicular to the substrate and a low energy implantation in a diagonal direction, or once a high energy implantation in a diagonal direction is performed on the substrate. The method performed in
[0095]
The impurity element added to the pinning region is preferably activated by furnace annealing, laser annealing, lamp annealing, or the like. In particular, activation by the RTA method is preferable in order to minimize the diffusion of impurities.
[0096]
Next, formation of a pinning region in a region in which wiring is drawn from the source region, drain region, and pinning region will be described. An example of a cross-sectional structure when the pinning region crosses the drain region is shown in FIG. 3 and described in the embodiment. Since the pinning region has a fine structure, it is preferable to produce the pinning region by the self-alignment method. Therefore, the floating gate electrode is finely processed into an appropriate shape even in a region where a pinning region needs to be formed other than the active region, such as a source region and a drain region. And it is preferable to form simultaneously with the pinning area | region in an active region by the ion implantation method by using a floating gate electrode as a mask.
[0097]
Eventually, the floating gate electrode other than the active region is removed. The resist may be used as a mask, or the control gate electrode may be removed as a mask.
[0098]
Impurity doping into the source region and the drain region is performed by a self-alignment method using the control gate electrode as a mask. At this time, the depth of implantation into the source / drain regions is adjusted to be shallower than the depth of the pinning region. Further, the impurity concentration of the source / drain region needs to be higher than the impurity concentration of the pinning region so that the source / drain region is not divided by the pinning region. In this way, the cross-sectional structure shown in FIG. 3 is formed. It should be noted that making the depth of implantation into the source / drain regions shallower than the depth of the pinning region is important for the purpose of effectively suppressing the spread of the depletion layer in the drain region.
[0099]
In the case where the source region and the drain region are divided by the pinning region, after forming the contact hole, first, impurities having the same conductivity type as the source / drain region (typically, n-type is phosphorus, p-type is used). After forming a polysilicon film containing boron, a source film and a drain region contact can be made by forming a metal film such as aluminum.
[0100]
In this embodiment, in the manufacturing method of the pinning type memory transistor of the present invention, the manufacturing method of the pinning region and the ultrafine processing have been described. By appropriately incorporating these processes into a known memory transistor manufacturing process, the nonvolatile memory of the present invention can be manufactured. Of course, any manufacturing method may be used as long as it is a method for manufacturing the structure of the pinning memory transistor described in the embodiment mode or the circuit structure described in Examples 3 and 5.
[0101]
(Example 2)
In this example, a configuration example of a pinning memory transistor having a split gate structure will be described with reference to FIG. 6 as an example different from the configuration of the pinning memory transistor described in the embodiment mode (see FIG. 1).
[0102]
Note that the region excluding the structures of the floating gate electrode and the control gate electrode has the same structure as that of the stacked gate type memory transistor shown in FIG. 1, and the reference numerals used in the description of FIG. 1 are used. That is, in FIG. 6, the description with reference to FIG. In this embodiment, a floating gate electrode and a control gate electrode will be particularly described.
[0103]
The split gate structure refers to a structure in which a part of the control gate electrode 610 is directly stacked on the active region via a first gate insulating film as shown in FIG. Accordingly, the channel formation region is divided into a region where the floating gate electrode 608 is formed via the first gate insulating film and a region where the control gate electrode is formed.
[0104]
FIG. 14 shows an equivalent circuit of the pinning memory transistor having the split gate structure shown in FIG. The operation method of the split gate structure pinning memory transistor may be the same as the operation method of the stack structure pinning memory transistor. The advantage of using the split gate structure is that a region in which a control gate electrode is formed on the channel formation region functions as a selection transistor. That is, there is a function of increasing the selectivity of the pinning memory transistor and a function of maintaining an off state even when the non-selected cell is in an overerased state during reading.
[0105]
Note that the split gate structure pinning memory transistor can be manufactured by the same process as that of the stack structure pinning memory transistor. That is, it can be manufactured using the process shown in Embodiment 1.
[0106]
(Example 3)
In this embodiment, a circuit in which the multilevel memory transistor of the present invention is applied to a NAND flash memory will be described. However, the present invention is different from the conventional NAND type flash memory in that it has wiring for controlling multi-values called pinning lines, and the write, erase, and read methods are different accordingly.
[0107]
FIG. 7 is a circuit diagram of a NAND type memory cell array in which memory cells are arranged in a matrix of 8 vertical × n horizontal (n is an integer of 1 or more). Each memory cell is composed of one pinning type memory transistor surrounded by a square broken line.
[0108]
In the present embodiment, the case where each pinning type memory transistor has three floating gate electrodes will be described. However, in general, the present embodiment also includes a case where k floating gate electrodes (k is an integer of 1 or more) are included. It is easy to apply. Further, in this embodiment, a description will be given of a vertical 8 × n horizontal memory cell array, but it is not necessary to be limited to this configuration. The memory transistors (1, 1) to (n, m) may be either n-channel type or p-channel type conductive transistors, but in this embodiment, they are n-channel type transistors.
[0109]
In FIG. 7, pinning memory transistors (for example, (1, 1) to (1, 8) in the first column) arranged in the same column are connected in series. In addition, in the pinning memory transistors (for example, (1, 1) to (n, 1) in the first row) arranged in the same row, each control gate electrode is connected to one word line W1. .
[0110]
Note that connecting the pinning memory transistors in series means that the sub memory transistors and the pinning regions constituting the pinning memory transistors are connected in series. The control gate electrode of the pinning type memory transistor is common to all the sub memory transistors constituting the pinning type memory transistor.
[0111]
The selection transistors (1, 0) and (1, 9) are connected in series to both ends of eight pinning type memory transistors (for example, (1, 1) to (1, 8) in the first column) connected in series. It is connected to the. That is, selection transistors (1, 0) to (n, 0) are provided above the memory cells in the first row, and selection transistors (1, 9) are provided below the memory cells in the eighth row. To (n, 9) are arranged. Bit lines B1 to Bn are connected to one of the remaining source and drain electrodes of the selection transistors (1, 0) to (n, 0), and a selection gate line S1 is connected to the gate electrode. . Further, a common source potential Vs is applied to the remaining one of the source and drain electrodes of the selection transistors (1, 9) to (n, 9), and a selection gate line S2 is connected to the gate electrode. ing.
[0112]
The four pinning regions of the eight pinning memory transistors connected in series (for example, (1,1) to (1,8) in the first column) are respectively connected to the pinning lines P (1; 0), P (1; 1), P (1; 2), and P (1; 3).
[0113]
An operation method of the nonvolatile memory of the present invention configured as described above will be described. In the present invention, as described in the embodiment, writing and erasing are performed by a tunnel current between the floating gate electrode and the pinning region, and a reading method can be a one-value / FG method or a one-bit / FG method. In the case of the 1-value / FG method, the nonvolatile memory of this embodiment can store 4-value, that is, 2-bit data in each memory cell, and thus has a storage capacity of 8 × n × 2 bits. In the case of the 1-bit / FG method, the nonvolatile memory of this embodiment can store 3 bits in each memory cell, and thus has a storage capacity of 8 × n × 3 bits. Note that writing and erasing will be described with respect to simultaneous writing in one row and batch erasing.
[0114]
In the conventional NAND flash memory, the writing method and the erasing method are performed by a tunnel current between the floating gate electrode and the entire channel formation region (well), but it is not necessary to control such a well potential in the present invention. . In addition, since the tunnel current uses an overlap region, a coupling ratio can be increased as compared with the conventional method using the entire channel region, and a low operating voltage can be realized.
[0115]
In this embodiment, the “0” state means a state where charges are accumulated in the floating gate electrode of the memory transistor, and the “1” state means a state where no charge is accumulated in the floating gate electrode of the memory transistor. Point to. The threshold voltage of the memory transistor in the “0” state is 0.5 V to 3 V, and the threshold voltage of the memory transistor in the “1” state is −1 V or less.
[0116]
First, one line simultaneous writing will be described. As a specific example, the pinning type memory transistors (1, 1) to (n, 1) in the first row are taken, and “0” is set to the sub memory transistors (1, 1; 1) constituting the memory transistor (1, 1). "1" is set to the other sub memory transistors (1, 1; 2) and (1, 1; 3), and all the sub memory transistors constituting the memory transistors (2, 1) to (n, 1) are set. A case where “1” is written will be described. Note that the state is all “1” immediately before writing.
[0117]
First, the pinning line P (1; 1) and the source potential Vs are dropped to GND, and the pinning lines P (1; 0), P (1; 2), and P (1; 3) are set to 7V. Further, 0V is applied to the selection gate lines S1 and S2, respectively, and the selection transistors (1, 0) to (n, 0) and (1, 9) to (n, 9) are turned off. Then, 15V is applied to the word line W1, 7V is applied to the word lines W2 to W8, and 0V is applied to the bit lines B1 to Bn.
[0118]
As a result, in the memory transistor (1, 1), a high voltage (about 15 V) is applied only between the floating gate and the pinning region of the sub memory transistor (1, 1; 1), and the charge to the floating gate due to the tunnel current is applied. Implantation is performed and “0” is written. At most, a potential difference of 8 V is generated between the pinning region and the floating gate constituting the sub memory transistors (1, 1; 2), (1, 1; 3) and the memory transistors (2, 1) to (n, 1). And no charge injection into the floating gate. That is, the sub memory transistors (1, 1; 2) and (1, 1; 3) and the memory transistors (2, 1) to (n, 1) remain in the “1” state. For the memory transistors other than the first row, only a potential difference of 7 V is generated at most between the floating gate and the pinning region, and no charge is injected into the floating gate. In this way, one line is written simultaneously.
[0119]
Next, reading of the one-value / FG method from the memory transistor (1, 1) will be described. First, the pinning lines P (1: 0) to P (1; 3) are dropped to GND, and 0V is applied to the word line W1 and 5V is applied to the word lines W2 to W8. As a result, all the memory transistors in the second to eighth rows are turned on. In the memory transistor in the first row, the sub memory transistor in the “1” state is turned on, and the sub memory transistor in the “0” state is turned off. That is, the current amount of the eight memory transistors connected in series is determined by the number of sub-memory transistors in the “1” state constituting the memory transistor (1, 1) in the first row. Then, 5V is applied to the selection gate lines S1 and S2 to turn on the selection transistor, and the source potential Vs is lowered to GND, whereby the data is stored in the memory transistor (1, 1) through the bit line B1. It is possible to read the four-valued data.
[0120]
Next, reading of the 1-bit / FG method from the memory transistor (1, 1) will be described. First, a method of selectively reading 1-bit information from the sub memory transistor (1, 1; 1) will be described. First, the pinning lines P (1; 0) and P (1; 1) are dropped to GND, and −5V is applied to the pinning lines P (1; 2) and P (1; 3), and 0V is applied to the word line W1. As a result, all the memory transistors in the first row are turned off except for the sub memory transistors (1, 1; 1). The sub memory transistor (1, 1; 1) is turned on when it is “1”, and is turned off when it is “0”. On the other hand, 5V is applied to the word lines W2 to W8. As a result, in the memory transistors in the second to eighth rows, all the sub memory transistors connected in series with the sub memory transistors (1, 1; 1) are turned on. As a result, the conduction and non-conduction of the eight memory transistors connected in series is determined by the state of the sub memory transistor (1, 1; 1). Then, 5V is applied to the selection gate lines S1 and S2 to turn on the selection transistor, and the source potential Vs is lowered to GND, whereby the sub memory transistor (1, 1; 1) is transmitted through the bit line B1. ) Data can be read out. In exactly the same manner, 1-bit information can be read from the sub-memory transistors (1, 1; 2) and (1, 1; 3), and 3-bit information can be read from the memory transistors (1; 1). Can be read out.
[0121]
When performing batch erase, all word lines W1 to W8 are set to 0V, and all pinning lines P (1; i) to P (n; i) (i = 0 to 3) are set to 15V. As a result, a high potential difference is generated between the floating gate electrode and the pinning region, and erasing by a tunnel current is performed. Note that the potentials of the selection gate lines S1 and S2 are determined so that the selection transistor is turned off.
[0122]
Of course, the value of the operating voltage described above is an example, and is not limited to that value. Actually, the voltage applied to the memory transistor depends on the thickness of the semiconductor active layer of the memory transistor, the capacitance between the control gate electrode and the floating gate electrode, and the like. The operating voltage of the memory transistor changes accordingly.
[0123]
Note that erroneous erasure or erroneous writing may occur when a voltage is applied to memory cells in the same column or row at the time of writing to or reading from the memory transistor. The operating voltage needs to be set so as to minimize such writing stress and reading stress and prevent erroneous erasure and erroneous writing.
[0124]
Note that the circuit configuration of this embodiment can be manufactured by using the process shown in Embodiment 1. In particular, with respect to the select transistor, the floating gate electrode may be processed by self-alignment to form the pinning region after etching the floating gate electrode in the same manner as other sub-memory transistors.
[0125]
Example 4
In this embodiment, an upper surface structure of a memory cell constituting a nonvolatile memory using a pinning region of the present invention will be described. FIG. 8 shows an example of a top view of the memory cell array constituting the NAND flash memory shown in the third embodiment.
[0126]
The top view shown in FIG. 8 is a top view of a memory cell array in which two pinning type select transistors 810 and eight pinning type memory transistors 811 (only three are shown) are connected in series, and a region 801 is a field oxide film. , Region 808 is a pinning region. In FIG. 8, each pinning type memory transistor 811 has three floating gate electrodes 805 and is constituted by three sub memory transistors 812. The control gate electrode of the memory transistor 811 also serves as the word line 804, and the gate electrode of the selection transistor 810 also serves as the selection line 803. The drain region of the selection line transistor and the wiring (bit line) 809 are electrically connected through a contact hole 807.
[0127]
Note that this example is an example of a top view of the memory cell in the embodiment. Of course, any other top view may be used as long as it matches the circuit configuration described in the third embodiment.
[0128]
(Example 5)
In this embodiment, a circuit in which the multilevel memory transistor of the present invention is applied to a NOR flash memory will be described. However, the present invention is different from the conventional NOR type flash memory in that it has wiring for controlling multi-values called pinning lines, and the writing, erasing and reading methods are different accordingly.
[0129]
FIG. 9 is a circuit diagram of a NOR type memory cell array in which memory cells are arranged in a matrix of m rows and n columns (m and n are integers of 1 or more, respectively). Each memory cell is composed of one pinning type memory transistor surrounded by a square broken line.
[0130]
In the present embodiment, the case where each pinning type memory transistor has three floating gate electrodes will be described. However, in general, the present embodiment also includes a case where k floating gate electrodes (k is an integer of 1 or more) are included. It is easy to apply. The memory transistors (1, 1) to (n, m) may be either n-channel type or p-channel type conductive transistors, but in this embodiment, n-channel transistors are used.
[0131]
In FIG. 9, pinning type memory transistors (i, 1), (i, 2) to (i, 2) constituting m memory cells arranged in the i-th column (i is an integer of 1 to n). In m), the bit line Bi is connected to the drain electrode, and the source potential Vs is applied to the source electrode. Also, pinning lines P (i; 0), P (i; 1), P (i; 2), and P (i; 3) are connected to the four pinning regions, respectively. The memory transistors (1, j) and (2, j) to (n, j) constituting n memory cells arranged in the j-th row (j is an integer of 1 to m) A word line Wj is connected to the control gate electrode.
[0132]
An operation method of the nonvolatile memory of the present invention configured as described above will be described. In the present invention, as described in the embodiment, writing and erasing are performed by a tunnel current between the floating gate electrode and the pinning region, and a reading method can be a one-value / FG method or a one-bit / FG method. In the case of the 1-value / FG method, the nonvolatile memory of this embodiment can store 4-value, that is, 2-bit data in each memory cell, and thus has a storage capacity of m × n × 2 bits. In the case of the 1-bit / FG method, the nonvolatile memory of this embodiment can store 3 bits in each memory cell, and thus has a storage capacity of m × n × 3 bits.
[0133]
In the nonvolatile memory according to the present invention, since writing is performed using a tunnel current, the amount of current required for writing is smaller than that of a conventional NOR flash memory in which hot electron injection is performed. Therefore, boosting is easy, and speeding up of writing by simultaneous writing is possible.
[0134]
As a specific example, writing to and reading from the pinning memory transistor (1, 1) in FIG. 9 and batch erasure of the entire memory will be described.
[0135]
First, when writing to the sub memory transistors (1, 1; 1) constituting the pinning type memory transistor (1, 1), the source potential Vs and the bit lines B1 to Bn are dropped to GND and the word line W1 is set. A positive voltage (for example, 6V) and a negative voltage (for example, −6V) are applied to the pinning line P (1; 1). Moreover, 0V is applied to pinning lines other than P (1; 1). As a result, a high potential difference (about 12 V) is generated only between the floating gate and the pinning region of the sub memory transistor (1, 1; 1), and charge injection (that is, writing) to the floating gate by the tunnel current is performed. Writing to the other sub memory transistors (1, 1; 2) and (1, 1; 3) constituting the pinning type memory transistor (1, 1) can be performed in exactly the same manner.
[0136]
Next, reading of the one-value / FG method from the memory transistor (1, 1) will be described. First, the source potential Vs and the pinning lines P (1: 0) to P (1; 3) are dropped to GND, and a predetermined potential is applied to the word line W1. As a result, in the memory transistor (1, 1), the sub memory transistor in which charge is not accumulated in the floating gate electrode is turned on, and the sub memory transistor in which charge is accumulated in the floating gate electrode is turned off. . That is, the total channel width formed in the memory transistors (1, 1) is proportional to the number of floating gate electrodes in which no charge is accumulated. In this way, the four-value data stored in the memory transistor (1, 1) is read from the bit line B1.
[0137]
Next, reading of the 1-bit / FG method from the memory transistor (1, 1) will be described. First, a method of selectively reading 1-bit information from the sub memory transistor (1, 1; 1) will be described. First, the source potential Vs and the pinning lines P (1; 0) and P (1; 1) are dropped to GND, the pinning lines P (1; 2) and P (1; 3) are −5V, and the word line W1 is predetermined. Is applied. As a result, all the memory transistors in the first row are turned off except for the sub memory transistors (1, 1; 1). Further, the sub memory transistor (1, 1; 1) is turned on when no electric charge is accumulated in the floating gate electrode, and is turned off when electric charge is accumulated in the floating gate electrode. Therefore, 1-bit data stored in the sub memory transistor (1, 1; 1) can be read from the bit line B1. In exactly the same manner, 1-bit information can be read from the sub-memory transistors (1, 1; 2) and (1, 1; 3), and 3-bit information can be read from the memory transistors (1; 1). Can be read out.
[0138]
The predetermined voltage is a threshold voltage in an erased state (a state in which electrons are not accumulated in the floating gate electrode) and a threshold voltage in a written state (a state in which electrons are accumulated in the floating gate electrode). What is necessary is just to set between voltages. For example, when the memory transistor in the erased state has a threshold voltage of 0.5 V or more and 3.5 V or less, and the memory transistor in the written state has a threshold voltage of 6.5 V or more For example, 5V can be used as the predetermined voltage.
[0139]
Note that the potentials of the signal lines B2 to Bn, W2 to Wm, and P (2; i) to P (n; i) (i = 0 to 3) that are not selected at the time of writing and reading are all 0V. To do.
[0140]
When performing batch erase of the entire memory, the source potential Vs, the bit lines B1 to Bn, and the word lines W1 to Wm are dropped to GND. Then, when a positive voltage (for example, 12V) is applied to the pinning lines P (1; 1) to P (n; 3), electrons accumulated in the floating gate electrode are transferred to the pinning region by the tunnel current in all the memory transistors. The injected and stored data is erased.
[0141]
Of course, the value of the operating voltage described above is an example, and is not limited to that value. Actually, the voltage applied to the memory transistor (1, 1) depends on the film thickness of the semiconductor active layer of the memory transistor, the capacitance between the control gate electrode and the floating gate electrode, and the like. The operating voltage of the memory transistor (1, 1) also changes accordingly.
[0142]
Note that, when data is written to and read from the memory transistor (1, 1), erroneous erasure or erroneous writing may occur when a voltage is applied to memory cells in the same column or row. The operating voltage needs to be set so as to minimize such writing stress and reading stress and prevent erroneous erasure and erroneous writing.
[0143]
Note that the circuit configuration of this embodiment can be manufactured by using the process shown in Embodiment 1. It is also possible to use the memory transistor having the split gate structure shown in Embodiment 2.
[0144]
(Example 6)
In this embodiment, an upper surface structure of a memory cell constituting a nonvolatile memory using a pinning region of the present invention will be described. FIG. 10A illustrates an example of a top view of a memory cell array included in the NOR flash memory described in the embodiment.
[0145]
The top view shown in FIG. 10A is a top view including two parallel pinning type memory transistors in the NOR type flash memory shown in Embodiment 5, wherein the region 1001 is a field oxide film, and the region 1007 is a pinning region. It is. In FIG. 10A, each pinning memory transistor 1009 has three floating gate electrodes 1005 and is constituted by three sub memory transistors 1010. A region 1011 is a source region, 1012 is a drain region, and the drain region 1012 and a wiring (bit line) 1008 are electrically connected through a contact hole 1006. Further, the control gate electrode of the memory transistor 1009 also serves as the word line 1004.
[0146]
In FIG. 10A, in order to match the circuit structure shown in Embodiment 5, the pinning region is electrically connected between the two memory transistors, and the source / drain regions are electrically connected. Must be disconnected. In order to achieve such a structure, a substantially intrinsic region is formed in the region 1003 without adding impurities, or more preferably, an impurity such as oxygen is added to make the region 1003 nonconductive for both electrons and holes. A good impurity region may be formed. In particular, FIG. 10B shows a cross-sectional view regarding the line segment BB ′ when oxygen is added. In FIG. 10B, a region 1007 is a pinning region, and a region 1003 is an impurity region to which oxygen is added.
[0147]
Note that this example is an example of a top view of the memory cell in the embodiment. Of course, any other top view may be used as long as it matches the circuit configuration described in the fifth embodiment.
[0148]
(Example 7)
In this embodiment, an example in which the nonvolatile memory of the present invention is applied to a microprocessor such as a RISC processor or an ASIC processor integrated on one chip will be described.
[0149]
FIG. 11 shows an example of a microprocessor. The microprocessor typically includes a CPU core 1101, a cache memory 1102 (may be a RAM), a clock controller 1103, a flash memory 1104, a cache controller 1105, a serial interface 1106, an I / O port 1107, and the like.
[0150]
Needless to say, the microprocessor illustrated in FIG. 11 is a simplified example, and various circuit designs are performed on an actual microprocessor depending on the application.
[0151]
In the microprocessor shown in FIG. 11, a CPU core 1101, a clock controller 1103, a cache controller 1105, a serial interface 1106, and an I / O port 1107 are constituted by CMOS circuits.
[0152]
As the flash memory 1104, the non-volatile memory of the present invention is used, and a multi-value flash memory using a pinning memory transistor is used. As the circuit configuration of the flash memory 1104, the circuit configuration shown in Embodiment 3 or 5 can be used, and other circuit configurations can also be used. Note that the nonvolatile memory of the present invention can also be used as the cache memory 1102.
[0153]
It is also effective to provide a pinning region used in the present invention for the CMOS circuit constituting the CPU core 1101, the clock controller 1103, the cache controller 1105, the serial interface 1106, and the I / O port 1107. For details on applying a pinning region to a transistor including a CMOS circuit, reference can be made to, for example, JP-A-10-65162.
[0154]
In this manner, the pinning region can be provided at a necessary place at the stage of circuit design, and the practitioner may appropriately determine whether to use the pinning region for the entire circuit or a part thereof. When the present invention is applied to a hybrid IC in which various performances are combined, such a degree of freedom in circuit design is very effective.
[0155]
(Example 8)
The nonvolatile memory according to the present invention can be incorporated into electronic devices in various fields as a recording medium for storing and reading data. In this embodiment, such an electronic device will be described.
[0156]
Electronic devices that can use the nonvolatile memory of the present invention include video cameras, digital cameras, projectors (rear type or front type), head mounted displays, goggle type displays, game machines, car navigation systems, personal computers, and portable information terminals. (Mobile computer, cellular phone, electronic book, etc.). Examples of these are shown in FIGS.
[0157]
FIG. 12A illustrates a display, which includes a housing 2001, a support base 2002, a display portion 2003, and the like.
The present invention is connected to the display unit 2003 and other signal control circuits, and is used for correcting image signals and storing processed data.
[0158]
FIG. 12B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention is incorporated in a built-in LSI substrate and used for functions such as image data storage.
[0159]
FIG. 12C shows a part (right side) of the head mounted display, which includes a main body 2201, a signal cable 2202, a head fixing band 2203, a display portion 2204, an optical system 2205, a display device 2206, and the like. The present invention is connected to a display device 2206 and other signal control circuits, and is used for correcting image signals and storing processed data.
[0160]
FIG. 12D shows an image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2301, a recording medium 2302, an operation switch 2303, a display portion (a) 2304, and a display portion (b) 2305. Etc. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention is incorporated in a built-in LSI substrate and used for functions such as storage of image data and processing data.
[0161]
FIG. 12E illustrates a goggle type display, which includes a main body 2401, a display portion 2402, and an arm portion 2403. The present invention is connected to the display unit 2402 and other signal control circuits, and is used for correcting image signals and storing processed data.
[0162]
FIG. 12F illustrates a personal computer, which includes a main body 2501, a housing 2502, a display portion 2503, a keyboard 2504, and the like. The present invention is incorporated in a built-in LSI substrate and used for storing processing data and image data.
[0163]
FIG. 13A illustrates a mobile phone, which includes a main body 2601, an audio output portion 2602, an audio input portion 2603, a display portion 2604, operation switches 2605, and an antenna 2606. The present invention is incorporated in a built-in LSI substrate and used to add an address function for recording a telephone number.
[0164]
FIG. 13B illustrates a sound reproducing device, specifically a car audio, which includes a main body 2701, a display portion 2702, and operation switches 2703 and 2704. The present invention is incorporated in a built-in LSI substrate and used for functions such as storage of image data and processing data. Moreover, although the vehicle-mounted audio is shown in the present embodiment, it may be used for a portable or household sound reproducing device.
[0165]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic device of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-6.
[0166]
【Effect of the invention】
By utilizing the present invention, the influence of a fine effect typified by a short channel effect or the like can be minimized, and further miniaturization of the nonvolatile memory can be promoted.
[0167]
In addition, according to the present invention, it is possible to multi-value cells by a completely different method from the conventional multi-value technique for controlling the charge accumulation amount of the floating gate electrode, and the multi-value is advanced more than before. It becomes possible.
[0168]
As a result, it is possible to realize a nonvolatile memory with an extremely high integration density.
[0169]
Furthermore, by mounting the non-volatile memory with high integration density of the present invention, a semiconductor device capable of high functionality and multi-function can be provided.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall configuration of a nonvolatile memory according to the present invention.
FIG. 2 is a top view illustrating a partial configuration of a nonvolatile memory according to the present invention.
FIG. 3 is a cross-sectional view illustrating a partial configuration of a nonvolatile memory according to the present invention.
FIG. 4 is a diagram for explaining a change in an energy band.
FIG. 5 is a diagram showing an equivalent circuit of the nonvolatile memory of the present invention.
FIG. 6 is a diagram showing an overall configuration of a nonvolatile memory according to the present invention.
FIG. 7 is a diagram showing a circuit configuration of a nonvolatile memory according to the present invention.
FIG. 8 is a top view of a nonvolatile memory according to the present invention.
FIG. 9 is a diagram showing a circuit configuration of a nonvolatile memory according to the present invention.
FIG. 10 is a top view of a nonvolatile memory according to the present invention.
FIG. 11 is a diagram showing a semiconductor circuit using a nonvolatile memory of the present invention.
FIG. 12 is a diagram showing an electronic device using the nonvolatile memory of the present invention.
FIG. 13 is a diagram showing an electronic device using the nonvolatile memory of the present invention.
FIG. 14 is a diagram showing an equivalent circuit of the nonvolatile memory of the present invention.
[Explanation of symbols]
101 Silicon substrate
102 Field oxide film
103 Source area
104 Drain region
105 Pinning area
106 Channel formation region
107 first gate insulating film
108 Floating gate electrode
109 Second gate insulating film
110 Control gate electrode
111 Interlayer film
112 Wiring

Claims (13)

A source region formed from a single crystal semiconductor, a drain region, and a region sandwiched between the source region and the drain region;
A first gate insulating film formed on a region sandwiched between the source region and the drain region;
A plurality of floating gate electrodes formed on the first gate insulating film;
A second gate insulating film formed on the plurality of floating gate electrodes;
A control gate electrode formed on the second gate insulating film;
A non-volatile memory comprising a memory transistor having
The region sandwiched between the source region and the drain region is formed by a plurality of impurity regions formed in a stripe shape in the channel length direction and a plurality of channel formation regions sandwiched between the plurality of impurity regions,
The plurality of impurity regions are doped with impurities having a conductivity type opposite to that of the impurities added to the source region and the drain region,
The plurality of floating gate electrodes are formed one on each of the plurality of channel formation regions through the first gate insulating film,
The non-volatile memory, wherein the memory transistor stores multi-value data. A source region formed from a single crystal semiconductor, a drain region, and a region sandwiched between the source region and the drain region;
A first gate insulating film formed on a region sandwiched between the source region and the drain region;
A plurality of floating gate electrodes formed on the first gate insulating film;
A second gate insulating film formed on the plurality of floating gate electrodes;
A control gate electrode formed on the second gate insulating film;
A non-volatile memory comprising a memory transistor having
The region sandwiched between the source region and the drain region is formed by a plurality of impurity regions formed in a stripe shape in the channel length direction and a plurality of channel formation regions sandwiched between the plurality of impurity regions,
The plurality of impurity regions are doped with impurities having a conductivity type opposite to that of the impurities added to the source region and the drain region,
The plurality of floating gate electrodes are formed one on each of the plurality of channel formation regions through the first gate insulating film,
The plurality of impurity regions can independently control the potential,
The non-volatile memory, wherein the memory transistor stores multi-value data. According to claim 1 or claim 2, nonvolatile memory, wherein each of the plurality of floating gate electrodes, and one of the plurality of impurity regions via the first gate insulating film, the overlapping portion . In any one of claims 1 to 3, wherein the source region and the drain region of the plurality of impurity regions formed in a region sandwiched, even in one or both of the source region and the drain region A non-volatile memory formed continuously. Non-volatile memory, characterized in that in any one of claims 1 to 4, the impurity of the plurality of impurity regions is selected from group 13 or group 15. In any one of claims 1 to 5, the impurity of the plurality of impurity regions is selected from group 13 or group 15, it extends toward the source region from the drain region by the plurality of impurity regions depletion layer Non-volatile memory characterized in that In the claims 1 to any one of claims 6, wherein the concentration of impurities of the plurality of impurity regions is 1 × ¹⁰ 17 atoms / cm ³ or more 5 × ¹⁰ 20 atoms / cm ³ or less non Sex memory. In any one of claims 1 to 7, the channel length of the memory transistor, a nonvolatile memory, characterized in that at 0.01μm than 1μm or less. In any one of claims 1 to 8, a non-volatile memory, wherein the width of said plurality of impurity regions is 0.01μm or 1μm or less. In any one of claims 1 to 9, a non-volatile memory, wherein the width of said plurality of channel formation regions is 0.01μm or 1μm or less. In any one of claims 1 to 10, a semiconductor device which is characterized by utilizing the non-volatile memory as a recording medium. 12. The semiconductor device according to claim 11 , wherein the semiconductor device is a microprocessor. 12. The semiconductor device according to claim 11 , wherein the semiconductor device is a display, a video camera, a head mounted display, a DVD player, a goggle type display, a personal computer, a mobile phone, or a car audio.

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