JPH11150198A - Nonvolatile storage device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a storage device of high performance by effectively restraining the short-channel effect which accompanies the microstructuring of a nonvolatile storage device. SOLUTION: In a nonvolatile storage device, a pinning region 105 is formed locally in an active region surrounded by a field oxide film 102, a source region 103 and a drain region 104. The pinning region 150 restrains a depleted layer, stretching from the drain side towards the source side and prevents a punch- through phenomenon which accompanies short-channel effect.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a configuration of a nonvolatile memory formed using a semiconductor. In particular, the present invention is effective for a nonvolatile memory having a channel length of 2 μm or less, and further, 0.5 μm or less.

[0002]

2. Description of the Related Art IC memories for storing and holding data inside a computer are roughly classified into RAMs and ROMs.
Divided into Examples of a RAM (Random Access Memory) include a DRAM (Dynamic RAM) and an SRAM (Static RAM), but when these are turned off, data is lost.

On the other hand, mask ROMs, PR
An OM (programmable ROM) is known and has an advantage that data is not lost even when the power is turned off. Furthermore, P
The ROM is an EPROM (Erasab) that erases data with ultraviolet light.
le-PROM), EEPROM that electrically erases data
M (Electrically-EPROM), flash memory (flash-EEPROM) that electrically erases data collectively
And so on.

[0004] Research and development of non-volatile memory has been proceeding at a remarkable pace in order to take advantage of the excellent advantage of permanent data retention. Recently, the possibility of magnetic memory as an alternative memory has been discussed.

In such an IC memory, it is necessary to pursue reliability and performance, and at the same time, expand the storage capacity. That is, as with other ICs, miniaturization technology is always adopted, and development is proceeding in accordance with the scaling rule.

However, the nonvolatile memory basically stores data using the same operation principle as a field effect transistor (hereinafter, referred to as an FET). Therefore, the short channel effect, which is known to cause a serious adverse effect on the FET operation with miniaturization, also causes a serious adverse effect on the operation of the nonvolatile memory.

In particular, the phenomenon called punch-through makes it difficult to control the current by the gate electrode by lowering the source-drain breakdown voltage. Therefore, there has been an example in which a structure called a SSW-DSA structure (NIKKEI MICRODEVICES, pp. 47-48, May, 1992) is conventionally used to enhance punch-through resistance.

[0008]

The above-mentioned SSW-DSA
The structure utilizes a technique also called a pocket structure in the field of FETs, and has a structure in which an impurity region of the same conductivity type as the substrate is provided at the channel / drain junction. By doing so, the spread of the drain depletion layer can be suppressed, and the occurrence of punch-through can be suppressed.

However, in the nonvolatile memory, impact ionization is positively caused at the channel / drain junction to generate an electron-hole pair. Therefore, at the same time as injection of electrons into the floating gate, a large amount of positive ions are applied to the substrate side. The hole flows.

However, in the above-described SSW-DSA structure, a large amount of holes must flow to the substrate terminal.
As a result, a problem that a kink phenomenon (a phenomenon in which a drain current abnormally increases) due to formation of a parasitic bipolar between the source, the substrate, and the drain may occur.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to effectively prevent or suppress a short-channel effect caused by miniaturization of a non-volatile memory and realize a high-performance memory. As an issue.

[0012]

According to the invention disclosed in this specification, a source region, a drain region and an active region formed by using a single crystal semiconductor and a stripe-shaped region provided in the active region are provided. An impurity region and an intrinsic or substantially intrinsic channel forming region sandwiched between the impurity regions are provided.

According to another aspect of the invention, a source region, a drain region, and an active region formed using a single crystal semiconductor, a stripe-shaped impurity region provided in the active region, An intrinsic or substantially intrinsic channel-forming region sandwiched therebetween, wherein the impurity region is made of an element selected from Group 13 or Group 15.

According to another aspect of the present invention, a source region, a drain region, and an active region formed using a single crystal semiconductor, a stripe-shaped impurity region provided in the active region, An intrinsic or substantially intrinsic channel forming region sandwiched therebetween, wherein the impurity region is made of an element selected from Group 13 or Group 15 and spreads from the drain region toward the source region by the impurity region. The depletion layer is suppressed.

In the above structure, it is preferable that the impurity region is provided from the source region to the drain region.

In the above structure, the concentration of the element contained in the impurity region is 1 × 10 ^{17 to} 5 × 10 ²⁰ atoms / cm ^3.
It is preferred that

Further, it is effective to form a recording circuit using the nonvolatile memory having the above configuration as a recording medium and to incorporate the recording circuit into an electronic device.

The gist of the present invention is to form an impurity region locally in an active region and to suppress a depletion layer extending from a drain region toward a source region by the impurity region. Note that in this specification, a region surrounded by a source region, a drain region, and a field oxide film is called an active region, and the active region is further divided into an impurity region provided in a stripe shape and a channel formation region.

Further, the present inventors define the word "pinning" to mean "deterrence" since the effect of suppressing the depletion layer is regarded as pinning the depletion layer.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described.
A detailed description will be given using the following embodiments.

[0021]

[Embodiment 1] This embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view and a top view of a nonvolatile memory to which the present invention is applied. In this embodiment, an EEPROM having a basic stack structure will be described as an example.

In FIG. 1, 101 is single crystal silicon (P-type silicon), 102 is a field oxide film formed by LOCOS, 103 is a source region formed by adding arsenic (or phosphorus), and 104 is a drain region. is there. Here, an example of the structure of an N-type EEPROM is shown, but a P-type may also be used. In the case of P-type, boron may be added to N-type silicon to form source / drain regions.

Reference numeral 105 denotes the most important impurity region (hereinafter, referred to as a pinning region) in the present invention. The pinning region 105 is formed by adding an impurity having the same conductivity type as that of the silicon substrate 101. Here, in the case of FIG. 1, P-type silicon is used, so that an element selected from Group 13 (typically, boron) is added. Of course, N
In the case of using type silicon (in the case of manufacturing a P-type EEPROM), an element selected from Group 15 may be added to form a pinning region.

Note that the element selected from the above-described Group 13 or Group 15 forms an energy barrier for carriers (electrons or holes) by shifting the energy band of single crystal silicon. In that sense, the pinning region can also be referred to as a region obtained by shifting the energy band, and it is possible to use an element exhibiting such an effect even if it is not a Group 13 or Group 15 element.

Here, the elements that shift the energy band will be described with reference to a conceptual diagram as shown in FIG. FIG.
(A) shows an energy band state of single crystal silicon. When an impurity element (an element selected from Group 13) that shifts the energy band in a direction that hinders electron transfer is added thereto, the energy state changes as shown in FIG.

At this time, the energy band gap does not change in the added region, but the Fermi level (Ef) moves to the valence band (Ev). As a result, the energy state apparently shifts upward. Therefore, an energy barrier (for electrons) higher by ΔE than in the undoped region is formed.

When an impurity element (an element selected from Group 15) that shifts the energy band in the direction that hinders the movement of holes is added to the state shown in FIG. 2A, the energy state becomes as shown in FIG. Change like this.

In this case, the Fermi level in the added region moves to the conduction band (Ec) side, and the energy state apparently shifts downward. Therefore, an energy barrier higher by ΔE (for holes) is formed than in the undoped region.

As described above, an energy difference corresponding to ΔE is generated between the region where the impurity is not added (undoped) and the pinning region. This energy (potential)
The height of the barrier varies depending on the concentration of the impurity element added. In the present invention, the concentration of this impurity element is set to 1 × 10 ¹⁷ to
5 × 10 ²⁰ atoms / cm ³ (preferably 1 × 10 ¹⁸ to 5 × 10 ¹⁹ at
oms / cm ³ ).

Since the pinning region 105 can be formed by utilizing a fine processing technique, the pinning region 105 can be formed by ion implantation or FIB (Focusd Ion Beam).
It is necessary to use an addition means suitable for fine processing. Also,
If an addition method using a mask is used, it is preferable to use fine processing such as forming a mask pattern using an electronic drawing method.

The pinning regions 105 are most typically arranged such that the pinning regions 105 and the channel forming regions 106 are substantially parallel to each other and are alternately arranged as shown in FIG. That is, a configuration in which a plurality of pinning regions are provided in a stripe shape in a region (active region) surrounded by the source region 103, the drain region 104, and the field oxide film 102 is preferable.

It is effective to provide a pinning region at the side end of the active region (the end where the active region is in contact with the field oxide film). If a pinning region is formed at the side end, it is possible to reduce the leak current transmitted through the side end.

The pinning region 105 only needs to be formed so as to cover at least the junction (drain junction) between the active region and the drain region 104. Since the depletion layer, which is a problem in punch-through, spreads from the drain junction, the effect can be obtained by suppressing this. That is, if the pinning region is provided in a dot shape or an elliptical shape with respect to the active region, and the part thereof is present at the drain junction, the expansion of the depletion layer can be suppressed.

Of course, as shown in FIG.
If it is formed over the region from 03 to the drain region 104, a more effective pinning effect can be obtained.

The implantation depth of the pinning region 105 is desirably at least larger than the junction depth of the source / drain regions. Therefore, an implantation depth of 0.1 to 0.5 μm (preferably 0.2 to 0.3 μm) is required.

Here, the channel length and the channel width are defined with reference to FIG. In FIG. 3, the distance between the source region 301 and the drain region 302 (corresponding to the length of the active region 303) is defined as a channel length (L). The present invention has a length of 2 μm or less, typically 0.05 to 0.5 μm.
m, preferably 0.1 to 0.3 μm. The direction along the channel length is called the channel length direction.

The width of an arbitrary pinning area 304 is defined as a pinning width (v _j ). The pinning width may be 1 μm or less, typically 0.01 to 0.2 μm, and preferably 0.05 to 0.1 μm. When the sum of the widths of all the pinning regions existing in the active region 303 is defined as an effective pinning width (V), the effective pinning region is defined as follows.

[0038]

(Equation 1)

In order to obtain the pinning effect, the active region 3
03 needs to be provided with at least one pinning area. That is, j = 1 or more is necessary as a condition.
In the case where a pinning region is provided at a side end portion (a portion in contact with a field oxide film) of active region 303, at least j = 2 or more is a necessary condition.

Further, the width of the channel forming region 305 and the channel width (w _i). The channel width can correspond to any case, but since the memory does not need to flow a large current, 1
μm or less, typically 0.05 to 0.5 μm, preferably 0.1
It may be set to about 0.3 μm.

Further, it defined as follows when the effective channel width (W) of the total sum of the channel widths (w _i).

[0042]

(Equation 2)

When the pinning region is provided only on the side end of the active region 303, i = 1. In order to effectively obtain the pinning effect, it is preferable to provide a pinning region other than the side end of the active region 303. In that case, i = 2 or more.

The total sum of the above-mentioned sum of the pinning regions (effective pinning width) and the sum of the channel forming regions (effective channel width) is defined as the _total channel width (W _total ) and is defined by the following equation.

[0045]

(Equation 3)

The total channel width (W _total ) corresponds to the width of the active region 303 (the length of the active region in the direction perpendicular to the channel length direction). The direction along the overall channel width will be referred to as the channel width direction.

As described above, since the present invention is intended to be applied to a non-volatile memory having a very short channel length, the pinning region and the channel forming region must be formed with extremely fine dimensions.

In FIG. 1, the impurity element added to the pinning region 105 is preferably activated by furnace annealing, laser annealing, lamp annealing, or the like. This activation step may be performed at the same time as the annealing treatment in a later step such as the formation of a gate insulating film, or may be performed separately.

The feature of the present invention is that a region functioning as a channel forming region in a conventional nonvolatile memory is:
The point is that a pinning region is provided locally (stripe shape). Therefore, other structures can follow the structure of the conventional nonvolatile memory as it is.

That is, the source region 103 and the drain region 1
04, a tunnel oxide film 107 is provided on the single crystal silicon provided with the pinning region 105. The tunnel oxide film is formed by a thermal oxidation process, and high quality film is desired.
In this embodiment, the thickness of the tunnel oxide film 107 is 11 nm. It goes without saying that the thickness of the tunnel oxide film is not limited to this value.

In the present embodiment, the pinning area 1 described above is used.
05 may be formed after the tunnel oxide film 107 is formed.

On the tunnel oxide film 107, a floating gate 108 made of a first polysilicon layer, a first interlayer film 109, a control gate 110 made of a second polysilicon layer, and a second interlayer film 111, bit line 11
2 is provided.

Of course, it is also possible to use a conductive layer such as a metal film instead of the polycrystalline silicon layer. It is also effective to use a laminated film (generally called an ONO film) represented by SiO ₂ / SiN / SiO ₂ as the interlayer film.

Incidentally, the double-layer polycrystalline silicon type E of this embodiment is used.
An EPROM is represented by a circuit diagram as shown in FIG.
In FIG. 1D, Vd denotes a drain voltage, Vs denotes a source voltage, CG denotes a control gate voltage, and FG denotes a potential of the floating gate.

In the EEPROM of this embodiment, the following voltages are applied when writing and erasing data.

[0056]

[Table 1]

Of course, the operating voltage need not be limited to Table 1. Further, the structure of this embodiment is not limited to this, and the present invention can be applied to all EEPROMs that electrically erase data.

(Operation and Effect of the Present Invention) First, the first effect of the present invention will be described. In FIG. 1, the pinning region 105 formed locally in the active region functions as a stopper for the depletion layer extending from the drain side, and effectively suppresses the expansion of the depletion layer. Therefore, the punch-through phenomenon due to the expansion of the depletion layer is prevented. In addition, since an increase in depletion layer charge due to the expansion of the depletion layer is suppressed,
A decrease in threshold voltage can be avoided.

Next, the second effect will be described. In the present invention, the narrow channel effect can be intentionally enhanced by the pinning region. The narrow channel effect is a phenomenon observed when the channel width is extremely narrow, and causes an increase in the threshold voltage (submicron device I; Mitsumasa Koyanagi et al., Pp. 88-138, Maruzen Co., Ltd., 1987). .

FIG. 4 shows the energy state (potential state) of the active region when the pinning TFT of this embodiment operates. In FIG. 4, regions indicated by 401 and 402 correspond to the energy state of the pinning region 105,
The region shown by corresponds to the energy state of the channel formation region 106.

As is clear from FIG. 4, the pinning region 1
05 forms a barrier with a high energy, and the channel formation region 106 forms a region with a low energy barrier. Therefore, carriers move preferentially in the channel formation region 106 having a low energy state.

As described above, in the pinning region 105, a high energy barrier is formed, and the threshold voltage at that portion increases. As a result, the threshold voltage observed as a whole increases. This narrow channel effect becomes more pronounced as the effective channel width becomes narrower.

As described above, according to the present invention, it is possible to control the strength of the narrow channel effect and adjust the threshold voltage by freely designing the impurity concentration added to the pinning region 105 and the effective channel width. It is possible. That is, by controlling the pinning effect, the desired value can be adjusted by balancing the decrease in the threshold voltage due to the short channel effect and the increase in the threshold voltage due to the narrow channel effect.

In the pinning region, a group 13 element is added in the case of an N-type, and a group 15 element is added in the case of a P-type. Shifts in the positive and negative directions for the P-channel type). That is, since the threshold voltage locally increases, the overall threshold voltage increases accordingly. Therefore,
In order to adjust the threshold voltage to a desired value, it is important to set the concentration of the impurity added to the pinning region to an appropriate value.

In a nonvolatile memory, a threshold voltage is changed by injecting electric charges (mainly electrons) into a floating gate, and it is detected whether or not a current flows through a bit line when a predetermined voltage is applied. Thus, “0” and “1” are identified. Therefore, when the threshold voltage becomes extremely small due to the short channel effect, the distinction between “0” and “1” must be distinguished by applying a very small voltage. That is, it is susceptible to noise and the like, and the risk of malfunction increases.

However, according to the present invention, since the threshold voltage can be controlled to a desired threshold voltage while suppressing a decrease in the threshold voltage, the discriminating ability of "0" and "1" is improved. That is,
It is possible to realize a highly reliable nonvolatile memory.

Next, the third effect will be described. The non-volatile memory of the present invention has an advantage that the channel formation region 106 is formed of a substantially intrinsic region, and majority carriers (electrons in the case of N type, holes in the case of P type) move in the region.

Here, the substantially intrinsic region basically refers to an undoped single crystal semiconductor region. In addition, a region in which the conductivity type is intentionally canceled by adding an impurity element of the opposite conductivity type, and a region having one conductivity type in a range where the threshold voltage can be controlled are included.

For example, if the dopant concentration is 5 × 10 ¹⁶ atoms /
cm ³ or less (preferably 5 × 10 ¹⁵ atoms / cm ³ or less), and the concentration of carbon, nitrogen and oxygen contained is 2 × 10 ¹⁸ atoms / cm ³
A silicon wafer having a size of not more than cm ³ (preferably not more than 5 × 10 ¹⁷ atoms / cm ³ ) can be said to be substantially intrinsic. In this sense, a commonly used silicon wafer is substantially intrinsic unless impurities are intentionally added during the process.

When the region where carriers move is substantially intrinsic, the decrease in mobility due to impurity scattering is extremely small, and high carrier mobility can be obtained. That is, the influence of the lattice scattering is dominant on the carrier mobility, and the mobility becomes very close to an ideal state.

Also, as shown in FIG. 1A, when a linear pinning region is provided from the source region to the drain region, there is obtained an effect that the movement path of majority carriers is defined by the pinning region. .

As described above, the energy state of the channel forming region sandwiched between the pinning regions is as shown in FIG. In the configuration shown in FIG. 1A, it is considered that a plurality of slits in an energy state as shown in FIG. 4 are arranged.

FIG. 5 schematically shows this state. In FIG. 5, reference numeral 501 denotes a pinning region, and 502 denotes a channel forming region. Reference numeral 503 denotes a majority carrier (electron or hole). As shown in FIG. 5, the carrier 503 cannot move beyond the pinning region 501, and therefore moves preferentially in the channel forming region 502. That is, the movement path of the majority carrier is defined by the pinning area.

By defining the moving path of the majority carrier, scattering due to self-collision between carriers is reduced. This greatly contributes to improving mobility. Furthermore, since there are very few impurity elements in the substantially intrinsic channel formation region, the velocity overshoot effect (K. Ohuchi et al.) At which electron mobility is higher than usual even at room temperature.
l., Jpn. J. Appl. Phys. 35, pp. 960, 1996), so the mobility becomes extremely large.

As described above, since high carrier mobility is obtained, the effect of shortening the charge write time and the charge read time appears, and the memory function is enhanced. In addition, since the carrier mobility is high, since the energy is so high, the charge writing efficiency by the channel hot electron injection (CHE injection) is greatly improved.

Next, the fourth effect will be described. When the configuration of the present invention is adopted, the electric field concentration at the junction between the pinning region and the drain region (typically, ap ⁺ / n ⁺⁺ junction or n ⁺ / p ⁺⁺ is formed) becomes very large. . Therefore, a large amount of electrons that are accelerated and have high energy and electrons generated by impact ionization (these are collectively called hot electrons) are generated.

That is, charge injection into the floating gate is performed very efficiently, and the data write time is reduced. Thus, by providing the pinning region, the efficiency of hot electron injection at the drain junction can be increased.

Next, the fifth effect will be described. Although the pinning region of the present invention has already been described as having a function of preventing a short channel effect and controlling a threshold voltage, it is also very important in preventing conduction of a parasitic bipolar due to impact ionization (impact ionization). Role.

Conventionally, of the electron-hole pairs generated by impact ionization, electrons are injected into the floating gate, and holes flow to the substrate. Then, the holes flowing to the substrate become the substrate current and conduct the parasitic bipolar.

However, in the present invention, holes generated by impact ionization immediately move into the pinning region, and are drawn out into the source region through the inside. Therefore, the parasitic bipolar is not made conductive, and the withstand voltage between the source and the drain is not reduced.

It is needless to say that such an effect is particularly prominent when the pinning region is formed from the source region to the drain region. If the pinning region is in contact with the extraction electrode in the source region, holes can be more effectively extracted.

[Embodiment 2] The two-layer polycrystalline silicon type EEPROM shown in Embodiment 1 is of a byte erasing type (erasing data for each unit memory element) and a flash type (collective data erasing of a group of memory elements). Do)).

A flash type EEPROM is also called a flash memory.
It can also be applied to EPROM.

The data erasing method is a source erasing type,
There are various methods such as a source gate erasing type and a substrate erasing type, and the present invention can be applied in any case.

[Embodiment 3] In the embodiment 1 and the embodiment 2,
Although the example of the layer polycrystalline silicon type EEPROM is shown, in this embodiment, an example in which the present invention is applied to the example of the three-layer polycrystalline silicon type EEPROM will be described with reference to FIG.

Since the basic structure is the same as that of the two-layer polycrystalline silicon type EEPROM described in the first embodiment,
The reference numerals used in the description of FIG. 1 are used. That is, in FIG. 6, the same reference numerals as in FIG. 1 may refer to the description of FIG. In the present embodiment, a description will be given by assigning new symbols only to different portions.

FIG. 6A is different from FIG. 1A in that an erase gate 601 is provided. That is, the erase gate 601 is constituted by the first polycrystalline silicon layer, and subsequently, the floating gate 108 and the control gate 11 are formed by the second and third polycrystalline silicon layers, respectively.
0 is configured.

In the EEPROM having the structure of the first embodiment, data is erased by extracting electrons injected into the floating gate 108 to the substrate side (source region or bulk substrate).
The electrons injected at 08 are extracted to the erase gate 601 to erase data.

Therefore, in FIG. 1B, the insulating film 602 for insulating and separating the erase gate 601 and the floating gate 108 is as thin as possible (preferably 8) so that a tunnel current (Fowler-Nordheim current) can flow. 1212 nm) and a high quality film having high durability.

In the case of this embodiment, after the pinning region is provided, the steps of forming the erase gate 601 and the erase gate insulating film 602 are increased, so that it can be basically manufactured by the same steps as the structure shown in the first embodiment. .

An EEPROM having an erase gate as in this embodiment is represented by a circuit diagram as shown in FIG. In FIG. 6D, Vd is the drain voltage, Vs
Denotes a source voltage, EG denotes an erase gate voltage, CG denotes a control gate voltage, and FG denotes a potential of the floating gate.

In the EEPROM of this embodiment, the following voltages are applied when writing and erasing data.

[0093]

[Table 2]

Of course, the operating voltage need not be limited to Table 2. The structure of this embodiment is not limited to this, and the present invention can be applied to all EEPROMs having an erase gate structure.

[Embodiment 4] The nonvolatile memories shown in Embodiments 1 to 3 use hot electron injection for writing data and use Fowler-Nordheim current for erasing data. A Fowler-Nordheim current may be used for writing.

In particular, when a memory having a large capacity of 256 Mbits or more is formed, it is preferable to write data using a Fowler-Nordheim current in order to improve reliability (suppress deterioration and extend life). .

[Embodiment 5] In the structure of the double-layer polycrystalline silicon type shown in the embodiment 1, E is used to electrically erase data.
Although an EPROM has been described as an example, a non-volatile memory using a method in which electrons injected into a floating gate are excited by ultraviolet light irradiation or heat and extracted to a source or a substrate is called an EPROM. The present invention provides such an EPRO
M can also be applied.

Also, a floating gate is not used in the EPROM, but a two-layered gate insulating film is provided between the control gate and the silicon substrate, and a non-volatile type in which hot electrons are captured at the interface state is provided. There is also memory. For example, a type in which hot carriers are captured at an interface between a silicon oxide film and a silicon nitride film is called an NMOS nonvolatile memory.

Further, there is a nonvolatile memory of a type in which a metal cluster, a silicon cluster, or the like is intentionally formed at the interface of an insulating film and hot carriers are captured there.

The present invention is applicable to all types of E as described above.
It is also possible to apply to a PROM.

[Embodiment 6] Since the nonvolatile memory of the present invention is applicable to all conventional nonvolatile memories, the circuit configuration can be applied to all known circuit configurations. Therefore, in this embodiment, a case will be described in which the present invention is applied to a flash memory designed with a NAND type and a NOR type architecture.

First, the NAN shown in FIGS. 7A and 7B
The configuration of the D-type memory circuit will be described. Although FIG. 7 shows two circuits each including eight memory transistors and two selection transistors, only one of them will be described.

In FIG. 7A, reference numerals 701 and 702 denote selection transistors, and select lines S1 and S2 indicated by 703 and 704 are gate electrodes. The selection transistor 701 includes a bit line 705 indicated by B1 (or B2) and eight memory transistors 706 to 706.
13 is connected.

Although the present embodiment shows an example in which eight memory transistors are connected in series, the number is not limited to this.

The last stage memory transistor 713
Is connected to a selection transistor 702, and one terminal of the selection transistor 702 is grounded. Of course, the operation can be performed even when the power supply line is connected instead of the ground.

The memory transistors 706 to 713 use word lines 714 to 721 (represented by W1 to W8) as control gates.

FIG. 7B schematically shows the NAND memory circuit of FIG. 7A as a circuit pattern. In each memory transistor, a hatched region indicates a floating gate provided below the control gates 714 to 721.

Next, the NOR shown in FIGS. 8A and 8B will be described.
The configuration of the type memory circuit will be described. Although FIG. 8 shows two circuits each including four memory transistors, only one of the circuits will be described.

In FIG. 8A, four memory transistors 802 are individually connected to a bit line 801 indicated by B1.
To 805 are connected. The terminals (source regions) of the memory transistors 802 to 805 on the side not connected to the bit line 801 are connected to the ground line 806.

The memory transistors 802 to 805
Are word lines 807 to 810 indicated by W1 to W4.
Is used as a control gate.

FIG. 8B schematically shows the NOR type memory circuit of FIG. 8A as a circuit pattern. In each memory transistor, a hatched region indicates a floating gate provided below the control gates 807 to 810.

Although the NAND type circuit as shown in FIG. 7 has disadvantages such as a fixed write order and a slow read access time, it has an advantage that the degree of integration can be greatly improved.

A NOR type circuit as shown in FIG.
This configuration is effective for performing precise injection of electrons into the floating gate and accurate reading of the charge amount. This is a feature of the NOR type architecture in which individual memory transistors are directly connected to source / drain bus lines.

Although the present embodiment has described a nonvolatile memory using electrodes having a two-layer structure (such as polycrystalline polysilicon), an electrode having a three-layer structure as shown in the third embodiment (including an erase gate). Non-volatile memory having the following structure).

[Embodiment 7] In this embodiment, an example will be described in which the nonvolatile memory of the present invention is applied to a microprocessor such as an RISC processor or an ASIC processor integrated on one chip.

FIG. 9 shows an example of a microprocessor. The microprocessor typically includes a CPU core 11, a flash memory 12 (or a RAM), a clock controller 13, a cache memory 14, a cache controller 15, and a serial interface 1.
6, an I / O port 17 and the like.

Of course, the microprocessor shown in FIG. 9 is a simplified example, and an actual microprocessor is designed for various circuits depending on the application.

In the microprocessor shown in FIG.
Core 11, clock controller 13, cache controller 15, serial interface 16, I / O
The port 17 is constituted by a CMOS circuit 18. The CMOS circuit 18 has the pinning region 19 disclosed in the present invention.

As described above, the present invention can be applied not only to nonvolatile memories but also to MOSFETs. The details have already been filed in Japanese Patent Application No. 8-232553.

Further, the nonvolatile memory of the present invention is used for the flash memory 14, and the memory circuit 20 is formed. All memory cells constituting the memory circuit 20 are provided with pinning regions 21. Note that the nonvolatile memory of the present invention can be used as the cache memory 12.

As described above, FIG. 9 shows an example in which the pinning technique disclosed in the present invention is used for all of the memory section and other logic sections.

Further, in some cases, a configuration as shown in FIG. 10 may be employed. FIG. 10 shows an example in which a logic unit other than the memory unit is configured by a normal CMOS circuit 22.
In this case, the configuration may be such that the pinning region is not provided only in the logic portion.

As described above, the pinning region can be provided at a necessary portion at the stage of circuit design, and whether to use the entire circuit or a part thereof may be determined as appropriate by an operator. When the present invention is applied to a hybrid IC in which various performances are combined, such a degree of freedom in circuit design is very effective.

[Embodiment 8] A semiconductor circuit (memory circuit) constituted by a nonvolatile memory according to the present invention stores data.
As a recording medium for reading, it can be incorporated in electronic devices in various fields. In this embodiment, an example of such an electronic device is shown in FIG.

[0125] Electronic devices that can use the non-volatile memory of the present invention include video cameras, electronic still cameras, projectors, head mounted displays, car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones, PHS, etc.). Is mentioned.

FIG. 11A shows a mobile phone, and the main body 20 is provided.
01, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 200
6. The present invention is incorporated into a built-in LSI board and is used for adding an address function for recording a telephone number and the like.

FIG. 11B shows a video camera, which includes a main body 2101, a display device 2102, an audio input unit 2103, an operation switch 2104, a battery 2105, and an image receiving unit 21.
06. The present invention is incorporated in a built-in LSI board and used for functions such as storage of image data.

FIG. 11C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display device 2205. The present invention is a built-in LSI
It is built into a substrate and used for storing processing data and image data.

FIG. 11D shows a head-mounted display, which comprises a main body 2301, a display device 2302, and a band 2303. The present invention is connected to the display device 2302 as a correction circuit for an image signal.

FIG. 11E shows a rear type projector, in which a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The present invention can be used as a storage circuit for storing data to be provided to the gamma correction circuit.

FIG. 11F shows a front type projector, which includes a main body 2501, a light source 2502, and a display device 250.
3. It comprises an optical system 2504 and a screen 2505. The present invention can be used as a storage circuit for storing data to be provided to the gamma correction circuit.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. In addition, it can be used as a storage medium indispensable for various control circuits and information processing circuits.

[0133]

By utilizing the present invention, the effect of a fine effect represented by a short channel effect or the like is minimized,
Further miniaturization of the nonvolatile memory can be promoted.

Further, it is possible to realize a nonvolatile memory realizing a large capacity with a small area while securing high reliability.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a nonvolatile memory of the present invention.

FIG. 2 is a diagram illustrating a change in an energy band.

FIG. 3 is a diagram for explaining definitions of a channel length and a channel width.

FIG. 4 is a diagram showing an energy state of an active region.

FIG. 5 is a diagram showing an energy state of an active region.

FIG. 6 is a diagram showing a configuration of a nonvolatile memory of the present invention.

FIG. 7 is a diagram showing a circuit using the nonvolatile memory of the present invention.

FIG. 8 is a diagram showing a circuit using the nonvolatile memory of the present invention.

FIG. 9 is a diagram showing a semiconductor circuit using the nonvolatile memory of the present invention.

FIG. 10 is a diagram showing a semiconductor circuit using the nonvolatile memory of the present invention.

FIG. 11 is a diagram showing an electronic device using the nonvolatile memory of the present invention.

Claims (6)

[Claims] A source region, a drain region, and an active region formed using a single crystal semiconductor; an impurity region provided locally with respect to the active region; And a substantially intrinsic channel forming region. 2. A source region, a drain region and an active region formed using a single crystal semiconductor, an impurity region locally provided in the active region, and an intrinsic or substantially interposed region between the impurity regions. A non-volatile memory region, wherein the impurity region is made of an element selected from Group 13 or Group 15. 3. A source region, a drain region, and an active region formed using a single crystal semiconductor, an impurity region locally provided in the active region, and an intrinsic or substantially interposed region between the impurity regions. Wherein the impurity region is made of an element selected from Group 13 or Group 15, and the impurity region suppresses a depletion layer extending from the drain region toward the source region. Non-volatile memory characterized by the above-mentioned. 4. The nonvolatile memory according to claim 1, wherein said impurity region is provided in a stripe shape from said source region to said drain region. 5. The semiconductor device according to claim 1, wherein the concentration of the element contained in the impurity region is 1 × 10 ¹⁷ to 5 × 10 ²⁰ atoms.
s / cm ³ , a non-volatile memory. 6. An electronic apparatus using the nonvolatile memory according to claim 1 as a recording medium.