TW521544B - Arrangement of many circuit-modules - Google Patents
Arrangement of many circuit-modules Download PDFInfo
- Publication number
- TW521544B TW521544B TW090111641A TW90111641A TW521544B TW 521544 B TW521544 B TW 521544B TW 090111641 A TW090111641 A TW 090111641A TW 90111641 A TW90111641 A TW 90111641A TW 521544 B TW521544 B TW 521544B
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- TW
- Taiwan
- Prior art keywords
- configuration
- scope
- item
- circuit module
- connection
- Prior art date
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- Condensed Matter Physics & Semiconductors (AREA)
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- Wire Bonding (AREA)
- Connector Housings Or Holding Contact Members (AREA)
- Multi-Conductor Connections (AREA)
Description
521544 五、發明説明(1 ) 本發明涉及一種依據申請專利範圍第1項前言之多 個電路模組所形成之配置。 就電路技術而言,特別是半導體電子技術,長久以來 即力求形成一些電路配置,其以最小之空間達成一種數 目儘可能多之元件及/或電路功能。因此,力求在實際 上可能較大之範圍中使相對應之元件及切換功能變 少。由於實際上固定之極限不可更小,因此須注意:就 每一電子元件而言,一方面須設置一種與實際原理有關 之最小値,但另一方面是此種最小値只能以巨大之成本 來大量生產。 因此須探討一些方法,藉由適當之連接以確保一種儘 可能高之面積使用率。因上建議特別是在半導體模組 (晶片或全部一般之電路模組)中時在垂直方向中以上 下層之方式配置多個所需之電路模組。此種多個電路 模組之所謂堆疊因此由二維平面及封裝配置向外延伸 且在垂直方向中由於多個電路模組之相對應之封裝而 使第三空間可重疊地利用。 上下配置之電路模組通常須互相連接。即,至各別電 路模組之外部接觸區所需之各連接元件須藉由適當設 置之連接元件至少一部份在電性上及電路技術上與多 個上下配置之連接元件(即,介於電性隔離之電路模組 之間)互相連接。於是使用多種不同之槪念,以便應用 於各別電路模組之連接元件互相連接時。 在先前技術中已爲人所知的是:不同大小之電路模組 521544 五、發明説明(2 ) 上下配置著,使得在垂直方向中形成一種基面由下向上 逐漸變小之電路模組所造成之平截頭棱錐體形式之結 構,其以堆疊形式配置在相對應之載體上。爲了形成連 接作用,則相對應之連結線須各別由每一電路模組向下 延伸至共同載體之表面,此處可在相對應之導電基板上 向外以及向著各模組而達成特定之接觸作用。此種方 式之缺點是:須設計不同大小之電路模組(即,基面),因 此相同模組之組合是有問題的。另一方面是須分別形 成各別之連結線且延伸之,這樣雖未違反此種接觸作用 之自動化,但形成此種自動化過程是困難的。 反之,若相同大小之電路模組形成堆疊而上下配置著, 只有當最下方之電路模組例如依據覆晶(F 1 i p - c h i p )技 術而固定在共同之載體上且可接觸時,則位於上方之電 路模組才需要藉由適當之連結線來連接。 爲了克服此種問題,則須採用其它方式。例如,1;8-P S - 5 0 1 6 1 3 8中揭示許多電路模組所形成之配置,其中各 電路模組以堆疊之形式上下配置著。設有一種連接裝 置(其包含許多連接元件)使電路模組可與外界相接 觸。在習知之US-PS 5 0 1 6 1 3 8之先前技藝中,此種連接 裝置以下述方式達成··各別之晶片配置在各別之載體 上。載體上此晶片之各接觸區經由載體邊緣上所施加 之電路配置而向外延伸至相對應之接觸銷(其配置在載 體之邊緣區域中)。接觸銷之各別之整體經由多個在側 面上包含此堆疊之接觸板及連接板且互相接觸及連 -4- 發明説明(3 ) 接。 此種方式之缺點是:每一電路模組須配置在載體上且 不同載體之互相連接使許多各別之組件之安裝是需要 的,因爲多個模組之原來之連接方式由於其自然之構造 在此是不可能的。 本發明之目的是提供多個電路模組所形成之配置,其 中多個上下配置之電路模組之連接是以特別可靠且同 樣簡單及成本有利之方式來達成。 本發明之目的以具有申請專利範圍第1項特徵之多 個電路模組所形成之配置來達成。有利之其它形式描 述在申請專利範圍各附屬項中。 在多個電路模組之此種配置中,各電路f吴組是以堆豐 之形式上下配置著。爲了使各電路模組達成外部之接 觸作用,則一種連接.裝置設有多個連接元件。各電路模 組之連接裝置之間至少一部份設有電性連接件。 本發明中多個電路模組所形成之配置之特徵是:不同 連接裝置之相互間之電性連接是藉由不同連接裝置之 各連接元件之間直接之機械及電性接觸而形成。 本發明之基本槪念是,在多個電路模組之配置中以下 述方式達成一種電性接觸,因此亦達成電路模組之連接: 各電路模組之連接元件(其對電路模組之每一相對應之 連接裝置形成一種至外部之接觸作用)直接上下配置而 無中間電路或未使用其它接觸元件而形成。若上下配 置之電路模組必須互相連接,則本發明中以下述方式達 521544 五、發明説明(4 ) 成:形成各電路模組之連接裝置所用之各連接元件可互 相直接形成接觸。”直接”之意義不與”接觸及固定時所 設置之焊接元件”相違逆。 本發明此種配置在使上下配置之電路模組相接觸時 原則上不需其它之組件(其在電路模組之各連接元件之 間須形成該接觸作用)。此種安裝因此可簡化且較可 靠。 若各連接元件就其幾何上,機械上及/或電性上以相 同方式或相同作用構成,則本發明之多個電路模組之配 置是特別有利的。正如使用相一致之電路模組一樣,其 表示:整個連接元件(其形成各別電路模組之連接裝置) 以相同方式構成,這適合大量之生產過程。 各連接元件較佳是以連接線構成,其特別是可以線性 延伸之形式構成。利用此種連接線形式之此種連接元 件,則整個間距可以簡易之方式由電路模組之任一面上 之接觸區跨接至其邊緣。此外,各連接線就其形式穩定 性及機械上之可固持性而言具有特別有利之特性。其 可以簡易地製成,輕微地成型且仍具有足夠之阻抗性, 以便可用在自動之安裝-及裝配設備中。 在較佳之實施形式中,各連接元件(特別是連接線)分 別具有第一末端,其用來與各別之電路模組相接觸。此 外,設有第二末端,其同樣可用來與另一電路模組之至 少另一連接元件相接觸。此外,此連接元件(特別是連 接線)具有一個主區,其在此連接元件之第一末端和第 521544 五、發明説明(5 ) 二末端之間延伸且特別是可測定此種待接觸之區域之 間距。 特別簡單之幾何配置之設計方式是:各連接元件(特 別是連接線)之第二末端分別具有一種線性及/或垂直 於主區而延伸之區域。即,在連接兀件日寸主區及第^末 端分別互相垂直地與其它電路模組之其它連接元件相 接觸。因此,特別有利的是:各連接元件(特別是連接線) 較佳是具有(特別是縱向延伸之)鈎形,L形,爪形或類似 之形式。此外,較佳是在連接元件之主區及連接元件之 第一及/或第二末端之間之過渡區中形成一種肩形件或 類似件。 由於前述之措施,則可以上述之連接元件以特別簡易 之方式在接觸區之一側上形成一種對即將連接之電路 模組之接觸區且在另一側上可與垂直相鄰之電路模組 相連,其中上述之肩形件(特別是連接元件之第二末端 區中者)適合用來形成一種對其它連接元件之接觸區。 本發明之多個電路模組之配置在安裝時須防止各連 接元件或連接裝置持續地變形。但由於在設有連接元 件之電路模組定位時定位中之某種容許度及各別電路 模組在垂直或水平方向中之移動不可避免,則特別有利 的是:本發明此種配置之連接元件(特別是連接線)特別 是在第二末端區中須以彈性方式構成。由於此種特性, 則連接元件在定位時可接收各容許度(tolerance)且因 此可容許所產生之機械上之損傷而不會在連接元件本 -7- 521544 五、發明説明(6 ) 身或接觸位置上造成缺陷。 本發明之配置可有利地以下述方式形成:各電路模組 就其幾何上,機械上及/或電性上(特別是電路技術上)之 特性而言以相同方式及/或相同作用而形成。 若可達成一種高的封裝密度或堆疊密度,則以習知方 式可形成特別省空間之配置或堆疊。依據經驗,高的堆 疊-或封裝密度特別是在幾何上及機械上之特性中所需之 前提是相同形式。此外,當電性及特別是電路特性相對 應地互相調整時,則這樣亦是有利的。 各電路模組較佳是以平坦形式,層形式或類似形式及 /或一種具有上側及下側之平面來構成。這同樣可達成 一種特別高之封裝密度,其可以簡易方式達成,特別是 在自動生產過程時。 各電路模組較佳是分別具有至少一個半導體晶片(特 別是記憶體裝置)及/或以一種所謂裝置來構成。各記 憶元件所形成之堆疊之重大優點是:相同電路模組之電 路技術上之相同形式可予以利用。就像在記憶體裝置 中者一樣,使連接面達成一種儘可能高之使用率是需要 的且是値得追求的。這由於本發明之配置而可以簡易 之方式達成。 爲了使電路模組可與其連接裝置(特別是各別之連接 元件)相接觸,則各電路模組分別具有至少一個接觸區, 其特別是設有多個外部接觸用之接觸區。在半導體模 組或晶片中,這些接觸區通常由所謂PADs構成,其使內 521544 五、發明説明(7 ) 部之半導體結構可與外界相接觸。本發明之設計方式 是:電路模組之連接裝置之連接元件(特別是其第一末 端)分別與各別電路模組之接觸區相接觸。 各接觸區較佳是由電路模組上之金屬區所形成,且較 佳是形成在其下側以及特別是由所謂P A D s所形成。 特別是在記憶體模組中已顯示之優點是:各接觸區在電 路模組之下側上分別形成在其中央區中。在工業標準 中這稱爲中央pad晶片(CPC)。 在此種連接裝置之構造中,這些指定之構造形式已證 實是特別有利的。因此,此種連接裝置具有至少一個列 配置,特別是等間隔,平行及/或齊平地對準及/或相同指 示之連接元件,較佳是沿著各電路模組之至少一個邊緣 區域而對準。特別有利的是:連接線以相同形式及長度 互相平行且齊平地(依據梳子之形式)而對準。 較佳是:此連接裝置具有二個由連接元件所形成之列 配置,且列配置(特別是其連接元件)在橫向中須互相一 致地配置著或互相配置在空隙上,其中這些列配置較佳 是位於共同之平面上且對此平面中之軸成鏡面對稱而 配置著。 各連接元件之此二個列配置因此可互相面對地配置 著,各列之連接元件之第一末端互相面對且第二末端 (至外部之接觸用)分別互相以最大間距相隔開。由於 配置在空隙上或相一致地配置著,則各接觸區之各別之 配置可設在此電路模組之下側上。 -9· 521544 五、發明説明(8 ) 各連接元件或連接線例如可形成各接觸腳,各腳在 相一致之配置中以共線之方式而對準。每一個列配置例 如沿著所屬電路模組之邊緣而延伸,使二個相面對之邊 緣保持裸露,而各連接元件之二個列配置之至少一部份 是沿著此電路模組之其它二個相面對之邊緣而延伸。 在本發明之配置之其它有利之實施形式中,此連接裝 置分別具有由各連接元件所形成之4個列配置。此4 個列配置分別沿著至少一個邊緣區而配置且以成對方 式而互相面對。例如,在具有正方形基面或矩形基面之 電路模組中一列連接元件可沿著此電路模組之一個邊 緣而延伸。以此種方式可形成數目特別多之連接裝 置。 許多個列配置(特別是其連接元件)亦可位於一個共 同之平面中。此外,各別相面對之列配置(特別是各連 接元件)以鏡面對稱於此平面之軸而對準。各別相對之 列配置之各連接元件又以共線或相一致之方式而對準 或各連接元件直立在空隙上。 各別之列配置可由各別相隔開之連接元件所形成。 有利之方式是各別之列配置分別由各連接元件之結合 所形成,各連接兀件配置在及/或固定在一種連接載體 上。因此可形成一種特別是雙面之黏合介質(特別是帶 狀),其上特別是可施加及/或可埋入各別之連接元件。 因此,實際上可考慮一種雙面黏合帶之形式或相對應之 埋入-或黏合材料。 -10- 521544 五、發明説明(9 ) 爲了使上下配置之電路模組可上下接觸及連接,則本 發明之設計方式是:直接上下配置之電路模組之列配置 至少一部份具有垂直方向相一致之連接元件。因此,能 以特別簡易之方式使直接上下配置之電路模組之直接 相鄰之連接元件互相接觸,使電路模組相連。 有利之方式是:須形成直接上下配置之電路模組之垂 直相一致之連接元件之至少一部份(特別是其方位,其 幾何大小及/或類似物),以便在機械上及電性上互相接 觸,其中特別是垂直方向中配置於較高處之第一電路模 組之各連接元件可與其肩形件之區域中之第二末端相 接觸或可與直接垂直配置於下方之第二電路模組之各 別垂直相一致之連接元件之第二末端相接觸。 這可特別簡易地以下述方式達成:各連接元件之機械 上和電性上之接觸區分別藉由焊接(特別是雷射焊接) 及/或由於利用彈簧應力之非正鎖定(11 ο η - ρ 0 s i t i V e locking)而形成在連接元件之第二末端區中。 爲了改良本發明中此配置之接觸性及使用性及其可 操縱性,則須設置一種載體,其上配置此種垂直方向中 上下配置之電路模組之最下方之一個,使之固定及/或 使之可被電性接觸。此外,有利之方式是形成一種外殻 裝置(特別是澆注材料之形式),其中可容納至少一個電 路模組。藉由此種措施,則可使此種多個電路模組所形 成之配置以簡單之方式整體式地受操控。此載體亦可 具有相對應之連接及接觸區,以裝入其下級裝置中。 -11- 521544 五、發明説明(】0 ) 先前技藝中由電路模組所形成之配置所具有之缺點 是:所使用之各電路模組必須互相適應,但必須忍受各 電路模組上下連接時所需之巨大之費用。
特別是在所謂中央PAD晶片上下配置(特別是所謂 c h i p - s c a 1 e - p a c k a g e)時,則此種缺點是不允許的。在本 發明之配置中,此種缺點以下述方式來防止:所有上下 配置之電路模組之基本連接槪念是共通的。藉由本發 明之構成,則各電性接點可向外延伸至此電路配置之邊 緣且能以簡易之方式藉由各別之連接裝置而圍繞在此 電路配置之周圍。因此可形成統一之單一組件(即,電 路模組),其可上下安裝及配置著,且能以特別簡易之方 式使接近(a c c e s s )方式自動化。電性連接藉由重疊及連 接元件或連接線之持續地連接而達成。可各別施加各 連接線或連接元件或以結構化之鬆帶(Flex-Tape)來構 成。 可以簡易之方式上下安裝多於二個之電路模組或晶 片。此外,可簡易地由上下配置之相連之電路模組所形 成之堆疊中取出有缺陷之組件。 本發明以下將依據圖式中之較佳之實施例來詳述。 圖式簡單說明: 第1圖用於本發明之配置之實施形式中之電路模 組之已部份切開之側視圖。 第2圖第1圖之電路模組之由下方所看到之部份 圖。 -12- 521544 五、發明説明(11 ) 第3圖另一電路模組之由下方所看到之部份圖。 第4圖用在本發明之實施例中之連接元件之側視 圖。 第5圖第1圖之電路模組之下側之透視圖。 第6圖本發明之另一實施例之部份已切開之側視 圖。 第1圖是電路模組之已部份切開之側視圖,此電路模 組2用在本發明之配置中。 此電路模組2在此情況中由晶片20構成,其例如可 設在相對應之基板中。此電路模組2具有一種平坦式 板形之正方形之形式且具有一種邊緣區或側面區 1 1 a,1 1 b。在電路模組2之上側2b保持空著的時候,外 部接觸用之連接裝置5形成在此電路模組之下側2a 上。 此連接裝置5由形成在連接載體1 2上之連接元件6 之二個列配置l〇a及l〇b所構成。 各連接元件6具有主區9,第一末端區7及第二末端 區8。末端區7之作用是與電路模組2之接觸區3相 連且特別是與接觸區4相連。反之,連接元件6之第二 末端8用來與另一電路模組2之另一連接元件6相接 觸。各連接元件6在主區9及第二末端8之間之過渡 區中分別具有一個肩形件8 a。在主區9及連接元件6 之第一末端之間之過渡區中分別設有一個肩形區7 a ° 爲了適應地使上下配置之電路模組2相隔開,則須在 521544 五、發明説明(12 ) 電路模組2之下側2a上形成一種所謂間隔件22。 第2圖是在間隔件22省略之情況第1圖所示電路模 組2之下側2 a。 在電路模組2之下側2a之中央區2c中形成該接觸 區3,其具有多個接觸區4。連接線6a形式之連接線6 由接觸區4開始延伸,各連接線6 a可與接觸區4上之 其第一末端7相接觸。各線6 a由下側2 a上之中央區 2 c開始直線地延伸至邊緣區1 1 a和1 1 b,在其第二末端 8向外延伸,第二末端8垂直向上由圖式之平面向外延 伸。 連接裝置5之連接元件6或連接線6a(其屬於此電 路模組2之邊緣區1 1 a及1 1 b)分別形成一種列配置 1 0 a和1 0 b (其齊平地配置在各空隙上)。各連接線6 a 向右外方或向左外方交替地延伸至此電路模組2之邊 緣區1 1 b或1 1 a。 . 第3圖顯示:列配置1 〇 a和1 〇 b之連接元件6或6 a 亦可相一致地對準,其中在電路模組2之下側2 a之中 央區2 c中設置二個由接觸區4所形成之相鄰之列於此 電路模組2之接觸區3中。 第3圖所示之構造在其它方面是與第2圖所示者相 同。 第4圖是連接元件6或連接線6a之已部份切開之側 視圖,其亦用在第1圖所示之電路模組2中使各電路模 組2可與外部相接觸。 •14- 521544 五、發明説明(13 ) 連接線6 a或連接元件6由一個直線延伸之主區9所 形成。連接線6a具有第一末端7,其由連接線6主區9 開始而由第一肩形區7a伸出。第二末端8面對第一末 端7而形成,第二末端8由連接線6a之主區9開始而 由第二肩形區8 a中伸出。第二末端8 a由直線形之線 段所形成,其垂直於連接線6主區9。本實施例中整體 而言此連接線6a具有一種縱向而延伸之鈎形,爪形 或”L”形。 爲了進一步說明本發明之配置中所使用之電路模組 2之構成,則第5圖中以透視圖由下方顯示第1圖之此 種電路模組2,其中省略該間隔件2 2中之一以便可更淸 楚地說明。 此電路模組2由電路配置20所構成,其需要時容納 於相對應之澆注材料中。此電路配置20之上側亦形成 電路模組2之上側2b。此電路模組2之下側2a由連 接裝置5所形成,其具有二個由連接元件6或連接線6s 所形成之列配置1 〇 a和1 0 b。 連接元件6或連接線6a具有縱向延伸之鈎形或爪形 或L形,其中一個線性延伸之主區9設有第一末端7及 第二末端8。 此二個列配置1 〇 a和1 0 b之多個連接元件6或連接 線6a此處互相偏移而設置在各空隙上且以其第一末端 7在接觸區3之一個接觸區4中由電路模組2之下側 2 a之中央區2 c中開始垂直地延伸至電路模組2之邊 -15- 521544 五、發明説明(15 ) 較佳是凸出於邊緣區上方以擴大其表面,各邊緣區未被 各接觸元件所佔用。 由第5圖可知,一種在垂直方向中配置於上方之電路 模組2之連接元件6或連接線6 a以其第二末端8來與 垂直方向中直接配置於其下方之電路模組2之連接裝 置6或連接線6機械上及電性上之接觸,這特別是在連 接元件6或連接線6 a之所謂肩形區8 a中達成。最下 方之電路模組2之連接線6或連接元件6 a直接固定在 載餅1 4上且相接觸,因此可達成此種例如配置在上級 電路裝置中之外部連接或達成其應用目的。 符號說明 2.. .電路模組 3.4.. .接觸區 5.. .連接裝置 6.. .連接元件 7,8 ...末端 9 ...主區 10a,10b,10c,10d…列配置 1 la,l lb,l lc,l Id...邊緣區 12…連接載體 14.. .載體 15…外殻裝置 2〇··.電路配置 22.. .間隔件 -17-
Claims (1)
- 521544 請 委 員 六、申請專利範圍 本 修 J匕 後 是 否 變 f h 實 1-ί η 第901 1 1641號「多個電路模組所形成之配置」專利案 (90年10月修正) 六申請專利範圍 1. 一種多個電路模組所形成之配置, -此電路模組(2)以堆疊之形式上下配置著, -分別設有一種連接裝置(5)使各電路模組(2)可與外部 接觸, -在電路模組(2)之各連接裝置(5)之間至少一部份設有 電性連接區, -不同之連接裝置(5)之電性連接區是藉由不同之連接 裝置(5)之直接之機械上及電性上之接觸區來形成, 其特徵爲: -此連接裝置(5)具有多個連接元件(6)所形成之至少一 部份是形成在一個平面中之列配置(10a-d), -多個連接元件(6)配置在連接載體(12)上及/或固定在 其上。 2·如申請專利範圔第1項之配置,其中各連接元件(6)就其幾 何上,機械上及/或電性上而言是以相同形式或相同作用方 式而構成。 3.如申請專利範圍第丨或第2項之配置,其中此連接元件(6) 以連接線(6a)構成。 4·如申請專利範圍第3項之配置,其中各連接線(6a)以直線 延伸方式構成。 5.如申請專利範圍第丨或第2項之配置,其中各連接元件 521544 六、申請專利範圍 (6)(特別是連接線(6a))分別具有:第一末端(7),以便與各別 之電路模組(2)相接觸;第二末端(8),需要時可與另一電路 模組之至少一連接元件(6)相接觸;以及一個在此二個末端 (7,8)之間延伸之主區(9)。 6. 如申請專利範圍第5項之配置,其中各連接元件(6)(特別 是連接線(6a))之第二末端(8)分別具有一種直線延伸區及/ 或垂直於主區(9)而延伸之區域(9)。 7. 如申請專利範圍第3項之配置,其中各連接元件(6)(特別 是連接線(6a))分別具有一種(特別是縱向延伸之)鈎形,”L” 形,爪形或類似之形式,其中在主區(9)和第一及/或第二末 端(7,8)之間之過渡區中形成一種肩形件(7a,8a)或類似 物。 8. 如申請專利範圍第6項之配置,其中各連接元件(6)(特別 是連接線(6a))分別以彈性方式特別是形成在第二末端(8) 之區域中。 9. 如申請專利範圍第1項之配置,其中各電路模組(2)就其幾 何上,機械上及/或電性上且特別是電路特性上而言是以相 同方式及/或相同作用而構成。 10. 如申請專利範圍第1項之配置,其中各電路模組(2)分別以 平坦式,層之形式或類似形式及/或以具有上側(2a)和下側 (2b)之平面形式來形成。 11·如申請專利範圍第1或第10項之配置,其中各電路模組(2) 分別具有至少一個半導體晶片(特別是記憶體裝置)及/或 以此種晶片構成。 521544 六、 申請專利範圍 12. 如 串 m 專利範圍第11項之配置,其中 - 各 電路模組(2)分別具有至少一個接觸區(3),其具有多 個 外 部 接觸用之接觸區(4), - 電 路模組(2)之連接裝置(5)之連接元件(6)(特別是其 第 一 末 端(7))分別與各電路模組(2)之接觸區(3)之至少一 個 接 觸 區(4)相接觸。 ia 如 甲 F?丰 曰円 專利範圍第12項之配置,其中在電路模組(2)上設 置 金 屬 區(特別是所謂PADS)作爲接觸區(4)。 14. 如 串 三主 pR 專利範圍第12項之配置,其中此電路模組(2)之下 側(2b)上之接觸區(3)分別形成在中央區(2c)中。 15. 如 串 請 專利範圍第1或第2項之配置,其中列配置(l〇a-d) 之 各 連 接元件(6)分別以等間距,平行及/或齊平方式而對 準 及 /或相同地定向著,較佳是沿著各別電路模組(2)之至 少 —^ 個 邊緣區(lla-d)而對準。 16. 如 串 請 專利範圍第15項之配置,其中 一 此 連接裝置(5)具有二個由連接元件(6)所形成之列配 置 (10a-d)9 - 此 列配置(10a-d)(特別是其連接元件(6))在橫向中互 相 一 致 地配置著或互相配置在空隙上, - 特 別是列配置(10a-d)位於一種共同平面中且以鏡面 對 稱 於 此平面中之軸而對準。 17. 如 串 請 專利範圍第15項之配置,其中 -itt :連接裝置(5)分別具有4個由連接元件(6)所形成之 列 配 置 (10a-d), -3- 521544 、申請專利範圍 -各列配置(10a-d)(特別是其連接元件(6))分別沿著至 少一個邊緣區(1 la-d)而以成對相面對之方式配置著, -特別是列配置(10a-d)位於一種共同平面中且每二個 互相面對之列配置(10a-d)分別以鏡面對稱於一種位於該 共同平面中之軸之方式而對準。 18. 如申請專利範圍第16項之配置,其中 -此連接裝置(5)分別具有4個由連接元件(6)所形成之 列配置(10a-d), -各列配置(10a-d)(特別是其連接元件(6))分別沿著至 少一個邊緣區(1 1 a-d)而以成對相面對之方式配置著, -特別是列配置(10a-d)位於一種共同平面中且每二個 互相面對之列配置(10a-d)分別以鏡面對稱於一種位於該 共同平面中之軸之方式而對準。 19. 如申請專利範圍第16項之配置,其中此列配置(l〇a-d)分別 由各別相分開之連接元件(6)所形成及/或由連接元件(6) 之結合而形成。 20. 如申請專利範圍第19項之配置,其中此連接載體(12)較佳 是以雙面黏合之介質(較佳是帶狀)來形成,其上或其中可 施加或可埋入各連接元件(6)。 21. 如申請專利範圍第16項之配置,其中直接重疊而設置之電 路模組(2)之列配置(10a-d)至少一部份具有垂直相一致之 連接元件(6)。 22·如申請專利範圍第2 1項之配置,其中特別就定向,幾何大 小及/或類似件而言須形成直接重疊配置之各電路模組(2) -4- 521544 、申請專利範圍 之垂直相一致之各連接元件(6)之至少一部份以便在機械 上及電性上互相接觸,其中配置在垂直方向中較高之第一 電路模組(2)之特別是連接元件(6)在肩形件(8a)之區域中 或在直接垂直配置於下方之第二電路模組(2)之垂直相一 致之連接元件之第二末端(8)之區域中是可接觸的。 23. 如申請專利範圍第1或第2項之配置,其中各連接元件(6) 之機械上及電性上之接觸區分別藉由焊接(特別是雷射焊 接)及/或由於彈簧應力所造成之非正(non-positive)鎖定 (locking)而可形成在各連接元件(6)之第二末端(8)之區域 中〇 24. 如申請專利範圍第1,9或10項之配置,其中設有一種載體 (14),其上可配置,固定及/或電性接觸此種在垂直方向中配 置在最下方之電路模組(2)。 25·如申請專利範圍第1,9或10項之配置,其中設有一種特別 是澆注材料形式之外殼裝置(15),其中至少可容納此電路 模組(2)。 26如申請專利範圍第24項之配置,其中設有一種特別是澆注 材料形式之外殼裝置(15),其中至少可容納此電路模組 ⑵。 27·如申請專利範圍第1,9或10項之配置,其中在二個電路模 組(2)之間分別設置一種間隔件(2 2),其特別是用來去除電 路模組之熱量及/或作爲吸熱用。 2&如申請專利範圍第24項之配置,其中在二個電路模組(2) 之間分別設置一種間隔件(22),其特別是用來去除電路模 521544 ^、申請專利範圍 組之熱量及/或作爲吸熱用。 2S.如申請專利範圍第25項之配置,其中在二個電路模組(2) 之間分別設置一種間隔件(22),其特別是用來去除電路模 組之熱量及/或作爲吸熱用。
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US5016138A (en) * | 1987-10-27 | 1991-05-14 | Woodman John K | Three dimensional integrated circuit package |
US5036431A (en) * | 1988-03-03 | 1991-07-30 | Ibiden Co., Ltd. | Package for surface mounted components |
DE3911711A1 (de) * | 1989-04-10 | 1990-10-11 | Ibm | Modul-aufbau mit integriertem halbleiterchip und chiptraeger |
US5019943A (en) * | 1990-02-14 | 1991-05-28 | Unisys Corporation | High density chip stack having a zigzag-shaped face which accommodates connections between chips |
KR0124494B1 (ko) * | 1992-03-31 | 1997-12-10 | 사또 후미오 | 플라스틱 패키지 반도체 디바이스와 그 제조방법 및 제조장치 |
KR100209782B1 (ko) * | 1994-08-30 | 1999-07-15 | 가나이 쓰도무 | 반도체 장치 |
JPH1012811A (ja) * | 1996-06-21 | 1998-01-16 | Hitachi Ltd | 半導体集積回路装置及びその製造方法 |
JPH1041455A (ja) * | 1996-07-18 | 1998-02-13 | Hitachi Ltd | 半導体装置及びモジュール構造体並びにその製造方法 |
DE19758197C2 (de) * | 1997-12-30 | 2002-11-07 | Infineon Technologies Ag | Stapelanordnung für zwei Halbleiterspeicherchips und Leiterplatte, die mit einer Vielzahl derartiger Stapelanordnungen bestückt ist |
US6020629A (en) * | 1998-06-05 | 2000-02-01 | Micron Technology, Inc. | Stacked semiconductor package and method of fabrication |
-
2000
- 2000-05-16 DE DE10023869A patent/DE10023869C2/de not_active Expired - Fee Related
-
2001
- 2001-04-27 EP EP01110454A patent/EP1156529A3/de not_active Withdrawn
- 2001-05-11 JP JP2001142357A patent/JP2002016218A/ja active Pending
- 2001-05-15 TW TW090111641A patent/TW521544B/zh not_active IP Right Cessation
- 2001-05-16 KR KR10-2001-0026692A patent/KR100538524B1/ko not_active IP Right Cessation
- 2001-05-16 US US09/858,421 patent/US6737581B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR20010106254A (ko) | 2001-11-29 |
DE10023869A1 (de) | 2002-01-17 |
EP1156529A2 (de) | 2001-11-21 |
EP1156529A3 (de) | 2004-09-29 |
JP2002016218A (ja) | 2002-01-18 |
US6737581B2 (en) | 2004-05-18 |
US20020050376A1 (en) | 2002-05-02 |
DE10023869C2 (de) | 2002-09-26 |
KR100538524B1 (ko) | 2005-12-23 |
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