TW518924B - Multi-layer printed wiring board and manufacturing method therefor - Google Patents

Abstract

The object of the present invention is to flatly form a wiring pattern on a connection hole, to make the connection hole finer, and further to make the wiring pattern thin. On a board 2, a 1st wiring pattern 3 is formed and on the board 2 provided with the 1st wiring pattern 3, a thin-film insulating layer 7 is formed; and a connection hole 8 is formed in the thin-film insulating layer 7 so that the 1st wiring pattern 3 is exposed to the outside, and a metal conductive layer 13 is formed on the thin-film insulating layer 7 having the connection hole 8 and then selectively removed to form metal bumps 9. An inter-layer insulating layer 11 is formed on the thin-film insulating layer 7, and a 2nd wiring pattern 12 is formed on the inter-layer insulating layer 11.

Description

518924 A.7 B7 V. Description of the Invention (彳) [Technical Field of the Invention] The present invention relates to an assembled multi-layer printed circuit board and a method for manufacturing a multi-layer printed circuit board in which a conductive layer is formed on an interlayer insulating film. [Previous technology] With the miniaturization of electronic equipment, high-density wiring of printed circuit boards is generally required. In response to this need, in printed circuit boards 2, the use of assembled multilayer printed circuit boards has become a trend. Such a multilayer printed circuit board is formed, for example, by forming an interlayer insulating layer on a first wiring pattern formed on the substrate, and forming a connection hole in this interlayer insulating layer so as to perform connection with the layer of the second wiring pattern. The interlayer insulation layer is fully copper-plated and patterned to form a second wiring pattern. The interlayer insulating layer formed on the first wiring pattern is formed by applying ink on the surface of the substrate or laminating a dry film on the surface of the substrate. The connection holes formed on the interlayer insulating layer are formed by photoetching, laser, etc. form. [Problems to be Solved by the Invention] However, since this multilayer printed circuit board is copper-plated on the surface of the interlayer insulating layer including the inner surface of the connection hole and patterned to form a second wiring pattern, the connection hole is formed. A notch P is formed in and around the portion. When a second wiring pattern, that is, a recess is formed on the outer layer pattern of the multilayer printed circuit board, electronic components cannot be mounted in a stable state. Therefore, although it is also possible to fill the connection holes with the conductive paste, thereby filling the connection holes, the second wiring pattern, that is, the portion forming the connection hole on the outer layer pattern and its surroundings will not have a recess. But because of this printed electricity -4-

518924 A7

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518924

Next, as shown in FIG. 4 (B), a conductor layer 10 is formed on the substrate 10i on which the wiring pattern 102 is formed so as to cover the wiring pattern 102. This conductive layer 103 is formed by a non-electrolytic plating method using a nickel-gold alloy and a tin-lead solder alloy. Here, the conductive layer 10 is selected from metals having resistance when the metal plating layer 104 described later is etched. Next, as shown in FIG. 4 (C), a metal plating layer 104 is formed on the conductor layer 103 using copper, nickel, or the like. Next, a photomask is formed on the metal plating layer 104, and the metal plating layer 104 is etched to form a metal bump 105 for maintaining electrical connection with the wiring pattern of the outer layer as shown in FIG. 4 (D). The etching target at this time is limited to the metal plating layer 104, and therefore, the conductive layer 103 provided on the substrate 101 will remain. That is, the conductor layer 103 has a function as a barrier layer for etching the metal plating layer 104. Next, as shown in FIG. 4 (E), the conductive layer 103 is removed by providing a photomask and performing etching. Next, as shown in FIG. 4 (F), an interlayer insulating layer 10 is formed in a region where the metal bump 105 is not provided, so as to keep the wiring pattern of the outer layer and the wiring pattern 102 of the inner layer insulated. Then, the surface of the interlayer insulating layer 10 is polished so that it is consistent with the end surface of the metal bumps 05. Next, as shown in FIG. 4 (G), copper plating is applied to the surface of the interlayer insulating layer 106, and the electric money layer is patterned to form a wiring pattern 107 as an outer layer. However, in the method shown in FIG. 4, it is necessary to form the conductive layer 10 as the etching stopper for the etching performed when the metal bump 105 is formed, and after the metal bump f05 is formed, the conductive layer must be removed. Bulk layer 1 03. That is, in order to form the metal bumps 105, this method must be performed two different times to form a conductive layer 103 and a metal plating layer 104, and perform two different terms. -6-This paper standard applies to Chinese national standards (CMS) A4 size (210 X 297 mm)

Hold

▲ 518924

The result is that the conductor layer 103 and the metal plating layer 104 are removed. As a result, the manufacturing process of the circuit board is very complicated. In addition, since the metal ghost 105 and the wiring pattern 102 are connected through the conductive layer M2, there are two things to perform interface processing to improve the adhesion between the wiring pattern and the conductive layer, and the conductive layer 103 and the metal bump 105. Of tightness. An object of the present invention is to provide a layered printed circuit board and a method for manufacturing the printed circuit board, which can form the wiring pattern on the connection hole in a flat shape and further form the connection hole to further finer the wiring pattern. Another object of the present invention is to provide a multilayer printed circuit board and a method for manufacturing the printed circuit board that can improve production efficiency while achieving the above-mentioned objects. [Means for solving problems] In order to solve the above-mentioned problems, the multilayer printed circuit board of the present invention includes a substrate that forms a wiring pattern; a thin-film insulating layer that forms a wiring pattern on the substrate; an interlayer insulating layer , Which is provided on a thin-film insulating layer; metal bumps, which are surrounded by a thin-film insulating layer and an interlayer insulating layer, are protruded by the thin-film insulating layer, and are provided on a wiring pattern; and wiring patterns, which are It is provided on the interlayer insulation layer and is connected to the metal bump. In order to solve the above problems, the above-mentioned method for manufacturing a multilayer printed circuit board includes a wiring pattern forming step, which is a step of forming a wiring pattern on a substrate, and a thin film insulating layer forming step, which is a method of covering the wiring pattern with a thin film insulating layer. Formed on a substrate provided with a wiring pattern; the step of forming a connection hole is to form the connection hole in such a way that the wiring pattern faces the outside. 7- This paper is compliant with the Chinese Standard (CNS) Α Grid (210X297) Public)

Pretend

Those formed on the thin film insulation layer; the step of forming the metal conductive layer, which is electroplated to turn the metal conductive sound; Λ ', the dimple slip is formed on the thin film insulation layer forming the connection hole; the step of forming the metal bumps uses the selectivity Remove the metal guide; the way of the layer 'forms the metal bumps protruding from the insulating layer; the interlayer insulation layer forming step is to form the interlayer insulating layer on the thin film insulating layer in a manner of surrounding the metal bumps; and A wiring pattern forming step in which another wiring pattern is formed on the interlayer insulating layer using a second plating process of the same kind as the first plating process. [Embodiments of the invention] Hereinafter, a multilayer printed circuit board to which the present invention is applied and a method of manufacturing the printed circuit board will be described with reference to the drawings. As shown in Fig. 1, a multilayer printed circuit board to which the present invention is applied has a substrate 2 which is an insulating substrate formed by impregnating glass fibers with an insulating resin such as epoxy resin. The first wiring patterns 3 and 3 constituting the inner layer are formed on both sides of the substrate 2 by etching copper foils attached to both sides of the substrate 2. In addition, a connection hole 4 is formed on the substrate 2 to allow the first wiring patterns 3 and 3 to be electrically connected. An electric ore layer 5 is provided in the connection hole 4 so that the first wiring pattern 3 ′ 3 can be electrically maintained. Sexual connection. The connection hole 4 is permanently filled with a conductive or insulating paste 6 in order to planarize the substrate 2. On both surfaces of the substrate 2, thin-film insulating layers 7, 7 are formed so as to cover the first wiring patterns 3, 3. The thin-film insulating layers 7 and 7 are formed using an insulating material such as an alkali-developing photoresist material and an insulating ink for light adaptation. The thickness of the thin-film insulating layer 7 ′ 7 is 1 / im˜30 // m. This is because when the thickness of the thin-film insulating layers 7, 7 is less than 1 V m, the adhesiveness with the first wiring patterns 3, 3 will be deteriorated. At -8-, this paper size applies the Chinese National Standard (CMS) A4 specification (210X297 (Issue) 518924 A7 ______B7 V. Description of the invention (6) When the surface modification of the thin film insulation layers 7, 7 is implemented, the thin film insulation layers 7, 7 may be peeled off; the thickness of the thin film insulation layers 7, 7 is greater than 3 〇 // m, the adhesion of the metal conductive layers 13, 13 to the first wiring patterns 3, 3 in the connection holes 8 '8 formed in the next process, that is, the adhesion of the plating will be poor, and even if it is formed, Polishing the surfaces of the metal conductive layers 13 and 13 of the second wiring patterns 12 and 12 does not smooth them. The thickness of the thin-film insulating layers 7 and 7 is more preferably 5 / zm to 20 / zm. Connection holes 8, 8 are formed in the first wiring patterns 3, 3 of the thin film insulation layers 7, 7. In the connection holes 8, 8, metal bumps 9, 9 are formed in a protruding manner from the thin film insulation layers 7, 7. In order to make contact with the first wiring patterns 3 and 3, the first wiring patterns 3 and 3 on the inner layer and the second wiring patterns of the outer layer are electrically connected. The metal bumps 9 and 9 are formed of ferrous chloride and cuprous chloride, for example. In addition, interlayer insulating layers 11, 11 are formed on the thin film insulating layers 7, 7 so as to surround the metal bumps 9, 9 so as to keep the first wiring patterns 3, 3 on the inner layer and the second wiring patterns on the outer layer insulated. Interlayer insulation layer 丨 i, 丨 丨 are made of thermosetting resins such as epoxy resins, phenolic resins, urea resins, or polyethers, polyethers, polyethers, polyphenylene ethers, polyimines, and polyfluorenes. Formed from a thermoplastic resin such as imine. The second wiring patterns 12, 12 constituting the outer layer are formed on the interlayer insulating layers 11, u. The second wiring patterns 12, 12 are connected to the end faces of the metal bumps 9, 9 facing the outside by the interlayer insulating layer 11'n, and communicate with the inner layer. The first wiring patterns 3 and J remain electrically connected. When the following describes the manufacturing method of the multilayer printed circuit board 丨 with reference to FIG. 2, as shown in FIG. 2 (A), first, a first wiring pattern is formed on the substrate 9-518924 A7 Invention Description J 3 Specifically, 5 is a copper foil laminated board (for example, TLC-W_551 manufactured by Toshiba Chemical Co., Ltd. with a substrate thickness of 0 and a copper foil thickness of 1.8 // m) on both sides of the substrate 2 to form a connection hole 4 to make the structure The copper foils of the first wiring patterns 3 and 3 on each side are electrically connected. This connection hole 4 is formed by, for example, an NC (numerical control) drilling machine (for example, a drill is manufactured by Hitachi Manufacturing Co., Ltd.) and a hole having a diameter of 0.25 mm is formed. A copper plating layer (thickness 18 / zm) is formed on the copper foil provided on both sides of the substrate 2 including the inner surface of the connection hole 4 by using electroless copper plating or the like, so that a conductive layer is also formed on the inner surface of the connection hole 4 and provided on the substrate. 2 The copper foils on both sides remain electrically connected. Thereafter, in order to flatten the surface of the substrate 2, a conductive or insulating paste 6 is permanently filled in the connection hole 4 provided with a shaft layer on the inner surface. Thereafter, mechanical and chemical treatments (such as sulfuric acid cleaning and brush grinding) are provided on the copper foil with a plating layer, and the entire surface of the conductive layer on the plate 2 is applied. Next, a photosensitive etching resist (for example, Mitaka AQ5044, manufactured by Asahi Kasei) is applied to the conductive layer on the second surface, and exposed using an exposure device (HMW-55 1D exposure machine, manufactured by Ohm Corporation) provided with a pattern film. Then, the exposed conductive layer was developed by using 1% anhydrous sodium carbonate, and then rubbed with ferric chloride or copper chloride aqueous solution. After that, the dry film of the conductive layer was peeled with 3% caustic soda to form the first wiring patterns 3, 3. Next, as shown in FIG. 2 (B), thin-film insulating layers 7, 7 are formed on the substrate 2 on which the first wiring patterns 3, 3 have been patterned. The thin-film insulating layers 7 and 7 are coated with an insulating material such as an alkali-developing photoresist material, a light-resistant insulating ink (for example, psR-4OO, manufactured by Sun Ink Co., Ltd.) using a screen printing method to complete the first wiring. Patterns 3 and 3 are patterned on the substrate 2. c Implementation of% minutes -10- --- This paper wave scale is applicable to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) 5. Description of the invention (Drying into a semi-hardened state. Next, the thin film insulation layer 7 7 and 7 form connection holes 8 and 8 with the first wiring patterns 3 and 3 facing outward 4. The connection holes 8 and 8 are formed by engraving thin-film insulating layers 7 and 7 with a photo money engraving method. Thereafter, connection holes will be formed. The thin film insulation layers 7 and 7 of 8 and 8 are heated at 16 ° C for 60 minutes to completely harden. At this time, as described above, the thickness of the thin film insulation layers 7 and 7 formed is 1 // m ~ 3 〇 / ^ ^ The good condition is between “melon and ⑼㈣”. This is because when the thickness of the thin-film insulating layers 7, 7 is less than 1 // 〇1, the adhesion with the first wiring patterns 3, 3 will change. Poor. When the surface modification of the thin film insulating layers 7 and 7 is implemented, the thin film insulating layers 7 and 7 may be peeled off. When the thickness of the thin film insulating layers 7 and 7 is greater than 30 # m, the metal conductive layer 13 And 13 pairs of the first wiring patterns 3, 3 in the connection holes 8 ′ 8 formed in the next process, the tightness of the electric clock will be worse, and even if the first The wiring patterns 12, 12 are not smoothed by polishing the surfaces of the metal conductive layers 13, 13. Although the connection holes 8, 8 are formed in the thin-film insulating layer 7/7 by using a photo-etching method, this is used as an example. Note, but the connection holes 8 and 8 can also be formed by drilling or laser processing. That is, firstly, on the substrate 2 on which the first wiring pattern J ^ is formed, a thermosetting or thermoplastic insulating ink or The thin film forms the thin film insulating layers 7, 7. For example, a screen printing plate (T-3 00N, thickly installed in a screen printing device (New Long printing press LS-150)), and a screen printing method is used to apply a thermosetting ink (Asahi Chemical CR-15 manufactured by the research institute) is printed on the substrate 2 on which the first wiring patterns 3 and 3 are formed to form the thin-film insulating layers 7, 7. Then, the substrate 2 on which the thin-film insulating layers 7, 7 are formed in an unboxed state, Heat at 60 ° C for 60 minutes to harden the thin film insulation layers 7, 7 and then

At a specific position of the hardened thin film insulating layers 7, 7, a laser hole device (LC0-1A21 manufactured by Hitachi Bikanex Corporation) is used to form the connection holes 8 so that the first wiring patterns 3 and 3 face the outside. ,8. Secondly, surface modification is performed on the surface of the thin-film insulating layers 7 and 7 to improve the adhesion with the metal conductive layer formed by the human process. This surface modification is performed in the following manner: The substrate 2 forming the thin-film insulating layers 7 and 7 is immersed in N_methylpyrrolidone, sodium permanganate, and thallium sulfate by using a Desmac treatment device and the like. After the process, it is washed and dried to complete the modification process. In addition, this surface modification can also use oxidizing agents such as potassium permanganate, dichromate, sodium dichromate, concentrated sulfuric acid, such as sodium hydroxide, potassium hydroxide and other test agents, N, N-dioxine, etc. Organic solvents such as osmamine and dimethylphosphine, plasma treatment, and ultraviolet irradiation treatment are completed. Next, as shown in FIG. 2 (C), metal conductive layers 13, 13 for forming metal bumps 9, 9 are formed on the thin-film insulating layers 7, 7 after surface modification. The metal conductive layers 13 and 13 are formed to a thickness of 60 to 111 by using electroless bell copper or the like in order to ensure the strength of the connection between the first wiring patterns 3 and 3 formed with the copper foil. In addition to copper, conductive materials such as nickel, copper, and silver can also be used. Next, as shown in FIG. 2 (D), the metal conductive layers 13, 13 are formed by removing a specific region to form a thin-film insulating layer. 7, 7 protruding metal bumps 9, 9. The formation of the metal bumps 9, 9 is achieved by the following methods: that is, using chemical polishing such as sulfuric acid, hydrochloric acid, organic acid, or physical polishing such as scrubbing, scraping, brushing, etc. Metal conductive layers 13,13, after finishing the surface of metal bumps 9,9, a resist layer is formed on metal conductive layers 13,13, and the selection is made by etching -12- This paper applies the Chinese National Standard (CNS) Λ4 specification ( 210X 297 mm) A7 B7

518924 V. Description of the invention (formed by removing metallic conductive layers 13, 13 at this time. At this time, the thin-film insulating layers 7, 7 have a function as an etching stopper when metal bumps 9, 9 are formed. Specifically, it is used A dry film with a thickness of 30 / zm (NIT_230 manufactured by Nippon Morton Co., Ltd.) 'as an etching resist, and after lapping, this dry film was bonded to the metal conductive layers 13 and 13 by a laminator, and then exposed by exposure Device (NT-800 manufactured by Ono Detector Co., Ltd.), and then the metal conductive layers 13, 13 are used to peel off the dry film to form metal bumps 9, 9. Also, the anti-money engraving agent can also be used. , Printed on the metal conductive layers 13 and 13 by screen printing, or formed by using an electrophoretic deposition method (ED method) of an electrolytic deposition etching resist. Also, the metal conductive layer 13 should be taken into consideration during etching. The materials and materials used for etching resists are the most appropriate method. For example, when ferrous chloride or cuprous chloride is used for metal conductive layers 13, 13, the etching resist is removed by using a strong alkaline solvent. And other chemicals or scrubbing The physical polishing method is used to remove it. Next, as shown in FIG. 2 (E), interlayer insulating layers 11, 11 are formed on the thin film insulating layers 7, 7 so that the first wiring patterns 3, 3 on the inner layer and the second wiring patterns 3 on the outer layer are formed. The wiring patterns 12, 12 are electrically insulated. The interlayer insulation layer is made of epoxy resin, melamine resin, brewed resin, uric acid: resin or other thermosetting resin or polyether, polyetherketone, or polyether. It is formed by thermoplastic resins such as hard, polyphenylene ether, polyimide, and polyimide, and it has a height equal to or slightly higher than the metal bumps 9, 9, and the interlayer insulation layers η, 11 are It is formed by using a lamination device (product of Mingji Co., Ltd.) to perform vacuum lamination on the dry film. In addition, the interlayer insulation layers 11, 11 can also be coated with the above materials by curtain flow coating, or -13- this paper size Applicable to China National Standard (CNS) A4 (210 X 297 mm)

Binding

Line A7 -------- __B7 Third, the description of the invention (~-Formed by screen printing method to print the above materials and other methods. After that, the surface of the interlayer insulation layer U'u was polished to implement metal bumps 9, 9 The head is exposed and smoothed. At this time, a physical grinding method such as belt sanding and scraping grinding with a large grinding force is used. Here, the above-mentioned film uses this grinding to make the metal bumps 9, 9 The end surface and the surfaces of the interlayer insulation layers U and η continuous to this end surface are kept smooth, and when the second wiring patterns 12, 12 are formed, it is possible to prevent the formation of recesses on the connection holes 8, 8 and their peripheral portions as in the past. Roughening the surface of the interlayer insulating layer 丨 丨 u that has been smoothed to improve the adhesion of the second wiring patterns 12, 12 formed here. Specifically, this roughening treatment uses horizontal Desma Processing device, etc. 'The interlayer insulation layers 11 and 11 are impregnated with N-methyl-2--2- alkane, the same and too fierce § Wen Na H towel, and then the interlayer insulation layers u and ^ are washed with water and dried. Dry, and this roughening treatment can also use potassium permanganate, dichromic acid Oxidants such as sodium and concentrated sulfuric acid, alkaline agents such as sodium hydroxide and potassium hydroxide, N-methyl-2-pyrrolidone, N, dimethylformamidine, diamidine, dioxin Organic solvents such as rolidone are applied. Thereafter, as shown in FIG. 1 described above, the second wiring patterns 12 and 12 are formed on the interlayer insulating layers 11 and 11. Specifically, they are formed on the interlayer insulating layers 11 and 11. The thickness of at least the second wiring pattern 12, 12 formed in the fine pattern will not be disconnected, for example, a copper plating layer of 30 // m or less. Here, an electroless copper plating is used to form 18 / zm copper plating layer. This is because the thickness is more than 30 / zm, which is disadvantageous for the formation of fine patterns. After that, it is recommended to use the standard _ house standard -14-518924

V. Description of the invention (A7 B7

At a temperature of 120 ° C to 200 ° C, a heat treatment is performed on the substrate 2 provided with a copper plating layer for 10 minutes to 120 minutes to improve the bifurcation between the copper plating layer and the interlayer insulation layer. This is because when the time is less than 120 or 10 minutes, the adhesion cannot be improved, and it is more than 200. (: At 120 minutes, the substrate 2 itself will be oxidized, which reduces the reliability of the substrate 2.

Next, the heat-treated copper-plated layer was immersed in N-methyl-2-pyrrolidone, sodium permanganate, and thallium sulfate using a horizontal Desmarck treatment device, etc. Wash with water. Thereafter, the bell copper layer is engraved by the last name after exposure and development to form the second wiring patterns 2 and 12. On the printed circuit board after the above treatment, a solder resist layer (p ^ 4000 series made by Sun Ink Co., Ltd.) is formed on the surface on which the second wiring patterns 12, 12 are formed, and then the second wiring patterns 12, 12 are pre-planned. The Ni / Au (nickel / gold) layer is formed by the conduction process.

The multilayer printed circuit board 1 above the line is formed with the first wiring pattern 33, and then formed with thin film insulation layers 7, 7, and after the connection holes 8, 8 are formed in the thin film insulation layers 7, 7, a metal conductive layer is formed. 13, and the thin film insulating layers 7, 7 are used as the etch-resistant barrier layer to etch the metal conductive layers 13, 13 to form metal bumps 9, 9; therefore, metal bumps directly connected to the first wiring patterns 3, 3 can be formed. Blocks 9, 9 improve connection reliability. That is, the adhesion between the first wiring patterns 3, 3 and the metal bumps 9, 9 can be improved, so that the diameter of the connection holes 8, 8 can be reduced, and the diameters of the metal bumps 9, 9 can be reduced. In addition, since the plating process for forming the metal bumps 9, 9 and the plating process for forming the second wiring pattern 12'12 are performed separately, the film thickness of the second wiring patterns 12, 12 can be reduced to achieve Fineness of the second wiring pattern I], I] -15-

518924 A7 B7 V. Description of the Invention (Linearization) At the same time, the perimeters of the metal bumps 9, 9 also become flat. Because the metal conductive layers 13, 13 used to form the metal bumps 9, 9 and used to form the second wiring The copper plating layers of the patterns 12 and 12 are subjected to the same kind of electroplating treatment, so the same electroplating device can be used, and at the same time, the same etching solution can be used during etching, so that the manufacturing process can be simplified. When the bumps 9 and 9 are used for the last name engraving,

The thin-film insulating layer 7'7 serves as an etching stopper. Therefore, the amount of etching of the metal conductive layer and 13 can be reduced, and the accuracy of the etching can be improved. As a result, a fine pattern can be formed. Also, "measure the junction resistance between the first wiring patterns 3, 3 and the second wiring patterns 12, 12 of the multilayer printed circuit board 1 formed in the above manner, and find that the value is 0.4Q, which shows that good results can be obtained. Its conduction characteristics. In addition, this multilayer printed circuit board was subjected to a “hot and cold” treatment repeatedly, and a thermal shock test was performed 20 times in accordance with the JIS (Japanese Industrial Standard) C 50 to investigate the second wiring pattern 12, 12 As a result of characteristics such as peeling state, it was confirmed that the conductor resistance value between the first wiring patterns 3 and 3 and the second wiring patterns 12 and 12 was 0.6 Ω, and the effect was quite good. The multilayer printed circuit board is then compared with the fine pattern of the multilayer printed circuit board 1 formed by applying the present invention. In order to manufacture a conventional multilayer printed circuit board 21, as shown in FIG. 3 (A), first, The first wiring patterns 23 and 23 are formed on the substrate 22. The first wiring patterns 23 and 23 are formed in the same manner as the first wiring patterns 3 and 3 formed on the substrate 2. At this time, the substrate 22 is formed with The inner surface is provided with plated connection holes 32 so as to be provided on the substrate ㈣ -16- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 518924

Electrical connection is maintained between the first-wiring patterns 23 and 23, and a conductive or insulating paste 33 is filled in this connection hole 32. Next, on the substrate 22 on which the first wiring patterns 23 and 23 are formed, as shown in FIG. 3 (B), a copper foil with resin (resin-coated copper foil RCC ·· resin coated Copper), and Sumitomo Beklett ApL-4. 〇i). That is, on the substrate 22 provided with the first wiring patterns 23, 23, interlayer insulating layers 24, 24 are formed, and copper cymbals 25, 25 are laminated on the interlayer insulating layers 24, 24. " Person as shown in FIG. 3 (c), 'the copper foils 25 and 25 are removed by etching, and then: at a specific position on the interlayer insulation layers 24 and 24, the first wiring pattern 23, 23%,% facing external connection holes. Next, the interlayer insulation layers 24, 24 forming the connection holes 26, 26 are treated with Dessma to remove the resin residue on the surface. Next, as shown in FIG. 3 (D), on the interlayer insulating layers 24 and 24, copper-plated layers 27 and 27 having a thickness of 18 mm are formed using non-electrolytic mineral copper or the like. This mineral copper layer 27, 27 is a layer for forming the second wiring pattern of the outer layer. In addition to being formed on the surface of the interlayer insulating layers 24, 24, it is also formed on the inner surface of the connection holes 26, 26, and is connected to the first wiring. The patterns 23 and 23 remain electrically connected. Thereafter, as shown in FIG. 3 (E), the connection holes%, 26 of the copper plating layers 27, 27 are provided on the inner surface, and the hole filling inks 28, 28 (FP-R12, manufactured by Asahi Chemical Research Institute) are filled, and Bake at a temperature of 12 ° C for 100 minutes, and then heat for 30 minutes at 180 ° C to harden it. Next, as shown in FIG. 3 (F), the copper plating layers 27 and 27 are electroless. Copper plating is performed to form copper plating layers 29 and 29, and then the copper plating layers 27 and 29 are exposed, developed, and etched to form second wiring patterns 30 and 30. This second wiring -17- this paper is suitable for China National Winter Standard (CNS) A4 specification (210 X 297) 518924 A7 B7 V. Description of the invention (15) The patterns 30 and 30 are formed by laminating copper layers 27 and 29, and the thickness is 36/2 m ° In the multilayer printed circuit board 1 to which the present invention is applied, the pattern width of the second wiring patterns 12 and the space width between the patterns can be formed to 50 // m / 5. In contrast, the multilayer shown in FIG. 3 Type printed circuit board 21 can form a pattern width / space between patterns of 70 // m / 70 # m, but if the thickness is reduced to 50 // m / 50 " m, the second wiring pattern 30, 30 Will break This is because the second wiring pattern 30 and 30 are composed of two copper plating layers 27 and 29, and the thickness of 36 / zm is greater than the thickness of 18 // m of the multilayer wiring circuit board 1 of the second wiring pattern. 12, 12 is thicker. In this way, compared with the printed circuit board 21 of the comparative example, the multilayer printed circuit board 1 to which the present invention is applied can form a wiring pattern having a smaller pattern width and a thinner and thinner wiring pattern. A printed circuit board provided with two conductive layers is described as an example, but the present invention is not limited to the number of the conductive layers. [Effects of the Invention] The present invention forms a thin film insulation after forming a wiring pattern on a substrate. Layer, after forming the connection hole in the thin-film insulating layer, a metal conductive layer is formed, and the metal conductive layer is etched with the thin-film insulating layer as an etch stop layer to form a metal bump, so it can form a direct connection with the wiring pattern on the substrate Metal bumps improve the reliability of the connection. That is, because the closeness between the wiring pattern on the substrate and the metal bumps can be improved, the diameter of the connection hole can be reduced, that is, the small diameter of the metal bumps can be achieved. The first plating process for forming metal bumps and the second plating process for forming wiring patterns on interlayer insulation layers are performed separately, so it can be reduced by -18- This paper size applies to Chinese National Standards (CNS) A4 specifications (21 ^? 297 issued)-;-518924 A7 B7 V. Description of the invention (16 The thickness of the wiring pattern of the outer layer is less, and the thinning of the wiring pattern on the interlayer insulation layer is improved, and the metal bumps are made at the same time The periphery can also be kept flat, so electronic components can be mounted in a stable state. Since the metal conductive layer forming the metal bumps and the plating layer forming the wiring pattern on the interlayer insulating layer are subjected to the same plating treatment, the same plating device can be used, and at the same time, the same etching solution can also be used during etching. Simplicity of the device is required while improving the adhesion. In addition, when the last engraving for forming metal bumps is carried out, a thin film insulating layer is formed as an etching stopper layer. Therefore, the amount of etching of the metal conductive layer can be reduced ', and the accuracy of etching can be improved. As a result, a fine pattern can be formed. [Brief description of the drawings] FIG. 1 is a cross-sectional view of a multilayer printed circuit board to which the present invention is applied. 2 (A) to (E) are explanatory diagrams of the manufacturing process of the printed circuit board shown in FIG. Figs. 3 (A) to (F) are explanatory diagrams of a manufacturing process of a multilayer printed circuit board as a comparative example. Figs. 4 (A) to (G) are explanatory diagrams of a manufacturing process of a conventional printed circuit board. [Explanation of component symbols] 1 multilayer printed circuit board, 2 substrates, 3 first wiring patterns, 4 connection holes, 5 plating layers, 6 pastes, 7 thin film insulation layers, 8 connection holes, 9 metal bumps, 11 interlayer insulation Layer, 12 second wiring pattern '13 metal conductive layer-19- This paper size applies to Chinese national standard ((:] ^ 3) a4 size (21〇x 297 mm)

Claims (1)

518924 8 8 8 8 AB c D 6. Application scope 1. A multi-layer printed circuit board, which is characterized by comprising: a substrate, which forms a wiring pattern; and a thin film insulation layer, which is formed to cover the wiring pattern. On the substrate; interlayer insulation layer provided on the thin film insulation layer; metal bumps surrounded by the thin film insulation layer and the interlayer insulation layer and protruding from the thin film insulation layer and provided on the The above wiring pattern; and the wiring pattern provided on the interlayer insulating layer and connected to the metal bump. 2. The multilayer printed circuit board as described in the first item of the patent application, wherein the thickness of the above-mentioned thin film insulating layer is l # m ~ 30 // m. 3. A method for manufacturing a multilayer printed circuit board, which is characterized by including a wiring pattern forming step for forming a wiring pattern on a substrate; a thin-film insulating layer forming step for covering the wiring pattern; A thin film insulating layer is formed on a substrate provided with the above-mentioned wiring pattern; a connection hole forming step includes forming the connection hole in the thin film insulating layer so that the wiring pattern faces the outside; a metal conductive layer forming step, The first electroplating process is used to form a metal conductive layer on the thin film insulating layer on which the above-mentioned connection hole is formed; the metal bump forming step is to form a protrusion from the thin film insulating layer by selectively removing the metal conductive layer. Those with metal bumps; -20- This paper size applies to China National Standard (CNS) A4 (210 X 297 public field) 4. The step of forming an interlayer insulating layer is one in which the interlayer insulating layer is formed on the thin film insulating layer in a manner of surrounding the above-mentioned metal bumps; and an additional 4. pattern forming step is performed by using the same process as the first electric ore treatment. The second electric clock of the same kind is processed by forming another wiring pattern on the interlayer insulating layer. In the method for manufacturing a multilayer printed circuit board according to Patent Claim 3, in which the above-mentioned thin film insulating layer is used as a photomask when the above-mentioned metal conductive layer is removed. For example, a method for manufacturing a multilayer printed circuit board according to claim 3, wherein the above-mentioned connection holes are formed in the above-mentioned thin-film insulating layer by any one of photoetching, drilling, or laser light. For example, the method for manufacturing a multilayer printed circuit board according to item 3 of the patent application 'wherein the above-mentioned metal conductive layer is formed before the above-mentioned thin-film insulating layer' includes a surface modification step for performing the surface of the above-mentioned thin-film insulating layer Reformer. For example, the method for manufacturing a multilayer printed circuit board according to item 6 of the patent application, wherein the surface modification of the thin-film insulating layer is at least one of oxidant treatment, alkaline treatment, organic solvent treatment, plasma treatment, and ultraviolet irradiation treatment. What has been done above. -21-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)