511256 五、創作說-明（l) · ·- 本發明係有關於一種可縮小元件組裝間距、提高解析 度之體積小、製程快之「發光二極體封裝及其製造方 法」，是提供光電業者另一項高密度、高解析度畫面發光 二極體者。 按，目前光電元件已普遍的應用於各種螢幕顯示器、 指標器或其它為顯示目的之作為上，其中與吾人生活習習 相關的如電腦主機板、發光二極體顯示器〈LED display〉、手機顯示板、電源顯示器等等即是；就業界 製造光電元件而言，有兩種方式被普遍的使用，皆必需仰 賴晶片與PCB本體之組各形成單一光學元件，再以SMT黏著 於系統母板〈mother board〉電路板上；其製造單元需備 有二極體晶片1及PCB本體2，於二極體晶片1上預先設定晶 粒1 1尺寸，而PCB本體2上亦設有晶粒單元基板21，且已預 設有金屬導線22〈如第二圖〉，其光電元件之製程為： 第一步驟一測試：測 極體.晶片1上母一早晶粒 1.1，若有瑕疵就以紅色油墨或其它方式作標記.1 2〈第一圖 a > ° 第二步驟一單晶粒之固位：次將二極體晶片1予以切 割成單一晶粒11，並於PCB本體2上每一晶粒單元基板2 1點 上導電銀膠13，如第一圖b、第二圖a所示，使晶粒11藉導 電銀膠1 3黏著於單元基板2 1上。 第三步驟一固晶··當完成整個PCB本體2之晶粒11置放 後，.放入烤箱烘烤〈一般為130°C〜1 50°C >以將導電銀膠 13與晶粒11完全固著。511256 V. Creation Statement-Ming (l) · ·-The present invention relates to a "light emitting diode package and its manufacturing method" which can reduce the assembly pitch of components, improve the resolution, and has a small volume and a fast manufacturing process. Another high-density, high-resolution light-emitting diode of the industry. At present, optoelectronic components have been widely used in various screen displays, indicators, or other display purposes. Among them, related to our daily life, such as computer motherboards, light-emitting diode displays (LED display), mobile phone display boards. For example, as for the manufacture of optoelectronic components in the industry, there are two methods that are commonly used, both of which rely on the combination of the chip and the PCB body to form a single optical component, and then use SMT to adhere to the system motherboard. board> circuit board; its manufacturing unit needs to be equipped with diode wafer 1 and PCB body 2. The size of die 11 is set on diode wafer 1 in advance, and the die body substrate 21 is also provided on PCB body 2. , And the metal wire 22 (as shown in the second picture) has been preset. The manufacturing process of the photoelectric element is as follows: The first step is a test: the pole body. The early grain of the mother chip on the wafer 1 is 1.1. Mark in other ways. 1 2 <First picture a > ° Second step 1 Retention of single crystal grains: Cut the diode wafer 1 into single crystal grains 11 at a time, and place each crystal on the PCB body 2 Granular unit substrate 2 1 Point the conductive silver paste 13 as shown in the first figure b and the second figure a, so that the die 11 is adhered to the unit substrate 21 by the conductive silver paste 13. The third step is a solid crystal ... After the placement of the die 11 of the entire PCB body 2 is completed, the oven is baked (typically 130 ° C ~ 150 ° C) > to place the conductive silver glue 13 and the die 11 fully fixed.
511256 五、創作說明（2) 第四步驟一打線：如第二圖b，使用銲線〈Au〉1 4自 電極1 5引線到PCB本體2上内接金屬導線22。 第五步驟一封膠：如第二圖c，使用透明膠體16藉模 壓〈molding〉製程將PCB本體2上的每個晶粒11予以包 ——窻:—〇 ---------------—-----------------... _ . _ _ _ — 第六步驟一切割：將位於PCB本體2上的各個封裝完成 的晶粒1 1予以切割。 _____________________第七步驟一第二次測試及包裝：、避免在以上之製程可 能發生的瑕疵，需再進行測試，並將好品置入整理盤 < tray )供薇商使用。 當使用時，係以SMT黏著於系統之母板3〈㈣士匕” board〉預没之錫點31上’如第三圖所示，依此種製成之 一極體S，包括有单元基板22、晶粒11、透明膠體16，故 不僅體積大’且母板3單位面積置放之發光二極體$受到一 定之限制，故解析度無法提升，製程也麻煩。 如第四、五圖所示者，為另一種製程，其亦備有晶片 1及PCB本體2，首先於各個晶粒1 1上設以銲接金屬凸塊17 〈solder bump〉，作為覆晶〈f 1 ip — Chip〉與 pCB 本體 2 接合之介物，次將晶片1進行電性測試，將不良品用紅色 油墨標記12，或是將不良品位置記錄在測試台之^記憶體 内，以便後續動作自動排除對不良品之加工，再將^ = i 切割成早一晶粒11 ’使用自動固晶機〈die bonder〉將良 品之晶粒11反轉覆置固定於PCB本體2上，如第五圖a所 、 示，續而使用模壓〈molding·〉熱固性透明膠〈ep〇xy〉封511256 V. Creation instructions (2) The fourth step is to make a wire: as shown in the second figure b, use the bonding wire <Au> 14 to lead from the electrode 15 to the PCB body 2 and connect the metal wire 22 inside. The fifth step is a glue: as shown in the second figure c, each die 11 on the PCB body 2 is wrapped by using a transparent gel 16 by a molding (molding) process—— 窻: -〇 -------- -------------------------... _. _ _ _ — Step 6: Cutting: Complete each package on the PCB body 2 The grains 1 1 are cut. _____________________ Step 7-Second test and packaging: To avoid possible defects in the above process, you need to test again and put the good product in the finishing tray < tray) for Wei merchants to use. When in use, it is adhered to the pre-tinned solder point 31 of the system's mother board 3 <㈣ 士 匕 板> with SMT. As shown in the third figure, a polar body S is made in this way, including a unit. The substrate 22, the die 11, and the transparent colloid 16 are not only bulky, but also the light-emitting diodes placed on a unit area of the mother board 3 are subject to certain restrictions, so the resolution cannot be improved, and the manufacturing process is troublesome. The figure shows another process. It also has a chip 1 and a PCB body 2. First, a solder bump 17 <solder bump> is set on each die 1 1 as a flip chip <f 1 ip — Chip. 〉 Intermediate connected with pCB body 2, conduct electrical test on chip 1 and mark the defective product with red ink 12 or record the location of the defective product in the memory of the test bench so that subsequent actions can be automatically excluded. The good product is processed, and then ^ = i is cut into an early die 11 '. Using an automatic die bonding machine (die bonder), the good product die 11 is inverted and fixed on the PCB body 2, as shown in Figure 5a, As shown in the figure. Continued to use mold <molding ·> thermosetting transparent glue <ep〇xy> seal
511256 五、創作說明（3) 裝，如第五圖b，第六步製程就是進行切割成單 發光 極體S ’如第五圖c 以此製成之發光二極體S體積也頗大，如第五圖c所 示’其寬度W約在2πι瓜，高度z約在1.2mm，而發光二極體S ^ 5& ^ X ^ ^ 2 m m £4 JL a ^此可知，於=定―面積母板3上 所佈設之光電元件s數量無法提高，其解析度也就無法有 效的握高，由上述製程不難得知，其高度主要包括了晶片 i及1^ C β本體2之厚度.所致。_ ., · ----------------…- ——____________________________________________— ________________" 緣此，本發明「發光二極體封裝及其製造方法」之主 要目的，係使發光二極體無有較厚之晶片及pCB本體單 元，而以微薄之單位光電元件跨設於兩金屬 玻璃基板使用，達到體積小、增加母板單位面積 之密度及解析度高之目的者。 、尤电疋件 本發明「發光二極體封裝及其製造方法」之第二 5:f以ί晶晶片與透明之玻璃基板上相對設.有列；之數 酬’使玻璃基板上呈現出之單位光電；； J：再上以一層絕緣體包覆各個單位光電元件 Π :。 ！刻使外引金屬線部裸露後，進行測試後切 吾J肉驭旱一贫光二極體單元者。 ·刀 本發明「發光二極體封裝及其製造方法」之 的，於進行蝕刻前，先將晶片予以研磨至〇. 〇 一 度，除有助快速蝕刻外，亦可降低整體 之厚 本發明所製成之發光二極體S，就如之第二示，其511256 V. Creation instructions (3) installation, as shown in the fifth figure b, the sixth step process is to cut into a single light emitting body S ', such as the fifth picture c made of light emitting diode S is also quite large, As shown in the fifth figure c, its width W is about 2 μm, its height z is about 1.2 mm, and the light-emitting diode S ^ 5 & ^ X ^ ^ 2 mm £ 4 JL a ^ It can be known that The number of photovoltaic elements s arranged on the area mother board 3 cannot be increased, and its resolution cannot be effectively held high. It is not difficult to know from the above process that its height mainly includes the thickness of the wafer i and 1 ^ C β body 2. Caused by. _., · ----------------…-——____________________________________________ ________________ " For this reason, the main purpose of the present invention "light emitting diode package and its manufacturing method" is to use The light-emitting diode does not have a thicker wafer and a pCB body unit, and a thin unit photoelectric element is used across two metal glass substrates to achieve a small volume, increase the density and high resolution of the unit area of the motherboard. ， Electrical components The second 5: f of the present invention "light-emitting diode package and its manufacturing method" is arranged opposite to a crystal wafer and a transparent glass substrate. It is listed; the number of rewards makes the glass substrate appear The unit photoelectric; J: and then cover each unit photovoltaic element with a layer of insulator Π :. !! After engraving the exposed metal wire part, cut the test and cut off the light-diode unit. · For the "light emitting diode package and its manufacturing method" of the present invention, the wafer is polished to a degree of 0.1 degree before etching, which can help to reduce the overall thickness of the present invention. The light-emitting diode S is made as shown in the second figure.
511256 五、創作說明（4) 係包含有一玻璃基板6、覆有單位光電元件5之晶粒41〈厚 約0. 0 5〜0. linm，面積約0· 3〜0· 3 7 5mra見寬〉，在本實施例 中，於玻璃基板6—端面上設有一對金屬銲片7，金屬銲片 7間相隔一距離，且各形成有内引金屬銲片部71及外引金 屬銲片—部 接金屬凸塊1 7，其則以晶粒41上之單位光電元件5使成連 結，而在其上佈設有絕緣體9〈約0· 001〜0. 0 02mm〉，而使 兩金屬銲片7之外引金屬銲片部7 2皆露出於絕緣體9外，如 第九圖所示。 以S Μ T黏著於母板3時，如第十圖示，係使玻璃基板6 向上而以外引金屬銲片部7 2與母板3之錫點3 1銲合，因此 時晶粒4 1係向下，而外引金屬銲片部7 2又位於左右兩側， 故可晶粒4i位於和錫點3 1之高度内，也就是與錫點31同 南’而藉此得降低發光二極體S設位於母板3之南度5且本 發明之發光二接體S亚無使羯P C B本體2 ’以及晶片係經研 磨至極薄片狀，約0 . 0 D〜0. 1 m πι，使羯的玻璃基板6可設定 在0 , 3 m m左右或者更薄，因此以S Μ T黏著於母板3上時，不 僅可縮短兩者之間距Ρ〈約在0 . 5 m m左右〉，除可大幅度增 加佈設密度以提高顯像之解析度外，也可縮小整體高度。 其中，該位於單位光電元件5與金屬銲片7内引金屬銲片7 1 之銲接金屬凸瑰1 7可直接先預設於任尸方者。 本發明所以能獲致上述之光學元件，其基本使用之單 元為具相同尺寸之覆晶晶片〈fi i p — c h i p〉4及玻璃基板 6，於玻璃基板6設有呈陣列之金屬銲.片7，如第六圖所511256 Fifth, the creation description (4) is a glass substrate 6, which is covered with crystal grains 41 of the unit photoelectric element 5 <thickness of about 0. 5 to 0. linm, an area of about 0. 3 to 0. 3 7 5mra see width 〉 In this embodiment, a pair of metal pads 7 are provided on the end face of the glass substrate 6-the metal pads 7 are separated by a distance, and the inner lead metal pad portion 71 and the outer lead metal pad are each formed— Partially connected to the metal bump 17, which is connected by a unit of the photovoltaic element 5 on the die 41, and an insulator 9 (about 0 · 001 ~ 0. 0 02mm) is provided thereon, so that the two metal pads The outer metal lead portions 7 2 are exposed outside the insulator 9 as shown in the ninth figure. When the SMT is adhered to the mother board 3, as shown in the tenth figure, the glass substrate 6 is drawn upward and the metal pads 7 2 are soldered to the solder point 3 1 of the mother board 3, so that the grain 4 1 It is downward, and the lead-out metal pad portion 72 is located on the left and right sides, so the grain 4i can be located within the height of the solder point 31, that is, the same south as the solder point 31, thereby reducing the light emission. The polar body S is located at the south 5 of the mother board 3 and the light-emitting diode S of the present invention is a PCB body 2 ′ and the wafer is ground to a thin sheet shape, about 0 D ~ 0. 1 m πι, The glass substrate 6 can be set to about 0, 3 mm or thinner, so when SMT is adhered to the mother board 3, not only the distance P between the two can be shortened (about 0.5 mm), except that It can greatly increase the layout density to improve the resolution of the image, and it can also reduce the overall height. Wherein, the welding metal bump 17 of the lead metal pad 7 1 located in the unit photoelectric element 5 and the metal pad 7 can be preset to the corpse directly. Therefore, the present invention can obtain the above-mentioned optical element. The basic unit used is a chip-on-chip <fi ip — chip> 4 and a glass substrate 6 with the same size. The glass substrate 6 is provided with metal welding in an array. Sheet 7, As shown in Figure 6
第7頁 511256 五、貪hi乍說明 （5) * ， 該ίέ璃基板6可以玄ι!的方式 r 將金屬亥j出彳目對/惹 於覆晶晶片 4 jl 各個金屬早[立光電 7C ί牛D才目對位置金屬薛片 7 ’該金屬録片7形成有内引金屬I單片部7 1及外引金屬I旱片 部7 2，其封裝過程如下： 哮 jK fflTi a L 人 · 进口 « u 4 ^ -r.^·. η Xr-^ 4k T a L 人 矛一少娜一一始勺、· 復品g一日/1斗兴攻靖签板◦彳曰多Γ始7 如第七圖示，使晶片4上之各個金屬單位光電元件5連接於 兩相對金屬銲片7之内引金屬銲片部7 1上，此可藉自動控 制達到準確之貼合位置。 第二步驟一研磨：係將晶片4予以研磨至0 · 0 5〜0 . i mm 之厚度，如第八圖所示，其目的除為節省下道蝕刻步驟之 時間外，也可減少製品之高度。 第三步驟一蝕刻：塗上光限液8 ·利用曝光顯影的方 法，如第九圖a，以選擇性蝕刻的方法，蝕刻液只钱刻晶 片4至底層或至金屬部ί分’籍各混二極體之間定義出來’ 取後將光F且液8清洗掉。 第Ε3步驟—塗伟‘·於玻璃基板7之金屬部份上以真空 蒸度或塗佈上一層絕緣體9，再使同光阻液及顯影曝光 法，將金屬外引金屬銲片部72裸露tB ，如第九圖b所示。 第五步驟一測試：進行電性及光學特性_試及分類。 第六步驛一切割：蔣各個接合區予以切割成單一發光 二極體S。 其中，若不計其数刻時間及發光二極體高度者，可籍 蝕刻步驟省略。 據以上簡單之步驟即可完成體積小之光電元件，因晶Page 7 511256 V. Attention (5) *, the glass substrate 6 can be used in a way! The metal can be exposed to the target chip / affixed to the flip chip 4 jl each metal early [立 光 7C The metal metal sheet 7 is located at the right position. The metal recording sheet 7 is formed with an inner lead metal I single piece part 7 1 and an outer lead metal I dry sheet part 7 2, and the packaging process is as follows: jk fflTi a L · Import «u 4 ^ -r. ^ ·. Η Xr- ^ 4k T a L Human spear one Shauna one spoon at the beginning, · Reproduction g one day / 1 Dou Xing attacking picking board 7 As shown in the seventh figure, each of the metal unit photoelectric elements 5 on the wafer 4 is connected to the inner lead metal pad portion 71 of the two opposite metal pads 7, which can be accurately bonded by automatic control. The second step is polishing: the wafer 4 is polished to a thickness of 0 · 0 5 to 0. I mm, as shown in the eighth figure. The purpose is not only to save the time of the next etching step, but also to reduce the product. height. The third step is an etching: coating with a light-limiting liquid 8. Using the method of exposure and development, such as the ninth figure a, the selective etching method, the etching liquid only engraved the wafer 4 to the bottom layer or to the metal part. Defined between the mixed diodes' After removing the light F and the liquid 8 was washed away. Step E3—Tu Wei '· The metal part of the glass substrate 7 is vacuum-evaporated or coated with a layer of insulator 9, and then exposed to the photoresist solution and the development exposure method to expose the metal lead-out metal pad portion 72. tB, as shown in the ninth figure b. Fifth step one test: conduct electrical and optical characteristics_test and classification. The sixth step is the first cutting: each junction area of Chiang is cut into a single light-emitting diode S. Among them, if the time and the height of the light emitting diode are not counted, the etching step can be omitted. According to the above simple steps, a small-sized photovoltaic element can be completed.
511256 五、創作說明（6) ..- 片4已經研磨至一定薄度，及無PCB本體之結構，而所切割 出之玻璃基板6係符合爾述金屬録片了及旱位光電το件5所 需之面積5故可增加母板3上单位面積之發光二極體S數 目’而提高了螢幕之解析度，且晶粒4 1係下位於母板3之 锡點3 1間，可降低整體組合母板3之高度；本發明藉上述 製程亦可應用於一般二極體或電晶體等光電元件之封裝製 程者。511256 V. Creation instructions (6) ..- Sheet 4 has been ground to a certain thickness and has no PCB body structure, and the cut glass substrate 6 is in accordance with the metal recording film and dry-level photoelectric το pieces 5 The required area 5 can increase the number of light-emitting diodes S per unit area on the mother board 3, thereby improving the resolution of the screen, and the grain 4 1 is located between the tin spots 31 of the mother board 3, which can reduce the The height of the overall combined mother board 3; the present invention can also be applied to packaging processes of general optoelectronic components such as diodes or transistors by the above process.
第9頁 511256 圖式簡單說明 第一圖a ' b :係為傳統晶片及PCB本體之示意圖。 第二圖a :係為傳統晶粒膠固於PCB本體上之示意圖。 第二圖b :係為前圖打線步驟之示意圖。 第二圖c :係為前圖封膠步驟之示意圖。 第三圖：係為前圖以SMT黏著於母板之示意圖。 第四圖·係為另^ 傳統於晶片上點録接金屬凸塊之不思 圖。 第五圖a、b :為前圖與PC Β本體與封膠步騍之示意圖。第 五圖c :係前圖以，S Μ T黏著於母板之示意圖° 第六圖：係本發明之所使用之覆晶晶片與玻璃基板結構示 意圖。 第七圖：係前圖覆晶晶片與玻璃基板結合之步驟示意圖。 第八圖·係籍晶片研磨之步骤不意圖° 第九圖a :本發明進行银刻之步驛示意圖。 第九圖b : 本潑、明進行塗佈絕緣體.之示意圖。 第九圖c :本發明·之發光二極體製成品。 第 十 圖.本 明實施SMT黏著於母板之示 意圖。 圖 號 說明 1 ·· ••晶片 1卜·· …晶粒 12···· ••標記 13 * * · …導電 銀 膠14… …銲線 15···· ••電極 16 … …透明 膠 體17… ^ · ·爲* ；&肩 凸塊 9 ·· .•PCB 本 A3JX. 21 - …單元基板 9 9 * ‘·· ••金屬 導 線 3: ••母板 31 ··· …鍚點 /i ••鲁 »· * 丄 晶片 41 … …晶粒 5…·, f•單位光電元件6 ^破離 基 板Page 9 511256 Brief description of the diagram The first diagram a'b: is a schematic diagram of a conventional chip and a PCB body. The second figure a is a schematic diagram of the traditional die bonding on the PCB body. The second picture b: is a schematic diagram of the wire drawing steps of the previous picture. The second figure c is a schematic diagram of the sealing step of the previous figure. The third picture: It is the schematic diagram of the previous picture that SMT is adhered to the motherboard. The fourth picture is another traditional diagram of recording metal bumps on a wafer. The fifth picture a, b: is a schematic diagram of the front picture, the PC Β body and the sealing step. The fifth figure c is a schematic view of the previous figure, and the MT is adhered to the mother board. The sixth figure is a schematic view showing the structure of a flip chip and a glass substrate used in the present invention. Fig. 7 is a schematic diagram of the steps of combining the flip-chip wafer and the glass substrate in the previous picture. Figure 8: The steps for polishing wafers are not intended ° Figure 9a: Schematic diagram of the step of silver engraving according to the present invention. The ninth figure b: a schematic diagram of coating insulators on the screen. Ninth figure c: The finished product of the light emitting diode system of the present invention. Figure 10: This figure shows the intention of SMT adhesion to the motherboard. Description of Drawing Numbers 1 ···· Wafer 1 ····· Die 12 ······· Mark 13 13 17… ^ · · is *; & shoulder bump 9 ·· ··································· for PCB 31 / i •• Lu »· * 丄 Wafer 41…… Die 5… ·, f • Unit Photoelectric Element 6 ^ Break off the substrate
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