TW454318B - Chip scale package structure - Google Patents

Chip scale package structure Download PDF

Info

Publication number
TW454318B
TW454318B TW89122198A TW89122198A TW454318B TW 454318 B TW454318 B TW 454318B TW 89122198 A TW89122198 A TW 89122198A TW 89122198 A TW89122198 A TW 89122198A TW 454318 B TW454318 B TW 454318B
Authority
TW
Taiwan
Prior art keywords
film
plural
opening
package structure
scale package
Prior art date
Application number
TW89122198A
Inventor
Xin-Hui Lee
Yi-Chuan Ding
Kun-Ching Chen
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW89122198A priority Critical patent/TW454318B/en
Application granted granted Critical
Publication of TW454318B publication Critical patent/TW454318B/en

Links

Abstract

A chip scale package structure is disclosed, which comprises: a semiconductor chip with plural die pads on its front side; a film substrate pasted on the front side of the semiconductor chip by an adhesive layer, the adhesive layer has plural hole gaps corresponding to the die pads, the film substrate comprises a film and plural conductive leads on it, wherein the film has plural first openings corresponding to the hole gaps of the adhesive layer, and plural second openings, each conductive lead has the first terminal protruded from the first opening of the film, and the second terminal part exposed from the second opening of the film; every hole gap and the corresponding first opening are filled with conductive paste which wraps the first terminal part of the conductive lead, thereby the die pads of the chip and the conductive leads of the film substrate are electrically connected; and plural solder bumps which are disposed on the second terminal of the conductive leads through the second opening of the film. The present invention also provides a method to manufacture the chip scale package structure.
TW89122198A 2000-10-19 2000-10-19 Chip scale package structure TW454318B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW89122198A TW454318B (en) 2000-10-19 2000-10-19 Chip scale package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW89122198A TW454318B (en) 2000-10-19 2000-10-19 Chip scale package structure

Publications (1)

Publication Number Publication Date
TW454318B true TW454318B (en) 2001-09-11

Family

ID=21661645

Family Applications (1)

Application Number Title Priority Date Filing Date
TW89122198A TW454318B (en) 2000-10-19 2000-10-19 Chip scale package structure

Country Status (1)

Country Link
TW (1) TW454318B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7898058B2 (en) 2001-12-31 2011-03-01 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US8492870B2 (en) 2002-01-19 2013-07-23 Megica Corporation Semiconductor package with interconnect layers
US8535976B2 (en) 2001-12-31 2013-09-17 Megica Corporation Method for fabricating chip package with die and substrate
US9030029B2 (en) 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7898058B2 (en) 2001-12-31 2011-03-01 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US8471361B2 (en) 2001-12-31 2013-06-25 Megica Corporation Integrated chip package structure using organic substrate and method of manufacturing the same
US8535976B2 (en) 2001-12-31 2013-09-17 Megica Corporation Method for fabricating chip package with die and substrate
US8835221B2 (en) 2001-12-31 2014-09-16 Qualcomm Incorporated Integrated chip package structure using ceramic substrate and method of manufacturing the same
US9030029B2 (en) 2001-12-31 2015-05-12 Qualcomm Incorporated Chip package with die and substrate
US9136246B2 (en) 2001-12-31 2015-09-15 Qualcomm Incorporated Integrated chip package structure using silicon substrate and method of manufacturing the same
US8492870B2 (en) 2002-01-19 2013-07-23 Megica Corporation Semiconductor package with interconnect layers

Similar Documents

Publication Publication Date Title
CA1217876A (en) Semiconductor device and a method for fabricating the same
JP3398721B2 (en) Semiconductor package and a method of manufacturing the same
US6975023B2 (en) Co-packaged control circuit, transistor and inverted diode
KR100369393B1 (en) Lead frame and semiconductor package using it and its manufacturing method
US7960816B2 (en) Semiconductor package with passive device integration
US6343019B1 (en) Apparatus and method of stacking die on a substrate
US5293301A (en) Semiconductor device and lead frame used therein
US6545347B2 (en) Enhanced leadless chip carrier
KR100260997B1 (en) Semiconductor package
TWI290365B (en) Stacked flip-chip package
KR100339044B1 (en) ball grid array semiconductor package and method for making the same
CN101512762B (en) Stackable packages for three-dimensional packaging of semiconductor dice
US6175149B1 (en) Mounting multiple semiconductor dies in a package
US20030006055A1 (en) Semiconductor package for fixed surface mounting
KR100603799B1 (en) Metal foil having bumps, circuit substrate having the metal foil, and semiconductor device having the circuit substrate
JP2644711B2 (en) Chip scale package with a circuit board of the metal
US6297547B1 (en) Mounting multiple semiconductor dies in a package
JP3420153B2 (en) Semiconductor device and manufacturing method thereof
US6507114B2 (en) BOC semiconductor package including a semiconductor die and a substrate bonded circuit side down to the die
US6538313B1 (en) IC package with integral substrate capacitor
KR100263292B1 (en) Semiconductor package
JP3631120B2 (en) Semiconductor device
US7643311B2 (en) Electronic circuit protection device
US6586834B1 (en) Die-up tape ball grid array package
TW563233B (en) Process and structure for semiconductor package

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent