TW504768B - Method for obtaining channel length smaller than 0.1 micron - Google Patents

Abstract

The present invention relates to a method for obtaining a channel length smaller than 0.1 micron meter, which is suitable for a semiconductor substrate and mainly comprises: in a cleaning process prior to an implantation of a lightly-doped drain, adding NH4OH into the chemical cleaning solution; and in all the cleaning processes after the implantation, not adding NH4OH into the chemical cleaning solution. The former cleaning process is to form micro-dents in the lightly-doped drain region (or extended source/drain region); and the later cleaning process is to reduce the deterioration of the component efficiency and the electrical instability caused by a reduction and change in the amount of implantation dosage.

Description

504768

The present invention relates to a semiconductor deep sub-micron process, and more particularly to a method for obtaining a channel length range less than 01 micrometer. In the ultra-large integrated circuit (ULSI) process, silicon wafers must enter the high-temperature furnace tube for diffusion or oxidizing heat, before chemical vapor deposition of thin media, after thin film etching, and after ion implantation. After chemical cleaning, DI water rinse, and dehydration steps, the wafer surface can meet the requirements of high cleanliness. Therefore, wafer cleaning technology affects the wafer One of the important factors of factory yield, component quality and reliability. The purpose of cleaning is mainly to remove the contamination on the wafer surface, such as particles, organics, and metallic ions. In wafer cleaning technology, the traditional RCA chemical cleaning process is most commonly used, as shown in Figure 1. The chemical cleaning station 10 provided according to FIG. 1 includes a wafer load / unload station I / O 30 for loading a wafer to be cleaned there. The chemical cleaning station 10 is used for cleaning, and secondly, the robot arm 丨 2 is used to send the wafer into a plurality of process modules 1, 2, and 3 for cleaning. According to the standard rCa cleaning technology sequence, the wafer is first sent to module 1, which includes a chemical bath tank with a SCI solution and a water bath tank QDR-14 The chemical solution SCI uses APM (NH4〇H / H2O2) recipe, which has a lower removal ability for metal impurities, but has a higher effect on the removal of particles on the surface of silicon wafers. , The wafer is sent to the water washing tank QDR -14 for quick flushing (quick dump

504768 V. Description of the invention (2) rinse) to avoid residual chemical solution% 1. Next, the wafer is sent to module 2. The module 2 includes a chemical bath tank 13 with a SC2 solution and a water bath tank QDR-16. The chemical solution SC2 uses HPM (HC1 / H202) recipe, its month b is sufficient to effectively remove the metal impurities on the wafer surface, and then send the wafer into the water washing tank QDR-16 for quick dump rinse to avoid The chemical solution SC2 remains. Finally, the robot arm 12 sends the wafer to the drying machine DRYER-20 of the mold group 3 for dehumidification and drying. Among them, in order to prevent wafers from being carried out without drying, the chemical cleaning station sets the drying machine DRYER-20 as the final step. __ In the wet cleaning process of semiconductor manufacturing, it is required that after the cleanliness, the burial of the shixi substrate will not be caused, especially the burrow of the shixi substrate caused by the cleaning process after the implantation will reduce the amount of the implantation and change and cause electricity. Sexual instability. According to recent research, in the development of a 0.1 micron gate structure, the Nh4〇h component in the cleaning solution of the wet cleaning process will have a short channel effect on the NMOS device and the integrity of the gate oxide layer (gate 〇 〇 xide integrity (GOI) can have a significant impact. Removal of the ΝΗ40Η component in the wet cleaning process > Valley liquid will cause the threshold voltage (VT) to be greatly deteriorated and the short channel effect to be worsened. The reverse short channel effect (RSCE) is directly related to other phenomena, such as a significant decrease in the initial bias voltage and a decrease in the transient enhanced diffusion (TED) effect of boron. Sex. This new finding points out that the effect of instantaneous accelerated diffusion of boron can be tightly controlled by the lattice defects caused by ion implantation and its position.

3U4 / () 8 V. Description of the invention (3). The complementary metal-oxide-semiconductor field-effect transistor technology requires a channel length range of \) \ Μ ^ κ t / wood ’, which brings new challenges to the process of forming channels / sources // poles using traditional implantation techniques. Therefore, if a new system can be developed, the ultra-low-energy implantation (< lkev) or expensive annealing process can be used to obtain the required channel length range, which is worth developing. In view of this, the purpose of the present invention is to solve the above problems, and to provide a method obtained from a channel length range of less than 0.1 micron, which is suitable for a semiconductor substrate, and is mainly cleaned before the lightly doped drain is implanted. Process ^ ANH4OH was added to the chemical cleaning solution, and the washing after all the planting was prepared. In the chemical cleaning solution, ΝΗ40Η was not added. The cleaning process of the former is to generate micro-pits in the lightly doped drain region (or extended source / drain region), while the cleaning process of the latter is to reduce the reduction and change of the implantation dose and lead to component efficiency. Deterioration and electrical instability. ★ In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy to understand, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: Brief description of the drawings: FIG. 1 is Schematic diagram of a conventional chemical cleaning station for semiconductor wafers. The second A-2D diagram is a cross-sectional view of a process in which the obtained channel length range of the embodiment of the present invention is less than 0.1 μm. Symbol Description

0503-6627TWf; TSMC2001-0596; ycchen.ptd 504768 Description of the invention (4) 1 0 ~ chemical cleaning station; 11, 13 ~ chemical cleaning tank 20 ~ drying machine; 6 0 ~ substrate; G ~ gate structure; 6 6 ~ gate electrode; 70 ~ micro recess; 7 4 ~ gate insulating sidewall layer 12 ~ robotic arm; 14,16 ~ water washing tank; 30 ~ wafer loading and unloading station; 62 ~ shallow trench isolation layer 6 4 ~ gate dielectric layer; 68 ~ gate shield layer; 72 ~ extended source / drain; method of embodiment description This embodiment mainly provides a method for obtaining a channel length range of less than 0 micron. Refer to 2A This figure shows that the fabrication of this embodiment is based on the fabrication of an NMOS device. As shown in FIG. 2A, the surface of a p-type semiconductor substrate 60 includes a plurality of shallow trench isolation layers "to separate active areas. Money is formed on the semiconductor substrate—gate junction age. The gate structure G is composed of a gate dielectric layer 64, a gate electrode 66, and a gate shielding layer 68. In #, the gate dielectric layer 64 may be formed by Made of nitride nitride, oxynitride, or high-k dielectric material, and the gate electrode 66 may be polycrystalline silicon Layer or metal layer, the gate shielding layer 68 may be a silicon nitride layer or a silicon dioxide layer, but it is not limited thereto. Secondly, as shown in FIG. 2B, the semiconductor substrate 60 is implemented with a nioh The first chemical cleaning process is performed after the gate structure is formed to clean the electrode structure in a predetermined source and drain ejctensions:

504768 V. Description of the invention (5) Micro depression 70 is generated. For example, the semiconductor substrate 60 is cleaned by using a first chemical cleaning solution SC1 based on APM (NH40H / H202) formula and a second chemical cleaning solution sc2 based on HPM (HCl / H202) formula. The above-mentioned cleaning process 'which uses the above chemical cleaning solution to clean this substrate' respectively, at about 45-65 ° C, the cleaning time is about 3 to 10 minutes to remove particles and metal impurities on the wafer, Then, it is washed with deionized water (1) and 1 water). Next, as shown in FIG. 2C, an extended source »/ drain 72 is formed on the semiconductor substrate 60. The extended source / drain 72 can be completed by an ion implantation method. Furthermore, the semiconductor substrate 60 is subjected to a second chemical cleaning process that does not contain NΗ40Η, and is cleaned after the source / drain formation is performed. For example, the second chemical cleaning solution SC2 is used to clean the semiconductor substrate 60. In the above cleaning process, the substrate is cleaned by using the above chemical cleaning solution. At about 4 / i65 ^ CM, the cleaning time is about 3-10 minutes to remove particles and metal impurities on the wafer. Wash with DI water. Finally, as shown in FIG. 2D, gates are formed on both sides of the gate structure (i.e., gates on both sides of the gate structure J: edge side wall layer 74 'and the closed-pole insulating side wall layer 74 may be oxygen-cutting: It can be used in the washing steps and steps of each ion implantation process. In the washing step before the implantation, it is "NΗ40Η", and in the washing after all the implantation, ^ ^% σ is not added to people Can reduce the second, the deterioration of the efficiency of the element caused by the net solution and the reduction and change of the electrically unstable plant agent 1

V. Description of the invention (6) V. Description of the invention (6) Features and effects of the invention The method of obtaining the 俾 Xison method fm and 択 obtained by the present invention has a channel length range of less than 0.1 micron, which can achieve the following goals ... First, it can be obtained that the range of ϋ e ^ ^ ^ is less than 0.1 μm. Furthermore, it can be reduced by two; additional source / drain series resistance due to the sag phenomenon. And to obtain acceptable gate oxide integrity. The FF-til 3 t invention has been disclosed as above with a preferred embodiment, but it is not intended to be a Γ artist, without departing from the spirit of the invention

The attached application; KG; :::: The scope of protection of the present invention

Claims (1)

The method is applicable! A method for obtaining a semiconductor substrate with a channel length ranging from less than 0.1 micrometers to a semiconductor substrate includes the following steps: • forming a gate structure on the semiconductor substrate; performing a first chemical wash on the semiconductor substrate containing NΗ40Η The net system is washed after the formation of the closed-electrode structure to generate a predetermined expansion; micro-pits are formed; an extended source / drain is formed on the semiconductor substrate; a second chemistry that does not contain nh4oh is performed on the semiconductor substrate The washing process is performed after the extended source / drain is formed and washed; and a gate insulating sidewall layer is formed on both side walls of the gate structure. 2. The method as described in item 1 of Shen Qing's patent scope, wherein the first chemical cleaning process is to use a first chemical cleaning solution sci based on APM (NH4〇H / H2 02) formula and A second chemical cleaning solution SC2 was cleaned using HPM (HCl / H2O2) formula. 3. The method according to item 1 of the scope of patent application, wherein the second chemical cleaning process is to use a second chemical cleaning solution SC2 for cleaning. 4. The method as described in item 1 of the scope of patent application, wherein the cleaning processes are performed at 45-65 t :. 5. The method as described in item 1 of the scope of patent application, wherein the cleaning process has a cleaning time of 3-10 minutes. 6. The method according to item 1 of the scope of patent application, wherein the cleaning process includes cleaning the semiconductor substrate with deionized water. 7. The method according to item 1 of the scope of patent application, wherein 0503-6627TWf; TSMC2001 -0596; ycchen.ptd page l504 504768 6. Scope of Patent Application The source / drain extension is completed by ion implantation. ^ The method according to item 1 of the scope of patent application, wherein the gate structure is composed of a gate dielectric layer, a polycrystalline silicon layer, and a silicon nitride shielding layer. 9. The method according to item 1 of the scope of patent application, wherein the insulating insulating sidewall layer is oxidized; a layer or a nitride layer. 10 · —A method for obtaining a channel length in the range of less than 0.1 micrometers, suitable for a semiconductor substrate, including the following steps: performing a first chemical cleaning process containing NH4〇H on the semiconductor substrate, and washing before ion implantation ; And performing a second chemical cleaning process that does not contain NH 4 0H on the semiconductor substrate to perform ion implantation and cleaning. 11. The method as described in item 10 of the scope of the patent application, wherein the first chemical cleaning process is to use a first chemical cleaning solution separately ^ 丨 using APM (NH4〇H / H2 02) formula and A second chemical cleaning solution SC2 was washed with HPM (HC1 / H202) formula. 12. The method as described in item 10 of the scope of patent application, wherein the second chemical cleaning process is to use the second chemical cleaning solution SC2 for cleaning. 13. As described in item 10 of the scope of patent application, the net process is carried out at 45-65 ° C. , W ′ 14. The method as described in item 10 of the scope of patent application, the net process cleaning time is 3-10 minutes. , With ‘