JP3173655B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device capable of effectively removing heavy metal contamination formed near the surface of a semiconductor substrate.

[0002]

2. Description of the Related Art As the degree of integration of DRAMs increases, it becomes more difficult to maintain data retention time. The retention time is
P related to the source / drain region to which the capacitor is connected
It is greatly affected by the quality of the n-junction. One of the factors that increase the leakage current at the junction is contamination by heavy metal elements. Heavy metal contamination causing problems is DRAM
With the miniaturization of, the density becomes lower and its control is not easy. Heavy metal elements that cause contamination (hereinafter referred to as contaminated heavy metal elements) include, for example, Fe, Ni, and Cu. These elements form a deep level by forming a solid solution in Si, and when they exceed the solid solubility, they precipitate as silicide,
Deteriorates bonding characteristics. For further details on the effects of heavy metal contaminants on Si devices, see, for example, Metal.
Impurities in Silicon-De
vic Fabrication, by Klaus
This is described in Graff (Springer, 1994).

In general, a contaminant heavy metal element is mixed in from an LSI manufacturing apparatus or a used material. Therefore, these manufacturing apparatuses and materials need to be thoroughly cleaned. However, since the cost required to maintain a stable ultra-high degree of cleanliness is enormous, a gettering technique is generally used to compensate for this. The gettering technique is a technique for recognizing the presence of a certain amount of contaminant heavy metal elements in Si and removing as much as possible the contaminant heavy metal elements from the operating region of the device (for example, the area where the pn junction is formed). It is. The removed contaminated heavy metal element is captured in a gettering site provided in advance outside the operation region of the device. In addition, the contaminant heavy metal element in the device operation region needs to be captured after diffusing to the gettering site. Such a gettering technique is described in detail, for example, in Chapter 6 of VLSI Process Control Engineering, Hideki Tsuya (Maruzen, 1995).

[0004] The problem is that, as described above, with the increase in integration of DRAMs, the amount of heavy metal contamination in the device operation area must be suppressed to a very low concentration. On the other hand, when the DRAM is miniaturized, the heat treatment in the manufacturing process tends to be performed at a lower temperature and for a shorter time. Therefore, the contaminated heavy metal element in the device operation region is less likely to diffuse to the gettering site than in the related art. As a result, the amount of heavy metal contamination in the device operation region cannot be reduced, and it becomes very difficult to improve the junction leak characteristics. In order to solve such a problem, a method of forming a gettering site near a device active layer has been proposed. This method is described, for example, in Appl. Phys. Let
t. , Vol. 52, pp. 1023-1025 (19
88) byH. Wong, N .; W. Cheung, P .;
K. Chu, J .; Liu and J.J. M. As shown by Mayer, a gettering site is formed by ion implantation.

[0005]

However, when a gettering site is formed by ion implantation, once the gettered contaminated heavy metal element is re-emitted, there is a problem that it is easily diffused into the device active layer. . Further, for example, as shown in Takanori Hayato, pages 782 to 789 of Applied Physics Vol. 60, No. 8, the ion implantation step itself is a step of introducing heavy metal contamination into the Si wafer. It is not desirable that additional steps be added.

[0006] It is an object of the present invention to solve the above-mentioned problems of the prior art, with the aim of making it possible to getter even very low concentrations of contaminating heavy metals without using a high-temperature process, and The purpose is to prevent the gettered contaminant element from diffusing into the active region again.

[0007]

According to the present invention, there is provided, according to the present invention, (1) an opening for exposing a surface of a region on a semiconductor substrate in an interlayer insulating film provided on the semiconductor substrate. Forming, forming a through film on the bottom surface of the opening; (2) performing ion implantation of one conductivity type impurity through the through film; and (3) performing heat treatment to contaminate elements near the bottom surface of the opening. Gettering to the through film, and (4) a step of performing heat treatment in a halogenating atmosphere to halogenate the gettered contaminant element and remove the contaminated element out of the wafer. A method for manufacturing a semiconductor device is provided.

According to the present invention, in order to achieve the above-mentioned object, (1) a step of forming an opening exposing a surface of one region on a semiconductor substrate in an interlayer insulating film provided on the semiconductor substrate; (2) a step of ion-implanting one-conductivity-type impurity through the opening; and (3) a heat treatment in an oxidizing atmosphere to form an oxide film on the bottom surface of the opening while the vicinity of the bottom surface of the opening. And (4) a step of performing heat treatment in a halogenating atmosphere to halogenate the gettered contaminant element and remove the contaminant element out of the wafer. A method for manufacturing a semiconductor device, comprising:

[0009]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in the order of steps. Here, an example in which the present invention is applied to a method of manufacturing a cell capacitance contact portion of a DRAM will be described. In FIG. 1A, 1 is a p-well formed on a semiconductor substrate (not shown), 2 is an element isolation insulating film, 3
Is a gate insulating film, 4 is a gate electrode, 5 is an n-type diffusion layer connected to an information storage capacitor, 6 is an interlayer insulating film covering the transistor, and 7 is a silicon oxide film serving as a through film for implanted ions. It is. FIG. 1A shows a state in which an unintended contaminant heavy metal element (for example, Fe) 10 mixed during the DRAM manufacturing process exists near the pn junction of the n-type diffusion layer 3. Such contamination by heavy metal elements often enters from a manufacturing apparatus in processes such as high-temperature heat treatment, dry etching, and ion implantation. In such a situation, P ions are implanted through the silicon oxide film 7 to form a contact. The higher the impurity concentration (phosphorus concentration), the higher the solid solubility of the contaminated heavy metal. Therefore, if the peak of the impurity concentration (phosphorus concentration) is present at a shallower position, the contaminated heavy metal can be efficiently transferred to the gettering site on the substrate surface. Can be led to. Therefore, this ion implantation is preferably performed so that the peak of the implanted ion concentration exists at a position shallower than 30 nm. As the implanted ions, As ions can be used instead of P ions. When making contact with the p-type diffusion layer, B ions or BF ₂ ions are implanted.

Next, as shown in FIG. 1B, a heat treatment for activating the implanted P ions is performed. This heat treatment is performed using an electric furnace (diffusion furnace) or a lamp anneal. By this heat treatment, the contaminated heavy metal element 10 is diffused into the ion-implanted portion having a higher impurity concentration than the n-type diffusion layer 3, and furthermore, the silicon oxide film 7 having a higher solid solubility.
And gettered by the silicon oxide film 7. Thus, one of the features of the present invention is that the gettering site is very close to the device active layer.

For example, since Fe diffuses 70 μm at 900 ° C. for 30 seconds, it is possible to almost completely getter Fe existing in the device operation region, that is, the pn junction. For example, even if the activation of P is performed by lamp heating at 900 ° C. for 10 seconds, gettering can be performed to a considerable extent. Thus, the contaminating heavy metal elements are not always present at a uniform concentration inside the wafer. That is, the contaminated heavy metal element introduced by ion implantation, dry etching, or the like often exists locally at a high concentration. In particular, in such situations, for example, 900
The gettering effect is large even with a heat treatment at 30 ° C. for 30 seconds.
However, gettering becomes more reliable with a long heat treatment. For example, a heat treatment at 900 ° C. for 10 minutes using a diffusion furnace. And gettering efficiency can be further improved as follows. That is, for example, 900 ° C.1
After the heat treatment for 0 minutes, slow cooling is performed. For example, the wafer is taken out after cooling from 900 ° C. to 400 ° C. at 3 ° C./min in a diffusion furnace. The cooling rate is desirably 10 ° C. or less per minute, more preferably 5 ° C. or less per minute.

The gettering efficiency can be increased by slow cooling for the following reasons. The contaminated heavy metal to be gettered is the amount exceeding the solid solubility in silicon. Since the solid solubility is lower at lower temperatures, the amount of gettering is higher at lower temperatures. However, the contaminated heavy metal element needs to diffuse to the gettering site in order to be gettered. The diffusion distance is the diffusion constant D and the heat treatment time t
And the square root of the product Dt. The diffusion constant D depends on the temperature and is smaller at lower temperatures. That is, at low temperatures, the amount of heavy metal contamination that can be gettered increases, but there is a problem that it takes time to diffuse to the gettering site. In addition, when cooling is performed rapidly after the high-temperature heat treatment, gettering is not sufficiently performed during the high-temperature heat treatment, so that the concentration gradient of the contaminated heavy metal is loosened and the diffusion efficiency is reduced. Further, the cooling is likely to be completed before the contaminated heavy metal is gettered by the rapid cooling. Slow cooling is performed to solve such a problem. By gradually lowering the temperature, the concentration of heavy metal contamination that can be gettered gradually increases. On the other hand, the diffusion constant gradually decreases, but is sufficiently large as compared with the case where heat treatment is performed at a low temperature from the beginning. In other words, the effect of increasing the amount of heavy metal contamination that can be gettered can be expected by performing slow cooling while ensuring the longest possible diffusion length.

In recent LSI manufacturing lines, the absolute amount of heavy metal contaminating impurities that contaminate wafers has been reduced due to improvements in manufacturing equipment cleaning and wafer cleaning techniques. Therefore, sufficient gettering may not be performed without exceeding the solid solubility at the heat treatment temperature. Nevertheless, the need for gettering is due to the fact that the concentration of contaminants, which is a problem due to the miniaturization of devices, has been reduced. For example, the SIA roadmap [SIA (Semicond
uctor IndustryAssociation) “The NationalTechnolo
gy Roadmap for Semiconductors "p.64], the generation of 0.18 micron rule
^{Should be} 10 ¹⁰ cm ^-3 or less. Since this has a solid solubility of about 560 ° C., sufficient gettering may not occur unless heat treatment is performed at 560 ° C. or less. Therefore, as described above, in order to make Fe equal to or less than the above concentration,
It is desirable that the heat treatment is gradually cooled to 560 ° C. or less, for example, about 500 ° C. or less. That is, in general, the heat treatment is performed more completely by heating to a temperature at which the concentration of the contaminating heavy metal element becomes solid solubility, and then gradually cooling it to a temperature at which the allowable concentration of the contaminating element becomes solid solubility. Gettering can be performed.

After gettering the contaminated heavy metal element 10 in this way, the gettered contaminated heavy metal element is removed outside the wafer, and the silicon oxide film 7 is further removed.
That is, as shown in FIG. 1C, heat treatment is performed in an atmosphere of HCl + O ₂ . Thereby, the contaminated heavy metal element 10
Is halogenated and becomes chloride (for example, FeCl ₂ ) and is removed outside the wafer. At the same time, in the step of FIG. 1B, the contaminant heavy metal element 10 that cannot be gettered in the silicon oxide film 7 and remains near the pn junction is
Even during the step (c), gettering into the silicon oxide film 7 occurs, and further, it is removed as chloride (FeCl ₂ ). In this case, HCl alone is effective, but when O ₂ is added, oxidation proceeds further, and the volume of the oxide film as a gettering site increases. As a result, FIG.
The contaminant heavy metal element that could not be completely gettered in the step is once gettered in the silicon oxide film 7,
Excluded as chloride (FeCl ₂ ). Further, FIG.
The last step of (c), the silicon oxide film 7 is removed by HF vapor or H _2.

Finally, as shown in FIG. 1D, doped polysilicon 11 is formed, and the formation of the capacitor contact portion is completed. As described above, in the present invention, the contaminant heavy metal element such as Fe once gettered is removed outside the wafer, so that it is not re-emitted from the gettering site and diffused into the device active region to deteriorate the device characteristics. . Therefore, in a method having a gettering site near the device active region inside the wafer by ion implantation or the like, even if the contaminated heavy metal element is once gettered, it may be re-emitted by a subsequent heat treatment and re-diffused into the device active region. However, according to the manufacturing method of this embodiment, such a problem is solved.

FIG. 2 is a sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps. In FIG. 2, components that are the same as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted. As shown in FIG. 2A, in the present embodiment, P ions are implanted without passing through a through film (silicon oxide film). Next, as shown in FIG. 2B, heat treatment is performed in an oxidizing atmosphere. This heat treatment is performed in a dry atmosphere containing only O ₂ or a wet atmosphere containing H ₂ O. Therefore, during this heat treatment,
Silicon oxide film 7 is formed at the bottom of the contact hole. Then, the contaminated heavy metal element 10 is diffused into the ion-implanted portion having a higher impurity concentration than the n-type diffusion layer 3, and is diffused into the newly formed silicon oxide film 7 having a higher solid solubility, and the silicon oxide film 7 is formed. Gettered. Also in the present embodiment, more reliable gettering can be caused by slow cooling after the heat treatment.

Next, as shown in FIG.
Heat treatment is performed in an atmosphere of (or HCl + O ₂ ). As a result, the contaminant heavy metal element 10 is halogenated and becomes a chloride (for example, FeCl ₂ ) and is removed outside the wafer. At the same time, the contaminant heavy metal element 10 that could not be gettered completely in the silicon oxide film 7 in the step of FIG. 2B and remained near the pn junction was removed from the silicon oxide film 7 even in the step of FIG. Gettering, and is further removed as chloride (FeCl ₂ ). Further, FIG.
At the end of the step (c), the silicon oxide film 7 is removed by processing in an HF vapor or H ₂ atmosphere. And FIG.
As shown in (d), the TiN film 11 and the W film 1 are connected to connect the n-type diffusion layer 5 and a capacitor formed in an upper layer.
Formed as 2.

The embodiment described above is an example for explaining the present invention, and the present invention is not limited to the above-described embodiment, and various modifications are possible within the scope of the invention. is there. For example, in the embodiment described with reference to FIG. 1, a silicon oxide film is used as a through film for ion implantation, but the same effect can be obtained by using a polysilicon film instead. That is, polysilicon also has a strong gettering ability. When polysilicon is used, HCl + O ₂ is used in a process corresponding to FIG.
The polysilicon is oxidized by the atmosphere. This makes it possible to remove the oxide film in a subsequent HF vapor or H ₂ atmosphere.

The gettering step shown in FIGS. 1 (b) and 2 (b) and the halogenation / removal step of contaminating heavy metal elements shown in FIGS. 1 (c) and 2 (c) are performed in one step. Can be integrated. That is, gettering is performed in a halogenating atmosphere using HCl or the like or in a halogenating and oxidizing atmosphere using (HCl + O ₂ ) or the like, and at the same time, halogenation of the contaminating heavy metal element is performed. Good. In the above-described embodiment, doped polysilicon and TiN are used for contact formation. However, similar effects can be obtained by using silicide of Mo, Co, or Ti.

[0020]

EXAMPLES The extent to which heavy metal contamination was eliminated when a DRAM was manufactured by the manufacturing method according to the above-described embodiment was compared with experimental data. Comparative Example 1 An n-type diffusion layer having an impurity concentration of 1E20 / cm ³ was formed, and a sample intentionally doped with Fe was formed.
A 300 nm interlayer insulating film was formed, and a 0.25 μm square contact hole was formed. Phosphorus is supplied through this contact hole at an energy of 30 keV and a dose of 5E1.
Ion implantation was performed under the condition of 4 / cm ² . After an activation heat treatment at 900 ° C. for 10 minutes in a nitrogen atmosphere, a natural oxide film was removed by H ₂ gas treatment, and a contact plug was formed with doped polysilicon. For this sample, the junction leak current was measured at 50 points in the wafer plane. The result is shown in FIG. In the characteristic data, the horizontal axis indicates the reverse voltage of the pn junction, and the vertical axis indicates the junction leakage current (the same applies to (b) and (c)).

Example 1 The steps up to the formation of a contact hole were performed under the same conditions as in Comparative Example 1, a 20-nm-thick silicon oxide film was formed at the bottom of the contact hole by a CVD method, and phosphorus was passed through this oxide film. Energy: 3
Ion implantation was performed under the conditions of 0 keV and a dose of 5E14 / cm ² , and heat treatment was performed at 900 ° C. for 30 seconds. Then HC
After a heat treatment at 900 ° C. for 5 minutes in an atmosphere of l + O ₂ , the silicon oxide film was removed, and a contact plug was formed with doped polysilicon. About this sample,
The junction leak current was measured at 50 points in the wafer plane. The result is shown in FIG.

Example 2 The process up to the opening of the contact hole was performed under the same conditions as in Comparative Example 1, a 20-nm-thick silicon oxide film was formed at the bottom of the contact hole, and phosphorus was supplied through this oxide film at an energy of 30 keV. The ion implantation was performed under the conditions of a dose amount of 5E14 / cm ² . 900
After the heat treatment at 10 ° C. for 10 minutes, the temperature was gradually decreased from 900 ° C. to 500 ° C. at a rate of 5 ° C./min. Subsequently, heat treatment was performed at 900 ° C. for 5 minutes in an atmosphere of HCl + O ₂ . Thereafter, the silicon oxide film was removed, and a contact plug was formed with doped polysilicon. For this sample, the junction leak current was measured at 50 points in the wafer plane.
The result is shown in FIG.

In the case of FIG. 3A, there are many places where the leakage current abnormally increases as the reverse voltage increases. In addition, there are some places where the leakage current is large while the reverse voltage is low. 3 (b) and 3 (c), the leakage current was small, and no portion where the leakage current abnormally increased even when the reverse voltage was increased was found. Also,
In the case of FIG. 3C, the leak current is almost halved compared to FIG. 3B. This indicates that the slow cooling allows more complete removal of the contaminated heavy metal elements in the wafer.

Comparative Example 2 Impurity concentration 1E20 / cm ³
Was formed without intentional doping with Fe, a 300 nm interlayer insulating film was formed, and a 0.25 μm square contact hole was formed. Energy of phosphorus: 30k through this contact hole
Ion implantation was performed under the conditions of eV and a dose of 5E14 / cm ² . After performing an activation heat treatment at 900 ° C. for 10 minutes in a nitrogen atmosphere, a natural oxide film was removed by H ₂ gas treatment, and a contact plug was formed with doped polysilicon. Then, a MIS structure stacked capacitor was formed on the interlayer insulating film. Then, the data retention characteristics of the DRAM having 50 chips in the wafer plane were measured. The result is shown by (a) in FIG. In the figure, the horizontal axis represents the data retention time, and the vertical axis represents the standard deviation, and the graph shows the ratio of the cumulative number of bits that cannot maintain the data retention time as an integral value from -∞ of the normal distribution.

Example 3 The steps up to the opening of the contact hole were performed under the same conditions as in Comparative Example 1, a 20-nm-thick silicon oxide film was formed at the bottom of the contact hole by thermal oxidation, and phosphorus was passed through this oxide film. Energy: 30
Ion implantation was performed under the conditions of keV and a dose of 5E14 / cm ² , and heat treatment was performed at 900 ° C. for 1 minute. Then HCl +
After performing a heat treatment at 900 ° C. for 5 minutes in an atmosphere of O ₂ ,
The silicon oxide film was removed, and a contact plug was formed using doped polysilicon. Then, a MIS structure stacked capacitor was formed on the interlayer insulating film. Then, the data retention characteristics of the DRAM having 50 chips in the wafer plane were measured. The result is shown by (b) in FIG.

As for the data retention characteristics, the characteristics of the portion where the retention time is short are more important. This is because the shortest holding time determines the refresh time. Here, -5 of the standard deviation means a cumulative failure of about 0.00003%, and-
4 means a cumulative failure of about 0.003%. Thus, this failure rate can be reduced to, for example, 64M, which is currently mainstream.
When corresponding to a bit DRAM, -5 is several tens of bits,
4 is several thousand bits. As can be seen from the graph of FIG. 4, the cumulative number of defective bits in the data holding time of 1 second in the third embodiment is improved to 1/100 or less as compared with the comparative example 2. Further, even when the data retention time is long, the cumulative number of defective bits of Comparative Example 2 is always higher than that of Example 3, and it can be seen that the overall improvement is achieved by the present invention.

[0027]

As described above, according to the method of manufacturing a semiconductor device of the present invention, after a heavy metal element is contaminated in a through film through which ions to be implanted for forming a contact are transmitted, the gettered contaminant is removed. Since the element is halogenated and removed outside the wafer, the following effects can be obtained. Since the gettering site exists near the contaminant element, gettering can be effectively performed even with a low-concentration contaminant element without performing high-temperature treatment. The diffusion direction of the contaminated heavy metal element is determined by the impurity concentration gradient, so that gettering can be performed efficiently. Since the gettered contaminant element is halogenated and removed out of the wafer, there is no possibility that the active region is contaminated again. Therefore, the quality of the pn junction having the contact portion can be improved, and the leakage current can be reduced. Therefore, when the present invention is applied to a capacitance contact portion of a DRAM, the data retention characteristics of the DRAM can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device in a process order for describing a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device in a process order for describing a second embodiment of the present invention.

FIG. 3 is a characteristic diagram comparing a junction leakage current when the manufacturing method of the present invention is applied with that obtained when a conventional technique is used.

FIG. 4 is a characteristic diagram comparing a data retention characteristic when the manufacturing method of the present invention is applied and a data retention characteristic when the conventional technique is used.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 p-well 2 element isolation insulating film 3 gate insulating film 4 gate electrode 5 n-type diffusion layer 6 interlayer insulating film 7 silicon oxide film 8 contact diffusion layer 9 doped polysilicon film 10 contaminated heavy metal element 11 TiN film 12 W film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 21/8242 H01L 21/265 H 27/108

Claims (12)

(57) [Claims] 1. An opening for exposing a surface of a region on a semiconductor substrate is formed in an interlayer insulating film provided on a semiconductor substrate, and a through film for transmitting implanted ions is formed on a bottom surface of the opening. (2) a step of implanting ions of one conductivity type impurity through the through film; and (3) a step of performing heat treatment to getter contaminant elements near the bottom surface of the opening to the through film. A) a step of performing heat treatment in a halogenating atmosphere to halogenate the gettered contaminant element and removing the contaminated element out of the wafer. 2. The method according to claim 1, wherein the through film is a silicon oxide film or a polysilicon film. And (3) forming an opening in the interlayer insulating film provided on the semiconductor substrate to expose a surface of a region on the semiconductor substrate; and (2) forming an impurity of one conductivity type through the opening. (3) performing a heat treatment in an oxidizing atmosphere to form an oxide film on the bottom surface of the opening and gettering a contaminant element near the bottom surface of the opening to the formed oxide film; And (4) a step of performing heat treatment in a halogenating atmosphere to halogenate contaminant elements gettered and removing the contaminated elements out of the wafer. 4. The method according to claim 1, wherein the ion implantation in the step (2) is performed such that a concentration peak of the implanted impurity exists at a position shallower than a depth of 30 nm in the semiconductor substrate. Of manufacturing a semiconductor device. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment in the step (4) is performed in a halogenated and oxidizing atmosphere. 6. The heat treatment of the step (4) is performed by using HCl.
4. The method for manufacturing a semiconductor device according to claim 1, wherein the method is performed in an atmosphere containing HCl or an atmosphere containing HCl and O ₂ . 7. The method according to claim 1, wherein the step (3) and the step (4) are performed in the same step. 8. The heat treatment in the step (3) is performed at 10 ° C.
4. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of slow cooling at a rate of not more than / minute. 9. The heat treatment of the third step is performed after heating to a temperature at which the concentration of the contaminant element becomes a solid solubility or higher.
4. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of gradually cooling the semiconductor element to a temperature at which the allowable concentration of a contaminant element becomes a solid solubility at a temperature of not more than C / minute. 10. The method according to claim 1, further comprising: a step of removing the through film or the oxide film after the step (4); and a step of forming a conductive material layer in contact with the one region at a bottom surface of the opening. 2. The method according to claim 1, wherein the information is added.
4. A method for manufacturing a semiconductor device according to item 3. 11. The method according to claim 10, wherein the step is performed by exposing the wafer to an atmosphere containing HF or H ₂ . 12. The method according to claim 10, wherein the conductive material film is one of doped polysilicon, Mo silicide, Co silicide, Ti silicide, and Ti nitride.