TW490836B - Semiconductor device and mounting structure thereof - Google Patents

Semiconductor device and mounting structure thereof Download PDF

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Publication number
TW490836B
TW490836B TW089111833A TW89111833A TW490836B TW 490836 B TW490836 B TW 490836B TW 089111833 A TW089111833 A TW 089111833A TW 89111833 A TW89111833 A TW 89111833A TW 490836 B TW490836 B TW 490836B
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Taiwan
Prior art keywords
substrate
semiconductor device
semiconductor
main
side end
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TW089111833A
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Chinese (zh)
Inventor
Yukinaga Imamura
Keisuke Okada
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Mitsubishi Electric Corp
Mitsubishi Electric Eng
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447—Lead-in-hole components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/366—Assembling printed circuits with other printed circuits substantially perpendicularly to each other

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

In a mounting structure of a semiconductor device according to the present invention, a semiconductor chip is provided on each of front and back main surfaces of a package substrate. Lead pins are provided to one side end surface of the package substrate such that they protrude therefrom. The package substrate is attached perpendicularly to a printed circuit board with a surface to which the lead pins are attached facing toward the printed circuit board. With this structure, the semiconductor device allowing an efficient mounting of a semiconductor chip can be provided.

Description

490836 五、發明說明（l) [發明之領域] 本發明有關於用以安裝多個半導體晶片之具備有組件基 板和安裝基板之半導體裝置及其安裝構造。 [背景技術] 在習知技術中，所使用之半導體裝置是將設有半導體晶 片之組件基板，設置在安裝基板。習知之半導體裝置如圖 14 〜圖 17 所示之QFP-LSI(Quad Flat Package-Large Scale Integration Circuit)101，102 之方式，1 個之半導 體晶片1 0 5，經由連結襯墊1 〇 7被設在組件基板1 〇 8之一方 之主表面。另外，電連接到半導體晶片丨〇 5内部之電極之 線1 0 6 ’成為連到被設在組件基板1 〇 8之侧端面之接腳 109。另外，接腳1〇9和半導體晶片1〇5被造型1〇4被覆，和 被固定在組件基板108。該QFP-LSI 101，102如圖17所示， 以未設有半導體晶片105之側之面朝向安裝基板1〇3進行安 裝。 m 上述之QFP-LSI 101,102如圖17所示，在安裝基板1〇3之 上面，每一個需要有a x b之佔用面積。依照這種方式，要 ，安裝基板103上設置n個之QFP-LSI時，需要有ηχ ax匕之 安裝基板面積，和為著將電信號發送到QFp_LSI , φ要 用以設置連接到QFP_LSI之接腳之配線之配線區域:積。 在此種習知之QFP-LSI中，隨著半導體晶片之個數使 用安裝基板之面積增加。另外，隨著所設置之QFp_L 增加使接腳之數"加，會產生安裝基 雜之問題。另夕卜’在半導體元件被高速化和高密490836 V. Description of the Invention (l) [Field of the Invention] The present invention relates to a semiconductor device including a component substrate and a mounting substrate for mounting a plurality of semiconductor wafers, and a mounting structure thereof. [Background Art] In the conventional technology, a semiconductor device is used in which a component substrate provided with a semiconductor wafer is provided on a mounting substrate. A conventional semiconductor device is shown in the manner of QFP-LSI (Quad Flat Package-Large Scale Integration Circuit) 101, 102 shown in Fig. 14 to Fig. 17. One semiconductor wafer 105 is provided through a connection pad 107. On one of the main surfaces of the module substrate 108. In addition, a wire 10 6 ′ electrically connected to an electrode inside the semiconductor wafer 05 is a pin 109 connected to an end surface provided on a side of the module substrate 108. In addition, the pins 109 and the semiconductor wafer 105 are covered with a mold 104 and fixed to the module substrate 108. The QFP-LSIs 101 and 102 are mounted with the surface on the side where the semiconductor wafer 105 is not provided toward the mounting substrate 103 as shown in FIG. 17. m The above-mentioned QFP-LSIs 101 and 102 are shown in Fig. 17, and each of them needs an area of a x b on the mounting substrate 103. In this way, when n QFP-LSIs are provided on the mounting substrate 103, the area of the mounting substrate of ηχ ax is required, and in order to send electrical signals to QFp_LSI, φ is used to set the connection to the QFP_LSI. Wiring area of the wiring of the feet: product. In such a conventional QFP-LSI, the area of the mounting substrate increases with the number of semiconductor wafers. In addition, as the QFp_L is set to increase the number of pins " increase, there will be problems with installation complexity. In addition, semiconductor devices are becoming faster and denser.

490836490836

五、發明說明（2) ,::置中’需要對從半導體晶片排出之熱進行處理， :在i述方式之QFp-Lsi之構造中’為著更進一步的散 熱，需要追加散熱器或追加 為者更 [發明之揭示] ^發明用來解決上述之問題’其目的是提供半導體裝置 2 〃、安裝構造，經由將組件基板安裝成為對安裝基板垂 直’可以有效的安裝半導體晶片。 用以達成上述目的之本發明是一種半導體裝置，具備 •組件基板’具有互為表面和背面之第1和第2主表面， =側立而面；半導體晶片，被設在第1和第2之各主表面；和V. Description of the invention (2) :: "centering needs to process the heat exhausted from the semiconductor wafer," in the structure of the QFp-Lsi method described above "for further heat dissipation, additional heat sinks or additional For the sake of further [disclosure of the invention] ^ The invention is used to solve the above-mentioned problems. 'The purpose is to provide a semiconductor device 2 (2), a mounting structure, and a semiconductor wafer can be efficiently mounted by mounting a module substrate perpendicular to the mounting substrate. The present invention for achieving the above-mentioned object is a semiconductor device including a component substrate having first and second main surfaces that are front and back surfaces of each other, = side to side, and a semiconductor wafer provided on the first and second sides. Each major surface; and

二連接用接腳，被設在侧端面，以與第丨和第2主表面大致 平行之方向延伸。 向，=此種構造時，經由以組件基板之設有接腳之面，朝 °安裝基板的進行安裝，可以將組件基板安裝成對安裝基 f，成垂直。利用這種方式，（經由在組件基板之兩面分別 7裂半導體晶片，可以在對安裝基板垂直之方向設置更多 個之半導體裝置」。因此，在安裝η個半導體晶片時，組件 基板佔用安裴基板之面積，當與習知技術之只在組件基板 之方之主表面設置半導體晶片，以未設有半導體晶片之Two connection pins are provided on the side end surfaces and extend in a direction substantially parallel to the first and second main surfaces. In this type of structure, the module substrate can be mounted to the mounting base f perpendicular to the mounting substrate by mounting the module substrate with the pins on the mounting surface. In this way, (by splitting the semiconductor wafers on both sides of the module substrate, more semiconductor devices can be installed in a direction perpendicular to the mounting substrate. "Therefore, when n semiconductor wafers are mounted, the module substrate occupies ampere The area of the substrate, when compared with the conventional technology, a semiconductor wafer is provided only on the main surface of the module substrate.

=安裝到安裝基板之情況之半導體裝置之佔用面積比較 2 ’可以成為較小。「其結果是可以以相同之安裝基板面積 叹置更多個半導體晶片，所以可以平面式的高密度安半 導體裝置」。 另外’經由在組件基板之第1和第2主表面之至少一方設= Comparison of occupied area of a semiconductor device when mounted on a mounting substrate 2 ′ can be made smaller. "As a result, more semiconductor wafers can be placed with the same area of the mounting substrate, so a planar high-density semiconductor device can be used." In addition, ′ is provided on at least one of the first and second main surfaces of the module substrate.

五、發明說明（3) 置夕個半V體晶片，在對安裝基板垂直之方 個數，可以以相同之安裝基板面。置 果是可以平面式的高密集安裝 上i:卜墓i ί使發送共同信嬈和被設在組件基板之2個以 目ϋ 之接腳結合成為1個’則全體之接腳之數 Η可以減少。 之：：面=:月，半導體裝置中，經由在構成組件基板V. Description of the invention (3) For a half-V wafer, the number of squares perpendicular to the mounting substrate can be the same as the mounting substrate surface. The result is a high-density installation that can be carried out in a flat plane: i. Tomb i The combination of sending a common message and the two pins on the module substrate is combined into one. Then the number of all pins Can be reduced. :: face =: month, in semiconductor devices, via the component substrate

表面和背面雙方，直接設置半導體晶片，則可 U不需要習知所使用娈 门 J %件美板之一：造（習知 < 安裝構造是只在 乂 ％二f e _ 置半導體晶片，將該組件基板設置 少，&制基板）。因此，零件之數目可以減 夕，和製造工程可以簡化。 ^ 在本發明之半導體裝置 ^ ^ f 片之接地用平板，從側端面=把例中，設有半導體晶 指定之區域突出。未設有接腳之區域以外之 產二可以利用接地用平板，·使半導體晶片内 ΐ 積接地…大型 果是可以減低在半導r穿置 ^ 乂進仃低阻抗化。其結 響。 牛蜍版凌置之内部和外部產生之雜訊之影 接地用平板，在組件基板被安 最好使組件基板之側端面突出女態時’ 面和安裝基板之間殘留有間隙二衣，板面對之 田匁间丨舉了以用來插另外一個之半 89111833.ptd 第7頁 m 钎观36If you directly set the semiconductor wafer on both the front and back sides, you do n’t need to know one of the US J-pieces of the US board: fabrication (the conventional < installation structure is only to install the semiconductor wafer in This module substrate is provided with a small number of substrates. Therefore, the number of parts can be reduced, and manufacturing processes can be simplified. ^ In the semiconductor device of the present invention ^ ^ The f-plate for grounding is protruded from the side end surface = in the example where a semiconductor crystal is provided. For products other than the area without pins, a grounding plate can be used to ground the semiconductor chip .... Large-scale. It is possible to reduce the penetration of the semiconductor ^ and reduce the impedance. Its ringing. For the toad version, the internal and external noise generated by the ground is flat. When the module substrate is installed, it is best to make the side surface of the module substrate protrude from the female state. There is a gap between the surface and the mounting substrate. Facing the field 匁 丨 raised to insert another half 89111833.ptd page 7 m 观 观 36

490836 五、發明說明（5) 點1 5經由組件基板1 3之内部連接到内部配線1 4。 另外，内部配線1 4連接到從組件基板丨3之一側端面突出 到外部之接腳9。另外，上述之半導體晶片丨丨，丨2，連結襯 墊7 ’和線6，被覆蓋在組件基板13之表面之成型4加以被 覆。 另外，圖1至圖3所示之組件基板丨3，如圖4和圖5所示， 被安裝成對安裝基板3之主面垂直，具有接腳9之側端面面 對安裝基板3之主面，組件基板13在安裝基板3上之平面看 之佔用面積為cxd。 圖6〜圖8表示在組件基板13之表面和背面兩侧之主表面 各设置3個之半導體晶片16, 17, 18和半導體晶片19, 20, 21 之態樣。在本實施形態中是在組件基板丨3之主表面之表面 和背面兩側各設置3個半導體晶片，但是亦可以是在組件 基板1 3之表面和背面兩側之主表面之至少一方，設置多個 晶片之態樣。 利用此種構造，將組件基板1 3之設有接腳9之面朝向安 扁基板3安裝，可以將組件基板1 3安裝成為對安裝基板3垂 f °經由在組件基板13之主表面之表面和背面兩面分別安 裝半導體晶片1 1，1 2，可以在對安裝基板垂直之方向設置 r多個之半導體裝置。因此，在安裝n個半導體晶片之f 況’組件基板1 3佔用安裝基板之面積為η X c x d，當^習 知技，所示之只在一方之面設置半導體晶片之組件"基、板白， 其在安裝棊板上之佔用面積η X a X b比較時，可以使佔用 面積、s:小。其結果是在相同之安裝基板面積可以設置較多490836 V. Description of the invention (5) The point 15 is connected to the internal wiring 14 through the inside of the component substrate 13. In addition, the internal wiring 14 is connected to a pin 9 protruding from one end surface of the module substrate 3 to the outside. In addition, the above-mentioned semiconductor wafers 丨 丨, 丨 2, the connection pads 7 ', and the wires 6 are covered with a mold 4 covering the surface of the module substrate 13. In addition, the component substrates 3 shown in FIGS. 1 to 3 are mounted perpendicular to the main surface of the mounting substrate 3 as shown in FIGS. 4 and 5, and the side end surface with the pins 9 faces the main substrate of the mounting substrate 3. The mounting area of the module substrate 13 on the mounting substrate 3 is cxd. FIGS. 6 to 8 show the state where three semiconductor wafers 16, 17, 18 and semiconductor wafers 19, 20, 21 are provided on each of the main surfaces of the front and back sides of the module substrate 13. In this embodiment, three semiconductor wafers are provided on each of the main surface and the back surface of the module substrate 3, but it may be provided on at least one of the main surfaces on both the surface and the back surface of the module substrate 13 The appearance of multiple wafers. With this structure, the surface of the module substrate 13 with the pins 9 is mounted toward the flat substrate 3, and the module substrate 13 can be mounted so as to be perpendicular to the mounting substrate 3 through the surface on the main surface of the module substrate 13. The semiconductor wafers 11 and 12 are mounted on both sides of the back surface and the back surface, and a plurality of semiconductor devices can be provided in a direction perpendicular to the mounting substrate. Therefore, in the case of mounting n semiconductor wafers, the module substrate 13 occupies an area of the mounting substrate of η X cxd. As shown in the prior art, only one side of the semiconductor wafer is shown. White, when comparing the occupied area η X a X b on the mounting fascia, the occupied area, s: can be made small. As a result, more areas can be set on the same mounting substrate area.

1_1 第9頁 89111833.ptd 490836 五、發明說明（6) 之半導體晶片11，1 2，所以可以平面式的高密度安裝半導 體裝置。 另外’如同圖6〜圖8所示之半導體晶片16, 17, 18和半導 體K置1 9，2 0，2 1之方式，假如在組件基板1 3之至少一方之 面θ又置夕個半導體晶片時，則在相同之平面面積可以安裝 更多個之半導體晶片5。 另外’經由使發送共同信號之被設在組件基板1 3之2個 半導體晶片11，1 2之接腳結合成為1個，則全體之接腳9之 數目可以減少。 另外’經由將半導體晶片丨丨，丨2直接設置在組件基板丄3 之表面和背面，則可以不需要上述之習知技術之安裝構造 (白知技術之安裝構造是只在組件基板之一方之面設置半 導體晶片’將該組件基板設置在設有插座等之安裝基 板）’所以零件數目可以減少，和製造工程可以簡化。 (實施形態2) 下面將使用圖9至圖1 2用來說明本發明之實施形態2之半 導體裝置。本實施形態之半導體裝置如圖9至圖1 2所示， 在貫施形態1所說明之半導體裝置中，更設有接地用平板 22 ’分別從安裝有接腳9之側端面以外之3個側端面突出。 另外’在從組件基板1 3之左右之側端面突出之接地用平板 2 2之下$而和安裝基板3之間，設有指定之間隙e。經由設置 此種間隙e，在該部份可以插入組件基板之端部，該組件 基板只在一方之主表面設置半導體晶片，組件基板之另外 一方之主表面被設置成朝向安裝基板如同上述之習知技術1_1 Page 9 89111833.ptd 490836 V. Description of the invention (6) The semiconductor wafers 11, 12 can be used for high-density mounting of semiconductor devices. In addition, as in the manner of the semiconductor wafers 16, 17, 18 and the semiconductor K shown in FIG. 6 to FIG. 8 being set at 19, 20, 21, if a semiconductor θ is placed on at least one side of the module substrate 13 In the case of a wafer, more semiconductor wafers 5 can be mounted on the same plane area. In addition, the number of pins 9 of the whole can be reduced by combining the two pins of the semiconductor wafers 11 and 12 provided on the module substrate 13 to send a common signal. In addition, by mounting the semiconductor wafers 丨 丨, 丨 2 directly on the front and back of the module substrate 丄 3, the mounting structure of the conventional technology described above is not required (the mounting structure of the Baizhi technology is only on one side of the module substrate). The semiconductor wafer is installed on the surface 'the component substrate is set on a mounting substrate provided with a socket, etc.), so the number of parts can be reduced, and the manufacturing process can be simplified. (Embodiment 2) Next, a semiconductor device according to Embodiment 2 of the present invention will be described with reference to Figs. 9 to 12. The semiconductor device according to this embodiment is shown in FIGS. 9 to 12. In the semiconductor device described in the first embodiment, three ground plates 22 ′ are further provided from the end surface of the side on which the pin 9 is mounted. The side end faces protrude. In addition, a specified gap e is provided between the grounding flat plate 22 protruding from the left and right side end surfaces of the module substrate 13 and the mounting substrate 3. By providing such a gap e, an end of a module substrate can be inserted in this part. The module substrate is provided with a semiconductor wafer only on one major surface, and the other major surface of the module substrate is oriented toward the mounting substrate as described above. Know-how

89111833.ptd 第10頁 49083689111833.ptd Page 10 490836

所示。 利用此種構造，在半導體晶片丨丨，丨2内產生之熱，可以 一^利^用接地板22進〇另外，將接地用平板22引出 到外部’經由使接地面積擴大，禾一^ 點，可以減低在半導體裝置之内部和外部發生之雜訊之影 另外，如同上述之習知技術所示之組件基板丨〇 8，使只 在一方之主表面設置半導體晶片1〇5之組件基板1〇1，1〇2， 以其另外一方之主表面接合安裝基板，設置成使端部插入 到上述之間隙e之方式，所以在在相同之安裝基板面積可 以女裝更多個之半導體晶片。其結果是平面看到之半導俨 裝置之安裝密度可以更進一步的提高。 κ (實施形態3) 下面將使用圖1 3用來說明本發明之實施形態3之半導俨 裝置。本實施形態之半導體裝置如圖13所示，其構造與肢每 施形態1所示之半導體裝置大致相同，但是其不同部份/ 組件基板24, 25更具有接地用接腳26位於安裝到安裝基= δ亥組件基板2 4，2 5被安裝成為大致互相平行，和對安事 基板3大致垂直。另外，一方之組件基板24之安裝在安g 基板3之侧之相反側之接地用接腳26之全部，經由接地2 平板23，電連接到另外一方之組件基板25之安裝在安裝美 板3之側端面之相反側之侧端面之接地用接腳26之全部衣。土 利用此種構造，可以使用上述之接地用平板2 3作為散熱 490^36 五、發明說明（8) 基板，和經由使接地 m ^ ^ μ ^ ±面和擴大利用其可低阻抗化之功能， 響。 千^脰衣置之内部和外部產生之雜訊之影 ΐί Γ/,""##"26 ^^ 牧ΐϋ州十板23連接，但是亦可 处 雖然上面ρ付， 抹用其他之怨樣。 返之說明只作夷 a丰^明，但宜瞭解者上 精神和範圍只由所附之申往直剎r:制本發明，本發明之 [元件魄喵七上 曱叫專利乾圍限制。 ^ 1干編唬之說明] g 安裝基板 !, 接腳 11,19 13 半導體晶片 9〇 組件基板 22, 2卩 2^ 接地用平板 接地用接腳 ΦAs shown. With this structure, the heat generated in the semiconductor wafers 丨 丨, 丨 2 can be taken in by the grounding plate 22. In addition, the grounding flat plate 22 is led out to the outside. It is possible to reduce the influence of noise occurring inside and outside the semiconductor device. In addition, as shown in the above-mentioned conventional technology of the component substrate 丨 〇8, the component substrate 1 of the semiconductor wafer 105 is provided on only one main surface 〇1, 〇2, the mounting substrate is bonded to the other main surface, and the end portion is inserted into the above-mentioned gap e, so that more semiconductor wafers can be worn in the same mounting substrate area. As a result, the mounting density of the semiconducting device can be further improved. κ (Embodiment 3) Next, a semiconductor device according to Embodiment 3 of the present invention will be described with reference to Figs. The semiconductor device of this embodiment is shown in FIG. 13, and its structure is substantially the same as that of the semiconductor device shown in Embodiment 1. However, the different parts / module substrates 24 and 25 have grounding pins 26 and are installed and mounted. The base = δ 组件 module substrates 2 4 and 2 5 are mounted so as to be substantially parallel to each other and substantially perpendicular to the safety substrate 3. In addition, all of the grounding pins 26 of one of the component substrates 24 mounted on the opposite side of the Angular substrate 3 are electrically connected to the other component substrate 25 via the grounding 2 flat plate 23 and are mounted on the mounting board 3 All of the ground pins 26 on the opposite side of the side end surface. With this structure of earth, the above-mentioned grounding plate 2 3 can be used as a heat sink 490 ^ 36 V. Description of the invention (8) The substrate and the function of reducing the impedance by expanding the ground m ^ ^ μ ^ ± plane and using it , ring. The image of the noise generated by the inside and outside of the Qianyi place 脰 Γ /, " "## " 26 ^^ 牧 ΐϋ 州 十 板 23 连接, but it can also be used. Although it can be paid above, use other Resentment. The description here is only for reference. However, it should be understood that the spirit and scope of the application should only be applied to the direct brake. The invention of this invention, [the element of the soul of the cat seven on the howling patent limit is limited. ^ 1 Description of dry editing] g Mounting substrate !, Pins 11, 19 13 Semiconductor wafer 90. Module substrate 22, 2 卩 2 ^ Grounding plate Grounding pin Φ

8911⑻3.ptd 隨臟_丨iii8911⑻3.ptd with dirty_ 丨 iii

第12頁 490836 圖式簡單說明 —--- 圖1疋剖面圖’用來表示本發明之實施形態1之半導體裝 置之在組件基板之第1主表面和第2主表面雙方設有半導體 晶片之狀態。 圖2表不本發明之實施形態丨之半導體裝置之設有半導體 晶片之第1主表面。 圖3表不本發明之貫施形態丨之半導體裝置之設有半導體 晶片之第2主表面。 圖4疋斜視圖’用來表示本發明之實施形態1之半導體裝 置之將組件基板安裝成對安裝基板垂直之狀態。 圖5是立面圖，用來表示本發明之實施形態工之半導體裝 置之在組件基板之第1主表面和第2主表面之雙方設有半導 體晶片時之直立之狀態。 圖6表示本發明之實施形態丨之半導體裝置之在組件基板 之第1主表面設有多個半導體晶片之狀態。 圖7是立面圖’用來表示本發明之實施形態1之半導體裝 置之在組件基板之第1主表面和第2主表面設有多個半導體 晶片之狀恶。 圖8表示本發明之實施形態1之半導體裝置之在組件基板 之第2主表面設有多個半導體晶片之狀態。 圖9是剖面圖，用來表示本發明之實施形態2之半導體裝 置之在組件基板之側端面設有接地用平板之狀態。 圖1 0表示本發明之實施形態2之半導體裝置之在組件基 板之側端面設有接地用平板之狀態之第1主表面。 圖11是立面圖，用來表示本發明之實施形態2之半導體Page 490836 Brief description of drawings ----- Figure 1 (Cross-section view) is used to show a semiconductor device according to Embodiment 1 of the present invention in which a semiconductor wafer is provided on both the first main surface and the second main surface of a module substrate status. Fig. 2 shows a first main surface of a semiconductor device provided with a semiconductor wafer according to an embodiment of the present invention. Fig. 3 shows a second main surface of a semiconductor device provided with a semiconductor wafer according to the embodiment of the present invention. Fig. 4 is a perspective view 'showing a state in which the module substrate is mounted perpendicular to the mounting substrate in the semiconductor device according to the first embodiment of the present invention. Fig. 5 is an elevational view showing an upright state when a semiconductor wafer is provided with semiconductor wafers on both the first main surface and the second main surface of the module substrate according to the embodiment of the present invention. FIG. 6 shows a state where a plurality of semiconductor wafers are provided on a first main surface of a module substrate of a semiconductor device according to an embodiment of the present invention. Fig. 7 is an elevational view 'showing the state of the semiconductor device according to the first embodiment of the present invention in which a plurality of semiconductor wafers are provided on the first main surface and the second main surface of the module substrate. Fig. 8 shows a state where a plurality of semiconductor wafers are provided on the second main surface of the module substrate of the semiconductor device according to the first embodiment of the present invention. Fig. 9 is a cross-sectional view showing a state in which a ground plane is provided on a side end surface of a module substrate in a semiconductor device according to a second embodiment of the present invention. Fig. 10 shows a first main surface of a semiconductor device according to a second embodiment of the present invention in which a flat plate for grounding is provided on a side end surface of a module substrate. FIG. 11 is an elevation view showing a semiconductor according to a second embodiment of the present invention

89111833.ptd 第13頁 490836 圖式簡單說明 裝置之在 板直立之 圖12表 圖13表 平板電連 地用之接 圖1 4表 表面設置 圖15表 之習知之 圖16表 之習知之 圖1 7表 之多個半 接m 一平 示本發明之實施 接2個組件基板（ 腳之狀態。 示習知之半導體 半導體晶片之狀 示只在組件基板 半導體裝置之設 示只在組件基板 半導體裝置之未 示在習知之半導 導體晶片之狀態 組件基板之側端面設有接地用平板時，使組件基 狀態。 不本發明之實施形態2之半導體裝置之在組件基 第 2 面^ 形態3之半導體裝置之以接地用 被安裝成對安裝基板垂直）之接 裝置之只在組件基板之一方之主 態之剖面。 之一方之主表面設有半導體晶片 置有半導體晶片之面。 之一^方之主表面設有半導體晶片 設有半導體晶片之面。 體裝置中，設有對安裝基板平行89111833.ptd Page 13 490836 Schematic description of the device upright on the board Figure 12 Table 13 Table for flat ground connection Figure 1 4 Table surface setup Figure 15 Table of known Figure 16 Table of known Figure 1 The multiple halves of the table 7 indicate the state of the implementation of the present invention to connect two component substrates (pins. The state of the conventional semiconductor semiconductor wafer is shown only on the component substrate and the semiconductor device is shown only on the component substrate. The state of the conventional semiconductor chip is shown in the state of a semiconductor substrate. When a flat plate for grounding is provided on the side end surface of a module substrate, the module is in a base state. The grounding device is installed perpendicular to the mounting substrate, and the main device has only one cross section of the component substrate. One of the main surfaces is provided with a semiconductor wafer, and a surface on which the semiconductor wafer is placed. One of the squares is provided with a semiconductor wafer on the main surface thereof. Body device, parallel to the mounting substrate

89]11833.ptd 第14頁89] 11833.ptd Page 14

Claims (1)

1 · 一種半導體裝置，其特徵是具備有： 組件基板（13)，具有互為表面和背面之第1和第2主 面’和側端面； 又 —寧厂厂^上遲1^丁石^第〜 面；和 口主表 電連接用接腳（9 )，被設在上述之侧端面，以盎 1 j< 々>* /、，-r· 弟丄和弟2主表面大致平行之方向延伸。 2 ·如申請專利範圍第1項之半導體裝置，其中上述之 導體晶片（11，12)在上述之第1和第2主表面之至少“ 設置多個。 一方 3 ·如申請專利範圍第1項之半導體裝置，其 t ¥肢晶片（11，12)之接地用平板（ 22, 23 )，成為從上述侧 端面中之設有上述接腳（9 )之區域以外之指定區域突出 方式。 4·如申請專利範圍第3項之半導體裝置，其中在上述組 件基板（13)被安裝在安裝基板（3)之狀態，上述之接地用 平板（23) ’以在與上述安裝基板（3)面對之面和上述安裝 基板（3)之間殘留有可以插入之另外一個半導體裝置之間 隙之態樣，從上述組件基板（1 3 )之上述側端面突出。 5 ·如申請專利範圍第1項之半導體裝置，其中在上述侧 端面中之設有上述接腳（9 )之區域以外之區域，設有上述 半導體晶片（11，1 2)之接地用接腳（2 6)。 6· —種半導體裝置之安裝構造，在安裝基板之主面上’ 安裝多個包含有組件基板（1 3)之半導體裝置，該組件基板1. A semiconductor device, comprising: a module substrate (13) having first and second main surfaces and side end surfaces that are a front surface and a back surface of each other; and-Ningchang Factory ^ 上 迟 1 ^ 丁 石 ^ The first ~ surface; the pin (9) for electrical connection with the main meter is provided on the above-mentioned side end surface, and the main surface of -r · Di 丄 and Di 2 is approximately parallel Direction. 2 · If the semiconductor device according to the scope of the patent application item 1, wherein the above-mentioned conductor wafer (11, 12) is provided at least "at least" on the first and second main surfaces. In the semiconductor device, the ground plate (22, 23) of the limb chip (11, 12) is protruded from a designated area other than the area where the pins (9) are provided on the side end face. 4 · For example, in the semiconductor device of claim 3, in the state where the component substrate (13) is mounted on the mounting substrate (3), the grounding flat plate (23) 'faces the mounting substrate (3). The gap between the surface of the mounting substrate (3) and another semiconductor device that can be inserted remains, and it protrudes from the side end surface of the component substrate (1 3). A semiconductor device in which a ground pin (2 6) of the semiconductor wafer (11, 12) is provided in a region other than a region where the pin (9) is provided in the side end surface. 6 · —Semiconductor Installation structure of the device, 'Is mounted on the main surface a plurality of board mounting assembly comprising a substrate (13) of the semiconductor device, the substrate assembly 89111833.ptd 第15頁 490836 六、申請專利範圍 〇3)具有互為表面和背面之第1和第2主表 上述之第1和第2主表面對該主面成為垂直之丄和側端面’ 是： 農之方式；其特徵 半導體晶片（11，12)，被設在上述之第1釦 面；和 3乐2之各主表 電連接用之接腳（9)，被設在上述之側端品 之第1和第2主表面大致平行之方向延伸； ，以與上述 在上述多個半導體裝置之各個，於上述 上述接腳⑻之區域以外之區域，設有上述半而導體中曰曰之設有 (11，1 2 )之接地用接腳（2 6); 月丑日日 在上述多個半導體裝置之上述接地用接腳（2 6 )之間，以 接地用平板（2 3 )進行電連接。89111833.ptd Page 15 490836 6. Scope of patent application 03) The first and second main tables with mutually facing surfaces and back surfaces The above-mentioned first and second main surfaces become perpendicular to the main surface and side end surfaces' It is: agricultural method; its characteristic semiconductor chip (11, 12) is set on the first buckle surface; and the pin (9) for electrical connection of each main watch of 3 Le 2 is set on the above side The first and second main surfaces of the end product extend in a direction substantially parallel to each other, and the semiconductor device is provided with a semi-conductor in a region other than the region of the pin ridges as described above in each of the plurality of semiconductor devices. (11, 1 2) is provided with a grounding pin (2 6); the moon and the sun are between the above-mentioned grounding pins (2 6) of the plurality of semiconductor devices, and a grounding plate (2 3) Make electrical connections.
TW089111833A 1999-06-24 2000-06-16 Semiconductor device and mounting structure thereof TW490836B (en)

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US8053891B2 (en) * 2008-06-30 2011-11-08 Alpha And Omega Semiconductor Incorporated Standing chip scale package
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