JPS6188547A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6188547A
JPS6188547A JP59209237A JP20923784A JPS6188547A JP S6188547 A JPS6188547 A JP S6188547A JP 59209237 A JP59209237 A JP 59209237A JP 20923784 A JP20923784 A JP 20923784A JP S6188547 A JPS6188547 A JP S6188547A
Authority
JP
Japan
Prior art keywords
supporter
chip
motherboard
connection terminal
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59209237A
Other languages
Japanese (ja)
Inventor
Satoru Tanizawa
谷澤　哲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59209237A priority Critical patent/JPS6188547A/en
Publication of JPS6188547A publication Critical patent/JPS6188547A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To dissipate heat excellently, and to increase density by a method wherein a semiconductor chip is mounted onto one surface of a supporter, an electrode for the chip is connected to an inserting terminal fitted to the lower end surface of the supporter, a plurality of units manufactured in this manner are studded onto a mother board at regular intervals, and the inserting terminals are connected to receiving terminals for the board. CONSTITUTION:A semiconductor chip 2 is fixed onto one surface of a supporter 1, pads 3 fitted to the chip 2 are connected to first connecting terminals 4 as inserting terminals formed to the lower end surface of the supporter 1, and a plurality of units manufactured in this manner are studded onto a mother board 6 at regular intervals. The first connecting terminals 4 are connected to second connecting terminals 7 as receiving terminals set up to the mother board 6, thus manufacturing a multi-chip LSI. Accordingly, high-density constitution can be shaped while heat dissipation and repair are improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多数のチップで構成さる大規模集積回路（ＬＳ
Ｉ）の構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention applies to large-scale integrated circuits (LS) consisting of a large number of chips.
Regarding the structure of I).

集積回路（ＩＣ）チップを多数実装する際、平面より立
体実装の方が密度が上がることは勿論であるが、しかし
このときは、 ｉ、チップの配線の仕方、 ｉｉ　、放熱の仕方、 ｉｉｉ　、組立の難易度 等を考慮する必要がある。When mounting a large number of integrated circuit (IC) chips, it goes without saying that the density will be higher in three-dimensional mounting than in two-dimensional mounting, but in this case, there are several issues: i. How the chips are wired; ii. How heat is dissipated; iii. It is necessary to consider the difficulty of assembly, etc.

近年ＬＳＩの多機能化、高性能化にともない、多チップ
ＬＳＩが検討されるようになり、上記の留意点を考慮し
た構成が望まれようになった。In recent years, as LSIs have become more multi-functional and have higher performance, multi-chip LSIs have been considered, and a configuration that takes the above points into consideration has become desirable.

〔従来の技術〕[Conventional technology]

多チップＬＳＩの従来例として、半導体ウェハ上に多数
のチップとそれらを結ぶハスラインと各信号を制御する
制御回路とを設けた、所謂ウェハインテグレーション、
または機能ウェハと呼ばれるものもあるが、ここでは単
独のチップを組み合わせて構成したものに限定するこも
にする。A conventional example of multi-chip LSI is so-called wafer integration, in which a large number of chips, a lotus line connecting them, and a control circuit for controlling each signal are provided on a semiconductor wafer.
There are also called functional wafers, but here we will limit them to those constructed by combining individual chips.

この場合は熱伝淳率の大きい材料よりなる金属、または
セラミック等の基板上にチップをダイボンディングして
取り付け、チップと基板上の接続端子間はワイヤボンデ
ィングして、結線を行う平面実装であった。In this case, the chip is mounted on a metal or ceramic substrate made of a material with a high thermal conductivity by die bonding, and the connections are made by wire bonding between the chip and the connection terminals on the substrate. Ta.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来例による構造では平面実装のため、集積度が上がら
なかった。In the conventional structure, the degree of integration could not be increased because of flat mounting.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点の解決は、 （１）半導体チップをサポータ上に取り付け、該半導体
チップと該サポータの端面に設けられた第１の接続端子
とを結線してなるユニットを、マザーボードに略直角に
配置し、該マザーボード上に設けられた第２の接続端子
と前記第１の接続端子とを結線してなる本発明による半
導体装置、（２）半導体チップをサポータ上に取り付け
、該半導体チップと該サポータの端面に設けられた第１
の接続端子とを結線してなるユニットを、マザーボード
に略直角に配置し、該マザーボード上に設けられた第２
の接続端子と前記第１の接続端子とを結線し、かつ該ユ
ニットに略直角に光伝送路を組み込んだボードを配置し
てなる本発明による半導体装置、 により達成される。The solution to the above problem is as follows: (1) A unit formed by mounting a semiconductor chip on a supporter and connecting the semiconductor chip to a first connection terminal provided on the end face of the supporter is arranged approximately at right angles to the motherboard. and a semiconductor device according to the present invention, in which a second connection terminal provided on the motherboard is connected to the first connection terminal, (2) a semiconductor chip is mounted on a supporter, and the semiconductor chip and the supporter are connected together. The first plate provided on the end face of
A unit formed by connecting the connecting terminals is arranged approximately perpendicularly to the motherboard, and
This is achieved by the semiconductor device according to the present invention, in which a board is arranged in which the connection terminal of the unit is connected to the first connection terminal, and a board incorporating an optical transmission line is arranged substantially perpendicularly to the unit.

〔作用〕[Effect]

本発明によれば、チップを何層も重ねて立体的に配置で
きるため、集積度が向上する。According to the present invention, the degree of integration is improved because chips can be stacked in multiple layers and arranged three-dimensionally.

またチップをグイボンディングするサポータと、サポー
タを取り付けるマザーボードを熱伝導度の大きい金属や
セラミック等の材料を用い、かつサポータを間隔をおい
て平行に並べると、サポータに平行な方向に通風して冷
却できる。In addition, if the supporter to which the chip is bonded and the motherboard to which the supporter is attached are made of materials with high thermal conductivity, such as metal or ceramic, and if the supports are arranged parallel to each other at intervals, air will circulate in the direction parallel to the supporter and cool it down. can.

さらに光入出力（Ｉ　１０）素子をもつＩＣの場合は、
ユニットとマザーボードの各々に略直角に光伝送路を組
み込んだボードを配置すると、チップの側面より出る発
光素子からの信号を光伝送路に受けることができる。こ
の場合電源、接地線、光以外の信号線はユニットとマザ
ーボード間を結線して接続する。Furthermore, in the case of an IC with an optical input/output (I10) element,
By arranging a board incorporating an optical transmission path approximately at right angles to each of the unit and the motherboard, the signal from the light emitting element emitted from the side surface of the chip can be received by the optical transmission path. In this case, the power supply, grounding wire, and signal wires other than light are connected by wiring between the unit and the motherboard.

〔実施例〕〔Example〕

第１図（ａｌ、　（ｂｌはそれぞれ第１の発明によるユ
ニットとＬＳＩの斜視図である。FIGS. 1A and 1B are perspective views of a unit and an LSI according to the first invention, respectively.

第１図（ａｌにおいて、熱伝導率の大きいセラミックで
できたサポータ１の上にチップ２をダイボンディングし
、チップ２の周辺に形成されたパッド（接続端子）３と
、サポータ１の相対する２辺の端面にメタライズにより
、マザーボードと接続される第１の接続端子（挿入端子
）４を形成し、パッド３と第１の接続端子４をワイヤ５
によりボンディングして結線し、ユニットを構成する。In FIG. 1 (al), a chip 2 is die-bonded onto a supporter 1 made of ceramic with high thermal conductivity, and pads (connection terminals) 3 formed around the chip 2 and opposing 2 A first connection terminal (insertion terminal) 4 to be connected to the motherboard is formed by metallization on the end surface of the side, and a wire 5 is connected between the pad 3 and the first connection terminal 4.
to form a unit by bonding and connecting the wires.

第１図（ｂｌにおいて、マザーボード６に設けられた第
２の接続端子（受は端子）７に、前記サポータ１の第１
の接？ＦｊＥ端子４を挿入し、固定する。In FIG. 1 (bl), the second connection terminal (receptacle is a terminal) 7 provided on the motherboard 6 is connected to the first connection terminal of the supporter 1.
The contact? Insert and secure FjE terminal 4.

図はマザーボード６は１枚しか示されていないが、前記
サポータ１の対辺に接続するもう１枚のマザーボードを
取り付ける。Although only one motherboard 6 is shown in the figure, another motherboard is attached to the opposite side of the supporter 1.

このように構成されたＬＳＩは、矢印の方向に通風して
冷却する。The LSI configured in this manner is cooled by ventilation in the direction of the arrow.

第２図（ａｌ、　（ｂ）はそれぞれ第２の発明によるユ
ニットとＬＳＩの斜視図である。FIGS. 2A and 2B are perspective views of a unit and an LSI according to the second invention, respectively.

第２図（ａ）において、熱伝導率の大きいセラミックで
できたサポータｌの上にチップ２をダイボンディングし
、チップ２の周辺に形成されたパッド３と、サポータ１
の相対する２辺の端面にメタライズにより、マザーボー
ドに接続する第１の接続端子（挿入端子）４を形成し、
パッド３と第１の接続端子４をワイヤ５によりボンディ
ングして結線して、ユニットを構成する。In FIG. 2(a), the chip 2 is die-bonded onto the supporter l made of ceramic with high thermal conductivity, and the pad 3 formed around the chip 2 and the supporter 1
A first connection terminal (insertion terminal) 4 to be connected to the motherboard is formed by metallization on the end faces of two opposing sides,
The pad 3 and the first connection terminal 4 are bonded and connected by a wire 5 to form a unit.

チップの側面に露出する発光素子の活性層８より、信号
光が出射される。Signal light is emitted from the active layer 8 of the light emitting element exposed on the side surface of the chip.

第２図（ｂｌにおいて、マザーボード６に設けられた第
２の接続端子（受は端子）７に、前記サポータ１の第１
の接続端子４を挿入し、固定する。In FIG. 2 (bl), the second connection terminal (receiver is the terminal) provided on the motherboard 6 is connected to the first connection terminal of the supporter 1.
Insert and secure the connecting terminal 4.

つぎに受光部９と光伝送路１０を組み込んだボード１）
を、′サポータ１とマザーボード６の各々に直角に設け
る。Next, board 1) incorporating the light receiving section 9 and the optical transmission line 10
are provided at right angles to each of the supporter 1 and the motherboard 6.

図はボード１）は１枚しか示されていないが、前記サポ
ータ１がマザーボード６に接続する辺の対辺に配置する
もう１枚のボードを取り付ける。Although only one board 1) is shown in the figure, another board is attached to the side opposite to the side where the supporter 1 connects to the motherboard 6.

このように構成されたＬＳＩは、ボード１）を間隔をお
いて配置できるため、矢印の方向に通風して冷却できる
。In the LSI configured in this way, since the boards 1) can be arranged at intervals, they can be cooled by ventilation in the direction of the arrow.

第３図は光信号の授受を模式的に示すＬＳＩの断面図で
ある。FIG. 3 is a cross-sectional view of an LSI schematically showing transmission and reception of optical signals.

図において、チップ２の側面に形成された発光素子８よ
り出射された光は空間を経由してボード１）に設けられ
た受光部９で受け、光伝送路１０により伝送される。In the figure, light emitted from a light emitting element 8 formed on the side surface of a chip 2 passes through space, is received by a light receiving section 9 provided on a board 1), and is transmitted through an optical transmission line 10.

実施例ではチップには発光素子を、ボードには受光部の
みを設けたが、チップとボードそれぞれに発、受光素子
を設けて信号のやりとりを行ってもよい。In the embodiment, only a light emitting element was provided on the chip and only a light receiving section was provided on the board, but a light emitting element and a light receiving element may be provided on each of the chip and the board to exchange signals.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように本発明によれば、高密度構成
が可能で、放熱が良好で、補修が容易な多チツプ構成の
ＬＳＩが得られる。As described above in detail, according to the present invention, it is possible to obtain an LSI with a multi-chip structure that allows for a high-density structure, has good heat dissipation, and is easy to repair.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａｌ、　（ｂ）はそれぞれ第１の発明によるユ
ニットとＬＳＩの斜視図、 第２図（ａｌ、　（ｂｌはそれぞれ第２の発明によるユ
ニットとＬＳＩの斜視図、 第３図は光信号の授受を模式的に示すＬＳＩの断面図で
ある。 図において、 １はサポータ、　　　　２はチップ、 ３はパッド、 ４は第１の接続端子（挿入端子） ５はワイヤ、　　　　　６はマザーボード、７は第２の
接続端子（受は端子）、 ８は発光素子、　　　９は受光部、 １０は光伝送路、　　　１）はボード を示す。FIGS. 1(al) and (b) are perspective views of a unit and an LSI according to the first invention, FIGS. 2(al and bl) are perspective views of a unit and an LSI according to the second invention, respectively, and FIG. It is a cross-sectional view of an LSI schematically showing the transmission and reception of signals. In the figure, 1 is a supporter, 2 is a chip, 3 is a pad, 4 is a first connection terminal (insertion terminal), 5 is a wire, 6 is a motherboard, 7 8 is a light emitting element, 9 is a light receiving section, 10 is an optical transmission line, and 1) is a board.

Claims (2)

【特許請求の範囲】[Claims] （１）半導体チップをサポータ上に取り付け、該半導体
チップと該サポータの端面に設けられた第１の接続端子
とを結線してなるユニットを、マザーボードに略直角に
配置し、該マザーボード上に設けられた第２の接続端子
と前記第１の接続端子とを結線してなることを特徴とす
る半導体装置。(1) A unit formed by mounting a semiconductor chip on a supporter and connecting the semiconductor chip to a first connection terminal provided on the end face of the supporter is arranged approximately at right angles to the motherboard, and the unit is mounted on the motherboard. A semiconductor device characterized in that the second connection terminal and the first connection terminal are connected to each other. （２）半導体チップをサポータ上に取り付け、該半導体
チップと該サポータの端面に設けられた第１の接続端子
とを結線してなるユニットを、マザーボードに略直角に
配置し、該マザーボード上に設けられた第２の接続端子
と前記第１の接続端子とを結線し、かつ該ユニットに略
直角に光伝送路を組み込んだボードを配置してなること
を特徴とする半導体装置。(2) A unit formed by mounting a semiconductor chip on a supporter and connecting the semiconductor chip to a first connection terminal provided on the end face of the supporter is arranged approximately at right angles to the motherboard, and is mounted on the motherboard. What is claimed is: 1. A semiconductor device comprising: a board which connects a second connecting terminal and a first connecting terminal, and has an optical transmission line installed substantially perpendicularly to the unit;
JP59209237A 1984-10-05 1984-10-05 Semiconductor device Pending JPS6188547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59209237A JPS6188547A (en) 1984-10-05 1984-10-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59209237A JPS6188547A (en) 1984-10-05 1984-10-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6188547A true JPS6188547A (en) 1986-05-06

Family

ID=16569629

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59209237A Pending JPS6188547A (en) 1984-10-05 1984-10-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6188547A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63111636A (en) * 1986-10-29 1988-05-16 Mitsubishi Electric Corp Manufacture of semiconductor device
EP0340241A1 (en) * 1987-01-05 1989-11-08 Irvine Sensors Corp High density electronic package comprising stacked sub-modules.
JPH01283939A (en) * 1988-05-11 1989-11-15 Hitachi Ltd Semiconductor chip and substrate and electronic apparatus constituted with these parts
EP0354708A2 (en) * 1988-08-08 1990-02-14 Texas Instruments Incorporated General three dimensional packaging
US5057907A (en) * 1990-06-11 1991-10-15 National Semiconductor Corp. Method and structure for forming vertical semiconductor interconnection
US5146308A (en) * 1990-10-05 1992-09-08 Micron Technology, Inc. Semiconductor package utilizing edge connected semiconductor dice
EP0575806A3 (en) * 1992-06-24 1994-03-16 Ibm
US5313097A (en) * 1992-11-16 1994-05-17 International Business Machines, Corp. High density memory module
WO1995005005A1 (en) * 1993-08-05 1995-02-16 Honeywell Inc. Three dimensional package for monolithic microwave/millimeterwave integrated circuits
WO2005101490A3 (en) * 2004-04-19 2006-04-13 Siemens Ag Component that is situated on a cooling fin

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63111636A (en) * 1986-10-29 1988-05-16 Mitsubishi Electric Corp Manufacture of semiconductor device
EP0340241A1 (en) * 1987-01-05 1989-11-08 Irvine Sensors Corp High density electronic package comprising stacked sub-modules.
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