TW478167B - Halo structure for use in reduced feature size transistors - Google Patents

Halo structure for use in reduced feature size transistors Download PDF

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Publication number
TW478167B
TW478167B TW89123342A TW89123342A TW478167B TW 478167 B TW478167 B TW 478167B TW 89123342 A TW89123342 A TW 89123342A TW 89123342 A TW89123342 A TW 89123342A TW 478167 B TW478167 B TW 478167B
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patent application
item
gate
scope
integrated circuit
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TW89123342A
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Chinese (zh)
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Seunmuu Choi
Timothy Edward Doyle
Troy A Giniekki
Amar Ma Hamad
Pai H Yih
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Lucent Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A process is used to selectively implant dopants in reduced feature size integrated circuits while reducing shadowing. Illustratively, the present invention may be used to form a halo implant in a reduced feature size field effect transistor.

Description

五、發明說明（ 經濟部智慧財產局員工消費合作社印製 ， 憂_明範疇 本發明有關-種背光結構及其製造方法。 登明背景 田才貝月旦電路中閉長度減低時，Μ流子效應T以在金屬 氧化物半導體場效應電晶體_SFET)中產生不可接受的性 能特性。-種克服熱載流子效應的方法爲，藉由使用此微 _fe(LDD)結構。在一 LDD結構中，源極_有漸變 式的摻雜分佈。在最接近通道的源極與汲極區中，摻雜較 •低」較遠處q參雜較高。㉟些微摻雜之源極與没極 區作用來降低接近源極與汲極的通道區的電場。該降低之 吃％，藉由降低熱載流子射（injecti〇n)入覆蓋於通道區之上 閘氧化物的方式，改善低限穩定性。 另一從縮減特徵大小所產生的問題是短通道效應，一般 熟稱爲穿孔（punch-through)。穿孔爲由源極與汲極耗盡區合 併而產生的現象。當通道長度縮減時，·源極與汲極耗盡2 邊緣便接近了些。當基層中通道長度降低至大約爲該兩接 面耗盡見度的和時，該等耗盡區合併。此耗盡區之合併可 以造成載流子穿孔。於是可以了解的是，穿孔使得電荷控 制困難，並可能使電晶體之功能性打些折扣。 一個降低穿孔的技術是，有選擇地在於源極與汲極耗盡 •區之鄰接區反摻雜（counter-dope)。此方式是使用正交射入 (normal incidence)基層的方式覆蓋離子植入捧雜離子，並 且成功地降低了穿孔的問題。例如，在一 N通道金屬氧化物 -半導體（NMOS)裝置中，p-掺雜劑被離子植入於^通道中， -4- 本紙張尺度適用中國國家標準(CNS)A4規格（21〇xi公爱） ~ 一 ----— (請先M讀背面之注意事V； 裝--- Γ填寫本頁) 訂· -線· ^/^167 A7 ----------R7__ 五、發明說明（2 ) 然而，該覆蓋離子植入造成了通道的摻雜，至一不可接受 的範圍。此舉造成低限電壓的增加、減低載流子在通道中 的遷移率、以及驅動電流的減少。 因爲用來降低穿孔效應所使用之覆蓋離子植入可能的缺 點，圖5中所示的結構的研究近來較多。背光離子植入5〇3 形成於些微摻雜源極與汲極區（分別爲5〇1與5〇2)的内壁上。 此2使用一大角度離子植入，正常大約與基層法線（n〇rmai) 相父30度或30度以上。在形成較重（heavilyy#雜的源極與汲 極區（分別爲506與507)時，襯墊（spacer)作爲光罩使用。該 襯墊505形成於閘結構5〇8 (包含一閘氧化物5〇9)兩侧的任一 侧。此種背光離子植入選擇放置的方式，允許穿孔效應縮 減’並避免通道的過度摻雜。 雖然圖5中所示的結構明顯地較覆蓋離子植入好處爲多， 裝置定標（scaling)要求更進一步的縮減間距、或兩閘間的間 距。縮減間距會造成鄰接特徵（如閘結構）可能阻礙離子植入 ，而典法達到在基層中欲摻雜的位置。此阻礙效應被稱爲 遮蔽現象，可在觀看圖6後明瞭。 4爹考圖6心具有縮減間距的鄰接閘結構6〇3。閘間的間 距（以兩相同閘的間距” p ”表示），被縮減來成就所欲之積體 (integration)。如當閘長度（在圖6中以，，w，，表示）約在〇」6微 米4瑨時，pi値約在0·24微米之譜。該等特徵高度（以"h，· 表示）如閘結構603，大約在〇.5微米之譜。如此，因爲在特 徵間的間距、與特徵相對高度縮減，以相對於法線較大的 角度離子植入601，造成602區被鄰近之多晶矽閘6〇3遮蔽的 -5 · 氏張尺度適用巾@ @豕標準（CNS)A4規格（21G X 297公复1 --------— in —---.------裝·II (請先閱讀背面之注意事填寫本頁) 訂 -線· 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 見象‘敗現象造成在遮蔽區6〇2背尖 .^ ^ . 先的離子植入效率不彰 ，其降低穿孔的能力便減小了。 4知 如此，所需要的是，在此 二被朽_及極結構中製作背光離 子植入的技術，能有效地減少穿孔， ,r 而不降低在縮減特徵 大小氣日曰骨豆結構中裝置的性能。 發明概述 、本發明有關-種使用於積體電路中的背光結構及其製作 之方法。 根據本發明之一特性，於 〜 、 9上形成一個突出的特徵。 以-大約與基層正交的低射入角來離子植入。該離子植入 步驟並不會在突出特徵之下的基層某—區域注人摻雜劑。 本發明避免了縮減特徵大小積體電路中之遮蔽效應。 根據本發明的另一特性，一個具有長度約在〇 25微米之譜 =更低的突出特徵，佈置在基層±。基層的—部分換雜有 哭出特徵之下部份摻雜的掺雜劑的一部分。 圖式簡單説明^ 本發月最把夠由以下的説明並參考所附之圖來了解。要 強凋的疋，根據半導體工業的慣例，該變化的特徵並不一 足按比例來做圖示。事實上，該變化的特徵尺寸可以任意 增加或減少，用來讓説明更清楚。 -圖1爲本發明所示之背光離子植入的一具體實施範例橫剖 視圖。 圖2爲本發明所示以熱退火來做橫向擴散之一具體實施範 例橫剖視圖。 -6- (請先閱讀背面之注意事填寫本頁) 裝 ή^τ· -丨線· 478167 A7 ---_ 五、發明說明（4 ) 圖J爲本4明所不些微摻雜源極與沒極區之形成的一具體 實施範例橫剖視圖。 圖4爲本毛明所不具有背光區域之漸變式源極與没極區捧 雜分佈的一具體實施範例橫剖視圖。 圖5爲具有先㈤技藝之覆蓋離子植入電晶體的橫剖視圖。 圖6爲一先前技藝結構的橫剖視圖。 發明詳細説明 簡單地説，本發明有關些微摻雜汲極（ldd)結構及其製作 •方」去。在圖4所7F之具體實施範例中，一背光3〇3創造於一 金i氧化物半導體場效應電晶體（M〇SFE 丁）1〇〇中。用作示 範之用，該金屬氧化物半導體場效應電晶體（M〇SFET)有一 閘結構109，佈置於一通道1〇8之上。該背光示於3〇3處。一 小角度離子植入步驟用來形成該背光。接下來可以進行退 火步驟’於閘之下邵分擴散摻雜劑，直到2〇丨所示之點。該 冃光佈置於该通道與該些微摻雜之源極與汲極區（分別爲 404與40 1)之間。摻雜地較重之源極與没極區分別示於405 與402。泫小角度離子植入及退火步驟，允許在縮減特徵大 小、縮減間距裝置中背光的形成，同時也避免了遮蔽效應 及不能接受之通道的摻雜，如前所説明。爲了示範之故， 閘長度可以爲0.25微米或更短些，其與鄰接的閘結構間的 _間距爲0.3 5微米或更短些。 雖然具體實施範例中用的是N通道金屬氧化物半導體場效 應電晶體（NMOSFET)，然本發明可用於積體電路中的形成 (formed)選擇佈置的離子植入、任何爲了避免遮蔽現象之處 -7- 本紙尺度適用中國國豕標準（CNS)A4規袼（21〇 X 297公爱） ---- (請先閲讀背面5意事_填寫本ί ' .線 經濟部智慧財產局員工消費合作社印製V. Description of the invention (Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the scope of the present invention is related to a backlight structure and its manufacturing method. Deng Ming background Tian Caibei When the mid-close length of the circuit is reduced, the M-fluid effect T to produce unacceptable performance characteristics in metal oxide semiconductor field effect transistors (SFETs). A way to overcome the hot carrier effect is by using this micro_fe (LDD) structure. In an LDD structure, the source has a doped profile with a gradient. In the source and drain regions closest to the channel, the doping is “lower”, and the q-distance is higher at a distance. Some slightly doped source and dead regions act to reduce the electric field in the channel region close to the source and drain. This reduction in the percentage of improvement improves the stability of the lower limit by reducing the injection of hot carriers into the gate oxide covering the channel region. Another problem that arises from reducing the size of features is the short channel effect, commonly known as punch-through. Piercing is a phenomenon caused by the merging of the source and drain depletion regions. When the channel length is reduced, the source and drain depletion 2 edges are closer. When the channel length in the base layer is reduced to approximately the sum of the depletion visibility of the two interfaces, the depletion regions merge. Merging of this depletion region can cause carrier perforation. It can be understood that the perforation makes charge control difficult and may compromise the functionality of the transistor. One technique to reduce perforation is to selectively de-dope the adjacent regions of the source and drain. This method uses a normal incidence base layer to cover the ion implantation and to successfully reduce the problem of perforation. For example, in an N-channel metal oxide-semiconductor (NMOS) device, the p-dopant is ion-implanted into the ^ channel. -4- This paper size applies to the Chinese National Standard (CNS) A4 specification (21〇xi). Public love) ~ One ----— (please read the note V on the back; install --- Γ fill in this page) order ·-line · ^ / ^ 167 A7 ---------- R7__ 5. Description of the invention (2) However, the covering ion implantation caused doping of the channel to an unacceptable range. This results in an increase in the lower limit voltage, a decrease in the carrier mobility in the channel, and a decrease in the driving current. Because of the possible shortcomings of the covered ion implantation used to reduce the perforation effect, the structure shown in Figure 5 has been studied more recently. Backlight ion implantation 503 is formed on the inner walls of the slightly doped source and drain regions (501 and 502, respectively). This 2 uses a large-angle ion implantation, which is normally about 30 degrees or more relative to the base normal (n0rmai). When forming a heavilyy #heterous source and drain regions (506 and 507 respectively), a spacer is used as a photomask. The spacer 505 is formed in a gate structure 508 (including a gate oxide) Any of the two sides of the object 5009). This type of backlight ion implantation is selected to allow the reduction of the perforation effect and avoid excessive doping of the channel. Although the structure shown in Figure 5 is significantly more than the ion implantation There are many benefits. Device scaling requires a further reduction in the spacing, or the distance between two gates. Reducing the spacing will cause adjacent features (such as the gate structure) to hinder ion implantation. The position of the doping. This blocking effect is called the masking phenomenon, which can be understood after viewing Figure 6. Figure 6 shows the adjacent gate structure with a reduced spacing of 603. The gap between the gates (with the same gate spacing) "P" means), reduced to achieve the desired integration. For example, when the gate length (indicated by ,, w ,, in Figure 6) is about 0 "6 microns 4 瑨, pi 値 is about 0 · 24 micron spectrum. The characteristic height (indicated by " h, ·) For example, the gate structure 603 has a spectrum of about 0.5 micrometers. In this way, because the distance between features and the relative height of the features are reduced, ion implantation of 601 at a larger angle relative to the normal causes 602 to be adjacent to the polycrystalline silicon. Gate 6〇3 masked -5 · Applicable towel scale @ @ 豕 standard (CNS) A4 specification (21G X 297 public compound 1 --------— in —---.----- -Installation · II (Please read the notes on the back to fill in this page) Order-line · Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The phenomenon of failure caused the back tip of the 602 in the masked area. ^. The previous ion implantation efficiency was not good, and its ability to reduce perforation was reduced. 4 Knowing this, what is needed is that the two are dying. The technology of making a backlight ion implantation in a polar structure can effectively reduce perforation, and r without reducing the performance of the device in a reduced feature size gas-day bone bean structure. SUMMARY OF THE INVENTION The invention relates to a kind of integrated circuit used in integrated circuits Backlight structure and its manufacturing method. According to one characteristic of the present invention, in ~, 9 Form a prominent feature. Ion implantation at a low incidence angle-approximately orthogonal to the substrate. This ion implantation step does not inject dopants into a certain area of the substrate below the prominent feature. The invention avoids In order to reduce the shadowing effect in the feature size integrated circuit, according to another feature of the present invention, a prominent feature with a spectrum of about 0.25 microns in length = lower is placed on the base layer. Shows a part of the dopant doped under the feature. The diagram is briefly explained ^ This post is best understood from the following description and with reference to the attached drawings. To withstand the crickets, according to the conventions of the semiconductor industry The characteristics of this change are not fully scaled. In fact, the size of the feature can be increased or decreased arbitrarily to make the description clearer. -Figure 1 is a cross-sectional view of a specific embodiment of a backlight ion implantation shown in the present invention. Fig. 2 is a cross-sectional view of a specific embodiment of performing lateral diffusion by thermal annealing shown in the present invention. -6- (Please read the notes on the back first and fill in this page) Packing price ^ τ ·-丨 line · 478167 A7 ---_ V. Description of the invention (4) Figure J shows the slightly doped source electrode of 4 Ming A cross-sectional view of a specific embodiment of the formation of an AND region. FIG. 4 is a cross-sectional view of a specific implementation example of the gradual transition of the source and non-polar regions in the Maoming Institute without a backlight region. FIG. 5 is a cross-sectional view of a covered ion-implanted transistor having a prior art. FIG. 6 is a cross-sectional view of a prior art structure. Detailed description of the invention Briefly, the present invention relates to some micro-doped drain (ldd) structures and their fabrication. In the specific implementation example of 7F in FIG. 4, a backlight 303 is created in a gold i oxide semiconductor field effect transistor (MOSFE D) 100. As an example, the metal oxide semiconductor field effect transistor (MOSFET) has a gate structure 109 arranged on a channel 108. The backlight is shown at 303. A small angle ion implantation step is used to form the backlight. Next, the annealing step can be performed to diffuse the dopant under the gate until the point shown in FIG. The chirped light is arranged between the channel and the slightly doped source and drain regions (404 and 40 1 respectively). The heavily doped source and non-electrode regions are shown at 405 and 402, respectively.泫 Small-angle ion implantation and annealing steps allow the formation of backlight in devices with reduced feature size and reduced pitch, while also avoiding shadowing effects and unacceptable doping of channels, as previously explained. For demonstration purposes, the gate length may be 0.25 micrometers or less, and the distance between the gate structure and the adjacent gate structure is 0.3 5 micrometers or less. Although an N-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) is used in the specific implementation example, the present invention can be used for the formation of a selective arrangement of ion implantation in an integrated circuit, and to avoid any shadowing phenomenon. -7- The paper size is subject to China National Standards (CNS) A4 Regulations (21〇X 297 public love) ---- (Please read the first 5 notes on the back _ fill out this ‚'. Consumption of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by a cooperative

經濟部智慧財產局員工消費合作社印製 五、發明說明（5 ) 。例如，本發明可以使用在場效應裝置，包括⑴互補金屬 氧化物半導體（BiCM〇S)及互補金屬氧化物半導體（(：]^〇^裝 置中，當然以及其他在普通技藝範圍内的結構。本發明可 以特別地使用於場效應裝置，包括金屬半導體場效應電晶 體（MESFET)，及雙維電子氣體（2DEG)裝置，如高電子遷移 率電晶體（HEMT)。而且，當該範例之突出特徵爲閘及閘結 構時，本發明可用來避免由積體電路及其製造中，其他突 出特徵所產生的遮蔽現象。 參考圖1，'一底材101有一閘電介質102及一閘103形成於 其上。一硬式光罩佈置於104處。離子植入形成卜型背光在 1〇5處。在此具體實施範例中，離子植入的入射角大約與底 材表面110正交；用做示範之故，該離子植入與基層表面 110法線所成的角度在〇至7度間。於圖丨中所示的第一離子 植入步驟，產生該P-型背光離子植入區，在其處離子植入 擴展至通道區108，如示於1 〇6處。 用做示範的基層101爲一半導體如矽、坤化鎵、矽化鍺或 其他適當的材料。用做示範的基層爲卜型，因此該背光離 子植入107也爲P-型。該p-型背光離子植入1〇7以一標準之離 子離子植入技術實施之，雖然其他的技術也可以被使用來 形成背光。做爲示範之用的P-型離子，如硼或二氟化硼， 可以以5Xl〇i2/cm2的劑量於15 keVw能量離子植入。在圖i I具體貫施例中，一通當之硬光罩1〇4用做離子植入光罩， 來防止在通道區108的p-型摻雜。如此，便可以避免任何由 —於覆盍離子植入所引起，有關較高度摻雜通道的問題。 -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事填寫本頁) 裝 ·- -線· 478167 A7 妒·、濟部智慧財產局員工消費合作社印製Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (5). For example, the present invention can be used in field effect devices, including ⑴Complementary Metal Oxide Semiconductor (BiCMOS) and Complementary Metal Oxide Semiconductor ((:) ^^) devices, and of course, other structures within the ordinary technical scope. The invention can be particularly applied to field effect devices, including metal semiconductor field effect transistors (MESFETs), and two-dimensional electron gas (2DEG) devices, such as high electron mobility transistors (HEMT). Moreover, when this example is prominent When the features are gates and gate structures, the present invention can be used to avoid the shadowing phenomenon caused by integrated circuits and other prominent features in their manufacture. Referring to FIG. 1, 'a substrate 101 has a gate dielectric 102 and a gate 103 formed on Above it, a rigid photomask is arranged at 104. Ion implantation forms a Bu-shaped backlight at 105. In this specific implementation example, the incident angle of the ion implantation is approximately orthogonal to the substrate surface 110; it is used as a demonstration Therefore, the angle between the ion implantation and the normal of the base surface 110 is between 0 and 7 degrees. In the first ion implantation step shown in Figure 丨, the P-type backlight ion implantation region is generated. its The ion implantation extends to the channel region 108, as shown at 106. The base layer 101 used as a demonstration is a semiconductor such as silicon, gallium silicide, germanium silicide, or other suitable material. The base layer used as a demonstration is a Bu type, Therefore, the backlight ion implantation 107 is also a P-type. The p-type backlight ion implantation 107 is implemented using a standard ion ion implantation technology, although other technologies can also be used to form the backlight. As Demonstration P-type ions, such as boron or boron difluoride, can be implanted at a dose of 5 × 10i2 / cm2 at 15 keVw energy. In the specific embodiment shown in FIG. 104 is used as an ion implantation mask to prevent p-type doping in the channel region 108. In this way, any problems related to highly doped channels caused by ion implantation can be avoided. -8- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 public love) (Please read the notes on the back and fill out this page). Installation---Line 478167 A7 Jealousy, Ministry of Intellectual Property Printed by Employee Consumer Cooperative

(請先閱讀背面之注意事項吴填寫本頁) 478167 Α7 Β7 經濟部智慧財產局員工消費合作社印制衣 五、發明說明（） 離子植入3 03被橫佝延伸至點20 1處。因此，該對抗換雜背 光有效地佈置於通道108及些微摻雜源極與汲極區之間。如 此的佈置便使得一些微摻雜汲極與些微摻雜源極區適當地 產生。 圖3示以標準離子植入300形成些微摻雜源與汲區。在此 具體貫施範例中的離子植入，其裝置爲一 型金屬氧化物 半導體場效應電晶體（NMOSFET)，將η-型離子引入來形成 些微掺雜源極與汲極。參看圖3便可以明瞭該ρ-型背光區在 閘氧化物10 2之下的橫向擴散至點2 〇 1處，使得背光可以形 …成於些微摻雜汲極301與些微摻雜源極304直接鄰接之處。 最後，本發明的背光結構與傳統背光結構之不同，在於其 可能可以包含一下層區302。此下層區302爲本發明直接的 結不亥月光區形成於LDD區形成之前，清楚地與在圖5中 的先酌技#分別。在圖5中该背光形成於漸變式掺雜分佈源 極與没極、及觀塾之後。 圖4示本發明一具體實施範例之LDD結構。範例之摻雜步 驟疋以標準離子植入來形成源極與没極（分別爲402與405) 之較重掺雜區。該掺雜步驟使用一傳統之襯墊4〇3與該硬 光罩104爲光罩。更進一步可以使用任一先進技藝的處理 來進行。 最後，如先前所示，該選擇之具體實施範例爲一1^^4〇3裝 置。在此結構中，基層爲Ρ-型；通道爲ρ_型；背光結構爲ρ_ 型：些微換雜汲極與源極爲η-型；較重摻雜之源極與汲極 -區爲η-型。摻雜的濃度通常爲標準量，完全在此技藝之範 -10 - (請先閱讀背面之注意事填寫本頁) 裝 · ;線— 0 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 ---------B7___ 五、發明說明（8 ) ^ ^ —-(Please read the notes on the back first to fill in this page) 478167 Α7 Β7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the invention () Ion implantation 3 03 was extended to point 20 by Yokohama. Therefore, the anti-commutative back light is effectively arranged between the channel 108 and the slightly doped source and drain regions. This arrangement makes it possible to appropriately generate some micro-doped drain and some micro-doped source regions. FIG. 3 illustrates the formation of micro-doped sources and drain regions with a standard ion implantation 300. The ion implantation in this specific implementation example uses a type I metal oxide semiconductor field effect transistor (NMOSFET) to introduce η-type ions to form some slightly doped source and drain electrodes. Referring to FIG. 3, it can be seen that the p-type backlight region diffuses laterally under the gate oxide 102 to point 001, so that the backlight can be formed into a slightly doped drain 301 and a slightly doped source 304. Where it directly adjoins. Finally, the backlight structure of the present invention is different from the conventional backlight structure in that it may include a lower layer region 302. This lower layer area 302 is the direct formation of the moonlight region of the present invention before the formation of the LDD region, which is clearly different from the first discretion # in FIG. 5. In FIG. 5, the backlight is formed after the source and the electrode of the gradient doped distribution and the observation. FIG. 4 shows an LDD structure according to an embodiment of the present invention. The example doping step uses standard ion implantation to form heavier doped regions of the source and non-electrode (402 and 405, respectively). The doping step uses a conventional pad 403 and the hard mask 104 as a mask. Further, it can be performed using any advanced technique. Finally, as shown previously, a specific implementation example of this option is a 1 ^^ 403 device. In this structure, the base layer is P-type; the channel is ρ_-type; the backlight structure is ρ_-type: some slightly doped drain and source electrodes are η-type; heavier doped source and drain-regions are η- type. The doping concentration is usually the standard amount, which is completely within the range of this skill. -10-(Please read the notes on the back and fill in this page first) Loading ·; Line — 0 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) A7 --------- B7___ V. Description of the invention (8) ^ ^ —-

圍之中;做示範之用的背光離子植人爲至少i x 1()16，並可 以 土多爲 1χ1〇18。最後，一 PMOS^^'T 制此、w PM0S私置可以使用本發明來 ^作。孩PMOS裝置與讀⑽裝置的結構與製作方法可説是 幾乎完全-樣，當然，該基層、通道、些微接雜之源極與 汲極區、以及背光結構之導電度或極性與NM〇s中的各部分 (counterparts)爲相反。 本發明已詳細説明，可以明瞭的是本發明基本敎授的任 付修正木與麦化都在本技舊範圍之内。任何變化與修正， •只要其用來製作背光區而無遮蔽現象的方法，都在本發明 範曰壽之内。 -—·---_------裝--- (請先閱讀背面之·事寫本頁) .The backlight ion implantation for demonstration purposes is at least i x 1 () 16, and can be 1x1018. Finally, a PMOS system can be used for this purpose, and the WPMOS private system can be implemented using the present invention. The structure and manufacturing method of the PMOS device and the reading device can be said to be almost complete. Of course, the conductivity or polarity of the base layer, the channel, the slightly doped source and drain regions, and the backlight structure are the same as NMs. The counterparts in the opposite. The present invention has been described in detail, and it is clear that any of the modified wood and wheat germs basically taught by the present invention are within the scope of the present technology. Any changes and corrections, as long as it is used to make the backlight area without shadowing, are within the scope of the present invention. --- · ---_------ install --- (Please read the matter on the back first to write this page).

經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

&濟部智慧財產局員工消費合作社印製& Printed by Employee Consumer Cooperatives of the Ministry of Economic Affairs • 一種製造積體電路的方法，該方法包含： 在一基層上形成一突出特徵；及 以與孩基層大約正交的角度離子植入摻雜劑，該摻雜 劑不是離子植入於該突出特徵之下。 2·如申請專利範圍第1項之方法，其中該突出特徵包括一 閘。 3.如申請專利範圍第1項之方法，其中該閘具有—長度爲 0 · 2 5微米或短些。 4*如申請專利範圍第2項之方法，其中該閘具有一硬光罩形 〜成於其上，並且該硬光罩防止該摻雜劑進入該通道。 5·如申請專利範圍第2項之方法，其中佈置於該基層其上的 閘與其鄰接之閘間隔約〇·35微米或更少些。 6.如申請專利範圍第2項之方法，其中該摻雜劑之離子植入 形成一背光區。 7·如申請專利範圍第6項之方法，其中該背光區佈置於一通 道與一汲極區之間。 8 ·如申請專利範圍第2項之方法，其中進行一退火步驟來將 該摻雜劑部分擴散於該閘之下。 9·如申請專利範圍第1項之方法，其中該大約正交的角度爲 與該底·材法線形成七度或更小的角度。 10 ·如申凊專利範圍第7項之方法，其中該没極區包括一些微 摻雖區，鄰接於該背光區。 U·如申請專利範圍第6項之方法，其中該背光區佈置於一通 道與一源極區之間。 -12- 本紙張尺度適用i國家標準（CNS)A4規格_ GA method of manufacturing an integrated circuit, the method comprising: forming a protruding feature on a base layer; and ion-implanting a dopant at an angle approximately orthogonal to the base layer, the dopant not being ion-implanted in the protrusion Characteristics. 2. The method of claim 1 in the scope of patent application, wherein the prominent feature includes a gate. 3. The method of claim 1 in the scope of patent application, wherein the gate has a length of 0.25 microns or less. 4 * The method of claim 2 in which the gate has a hard mask shape formed thereon, and the hard mask prevents the dopant from entering the channel. 5. The method according to item 2 of the scope of patent application, wherein the gates disposed on the base layer and the gates adjacent thereto are spaced at a distance of about 0.35 micrometers or less. 6. The method of claim 2 in which the ion implantation of the dopant forms a backlight region. 7. The method according to item 6 of the patent application, wherein the backlight region is arranged between a channel and a drain region. 8. The method according to item 2 of the patent application, wherein an annealing step is performed to diffuse the dopant part under the gate. 9. The method according to item 1 of the scope of patent application, wherein the approximately orthogonal angle is an angle of seven degrees or less with the substrate normal. 10. The method of claim 7 in the patent scope, wherein the non-polar region includes some micro-doped regions adjacent to the backlight region. U. The method according to item 6 of the patent application, wherein the backlight region is arranged between a channel and a source region. -12- This paper size applies to National Standard (CNS) A4 specifications _ G 478167 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 12·如申請專利範獨第丨丨項之方法，其中与 微彳參雜區。 13· —種製造積體電路的方法，該方法包本 在一基層上形成至少兩個突出特徵，該等突 一 0.35微米或更小的間距；及 •以與該基層大約正交的角度離子植入摻雜劑。 14·如申請專利範圍第13項之方法，其中 τ必守土少兩個穸 特徵之一包括一閘。 15.如申請專利範圍第14項之方法，其中該閘有— • - -0.25微米或短些。 又馬 16:如申請專利範圍第14項之方法，其中該摻雜劑不離子植 入於該閘之下。 如申請專利範圍第16項之方法，其中進行一退火步驟來 將該摻雜劑部分擴散於該閉之下。 18. 如申請專利範圍第14項之方法’其中該換雜劑形成一背 光。 _ 19. 如申請專利範圍第18項之方法，其中該背光區佈置於一 通道與一没區之間。 20·如申請專利範圍第19項之方法，其中該没極區包括一些 微摻雜區。 2 1 · —種積體電路，包含： 一突出特徵佈置於一基層上，該突出特徵具有一長度 爲0.2 5微米或更小；及一些微摻雜區佈置於該基層中， 且部分於該突出特徵之下。 该源極區包括 突出特徵有 ---Ί:---:------裝--- (請先閱讀背面之注音？事寫本頁) 訂·. 線· 13 私紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 478167 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 22. 如申請專利範周第21項之積體電路，其中該突出特徵包 括一閘。 23. 如申請專利範圍第22項之積體電路，其中一通道佈置於 孩基層中位於孩閘之下，且該摻雜區佈置於該通道與一 没極區之間。 24. 如中請專利範圍第23項之積體電路，其中該捧雜區爲_ 背光，且該汲極區包括一些微摻錐區。 25. 如申請專利範圍第21項之積體電路，其中一鄰 特徵佈置於該基層上，該突出特徵有—〇35微米或：小 ._ —的間距。 26: —種積體電路，包含： 至少兩個突出特徵佈置於一基層上，該等突出特徵有 一 0·35微米或更小的間距；及 些微摻雜區佈置於該基層中，該等些微摻雜區之—部 分地佈置於每一該等突出特徵之下。 27. 如申請專利範圍第26項之積體電路，-其中該突出特徵包 括一閘。 28. 如申請專利範圍第27項之積體電路，其中該閘具有—長 度爲0.25微米或短些。 29·如申請專利範圍第28項之積體電路，其中該部分地佈置 於該閘之下的摻雜區爲一背光。 3 0.如申請專利範圍第29項之積體電路，其中該背光位於— 通道與一汲區之間。 •14- 本紙張尺度適用中國國家標準（CNS)A4規格（21Q χ 297公爱·· (請先閱讀背面之注意事ΐ -裝--- ?^寫本頁) . —線.478167 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Scope of patent application 12. If the patent application method of item 丨 丨 is applied, it is mixed with the micro area. 13. · A method of manufacturing an integrated circuit, the method comprising forming at least two protruding features on a base layer, the protrusions having a pitch of 0.35 micrometers or less; and • ions at an angle approximately orthogonal to the base layer Implant dopants. 14. The method according to item 13 of the scope of patent application, in which τ must guard the soil and one of the two features includes a gate. 15. The method according to item 14 of the patent application scope, wherein the gate has-•--0.25 micron or shorter. Ma Ma 16: The method of claim 14 in which the dopant is not ion-implanted under the gate. For example, the method according to item 16 of the patent application, wherein an annealing step is performed to diffuse the dopant part under the shutter. 18. The method according to item 14 of the patent application, wherein the replacement agent forms a backlight. _ 19. The method of claim 18, wherein the backlight area is arranged between a channel and a blank area. 20. The method of claim 19, wherein the non-polar region includes some micro-doped regions. 2 1 · —A kind of integrated circuit, comprising: a protruding feature arranged on a base layer, the protruding feature having a length of 0.2 5 μm or less; and some micro-doped regions arranged in the base layer, and part of the Under the features. The source region includes prominent features: --- Ί: ---: ------ install --- (Please read the phonetic on the back? Write this page first) Order · Line · 13 Private paper scales apply China National Standard (CNS) A4 specification (210 X 297 mm) 478167 A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Scope of patent application 22. For the application of the integrated circuit of item 21 of the patent application week, The prominent feature includes a gate. 23. For the integrated circuit of item 22 of the patent application, a channel is arranged in the child base layer under the child gate, and the doped region is arranged between the channel and an electrodeless region. 24. The integrated circuit of item 23 of the patent, wherein the miscellaneous region is a backlight and the drain region includes some micro-doped cone regions. 25. For the integrated circuit of item 21 in the scope of patent application, one of the adjacent features is arranged on the base layer, and the prominent feature has a pitch of -035 microns or: small. 26: A kind of integrated circuit, comprising: at least two protruding features arranged on a base layer, the protruding features having a pitch of 0.35 micrometers or less; and microdoped regions arranged in the base layer, the micro The doped regions are partially disposed under each of these prominent features. 27. The integrated circuit of item 26 of the scope of patent application, wherein the prominent feature includes a gate. 28. The integrated circuit of item 27 in the scope of application for a patent, wherein the gate has a length of 0.25 microns or less. 29. The integrated circuit of item 28 in the scope of patent application, wherein the partially doped region disposed below the gate is a backlight. 30. The integrated circuit of item 29 in the scope of patent application, wherein the backlight is located between the channel and a drain region. • 14- This paper size is in accordance with China National Standard (CNS) A4 (21Q χ 297 public love ... (Please read the precautions on the back first-install ---? ^ Write this page). --- line.
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