經濟部中央標準局員工消費合作社印製 ΑΊ B7 五、發明説明（/ ) ⑴發明領域 本發明乃有關於薄膜電晶體之製程及其結構，更明確的說本發 明爲一種增進薄膜電晶體元件特性及降低製作成本之製程。 ⑵背景說明 薄膜電晶體已被廣泛地應用於各領域中，在液晶顯示器(LCD) 方面，薄膜電晶體作被當成主動元件開關，控制每一像素的亮或 暗。這種薄膜電晶體現在絕大部份是由非晶矽氫薄膜電晶體(a-Si:H TFT)構成。最常使用的製程不外乎是在絕緣基板(如破璃)上形成一 閘極金屬，接著是形成閘極絕緣層，然後未摻雜的非晶矽及摻高濃 度雜質的非晶矽(通常是N+)相續形成。接下來鋪設第二層金屬並形 成源極和汲極時，因爲對準的誤差會造成元件中不可預期的寄生電 容；另外在光罩設計時考慮避免接觸不良,，而須加上額外尺寸.，這 也會引發額外的寄生電容。 圖1爲典型的TFT結構剖面圖。如,中所示，閘極2首先在絕緣 基板1上形成，閘極2上面覆蓋著閘極絕緣層3 ’未摻雜非晶矽21 ’ 高度摻雜(通常是N+)非晶矽22，以黃光、微影、餓刻法定出圖案’ 接下來形齡腿24，酿腦光、麟、瓣 層24及N+非晶砂22，形成間隙25。 除了麵所獅辨黯細外幢疊誠雜電_題外， 上述製程施補它賴。钟之-是：於錬婦雷塒讲非晶砂 (請先閲讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs AΊ B7 V. Description of the Invention (/) ⑴ Field of the Invention The present invention relates to the process and structure of thin film transistors. More specifically, the present invention is to improve the characteristics of thin film transistors And the process of reducing production costs. ⑵Background description Thin film transistors have been widely used in various fields. In liquid crystal displays (LCD), thin film transistors are used as active component switches to control the brightness or darkness of each pixel. Most of these thin-film transistors are now composed of amorphous silicon-hydrogen thin-film transistors (a-Si: H TFT). The most commonly used process is nothing more than forming a gate metal on an insulating substrate (such as broken glass), followed by forming a gate insulating layer, then undoped amorphous silicon and amorphous silicon doped with high concentrations of impurities ( It is usually N +). When the second layer of metal is laid next to form the source and drain, the misalignment will cause unintended parasitic capacitance in the component. In addition, in the design of the photomask, to avoid poor contact, additional dimensions must be added., This will also cause additional parasitic capacitance. FIG. 1 is a cross-sectional view of a typical TFT structure. As shown in, gate 2 is first formed on an insulating substrate 1, and gate 2 is covered with a gate insulating layer 3 'undoped amorphous silicon 21' highly doped (usually N +) amorphous silicon 22, Use yellow light, lithography, and starving to engrav the pattern. 'Next, shape the legs 24, create brain light, lin, valve layer 24, and N + amorphous sand 22 to form a gap 25. In addition to the superbly miscellaneous electric and electronic problems, the above process complements it. Zhong Zhi-Yes: Yu Yifu Lei Yi talk about amorphous sand (Please read the precautions on the back before filling this page)
本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（z) 22若蝕刻不足，部份N+非晶矽22殘留於非晶矽21表面，此將造成 TFT漏電流增加；若是N+非晶矽22過度蝕刻，非晶矽21的厚度將少 於原先預定厚度太多而造成TFT元件特性不佳(開啓電流太小）。這 問題必須藉助改變元件結構而加以改善。 另外一個本質上的問題是在上述元件結構中以非晶矽當作電晶 體的主動區域材料。而非晶矽有非常高的阻抗一即使在閘極施加電 壓而在閘極絕緣層表面形成通道。因此有許多硏究即在改善這本質 上的問題。例如把非晶矽加熱至600°C，把非晶矽變成複晶矽，但 是這種高溫製程會破壞元件其它層次(如TFT-LCD之結構中其它層 次特性)。所以在極短暫時間(例如··數百分之一微秒)內把特定區域非 晶矽加熱之方法即成爲很熱門的硏究題目，而雷射回火目前就是被廣 泛地應用於此硏究中。 於先前技藝Zhang等人(西元1996年元月之美國專利5,488,000 號)提出雷射回火，因雷射強度波動，在掃瞄區域會造成加熱不均 勻,，爲克服此問題，他們提出在形成非晶矽層上加一結晶核層(例如 用Nickel);先成結晶，而可使後續主結晶製程可用較低溫度；而在 本發明中，我們發現不須使用此技術。 參考圖2，在先前技藝中，複晶矽TFT製造方法一開始在一絕緣 基板1上形成未摻雜質的非晶矽。此非晶矽層可用雷射光束29加 以照射而結晶成複晶矽。 (請先閱讀背面之注意事項再填窝本頁) 裝· 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（B ) 如圖3所示，氧化層33覆蓋於層221上。金屬層(例如鉻)在層33 上形成並定義成閘極35。然後此結構受一高能量離子植入製程39而 使得雜質穿透層33並形成層32，而閘極以下通道區域被閘極檔住仍 保持非摻雜。經回火步驟後，區域32變成高度摻雜之複晶矽，而區 域30與閘極完全對準仍然是非摻雜區域。 圖4是此製程之完整結構。介電層42通常是由氧化矽構成。接 觸窗是挖穿介電層42而直達源極/汲極區域32 ,之後塡上傳導金屬 43 ;最後護層44覆蓋整個結構’該護層44通常由氮化Ϊ夕構成。 這個結構有許多缺點。首先用來摻雜源極、汲極的離子必須穿 透聞極氧化層33，所以必須有很大的能量，因而會帶來很大的輻射 破壞。要挽救這種破壞須要很高的回火溫度或者很長的回火時間。 而且在這製程中須要兩道回火步驟，其一是使非晶矽回火成複晶 矽，其二是使摻入雜質活化。 ⑶發明之簡要說明 本發明之目的在於製作一 TFT通道常度和閘極的寬度是相同。 ..本發明另一目的在於提供一TFT其結構可使源極/汲極和主動 層的複晶矽有低接觸阻値，而且可以使TFT在閘極爲負電壓時有低 的漏電流(對N型TFT而言）。 本發明又一目的在於使TFT的製造成本，較昔知技藝爲低。本 發明更在於不使用高能量離子植入製程，而使輻射對元件的損害大 爲降低；進而如前所述，提供只須一道回火步驟即可之製程。 本紙浪尺度適用中國國家標準（CNS〉A4規格（210X297公釐〉 (請先閱讀背面之注意事項再填寫本頁) 訂-- H. _ 1 -I--- - - · 經濟部中央標準局員工消費合作社印製 專智工 塌慧 逯財 Μ _ 81 五、發明説明（4*) 爲達到這些目的，其製程爲：使用一透明基板，源極到汲極的 距離靠從此透明基板背面曝光，以閘極當作光罩，使正光阻在沒閘 極擋住之處經此曝光、顯影而留下與閘極同寬的光阻區。這留下的 光阻區保護下層的非晶矽；接著在含摻雜物質之氣體之電漿照射 下、高度摻雜區因此形成，所以此高度摻雜區域與閘極是精確地對 準著。在光阻去除後，此結構用一道雷射來照射，不僅可使非晶矽 變成複晶矽，同時也可使摻入雜質活化。然後此結構按一般正常的 步驟來完成，如舖設第二層金屬，定義圖案形成源極/汲極；再舖 設護層，挖連接孔，接觸焊點等。 ⑷圖示之簡要說明 圖1係一習知技藝之非晶矽薄膜電晶體的剖面圖。 圖2係習知技藝之複晶矽薄膜電晶體的雷射回火示意圖。 圖3及圖4所示係習知複晶矽技藝薄膜電晶體之製造流程。 圖5係本發明利用閘極當光罩，經由基板背面曝光並顯影，形 成光阻屏蔽層之剖面圖。 至 6及圖11係描述本發明製作流程圖。 沒係本發明與習知技藝之複晶矽薄膜電晶體的汲極電流對閘 曲線圖。 (5)發明之較佳實施例 (請先閔讀背面之注意事項再填寫本頁)This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm). Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. A7 B7. 5. Description of the invention (z) 22 If the etching is insufficient, some N + amorphous silicon 22 remains in The surface of the amorphous silicon 21 will increase the TFT leakage current; if N + amorphous silicon 22 is over-etched, the thickness of the amorphous silicon 21 will be less than the original predetermined thickness and the TFT element characteristics will be poor (the turn-on current is too small) . This problem must be improved by changing the structure of the components. Another essential problem is the use of amorphous silicon as the active region material for the electrical crystals in the above device structure. Amorphous silicon has a very high impedance-even if a voltage is applied to the gate, a channel is formed on the surface of the gate insulating layer. So there are a lot of investigations that are improving this essential issue. For example, the amorphous silicon is heated to 600 ° C to change the amorphous silicon into a polycrystalline silicon, but this high-temperature process will destroy other layers of the device (such as the characteristics of other layers in the structure of the TFT-LCD). Therefore, the method of heating amorphous silicon in a specific area in a very short time (for example, several hundredths of a microsecond) has become a very popular research topic, and laser tempering is currently widely used in this area. Research. In previous techniques, Zhang et al. (US Patent No. 5,488,000, dated January 1996) proposed laser tempering, which caused uneven heating in the scanning area due to fluctuations in laser intensity. In order to overcome this problem, they proposed Adding a crystalline core layer (eg, Nickel) to the amorphous silicon layer; forming a crystal first, so that the subsequent main crystallization process can use a lower temperature; and in the present invention, we have found that this technology is not necessary. Referring to FIG. 2, in the prior art, a method for manufacturing a polycrystalline silicon TFT initially forms an undoped amorphous silicon on an insulating substrate 1. This amorphous silicon layer can be irradiated with a laser beam 29 to crystallize it into a polycrystalline silicon. (Please read the precautions on the back before filling in this page.) The size of the bound and bound paper is applicable to the Chinese National Standard (CNS) A4 (210X297 mm). Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. A7 B7. 5. Description of the invention (B) As shown in FIG. 3, the oxide layer 33 covers the layer 221. A metal layer (eg, chromium) is formed on the layer 33 and is defined as the gate 35. This structure is then subjected to a high-energy ion implantation process 39 to allow impurities to penetrate the layer 33 and form the layer 32, while the channel region below the gate is blocked by the gate and remains undoped. After the tempering step, the region 32 becomes a highly doped polycrystalline silicon, while the region 30 is fully aligned with the gate and remains an undoped region. Figure 4 is the complete structure of this process. The dielectric layer 42 is usually made of silicon oxide. The contact window is cut through the dielectric layer 42 to reach the source / drain region 32, and then a conductive metal 43 is applied; finally, a protective layer 44 covers the entire structure. The protective layer 44 is usually composed of nitride. There are many disadvantages to this structure. The ions used for doping the source and drain electrodes must pass through the oxidized oxide layer 33, so they must have a large amount of energy, which will cause great radiation damage. Rescuing such damage requires high tempering temperatures or long tempering times. Moreover, two tempering steps are required in this process, one is to temper the amorphous silicon into the polycrystalline silicon, and the other is to activate the doped impurities. (3) Brief description of the invention The purpose of the present invention is to make a TFT channel constant and gate width are the same. .. Another object of the present invention is to provide a TFT whose structure enables the source / drain and the polycrystalline silicon of the active layer to have a low contact resistance, and can make the TFT have a low leakage current when the gate voltage is negative (for N-type TFT). Another object of the present invention is to make the manufacturing cost of TFT lower than that of the prior art. The present invention further does not use a high-energy ion implantation process, and greatly reduces the damage to the components by radiation; furthermore, as described above, a process that requires only one tempering step is provided. The paper scale is applicable to Chinese national standards (CNS> A4 specification (210X297mm) (please read the precautions on the back before filling this page))-H. _ 1 -I -----· Central Bureau of Standards, Ministry of Economic Affairs Employee Consumer Cooperative Co., Ltd. Prints Specialist Workers _ 81 V. Description of Invention (4 *) To achieve these objectives, the process is as follows: a transparent substrate is used, and the distance from the source to the drain is exposed from the back of this transparent substrate The gate is used as a photomask, so that the positive photoresist is exposed and developed in the place where the gate is not blocked, leaving a photoresistive region with the same width as the gate. The remaining photoresistive region protects the underlying amorphous silicon. ; Then, under the plasma irradiation of the gas containing the doping substance, a highly doped region is formed, so this highly doped region is precisely aligned with the gate. After the photoresist is removed, this structure uses a laser After irradiation, not only amorphous silicon can be changed into complex silicon, but also doped impurities can be activated. Then the structure is completed according to normal steps, such as laying a second layer of metal to define a pattern to form a source / drain; Then lay a protective layer, dig connection holes, and contact solder joints. ⑷ Brief description of the diagram Figure 1 is a cross-sectional view of a conventional amorphous silicon thin film transistor. Figure 2 is a schematic diagram of laser tempering of a complex silicon thin film transistor of conventional technology. Figure 3 and Figure 4 Figure 5 shows the manufacturing process of a conventional polycrystalline silicon thin film transistor. Figure 5 is a cross-sectional view of the present invention using a gate electrode as a photomask, which is exposed and developed through the back surface of the substrate to form a photoresist shield layer. The production flow chart of the present invention. The drain current vs. gate curve of the multi-crystalline silicon thin film transistor of the present invention and the conventional technology is not included. (5) A preferred embodiment of the invention (please read the precautions on the back before filling in) (This page)
本紙浪尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） A7 _R7__ 五、發明説明（J* ) 圖5係本發明利用閘極當光罩’經由基板背面曝光並顯影’形 成光阻屏蔽層之剖面圖。此TFT是自我對準形成’作法是靠紫外光 從透明基板背面照射’因爲光線被閘極2擋住’所以閘極2當作是光 罩。顯影後，光阻屏蔽層51被留下來’作爲後續摻雜用低能量離子 流52植入之屏蔽，而該光阻屏蔽層51與閘極2是完全自我對準的。 參考圖6，本發明使用一透明絕緣基板71，可使波長在約350〜 25000A之間的光穿透，其中包含了適用於該光阻曝光的波長。一般 常用的基板爲含硼矽玻璃’另外像石英亦可。如圖7所示’在此透 明基板71正面形成一金屬層，此金屬可爲钽、鉻、鉬、鋁.…等’厚 度約在2000〜4000A之間’並定義成閘極72圖案。 如圖8所示，一絕緣層73，如氧化矽、氮化矽、鉅氧化物，或 相似材質在閘極72及基板71上形成，厚度約在2000〜4〇0〇A，然後 形成非晶矽74，厚度約500〜ΙΟΟΟΑ，通常是以化學汽相沈積(CVD) 法形成。 如圖9所示，非晶矽74上覆蓋正光阻，以紫外光從基板71背面 照射曝光，閘極72當作光罩，故經顯影後，除閘極72上，其餘皆無 光阻，而得到光阻屏蔽層75，所以此光阻屏蔽層75是和閘極72圖案 完全一致的。 如圖9所示，以氣體電漿77照射，其功率約在100〜1000W電漿 中摻有雜質77，如砷或磷或硼。（本例爲以摻磷的N型TFT),此雜質 滲透在沒有光阻屏蔽層75的非晶矽74表面，形成雜質摻雜區76。 本紙.張尺度適用中國國家榇準（CNS ) A4说格（210X 297公釐） (諳先閱讀背面之注意事項再填寫本頁)The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) A7 _R7__ V. Description of the invention (J *) Figure 5 is a photoresist formed by the gate electrode when the photomask is 'exposed and developed through the back of the substrate' in the present invention Sectional view of the shield. This TFT is self-aligned and formed. The method is to irradiate with ultraviolet light from the back of the transparent substrate. Since the light is blocked by the gate 2, the gate 2 is used as a mask. After development, the photoresist shielding layer 51 is left as a shield for subsequent doping implanted with a low-energy ion current 52, and the photoresist shielding layer 51 and the gate electrode 2 are completely self-aligned. Referring to FIG. 6, the present invention uses a transparent insulating substrate 71 to allow light with a wavelength between about 350 and 25000 A to pass through, including a wavelength suitable for the photoresist exposure. The commonly used substrate is borosilicate glass', and it may be like quartz. As shown in FIG. 7, 'a metal layer is formed on the front surface of the transparent substrate 71, and the metal may be tantalum, chromium, molybdenum, aluminum, etc.' and the thickness is between about 2000 to 4000 A 'and is defined as the gate 72 pattern. As shown in FIG. 8, an insulating layer 73 such as silicon oxide, silicon nitride, giant oxide, or similar material is formed on the gate 72 and the substrate 71 with a thickness of about 2000˜4000 A, and then a non-crystalline layer is formed. The crystalline silicon 74 has a thickness of about 500˜100 Å, and is usually formed by a chemical vapor deposition (CVD) method. As shown in FIG. 9, the amorphous silicon 74 is covered with a positive photoresist, and is exposed by ultraviolet light from the back of the substrate 71. The gate 72 is used as a photomask. Therefore, after development, except the gate 72, there is no photoresist. The photoresist shielding layer 75 is obtained, so the photoresist shielding layer 75 is completely consistent with the pattern of the gate electrode 72. As shown in FIG. 9, the plasma 77 is irradiated, and its power is about 100 ~ 1000W. The plasma is doped with impurities 77, such as arsenic or phosphorus or boron. (This example is an N-type TFT doped with phosphorus.) This impurity penetrates the surface of the amorphous silicon 74 without the photoresist shielding layer 75 to form an impurity-doped region 76. This paper. Zhang scale is applicable to China National Standards (CNS) A4 format (210X 297 mm) (谙 Please read the notes on the back before filling in this page)
A7 B7 經濟部中夬樣隼局貝i消費合阼枉印裂 五、發明説明（έ ) 如圖10 ’接下來把光阻屏蔽層75去除，並以雷射78加以照射。 此雷射照射同時完成兩件事：一是使非晶矽回火成複晶矽，二是使 在圖9之雜質摻雜區76，其表面的雜質被雷射擴散，並加以活化成 爲如圖10之雜質摻雜層Π6 〇 接下來製程是舖上金屬層如銘、欽、銷等，在複晶砂表面，並 經定義成源極/汲極83，如圖11所示。只要源極/汲極83和閘極72 沒有重疊，兩者之間的精確對準是不須要的，這是因爲層176已有 夠低的阻値(通常在100〜1000Ω/口）。接下來形成4000〜6000A厚的 護層82，並定義出銲墊，而完成整個製程。 從圖11可看出整個TFT的結構，包含透明絕緣基板71，其上有 寬約10〜30um的閘極’絕緣層73覆蓋在閘極上，上面則有複晶石夕、 .厚度在500〜ιοοοΑ。複晶矽在閘極上是沒摻雜質，阻値約在1〇6〜 108Ω/口，其餘是有摻雜質(如層176)。金屬的源極/汲極83和有摻 雜質的複晶矽接觸在一起，而護層82把整個結構包覆起來。 圖11的結構有一明顯的優點，即是製程、結構簡單，而且元件 的特性亦相當良好。在製程方面，不須要高能量的離子植入，而使 ’ 用氣體電漿照射，可避免輻射損害，同時亦可使光阻容易去除。而 且使用一次雷射回火即同時可使非晶矽結晶成複晶矽，並使摻入雜 '質活化，而達到簡化製程步驟，降低製作成本之目標。如圖12所 示，爲TFT的汲極電流對閘極電壓特性。曲線121爲傳統共平面結構 複晶矽TFT特性、曲線122爲本發明之TFT特性。由此圖可知，用簡 (請先閲讀背面之注意事項再填寫本頁) 裝· -訂 線 # 本紙張欠度適用中國國家標準（CNS > A4規格（210X297公釐） 83. 3.10,000 A7 B7 -- -— ：~ 五、發明説明（7 ) 、、 單的單一閘極結構，即可使tft漏電流降低’例如在圖12中所示， 在閘極電壓負14伏特時，本發明之177可使漏電流降低約百分之 —。而本結構爲自我對準之TFT，其寄生電容可大爲降低。 上述說明係本發明之舉例說日月’ 方令戶斤 改變，均包含本發明範圍與精神之內。 (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 —βββη^ 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4规格（21〇χ 297公釐）A7 B7 In the Ministry of Economic Affairs, the sample of the consumer package is broken. 5. Description of the Invention (Hand) As shown in Fig. 10 ', the photoresist shielding layer 75 is removed and irradiated with a laser 78. This laser irradiation accomplishes two things at the same time: one is to temper the amorphous silicon into the polycrystalline silicon, and the other is to make the impurity on the surface of the impurity doped region 76 in FIG. 9 diffused by the laser and activated as The impurity-doped layer Π6 in FIG. 10 is next covered with a metal layer such as an ingot, a pin, a pin, etc., on the surface of the polycrystalline sand, and defined as a source / drain 83, as shown in FIG. 11. As long as the source / drain 83 and gate 72 do not overlap, precise alignment between the two is not necessary, because the layer 176 has a sufficiently low resistance (usually at 100 ~ 1000Ω / port). Next, a protective layer 82 with a thickness of 4000 ~ 6000A is formed, and a solder pad is defined to complete the entire process. As can be seen from FIG. 11, the structure of the entire TFT includes a transparent insulating substrate 71 on which a gate electrode's insulating layer 73 having a width of about 10 to 30 μm is covered on the gate electrode, and there is polycrystalline stone, and the thickness is 500 to 500 ιοοοΑ. The polycrystalline silicon is undoped on the gate, and the resistance is about 106 ~ 108Ω / port, and the rest is doped (such as layer 176). The source / drain 83 of the metal is in contact with the impurity-doped polycrystalline silicon, and the protective layer 82 covers the entire structure. The structure of Fig. 11 has obvious advantages, that is, the manufacturing process is simple, and the characteristics of the components are quite good. In terms of manufacturing process, high-energy ion implantation is not required, and irradiation with a gas plasma can avoid radiation damage, and at the same time, can easily remove photoresist. In addition, the use of a single laser tempering can simultaneously crystallize amorphous silicon into polycrystalline silicon and activate the doped impurities, thereby achieving the goal of simplifying process steps and reducing manufacturing costs. As shown in Figure 12, it is the drain current vs. gate voltage characteristic of the TFT. Curve 121 is a characteristic of a conventional co-planar polycrystalline silicon TFT, and curve 122 is a TFT characteristic of the present invention. As you can see from this figure, use the simple (please read the precautions on the back before filling this page). Binding ·-Thread # This paper is inferior to the Chinese national standard (CNS > A4 size (210X297 mm) 83. 3.10,000 A7 B7 -----: ~ V. Description of the invention (7), a single single gate structure can reduce the tft leakage current '. For example, as shown in Figure 12, when the gate voltage is negative 14 volts, this Invention No. 177 can reduce leakage current by about-. And this structure is a self-aligned TFT, and its parasitic capacitance can be greatly reduced. The above description is an example of the present invention. It is within the scope and spirit of the present invention. (Please read the notes on the back before filling out this page.) Binding and binding—βββη ^ Printed on the paper by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. The paper size applies to the Chinese National Standard (CNS) A4 specification. (21〇χ 297 mm)