GB2362030A - Method of fabricating a halo structure in an integrated circuit for reduced size transistors - Google Patents

Method of fabricating a halo structure in an integrated circuit for reduced size transistors Download PDF

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Publication number
GB2362030A
GB2362030A GB0026736A GB0026736A GB2362030A GB 2362030 A GB2362030 A GB 2362030A GB 0026736 A GB0026736 A GB 0026736A GB 0026736 A GB0026736 A GB 0026736A GB 2362030 A GB2362030 A GB 2362030A
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Prior art keywords
recited
process
gate
integrated circuit
substrate
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Withdrawn
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GB0026736A
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GB0026736D0 (en )
Inventor
Seungmoo Choi
Timothy Edward Doyle
Troy A Giniecki
Amal Ma Hamad
Pai H Yih
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Nokia of America Corp
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Nokia of America Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107Substrate region of field-effect devices
    • H01L29/1075Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current

Abstract

A process for fabricating an integrated circuit involves forming a raised feature (109) over a substrate (101), and implanting dopants (105) at substrate surface (110) at a near orthogonal angle of up to 7 degrees from the normal. The raised feature may include a gate (109) of length less than 0.25 microns with gate oxide (102), and hard mask (104) to prevent dopants (105) from entering the channel (108) of the transistor. The orthogonal implantation may form halo region (303, Fig. 3) between lightly doped source (301, Fig. 3) and drain (304, Fig. 3) structures, where an anneal step is performed to diffuse the dopants partially under the gate (108). The gates (109) may be separated by 0.35 microns or less from each other. An integrated circuit comprising a raised feature (109) of length 0.25 microns or less, or two raised features separated by 0.35 microns or less from each other, with a doped region (201, Fig. 3) disposed partially under the raised gate (109) is also disclosed.

Description

S. Choi 15-1-6-1-2 2362030 Halo Structure For Use In Reduced Feature Size

Transistors Meld of the Invention The present invention relates to a halo structure and a method of its fabrication.

Backeround of the Invention As gate lengths are reduced in integrated circuits, hot carrier effects can result in unacceptable performance characteristics in metal-oxide semiconductor field effect transistors (MOSFET). One way to overcome hot carrier effects is through the use of lightly doped drain (LDD) structures. In an LDD structure, the source and drain have graded doping profiles. In the source and drain regions nearest the channel, the doping level is lower, relative to the more highly doped source and drain regions farther from the channel. The lightly doped source and drain regions act to lower the electric field in the region of the channel near the source and drain. This reduced electric field improves threshold stability by reducing hot carrier injection into the gate oxide overlying the channel region.

Another problem resulting from reduced feature sizes is a short channel effect known as "punch-through." Punch-through is a phenomenon that results from the merging of the source and drain depletion regions. As channel lengths are reduced the source and drain depletion region edges get closer. When the channel length is decreased to roughly the sum of the two junction depletion widths in the substrate, the depletion regions merge. This merging of the depletion regions can result in punchthrough of carriers. As can be appreciated, punch-through makes charge controldifficult and may compromise transistor functionality.

One technique to reduce punch-through is to selectively counter-dope the region adjacent to the source and drain depletion regions. This is done with a blanket implant of dopant ions at normal incidence to the substrate and is successful in reducing punch-through problems. For example, in an NMOS device, p-dopants are implanted in the p-channel However, the blanket implant results in doping of the channel to an unacceptable level T'his results in an increase in the threshold voltage, a reduction in carrier mobility in the channel, and a degradation of the drive current.

S. Choi 15-1-6-1-2 Because of the potential drawbacks of the blanket implant for reducing the effects of punch-through, the structure shown in Figure 5 has been more recently investigated. The halo implants 503 are formed on the inside walls of the lightly doped source and drain regions 501 and 502, respectively. This is done using a large angle implant, normally on the order of 30 degrees or more from the normal to the substrate.

The spacer is used as a mask during the formation of the more heavily doped source and drain regions, 506 and 507, respectively. The spacer 505 is formed on either side of the gate structure 508, which includes a gate oxide 509. This selective placement of the halo implants allows punch-through effects to be reduced, and avoids over-doping the channel While the structure shown in Figure 5 has clear advantages over the blanket implant, device scaling requires a far-ther reduction in the spacing or the spacing between gates. As a result of the reduced spacing, neighboring features, such as gate structures, may block the finplant from reaching intended locations in the substrate.

This blocking affect is referred to as shadowing, as can be appreciated from a review of Fig. 6.

Turning to Figure 6, adjacent gate structures 603 having reduced spacing is shown. The spacing between the gates (shown as the poly-poly spacing "p") is reduced to achieve the desired integration. For example when the gate length (shown a "w" in Figure 6) is on the order of 0. 16 pm, the value of p is on the order of 0.24 um. The height (shown as "h") of the features such as the gate structure 603, is on the order of about 0.5 pm. Accordingly, because of the reduced spacing between the features and relative height of the features, the implantation 601 at relatively large angles from the normal results in shadowing of regions 602 by the neighboring polysilicon gates 603. As a result of the shadowing, the halo implantation is not effectively disposed in the shadowed regions 602 and its ability to reduce punch through is dimini hed.

Accordingly, what is needed is a technique for fabricating a halo implant in a lightly doped drain structure which effectively reduces punch-through while not degrading device performance in reduced feature size transistor structures.

S. Choi 15-1-6-1-2 Sunnnarv of the Invention The present invention relates to a halo structure for use in an integrated circuit and its process for fabrication.

According to one aspect of the invention, a raised feature is formed over a substrate. An implant is carried out at a low angle of incidence approximately orthogonal to the substrate. The implant step does not substantially introduce dopants to a region of the substrate beneath the raised feature. The invention avoids shadowing effects in reduced feature size integrated circuits.

According to another aspect of the present invention, a raised feature having a length on the order of 0.25 pm or less is disposed over a substrate. A portion of the substrate is doped with a portion of the dopants being disposed partially beneath the raised feature.

Brief Desg]jRfion of the Drawine The invention is best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that, in accordance with practice in the semiconductor industry, the various features are not necessarily drawn to scale. In fact, dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Figure 1 is a cross-sectional view of an exemplary embodiment of the present invention showing the halo imp 0 Figure 2 is a cross-sectional view of an exemplary embodiment of the present invention showing lateral diffusion by thermal anneal Figure 3 is a cross-sectional view of an exemplary embodiment of the present invention showing the formation of the lightly doped source and drain regions.

Figure 4 is a cross-sectional view of an exemplary embodiment of the present invention showing the graded source and drain doping profiles with the halo regions.

S. Choi 15-1-6-1-2 Figure 5 is a cross-sectional view of a prior art transistor having a blanket implant.

Figure 6 is a cross-sectional view of a prior art structure.

Detailed Descri]Rflon of the Invention Briefly, the present invention relates to a lightly doped drain (LDD) structure and its method of fabrication. In an exemplary embodiment shown in Fig. 4, a halo 303 is created in a MOSFET 100. Illustratively the MOSFET has a gate structure 109 disposed over a channel 108. The halo is shown at 303. A small angle implant step is used to form the halo. A subsequent anneal step may be performed to diffuse dopants partially under the gate to a point shown at 201. The halo is disposed between the channel and the lightly doped source and drain regions 404 and 401, respectively.

The more heavily doped source and drain regions are shown at 405 and 402, respectively. The small angle implant and the anneal step allow for the formation of the halo in reduced feature size, reduced spacing devices while avoiding shadowing effects and the unacceptable doping of the channel, as discussed previously. For purposes of illustration, the gate length can be 0.25 Pm or less, with the spacing between adjacent gate structures being 0.35 pm or less.

While the exemplary embodiment is drawn'to an NMOSFET, the invention may be used to formed selectively disposed implants in integrated circuits where it is desired to avoid shadowing. For example, the present invention may be used in field effect devices including BiCMOS and CMOS devices, and of course, other structures within the purview of the artisan of ordinary skill. The invention may be used in field effect devices particularly, including metal semiconductor field effect transistors (MESFET) and two dimensional electron gas (2DEG) devices such a& high and high electron mobility transistors (HEMT). Furthermore, while the exemplary raised features are gates and gate structures, the invention can be used to avoid shadowing due to other raised features used in integrated circuits and their fabrication.

Turning to Fig. 1, a substrate 101 has a gate dielectric 102 and a gate 103 formed thereon. A hard mask is disposed as shown at 104. The implantation to form the p-type halo is shown at 105. In the exemplary embodiment, the angle of incidence of the implant is substantially orthogonal to the substrate surface 110; illustratively the implant angle is on the order of 0 to 7 degrees with respect to a S. Choi 15-1-6-1-2 normal to the substrate surface 110. The first implant step shown in Figure I results in the p-type halo implanted area, where the implant extends over to the channel region 108 as shown at 106.

Illustratively, the substrate 101 is a semiconductor such as silicon, gallium arsenide, silicon germanium or other suitable material. Illustratively, the substrate is p-type, and therefore the halo implant 107 is also p-type. Ile p-type halo implant 107 is carried out by a standard ion implantation technique, although other techniques can be used to carry out formation of the halo. Illustratively, p-type ions suc. h as boron or BF2 may be implanted with a dose of 5X10'2/cm at an energy of 15 keV. In the embodiment shown in Fig. 1, a suitable hard mask 104 serves as an implant mask preventing the implantation of the p-type doping in the channel region 108. Accordingly, the problems associated with the more highly doped channel due to a blanket implant are avoided.

The implant step of the present invention is particularly useful in fabricating a halo region in LDD's with reduced gate length and spacing. For example, 'when the gate length is on the order of 0.25 gm, the spacing is on the order of 0.35 gm and the gate structure has a height on the order of 0.5 gra, the shadowing effects discussed above can be particularly deleterious to the formation of the halo. Thus device functionality can be compromised. The finplant angle of the present invention results in selective location of dopants without the problems of shadowing in reduced spacing structures discussed previously. Moreover, the diffusion step discussed below Ru-ther aids in the selective location of dopants to create the halo structure.

It is important to note that the dimensions of gate length, spacing and height are merely illustrative, and it is clear that the present invention can be applied to structures having even smaller dimensions. Illustratively, the present invention c&n be used to substantially avoid the problems of shadowing in devices having gate lengths of 0.16 pm or less; -spacing of 0.24,tun or less; and gate stack height of 0.5 pm Again, the above dimensions are for purposes of illustration, and are not intended to be limiting. To be sure, it is envisioned that the present invention can be used in integrated circuits having gate lengths of 0.10 pm and less with spacing and gate stack height determined by rules of scaling known to one of ordinary skill in the art. Finally, the term spacing in the present disclosure is intended to refer to the spacing between two or more raised features.

S. Choi 15-1-6-1-2 After the implant step in the exemplary embodiment in Figure 1, the halo region is extended by a lateral diffusion process. In the exemplary embodiment, shown in Figure 2, the halo implant is laterally extended under the gate oxide 102 to a point 201. Illustratively, this diffusion step is carried out by a rapid thermal anneal step. The rapid thermal anneal (RTA) enables accurate control of the diffusion depth and has a thermal budget that is lower than other available techniques. Illustratively the RTA is done at 950"C for 10-20 seconds. As a result of the anneal step, the p-type halo implant 303 is laterally extended to a point 201. Thus, the counter doped halo is effectively placed between the channel 108 and the lightly doped source and drain regions. Thereby the placement of a lightly doped drain and lightly doped source region is suitably carried out.

Figure 3 shows the formation of the lightly doped source and drain regions by a standard ion implantation. 300. This implant in the exemplary embodiment in which the device is an NMOSFET, introduces n-type dopants to form the lightly doped source and drain. As can be appreciated by a review of Figure 3, the lateral diffusion of the p-type halo region over to a point 201 under the gate oxide 102, enables the fabrication of the halo immediately adjacent the lightly doped drain region 301 and lightly doped source 304. Finally, the halo of the present invention differs from conventional halo structures as it may include a lower region 302. This lower region 302 is a direct result of the fact that in the present invention, the halo region is formed before the formation of the IDD region. This is in clear contrast to the prior art structure shown in Figure 5, where the halo is formed after the graded doping profile source and drain, and the spacer.

Figure 4 shows the LDD structure of an exemplary embodiment of the present invention. A doping step is carried out for example by standard ion implantation to form the more heavily doped regions of the source and drain 402-and 405, respectively. Tliis doping step uses a conventional spacer 403 and the hard mask 104 as masks. Further processing may then be carried out as can be appreciated by one of ordinary skill in the art.

Finally, as previously noted the chosen illustrative embodiment is drawn to an NMOS device. In this structure, the substrate is p-type; the channel is p-type; the halos are p-type; the lightly doped drain and source are n-type; and the heavily doped source and drain regions are n-type. The doping concentrations are generally at standard levels, well within the purview of one of ordinary skill in the art. The halo S. Choi 15-1-6-1-2 implant is illustratively atleaSt 1 X 1016 and can be as great as 1 x loll. Finally, a PMOS device can be fabricated using the present invention. The PMOS device would be virtually identical in structure and fabricated in virtually the same manner as the NMOS device. Of course, the conductivity or polarity of the substrate, channel, lightly and heavily doped source and drain region and the halos would be opposite to their counterparts in the NMOS device.

The invention having been described in detail, it is clear that modifications and variations to the basic teachings of the present disclosure are withiLl the purview of one of ordinary skill in the art. To the extent that such variations and modifications result in a process for fabricating a halo region without the ill effects of shadowing among such are deemed within the scope of the present invention.

S. Choi 15-1-6-1-2

Claims (30)

What is Claimed:
1. A process for fabricating an fabricating an integrated circuit, the process comprising:
forming a raised feature over a substrate; and 5. implanting dopants at a substantially orthogonal angle relative to said substrate, said dopants not being implanted beneath said raised feature.
2. A process as recited in claim 1, wherein said raised feature includes a gate.
3. A process as recited in claim 1, wherein said gate has a length of 0.25 pm or less.
4. A process as recited in claim 2, wherein said gate has a hardmask formed thereover, and said hardmask prevents said dopants from entering said charmel.
5. A process as recited in claim 2, wherein said gate disposed over said substrate is separated from an adjacent gate by 0.35 = or less.
6. A process as recited in claim 2, wherein said implanting of said dopants forms a halo region.
7. A process -as recited in claim 6, wherein said halo region is disposed between a channel and a drain region.
8. A process as recited in claim 2, wherein an anneal step is performed to diffuse said dopants partially under said gate.
9. A process as recited in claim 1, wherein said substantially orthogonal angle is seven degrees or less relative to a normal to said substrate.
10. A process as recited in claim 7, wherein said drain region includes a lightly doped region adjacent said halo region.
11. A process as recited in claim 6, wherein said halo region is disposed between a channel and a source region.
12. A process as recited in claim 11, wherein said source region includes a lightly doped region.
8 S. Choi 15-1-6-1-2
13. A process for fabricating an integrated circuit, the process comprising:
forming at least two raised features over a substrate, said raised features having a spacing on the order of 0.35 pm or less; and implanting dopants at a substantially orthogonal angle to said substrate.
14. A process as recited in claim 13, wherein one of said at least two raised features include a gate.
15. A process as recited in claim 14, wherein said gate has a length of 0. 25 gm or Ims.
16. A process as recited in claim 14, wherein dopants are not implanted beneath said gate.
17. A process as recited in claim 16, wherein an anneal step is performed to diffuse said dopants partially under said gate.
18. A process as recited in claim. 14, wherein said dopants form a halo.
19. A process as recited in claira 18, wherein said halo is disposed between a channel and a drain region.
20. A process as recited in.claira 19, wherein said drain region includes a lightly doped region.
21. An integrated circuit, comprising:
a raised feature disposed over a substrate, said raised feature having a length of 0.25 pm or less; and a doped region disposed in said substrate and partially under said raised feature.
22. An integrated circuit as recited in claim. 21, wherein said raised feature includes a gate.
23. An integrated circuit as recited in claim. 22, wherein a channel is disposed in said substrate beneath said gate and said doped region is disposed between said channel and a drain region.
24. An integrated circuit as recited in claim 23, wherein said doped region is a halo and said drain region includes a lightly doped region.
9 S. Choi 15-1-6-1-2
25. An integrated circuit as recited in claim 21, wherein an adjacent raised feature is disposed over said substrate, said raised feature having a spacing of 0.35 pm or less.
26. An integrated circuit, comprising:
at least two raised features disposed over a substrate, said raised features having a spacing on the order of 0.35 pm or less; and doped regions disposed in said substrate, one of said doped regions being partially disposed under each of said raised features.
27. An integrated circuit as recited in claim 26, wherein one of said at least two raised features includes a gate.
28. An integrated circuit as recited in claim 27, wherein said gate has a length of 0.25 pm or less.
29. An integrated circuit as recited in claim 28, wherein said doped region partially disposed beneath said gate is a halo.
30. An integrated circuit as recited in claim 29, wherein said halo is between a channel and a drain region.
-
GB0026736A 1999-11-12 2000-10-30 Halo structure for use in reduced feature size transistor Withdrawn GB0026736D0 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16517999 true 1999-11-12 1999-11-12
US47838700 true 2000-01-06 2000-01-06

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GB0026736D0 GB0026736D0 (en) 2000-12-20
GB2362030A true true GB2362030A (en) 2001-11-07

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0535917A2 (en) * 1991-09-30 1993-04-07 Sgs-Thomson Microelectronics, Inc. Method for fabricating integrated circuit transistors
US5227321A (en) * 1990-07-05 1993-07-13 Micron Technology, Inc. Method for forming MOS transistors
US5328862A (en) * 1992-06-12 1994-07-12 Goldstar Electron Co., Ltd. Method of making metal oxide semiconductor field effect transistor
EP0607658A2 (en) * 1992-11-13 1994-07-27 AT&T Corp. MOSFET manufacture
US5504023A (en) * 1995-01-27 1996-04-02 United Microelectronics Corp. Method for fabricating semiconductor devices with localized pocket implantation
US5595919A (en) * 1996-02-20 1997-01-21 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned halo process for reducing junction capacitance
US5736446A (en) * 1997-05-21 1998-04-07 Powerchip Semiconductor Corp. Method of fabricating a MOS device having a gate-side air-gap structure
US5936278A (en) * 1996-03-13 1999-08-10 Texas Instruments Incorporated Semiconductor on silicon (SOI) transistor with a halo implant

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5227321A (en) * 1990-07-05 1993-07-13 Micron Technology, Inc. Method for forming MOS transistors
EP0535917A2 (en) * 1991-09-30 1993-04-07 Sgs-Thomson Microelectronics, Inc. Method for fabricating integrated circuit transistors
US5328862A (en) * 1992-06-12 1994-07-12 Goldstar Electron Co., Ltd. Method of making metal oxide semiconductor field effect transistor
EP0607658A2 (en) * 1992-11-13 1994-07-27 AT&T Corp. MOSFET manufacture
US5504023A (en) * 1995-01-27 1996-04-02 United Microelectronics Corp. Method for fabricating semiconductor devices with localized pocket implantation
US5595919A (en) * 1996-02-20 1997-01-21 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned halo process for reducing junction capacitance
US5936278A (en) * 1996-03-13 1999-08-10 Texas Instruments Incorporated Semiconductor on silicon (SOI) transistor with a halo implant
US5736446A (en) * 1997-05-21 1998-04-07 Powerchip Semiconductor Corp. Method of fabricating a MOS device having a gate-side air-gap structure

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Publication number Publication date Type
KR20010051564A (en) 2001-06-25 application
GB0026736D0 (en) 2000-12-20 grant
JP2001168332A (en) 2001-06-22 application

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