JP2001168332A - Halo structure used in transistor with feature of reduced size - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lightly doped drain(LDD) structure and to provide its manufacturing method. SOLUTION: While the influence of a shadowing operation is reduced by using a process by this invention, impurities are implanted selectively into an integrated circuit which features a reduced size. Concretely, the invention is used so that an implanted object of a halo structure is formed in a field-effect transistor which features a reduced size.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a halo structure and a method for manufacturing a halo structure.

[0002]

2. Description of the Related Art In integrated circuits, as the gate length is reduced, the effects of hot carriers cause metal oxide semiconductor field effect transistors (MOSFETs) to exhibit unacceptable operating characteristics. One way to reduce the effects of hot carriers is to use a lightly doped drain (lightly doped drain (LDD)) structure consistently. In an LDD structure, the source and the drain have a gradual doping characteristic. In the source and drain regions adjacent to the channel, the level of doping is lower,
Source and drain regions further away from the channel are relatively heavily doped. The heavily doped source and drain regions act to reduce the electric field in the channel region near the source and drain. The reduced electric field reduces hot carriers injected into the gate oxide covering the channel region and improves threshold stability.

[0003] Another problem that arises from reducing characteristic dimensions is the effect of short channels known as "punch-through". Punch-through is a phenomenon that occurs when a source region and a drain region come close to each other. As the channel length decreases, the edges of the source and drain depletion regions become closer. When the channel length is reduced to approximately the sum of the widths of the depletion layers at the two junctions in the substrate, the depletion regions come into contact. The contact of the depletion region causes punch-through of the carrier. When the carrier punch-through increases, it becomes difficult to control the charge, which impairs the functionality of the transistor.

One of the techniques for reducing punch-through is
This is a method of selectively doping regions adjacent to the source and drain depletion regions to opposite polarities. The above method is performed by coating and implanting impurity ions at an angle of incidence perpendicular to the substrate, and can reduce the problem of punch-through. For example, in an NMOS device, a p-type impurity is implanted into a p-channel. However, coating implants result in doping the channel to an unacceptable level. As a result, the threshold voltage increases, the mobility of carriers in the channel decreases,
The drive current becomes smaller.

Due to the potential drawbacks of coating injection that reduces the effects of punch-through, the structure shown in FIG. 5 has only recently been studied. The halo implant 503 comprises a lightly doped source region 50.
1 and the drain region 502. The above implants are performed by large angle implants, i.e., typically implanted into the substrate on the order of 30 degrees or more from a direction perpendicular to the substrate. Highly doped source and drain regions 506 and 50
Each uses a spacer as a mask during the formation of 7. Spacers 505 are formed on either side of the gate structure 508, and the gate structure 508 includes a gate oxide 509. The above selective arrangement of the halo-structured implant allows to reduce the effect of punch-through,
Prevents overdoping of the channel.

[0006]

The structure shown in FIG.
It has obvious advantages over cladding implants, but requires that the spacing or gate-to-gate spacing be further reduced in forming the device. As a result of the reduced spacing, adjacent structures, such as gate structures, can prevent the implant from reaching its intended location in the substrate. The effect of preventing the above injection is called shadowing as can be seen in FIG.

Referring to FIG. 6, a closely spaced gate structure 603 is shown. The spacing between gates (shown as structure-to-structure spacing "p") is reduced to achieve the required degree of integration. For example, if the gate length (shown as "w" in FIG. 6) is 0.
If on the order of 16 μm, the value of p is 0.2
It is on the order of 4 μm. The height (shown as "h") of a feature, such as gate structure 603, is approximately 0.
It is on the order of 5 μm. Therefore, due to the spacing between the structures and the relative height of the structures, the implant 601 at a relatively large angle with respect to the vertical will cause shadowing in the region 602 by the adjacent polysilicon gate 603. Cause. As a result of shadowing, halo-structured implants are not effectively placed in the shadowed regions 602, impairing the ability to reduce punch-through.

Accordingly, a halo-structured implant is formed in a lightly doped drain structure to effectively reduce punch-through without degrading device functionality in a transistor structure characterized by reduced dimensions. Technology is required.

[0009]

The present invention relates to a halo structure used in an integrated circuit and a manufacturing process thereof. According to one aspect of the invention, a raised feature is formed on a substrate. The implantation is performed at a small angle of incidence that is generally perpendicular to the substrate. In the implantation step, substantially no impurities are implanted in the region of the substrate just below the elevated feature. The present invention avoids the effects of shadowing on integrated circuits featuring reduced dimensions.

According to another aspect of the invention, 0.25 μm
Or a raised feature having a smaller order length is disposed on the substrate. A portion of the substrate is doped with a portion of the impurity that is partially disposed directly below the elevated feature.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS The invention can be best understood from the following detailed description when taken in conjunction with the accompanying drawings. It is noted that, according to semiconductor industry practices, various features are not necessarily drawn to scale. Indeed, the dimensions of the various features have been arbitrarily expanded or reduced to clarify the problem.

Briefly, the present invention relates to a lightly doped drain (LDD) structure and a method of making the same. In the exemplary embodiment shown in FIG.
Halo 303 is generated in MOSFET 100.
As can be seen, the MOSFET is a channel 108
Having a gate structure 108 disposed over the gate electrode 108. 303
Indicates a halo. The halo is formed using a small angle implantation step. Subsequently, an annealing step is performed to partially diffuse the impurities to the point indicated by 201 below the gate. The halo is located between the lightly doped source and drain regions 404 and 401 and the channel. The more heavily doped source and drain regions are 405 and 402, respectively.
Is shown in As discussed above, the small angle implant and anneal steps are characterized by reduced dimensions to avoid shadowing effects and unacceptable doping of the channel in devices with reduced spacing. Meanwhile, it is possible to form a halo. For illustrative purposes, the gate length can be 0.25 μm or smaller, and the spacing between adjacent gate structures is 0.35 μm or less.

Although the illustrative embodiment is illustrated for an NMOSFET, the principles of the present invention are used to form an implant that is selectively located in an integrated circuit where shadowing is required to be avoided. It is also possible. For example, the principles of the present invention can be used with BiCMOS devices and field effect devices, including CMOS devices, and, needless to say, those skilled in the art will be able to use the principles of the present invention with other structures. It is possible. Metal-semiconductor field-effect transistors (MESFETs) such as high electron mobility transistors (HEMTs) and two-dimensional electron gases
It is possible to use the principles of the present invention in field effect devices, including (2DEG) devices. Furthermore, while gates and gate structures have been given as examples of raised features, shadowing due to other raised features used in integrated circuits and their fabrication processes has been described. It is also possible to use the principles of the present invention to avoid it.

Referring to FIG. 1, a substrate 101 has a gate dielectric 102 and a gate 103 formed thereon. The hard mask is shown at 104. An implant for forming a p-type halo structure is shown at 105. In an exemplary embodiment, the angle of incidence of the implant is substantially perpendicular to the substrate surface 110, and for convenience of explanation, the angle of the implant is on the order of 0-7 ° with respect to the direction perpendicular to the substrate 110. . The first implantation step shown in FIG. 1 results in a p-type halo implant region in which the implant covers the substrate and, as shown at 106, covers the channel region. 108.

For convenience of explanation, substrate 101 is a semiconductor of silicon, germanium arsenide, silicon germanium, or other suitable material. Further, for convenience of explanation, the substrate is assumed to be p-type, and therefore the halo implant is also p-type. P-type halo implant 107
Are formed by standard ion implantation techniques, but other techniques can be used to form the halo structure. As an example, 5 × 10 with 15 keV energy
Implanting p-type ions ₂ such as boron or BF at a dose of ¹² / cm ^2. In the embodiment shown in FIG. 1, a suitable hard mask 104 is one in which a p-type implant is
It functions as an implantation mask for preventing doping of the element 08. Thus, it is possible to avoid the problem that the channel is more heavily doped by the coating injection.

The implantation step of the present invention is particularly useful for forming halo regions in LDDs having reduced gate lengths and reduced spacing. For example, if the gate length is 0.2
If the gate structure has a height on the order of 5 μm, the spacing on the order of 0.35 μm and the gate structure on the order of 0.5 μm, the shadowing effect discussed above is particularly detrimental to the formation of halo structures. Will.
Therefore, the functionality of the device is impaired. The implantation angle of the present invention allows the location of the impurities to be selected without considering the shadowing problem in structures with reduced spacing discussed above. Further, the diffusion step discussed below is useful in selecting the location of impurities to form a halo structure.

It should be noted that the gate length, spacing, and height dimensions are merely exemplary, and that it is possible to apply the present invention to smaller sized structures. Needless to say. For example,
Using the present invention, a gate length of 0.16 μm and 0.2
It is possible to substantially avoid the problem of shadowing in devices having 4 μm spacing and gates stacked at a height of 0.5 μm. Again, the above dimensions are for illustration and not limitation. However, it is envisaged to use the present invention in integrated circuits having gate lengths of 0.10 μm, smaller spacings and gate stack heights determined by rules of scale well known to those skilled in the art. After all,
The term spacing herein refers to the spacing between two or more raised structures.

After the implantation step of the exemplary embodiment of FIG. 1, the halo region is extended by a lateral diffusion step. In the exemplary embodiment shown in FIG. 2, the halo implant is extended laterally to a point 201 below the gate oxide 102. In practice, the diffusion step described above is performed by a rapid thermal anneal (RTA) step. The rapid thermal anneal method allows for proper control of the depth of diffusion, and its heat build-up is smaller compared to other selectable technologies. As an example, the RTA method is performed at a temperature of 950 ° C. for a length of 10 to 20 seconds. By the annealing step, the implant 303 having the p-type halo structure is expanded laterally to the point 201. Therefore,
An oppositely doped halo structure can be effectively placed between the channel 108 and the lightly doped source and drain regions. This ensures proper placement of the longitude doped drain regions and the lightly doped source regions.

FIG. 3 shows the formation of a lightly doped source and drain region by standard ion implantation 300. In this exemplary embodiment, the device is an NMOSFET and is implanted with n-type impurities to form lightly doped sources and drains. As can be seen in FIG. 3, the lateral diffusion of the p-type halo region completely to the point 201 below the gate oxide 102 results in a lightly doped drain region 301 and a lightly doped source region 304. It becomes possible to form a halo structure very close to the halo structure. After all, the halo structure of the present invention differs from a conventional halo structure because it may include a lower region 302. The lower region 302 described above is inevitably generated due to the circumstances of the present invention in which a halo region is formed before forming an LDD region. As can be seen with reference to FIG. 5, this is in sharp contrast to prior art structures which form a halo structure after forming source and drain regions and spacers with a gradual doping profile. is there.

FIG. 4 shows an exemplary embodiment of the LDD structure of the present invention. For example, a doping step is performed by standard ion implantation to form a more heavily doped source region 402 and a more heavily doped drain region 405, respectively. The above doping step uses a conventional spacer 403 and a hard mask 104 as a mask. If you are skilled in the art,
It will be appreciated that further processing can be performed.

Finally, as noted above, the selected exemplary embodiment is depicted for an NMOS device. In the above structure, the substrate is p-type,
The halo implant is p-type, the lightly doped drain and source regions are n-type, and the heavily doped source and drain regions are n-type. The concentration of doping is generally at a standard level as will be appreciated by those skilled in the art. The halo implantation is, for example, at least 1 × 10 ¹⁶ and may be as large as 1 × 10 ¹⁸ . Finally, it is possible to fabricate PMOS devices using the present invention. PMOS device is NM
It is essentially identical in structure to an OS device and can be manufactured in a substantially similar manner. Of course, in NMOS devices, the conductivity or polarity of the substrate, channel, lightly doped source and drain regions, heavily doped source and drain regions, halo implants, etc. are, of course, reversed. No.

Although the present invention has been described in detail, it is to be understood that modifications and alterations to the basic description herein are within the purview of those skilled in the art.
it is obvious. To the extent that the above modifications and alterations are attributable to the process of forming a halo region without the deleterious effects of shadowing, it is understood to be within the scope of the present invention.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an exemplary embodiment of the present invention showing halo implantation.

FIG. 2 is a cross-sectional view of an exemplary embodiment of the present invention showing lateral diffusion due to thermal annealing.

FIG. 3 is a cross-sectional view of an exemplary embodiment of the present invention showing the configuration of lightly doped source and drain regions.

FIG. 4 is a cross-sectional view of an exemplary embodiment of the present invention showing source and drain regions having a gradual doping profile with halo regions.

FIG. 5 is a cross-sectional view of a prior art transistor performing cladding injection.

FIG. 6 is a sectional view of a prior art structure.

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Timothy Edward Doyle United States 32822 Florida, Orlando, Gatlin Avenue 722 5785 (72) Inventor Troy A. Guinieck United States 34746 Florida, Kissimmee, North Stewart Street 2353 (72) Inventor Amal Ma Hamad United States 32828 Florida, Orlando, Fitzwilliam Way 507 (72) Inventor Pie etch E United States 32837 Florida, Orlando, Osprey Links Road 14024

Claims (30)

[Claims] 1. A method of manufacturing an integrated circuit, comprising: forming a raised feature on a substrate; and implanting an impurity at an angle substantially perpendicular to the substrate. The method wherein the impurities are not implanted under the raised features. 2. The method of claim 1, wherein the raised feature comprises a gate. 3. The method of claim 2, wherein said gate has a length of 0.25 μm or less. 4. The method of claim 2, wherein the gate has a hard mask formed thereon, the hard mask preventing the impurity from being implanted into the channel. 5. The method according to claim 2, wherein the gate disposed on the substrate is located at a distance of 0.3 from an adjacent gate.
Methods separated by 5 μm or less. 6. The method according to claim 2, wherein the impurity is implanted to form a halo region. 7. The method of claim 6, wherein said halo region is located between a channel and a drain region. 8. The method of claim 2, wherein an annealing step is performed to partially diffuse said impurities under said gate. 9. The method of claim 1, wherein the substantially perpendicular angle is 7 degrees with respect to a direction perpendicular to the substrate.
A method that is in degrees or smaller angles. 10. The method of claim 7, wherein said drain region comprises a lightly doped region adjacent said halo region. 11. The method of claim 6, wherein said halo region is located between a channel and a source region. 12. The method according to claim 11, wherein the source region comprises a lightly doped region. 13. A method of manufacturing an integrated circuit, the method comprising forming at least two raised features on a substrate, wherein the raised features include:
A method having a spacing on the order of 35 μm or less, the method further comprising implanting impurities at an angle substantially perpendicular to the substrate. 14. The method of claim 13, wherein one of the at least two raised features comprises a gate. 15. The method according to claim 14, wherein the gate has a length of 0.25 μm or less. 16. The method according to claim 14, wherein no impurities are implanted under the gate. 17. The method of claim 16, wherein an annealing step is performed to partially diffuse the impurities under the gate. 18. The method of claim 14, wherein said impurities form a halo structure. 19. The method of claim 18, wherein said halo structure is located between a channel and a drain region. 20. The method of claim 19, wherein said drain region comprises a lightly doped region. 21. An integrated circuit, comprising: a raised feature on a substrate; and a doped region disposed in the substrate and a portion below the raised feature. The raised feature is 0.25μ
An integrated circuit having a length of m or less. 22. The integrated circuit of claim 21, wherein said raised feature includes a gate. 23. The integrated circuit according to claim 22, wherein a channel is located in the substrate below the gate and the doped region is located between the channel and a drain region. . 24. The integrated circuit of claim 23, wherein said doped region has a halo structure and said drain region includes a lightly doped region. 25. The integrated circuit of claim 21, wherein adjacent raised features are disposed on the substrate, wherein the raised features have a spacing of 0.35 μm or less. Integrated circuit. 26. An integrated circuit, comprising at least two raised features disposed on a substrate, wherein the raised features have a height of 0.35 μm.
Or a smaller order spacing, wherein the integrated circuit comprises:
Further, an integrated circuit including a doped region disposed in the substrate, wherein one of the doped regions is partially disposed under each of the raised features. 27. The integrated circuit of claim 26, wherein one of said at least two raised features includes a gate. 28. The integrated circuit according to claim 27, wherein the gate has a length of 0.25 μm or less. 29. The integrated circuit according to claim 28, wherein the doped region partially disposed below the gate has a halo structure. 30. The integrated circuit according to claim 29, wherein said halo structure is located between a channel and a drain region.