A7 B7 45 59 3 2 4952twf.doc/006 五、發明說明（/) 本發明是有關於一種金氧半電晶體的製造方法，且特 別是有關於一種降低源極/汲極的接合電容unc t 1 on Capacity)之金氧半電晶體的製造方法。 習知之金氧半電晶體的源極/汲極區爲具有淡摻雜汲 極（LDD)的結構，以改善通道的熱電子效應。而其製造 方法係於閘極側壁的間隙壁形成之前進行低劑量的離子 摻雜，以做爲LDD的部份，之後，再於間隙壁形成之後進 行高劑量的離子摻雜，以做爲源極/汲極區的主體。其中 第一次的離子摻雜之劑量係爲l〇n至10”之間，而第二次 的離子摻雜之劑量則爲1〇15以上。由於具有高劑量離子濃 度的源極/汲極區與基底（或井區）的接面之間存在有接 合電容（Junction Capacitance)，且隨著其劑量的增加 會增加此接合電容，進而降低閘極的二極體（Gated diode)之崩潰電壓，因而影響元件的工作效能，嚴重時 甚至會使元件失效。 因此，本發明提供一種可以降低源極/汲極區與基底 (或井區）的接合電容之金氧半電晶體的製造方法，以提 高元件的工作效能。 本發明提供一種金氧半電晶體的製造方法，包括：於 基底上形成閘極，並於閘極的側壁形成間隙壁，之後，以 閘極和間隙壁爲離子植入罩幕，進行離子植入製程，於基 底中形成一淡摻雜區，以做爲金氧半電晶體的源極/汲極 區，其中所植入的劑量約介於1〇13/每平方公分至1015/每 平方公分之間，最後於閘極和淡摻雜區的表面形成金屬矽 3 (請先閲讀背面之注f項再填寫本頁) -----r I--訂 — I I I I---^ 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 455932 4 952twf. doc/Ο06 五、發明說明（i) 化物層。 此外，離子植入製程亦可於間隙壁形成之前進行。或 者於間隙壁形成之前和之後均進行離子植入製程，雖然在 此情況下，第一次和第二次的離子植入製程所植入的劑量 均約介於10"/每平方公分至1015/每平方公分之間，但第 二次離子植入製程所植入的劑量小於第一次離子植入製 程所植入的劑量。由於所形成的源極/汲極區具有較低的 離子濃度，故使得源極/汲極區到基底之間的雜散電容因 而降低，藉以增加閘極的二極體之崩潰電壓，以提高元件 的效能。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A圖至第1E圖係繪示根據本發明一較佳實施例之 一種金氧半電晶體的製造流程剖面圖； 第2圖係繪示根據本發明另一較佳實施例之一種金氧 半電晶體的剖面圖；以及 第3圖係繪示根據本發明另一較佳實施例之一種金氧 半電晶體的剖面圖。 其中，各圖標號與構件名稱之關係如下·· 10〇:基底 102 :井區 104 :淺溝渠隔離結構 4 F 裝 - ---„----訂------ ·線 _一 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） 4 5 5 94^2^ f. doc/006 A7 4 5 5 94^2^ f. doc/006 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（多） 106 :閘極氧化層 108 :閘極電極 110、114 :輕摻雜源極/汲極區 112 :間隙壁 116 :矽化金屬層 實施例 第1A圖至第1E圖所示，爲根據本發明一較佳實施例 之一種金氧半電晶體的製造流程剖面圖。 首先請參照第1A圖，提供一基底1〇〇，比如是半導體 矽基底，於基底100中形成元件隔離結構，比如淺溝渠隔 離結構104、場氧化層等（在此實施例係以前者爲圖例）， 用以定義出元件的主動區。之後於基底100中的主動區形 成井區102，比如是P井或N井，視實際的需要而定。接 著，進行啓始電壓（Threshold Voltage)的調整，比如 於井區102中摻雜一定濃度、一定深度和一定範圍的離 子，由於此非關本發明，在此不多贅言。之後，於基底100 的表面形成一層閘極氧化層106，其方法比如是熱氧化 法。 接著請參照第1B圖，於閘極氧化層106上形成一閘 極108，其材質比如是摻雜的複晶矽，其方法比如是於閘 極氧化層106上覆蓋一層摻雜的複晶矽層，之後再將其圖 案化。 接著請參照第1C圖，以閘極108和淺溝渠隔離結構 104爲離子植入罩幕，進行離子植入製程’以於閘極1〇8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） {靖先閱讀背面之注意事項再填寫本頁} 裝-----^----訂·！-----線- A7 B7 4 5 5 〇9^t这 .doc/006A7 B7 45 59 3 2 4952twf.doc / 006 V. Description of the invention (/) The invention relates to a method for manufacturing a metal-oxide semiconductor transistor, and in particular to a method for reducing the source / drain junction capacitance unc t 1 on Capacity) metal oxide semiconductor semi-transistor manufacturing method. The source / drain region of a conventional metal-oxide semiconductor transistor has a lightly doped drain (LDD) structure to improve the hot electron effect of the channel. The manufacturing method is to perform low-dose ion doping as a part of the LDD before forming the gap on the side wall of the gate, and then to do high-dose ion doping as the source after forming the gap. The body of the pole / drain region. The dose of the first ion doping is between 10n and 10 ", and the dose of the second ion doping is more than 1015. Due to the source / drain with high dose ion concentration There is a junction capacitance between the junction between the area and the substrate (or well area), and this junction capacitance will increase with the increase of its dose, thereby reducing the breakdown voltage of the gated diode. Therefore, the working efficiency of the device is affected, and the device may even be failed in severe cases. Therefore, the present invention provides a method for manufacturing a metal-oxide-semiconductor that can reduce the junction capacitance between the source / drain region and the substrate (or well region). The invention provides a method for manufacturing a metal oxide semiconductor transistor. The method includes: forming a gate electrode on a substrate, forming a gap wall on a side wall of the gate electrode, and then using the gate electrode and the gap wall as ion implants. Into the mask, an ion implantation process is performed to form a lightly doped region in the substrate as the source / drain region of the metal-oxide semiconductor transistor. The implanted dose is about 1013 / each Cm2 to 1015 / each Between the square centimeter, and finally the metal silicon 3 is formed on the surface of the gate and the lightly doped region (please read the note f on the back before filling this page) ----- r I--Order— III I --- ^ Printed by the Intellectual Property Bureau of the Ministry of Economy ’s Consumer Cooperatives This paper is printed in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm) Printed by the Employee ’s Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 455932 4 952twf. Doc / 〇06 V. Invention Note (i) The compound layer. In addition, the ion implantation process can be performed before the formation of the gap wall. Or the ion implantation process can be performed before and after the formation of the gap wall, although in this case, the first and second times The implanted dose of the ion implantation process is about 10 " / per square centimeter to 1015 / per square centimeter, but the dose implanted in the second ion implantation process is less than that in the first ion implantation process. Implanted dose. Because the formed source / drain region has a lower ion concentration, the stray capacitance from the source / drain region to the substrate is reduced, thereby increasing the gate diode. Breakdown voltage to improve component performance In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A to FIG. 1E is a cross-sectional view showing a manufacturing process of a metal-oxide-semiconductor crystal according to a preferred embodiment of the present invention; FIG. 2E is a metal-oxide-semiconductor crystal according to another preferred embodiment of the present invention; And FIG. 3 is a cross-sectional view of a metal-oxide semiconductor transistor according to another preferred embodiment of the present invention. Among them, the relationship between each icon number and the component name is as follows: 10: substrate 102: well Zone 104: Shallow ditch isolation structure 4 F installed---- „---- Order ------ · Line_One (Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS) A4 specifications (210 * 297 mm) 4 5 5 94 ^ 2 ^ f. Doc / 006 A7 4 5 5 94 ^ 2 ^ f. Doc / 006 A7 Description of the invention (multiple) 106: gate oxide layer 108: gate electrode 110, 114: lightly doped source / drain region 112: gap 116: a metal silicide layer to the embodiment shown in FIGS. 1A-1E of FIG, according to manufacturing process cross-sectional view of an embodiment of the metal oxide semiconductor transistor in a preferred embodiment of the present invention. First, please refer to FIG. 1A to provide a substrate 100, such as a semiconductor silicon substrate, to form an element isolation structure in the substrate 100, such as a shallow trench isolation structure 104, a field oxide layer, etc. (the former is a legend in this embodiment) ), Used to define the active area of the component. The active area in the substrate 100 is then used to form a well area 102, such as well P or N, depending on actual needs. Next, the threshold voltage is adjusted, such as doping a certain concentration, a certain depth, and a certain range of ions in the well region 102. Since this is not related to the present invention, it will not be repeated here. After that, a gate oxide layer 106 is formed on the surface of the substrate 100, such as a thermal oxidation method. Next, referring to FIG. 1B, a gate 108 is formed on the gate oxide layer 106. The material of the gate electrode 108 is, for example, doped polycrystalline silicon. The method is to cover the gate oxide layer 106 with a doped polycrystalline silicon. Layer and pattern it later. Then please refer to FIG. 1C, and use the gate 108 and the shallow trench isolation structure 104 as ion implantation masks to perform the ion implantation process' on the gate 10. This paper size applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) {Jing first read the precautions on the back before filling out this page} Install ----- ^ ---- Order ·! ----- line- A7 B7 4 5 5 〇9 ^ t this .doc / 006
五、發明說明（LM 兩側的基底100中形成低濃度的摻雜區（簡稱淡摻雜區） 110，其中植入的劑量約介於1〇13原子/平方公分至10”原 子/平方公分之間。 接著請參照第1D圖，於閘極108的側壁形成間隙壁 112，其材質比如是氧化矽或氮化。 在此實施例中僅進行一次的低劑量之離子植入製 程，並以所形成之淡摻雜區110做爲金氧半電晶體的源極 /汲極區，使得源極/汲極區到井區102之間的接合電容因 而降低，藉以增加閘極的二極體（Gated diode)之崩潰 電壓（Breakdown Voltage)，以提高元件的效能。 接著請參照第1E圖，進行自動對準金屬矽化物製程， 於閘極108的表面和淡摻雜區110所裸露出的表面形成矽 化金屬層116,其材質比如是矽化鈦（TiSi)、矽化鈷 (CoSi)、矽化鎳（NiSi)或矽化鉑（PtSi)，以矽化鈦 爲例，其形成方法比如是於晶片表面覆蓋一層鈦金屬層， 之後進行快速熱回火製程，以使鈦金屬和矽原子反應成矽 化鈦，最後再將未反應的鈦金屬予以剝除。 在上述的例子中，低劑量的離子植入製程係於間隙壁 112形成之前進行，當然，此低劑量的離子植入製程亦可 於間隙壁Π2形成之後進行。其方法係爲以間隙壁H2、 閘極108和淺溝渠隔離結構104爲離子植入罩幕’進行低 劑量的離子植入製程，以於閘極108兩側的間隙壁112外 之基底100中形成低濃度的摻雜區（簡稱淡摻雜區）114 ’ 其中植入的劑量約介於10"原子/平方公分至1〇15原子/平 6 本紙張尺度適用中因國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意ί項再填寫本頁) 褒-----U1I 訂·！ ！！ ·線· 經濟部智慧財產局員工消費合作社印製 oc/006 A7 B7 五、發明說明（f) 方公分之間，而後經自動對準金屬矽化物製程所製得之金 氧半電晶體的剖面圖如第2圖所示。以此方法所製得之金 氧半電晶體，除了亦可降低淡摻雜區Π4(即源極/汲極 區）到井區102之間的接合電容外，與第1Ε圖相較’還 具有較長的通道長度，且其通道長度可藉由間隙壁Π2之 底部寬度的控制而做調整。 再者，若爲了進一步降低源極/汲極區的電阻，亦可 以進行兩次的低劑量之離子植入製程，第一次的低劑量之 離子植入製程係於間隙壁112形成之前進行，於基底1〇〇 中形成淡摻雜區110，所植入的劑量約介於ίο13原子/平方 公分至10”原子/平方公分之間；而第二次的低劑量之離 子植入製程係於間隙壁112形成之後進行，於基底100中 形成另一淡摻雜區114,所植入的劑量約介於1013原子/ 平方公分至101S原子/平方公分之間，値得注意的是，第 二次低劑量離子植入製程所植入的劑量係小於第一次低 劑量離子植入製程所植入的劑量。而後經自動對準金屬矽 化物製程所製得之金氧半電晶體的剖面圖如第3圖所示。 本發明的優點爲，本發明所形成的源極/汲極區爲低 濃度的摻雜區，故可以降低源極/汲極區到井之間的接合 電容，藉以增加閘極的二極體之崩潰電壓，以提高元件的 效能。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 7 本紙張尺度適用+國@家標準（CNS)A4規格（21CU 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 ill·---訂 ------*線 * 經濟部智慧財產局員工消費合作社印製V. Description of the invention (low concentration doped regions (shortly doped regions) 110 are formed in the substrate 100 on both sides of the LM, wherein the implanted dose is about 1013 atoms / cm 2 to 10 ”atoms / cm 2 Next, referring to FIG. 1D, a spacer 112 is formed on the side wall of the gate 108, and the material is, for example, silicon oxide or nitride. In this embodiment, a low-dose ion implantation process is performed only once, and The lightly doped region 110 formed is used as the source / drain region of the metal-oxide semiconductor, so that the junction capacitance between the source / drain region and the well region 102 is reduced, thereby increasing the gate diode. (Breakdown Voltage) of the gated diode to improve the performance of the device. Next, please refer to FIG. 1E to perform an automatic alignment metal silicide process on the surface of the gate 108 and the lightly doped region 110. A silicide metal layer 116 is formed on the surface. The material is, for example, titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), or platinum silicide (PtSi). Taking titanium silicide as an example, the formation method is, for example, covering the surface of the chip. A layer of titanium, followed by rapid Tempering process to make titanium metal and silicon atoms react to form titanium silicide, and finally strip unreacted titanium metal. In the above example, the low-dose ion implantation process is performed before the formation of the spacer 112, Of course, this low-dose ion implantation process can also be performed after the formation of the spacer Π2. The method is to use the spacer H2, the gate 108 and the shallow trench isolation structure 104 as the ion implantation mask to perform low-dose ions An implantation process to form a low-concentration doped region (shortly doped region) 114 in the substrate 100 outside the gap wall 112 on both sides of the gate 108, wherein the implanted dose is about 10 " atoms / cm2 Up to 1015 atoms / flat 6 The paper size is applicable due to the national standard (CNS) A4 specification (210 X 297 mm) (Please read the note on the back before filling this page) 褒 ----- U1I Order ·！！ · Line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs oc / 006 A7 B7 V. Description of the invention (f) Between the centimeters, and then automatically aligned with the metal and silicide produced by the metal silicide process The cross-sectional view of the transistor is shown in Figure 2. The gold-oxygen semitransistor produced by the method can reduce the junction capacitance between the lightly doped region Π4 (that is, the source / drain region) and the well region 102. Compared with FIG. Long channel length, and its channel length can be adjusted by controlling the width of the bottom of the spacer Π2. Furthermore, in order to further reduce the resistance of the source / drain region, two low-dose ions can also be performed. The implantation process. The first low-dose ion implantation process is performed before the formation of the gap wall 112, and a lightly doped region 110 is formed in the substrate 100. The implanted dose is about 13 atomic centimeters per square centimeter. To 10 ”atoms / cm²; and the second low-dose ion implantation process is performed after the formation of the spacer 112, and another lightly doped region 114 is formed in the substrate 100. The implanted dose is about Between 1013 atoms / cm² and 101S atoms / cm², it should be noted that the dose implanted in the second low-dose ion implantation process is less than that implanted in the first low-dose ion implantation process. The dose. The cross-sectional view of the metal-oxide-semiconductor crystal produced by the automatic alignment metal silicide process is shown in FIG. 3. The advantage of the present invention is that the source / drain region formed by the present invention is a low-concentration doped region, so the junction capacitance between the source / drain region and the well can be reduced, thereby increasing the gate diode. The breakdown voltage to improve the performance of the device. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. 7 This paper size is applicable to + China @ 家 standard (CNS) A4 specification (21CU 297mm) (Please read the precautions on the back before filling this page) ill · --- order ------ * 线 * Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs