TW476883B - Data processing device - Google Patents
Data processing device Download PDFInfo
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- TW476883B TW476883B TW088113540A TW88113540A TW476883B TW 476883 B TW476883 B TW 476883B TW 088113540 A TW088113540 A TW 088113540A TW 88113540 A TW88113540 A TW 88113540A TW 476883 B TW476883 B TW 476883B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/329—Power saving characterised by the action undertaken by task scheduling
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Accessory Devices And Overall Control Thereof (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
Description
經濟部智慧財產局員工消費合作社印製 476883 A7 B7 五、發明說明(1 ) 技術領域 本發明係有關於一種可以並列地進行資料處理的資料 處理裝置,特別是有關於一種適合於例如進行錯誤訂正之 S I M D ( Single Instruction stream Multiple Data stream )型的資料處理裝置。 背景技術 在處理硬碟、C D — R 〇M ( Compact Disc-Read Only Memory )、D V D ( Digital Video Disc )、光磁碟等之 記錄媒體的資料記錄裝置等,乃使用能夠訂正在媒體中所 產生之記錄/讚取之錯誤的編碼語。編碼語則是根據例如 被稱爲伽羅瓦體(Galois field )之特殊的數的集合及與此 一起被定義之特殊的演算所定義。伽羅瓦體之數的集合根 據以被稱爲原始多項式的數的集合作爲定義的多項式,會 有多種的定義,同時,演算也會根據原始多項式而有不同 的定義。最常被使用的編碼語則有理得索羅門(Reed Solomon )碼,特別是當作在錯誤容易集中在一部分之資料 的儲存系統或是通信系統的錯誤訂正碼來使用。 錯無δ了正處理’則包含從所輸入之編碼語來計算療候 (Syndrome )的步驟,從癥候來演算錯誤位置多項式與錯 誤數値多項式的步驟,從錯誤位置多項式來求取錯誤位置 的步驟、從錯誤位置多項式與錯誤數値多項式來求取錯誤 數値的步驟、以友訂正錯誤的步驟。 由於是從儲存系統或是記錄_系統的媒體或是通信系統 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) iw— — — · — !· 裝 1! — 1 訂 —— ί!-線赢 (請I閱讀背夂面之注意事項再填寫本頁) -4- 476883 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(2 ) 的傳送路徑連續地接受到編碼語而處理,因此,用於包含 該錯誤訂正在內之資料處理所允許的時間,則是根據資料 的讀取速度以及受信速度等來決定。因此,乃對進行錯誤 訂正的電路要求某種程度的資料處理能力。由該觀點來看 ,利用S IMD型處理器等可以進行錯誤訂正。 但是近年來,如眾所皆知,不僅筆記型的個人電腦, 連利用A C電源之桌上型個人電腦,則也期待要降低消耗 電力。而將來對於以S I MD型式來進行錯誤訂正的電路 ,也不免要求降低消耗電力。 本發明人等在演算處理的性質上乃發現,即使不得不 利用並列演算處理來提高處理能力,在資料處理的某方面 ,也有可以不完全利用其所具備之全部的資料處理能力的 情形。例如,當上述錯誤訂正處理能力頻頻發生錯誤時, 則必須要應付,但是相反地當較少發生錯誤時,則可以幾 乎不需要進行上述錯誤訂正步驟。 基於該觀點之降低消耗電力的技術則被記載在特開平 9 — 18 5 5 8 9號公報中。而在此則記載了針對具有‘ Μ I MD ( Multiple Instruction stream Multiple Data stream )型並列處理器與電源供給控制器之資料處理裝置 進行任務分配,一邊維持所需要的處理力,且一邊對處於 休息狀態的處理器停止供給電源,而達成省電。然而,如 此所設定之電源控制必須要有〇S (〇p e r a t i n g S y s t e m ), 而使得控制變得非常的複雜。 在特開平9 - 7 3 7 0 9號公報中則記載有在錯誤訂 本紙張K度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) ▼裝----— II訂------|!線齡 -5- 476883 A7 B7 五、發明說明(3 ) 正電路,對於未檢查出錯誤符號(symbol )的資料,則不 進行以後的計算處理,而不對該資料區段(data block )供 給控制信號及時脈。該控制係根據進行錯誤訂正之電路本 身的判斷,而部分地停止供給時脈,在處理上,由於處理 沒有錯誤之資料的電路部分,此時不需要進行實質的動作 ,因此必然地連時脈信號等也停止供給,而此會降低消耗 電力。該技術並不是控制使錯誤訂正電路的訂正處理能力 產生變化,而只不過是根據處理內容,而呈動態地來控制 時脈信號的供給而已。針對未檢查出錯誤符號的情形,貝1J 錯誤訂正的處理能力不會改變。在特開平9 一 1 4 7 4 8 號公報,雖然也同樣地在處理上部分地抑止不必要的動作 ,而減低消耗電力,但是電路之處理能力本身則保持一定 。針對於演算處理能力的控制與對消耗電力的控制等兩者 ,則未加以考慮。 更者,在W0 9 9/1 4 6 8 5號則記載有錯誤訂正 使用S I M D型處理器的例子。記載於此的技術,則是讓 從控制部,將用於演算動作的控制資訊給予多個的資料處 理部,而令該些進行並列動作的S I MD型的處理器,具 有可根據資料處理部的演算結果,將資料處理部設成待機 狀態的待機控制手段,而由上述控制部進行讓各資料處理 部,從待機狀態恢復到活性狀態的控制。在待機狀態下, 則停止對資料處理部的演算電路供給時脈。因此,對於處 理沒有錯誤之資料的資料處理部,當其他的資料處理部在 執行錯誤訂正步驟時,則可以設成待機狀態。另一方面, 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閲讀背面之注意事項再填寫本頁) π裝--------訂-------線| 經濟部智慧財產局員工消費合作社印製 476883 Α7 Β7 五、發明說明(4) (請先閱讀背面之注意事項再填寫本頁) 當可以將全部的資料處理部設成待機狀態時,則控制部會 消除該待機狀態,而先讓各資料處理部執行下一個步驟, 藉此,很容易將因爲資料處理部的待機狀態所造成之無謂 (浪費)的週期抑制成最小限度,而可以根據s I M D形 式來提高並列演算處理性能。 該技術,若是基於低消耗電力的觀點,則與上述習知 技術同樣地,並不是控制使錯誤訂正電路之訂正處理能力 改變,而只不過是可以根據處理內容,呈動態地來控制時 脈信號的供給情形。當未檢查出錯誤時,則錯誤訂正的處 理能力不會改變。 本發明的目的則在於提供一種可以根據外部條件來控 制呈並列之資料處理部的資料處理能力及消耗電力的資料 處理裝置。 本發明之其他的目的則在於提供一種很容易控制呈並 列之資料處理部的資料處理能力及消耗電力的資料處理裝 置。 本發明之上述以及其他的目的與新的特徵,可以根據 本說明書以下的記載以及所附圖面而明白。 經濟部智慧財產局員工消費合作社印製 發明的揭露 〔1〕本發明之資料處理裝置的第1觀點,則設有可 以根據來自外部的指示,而保有控制資料的控制暫存器, 且由並列度控制部,根據由上述控制暫存器所保有的控制 資料,來決定多個資料處理部之並列動作的並列度。如此 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 476883 A7 _ B7 五、發明說明(5 ) ’藉著根據外部條件來控制資料處理部的並列度,很容易 根據外部狀況來控制資料處理裝置的處理能力及消耗電力 〇 上述並列度的控制,可以藉由對於資料處理部之時脈 信號的供給•停止的控制而實現。亦即,上述多個的資料 處理部則同步於從時脈產生電路所輸出之時脈信號而動作 請 先 閱 讀 背 面 之 注 意 經濟部智慧財產局員工消費合作社印製 上述並列度控制部具有可將上 上述資料處理部的選擇閘,而上述 資料,來決定是否要輸出時脈信號_ 〔$〕本發明之資料處理裝置 個可同步於時脈信號而動作的資料 ,設有可根據來自外部之指示,而 存器、以及可根據由上述控制暫存 來決定上述時脈信號之頻率的速度 部會根據由控制資料所指定的分頻 率。如此般,根據外部條件來控制 ,很容易根據外部狀況來控制資料 及電力消耗。 〔3〕本發明之資料處理裝置 部來控制資料處理部的並列度與動 由包含可同步於時脈信號而進行並 理部、根據來自外部的指示,而保 控制暫存器、根據來自外部的指示 述時脈信號分別供給到 選擇閘會根據上述控制 的第2 處理部 保有控 器所保 控制部 比來決 資料處 處理裝 觀點,在 的資料處 制資料的 有之控制 。例如速 定時脈信 理部的動 置的處理 具有多 理裝置 控制暫 資料, 度控制 號的頻 作速度 能力以 的第3觀點,可以從外 作速度兩者。亦即,係 列動作之多個的資料處 有第1控制資料的第1 ,而保有第2控制資料 項Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 A7 B7 V. Description of the Invention (1) Technical Field The present invention relates to a data processing device capable of processing data in parallel, and in particular, to a data processing device suitable for, for example, error correction. SIMD (Single Instruction stream Multiple Data stream) type data processing device. 2. Description of the Related Art A data recording device for processing a recording medium such as a hard disk, a CD-ROM (Compact Disc-Read Only Memory), a DVD (Digital Video Disc), or a magneto-optical disk, etc., is produced by using a data recording device The wrong code for recording / praising. Coding terms are defined based on, for example, a collection of special numbers called Galois fields and special calculations defined with them. The set of Galoisian numbers has multiple definitions based on the set of numbers called primitive polynomials as definitions. At the same time, calculations also have different definitions based on primitive polynomials. The most commonly used code is the Reed Solomon code, especially used as an error correction code in a storage system or communication system where errors are easily concentrated in a part of the data. There is no error δ positive processing 'includes the step of calculating the Syndrome from the input code words, the step of calculating the error position polynomial and the error number polynomial from the symptoms, and the error position polynomial to obtain the error position. Steps, a step of obtaining the error number from the error position polynomial and the error number polynomial, and a step of correcting the error with a friend. Since it is from the storage system or the recording medium of the system or the communication system, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) iw — — — — —! · Pack 1! — 1 Order—— ί! -Line Win (Please read the precautions on the back side and fill in this page) -4- 476883 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs 2) The transmission path continuously receives the code word for processing. Therefore, the time allowed for the data processing including the error correction is determined according to the reading speed and the receiving speed of the data. Therefore, a certain degree of data processing capability is required for the circuits for error correction. From this point of view, error correction can be performed using an S IMD type processor or the like. However, in recent years, it is well known that not only notebook personal computers but also desktop personal computers using AC power are also expected to reduce power consumption. In the future, for circuits that perform error correction using the SI MD type, it will inevitably require a reduction in power consumption. The present inventors have discovered in the nature of calculus processing that even if parallel calculus processing has to be used to improve processing power, in some aspects of data processing, there may be cases in which all the data processing capabilities that they have may not be fully utilized. For example, when the above error correction processing capability frequently makes errors, it must be dealt with, but on the contrary, when fewer errors occur, the above error correction step may be almost unnecessary. A technique for reducing power consumption based on this viewpoint is described in Japanese Patent Application Laid-Open No. 9-18 5 5 89. Here, it is described that task allocation is performed on a data processing device having a parallel processing processor and a power supply controller of the Μ I MD (Multi Instruction stream Multiple Data stream) type, while maintaining the required processing power, and at the same time resting. The state of the processor stops supplying power, thereby achieving power saving. However, the power control set here must have 0S (〇 p er a t i n g S y s t e m), which makes the control very complicated. Japanese Patent Application Laid-Open No. 9-7 3 7 0 9 states that the paper used in the wrong version of the paper has a Chinese standard (CNS) A4 (210 X 297 mm). (Please read the precautions on the back before filling in this Page) ▼ Install ----— Order II ------ |! Wire Age-5- 476883 A7 B7 V. Description of the Invention (3) Positive circuit. For the data that does not check the error symbol, then No subsequent calculation processing is performed, and no control signal or clock is supplied to the data block. This control partly stops the clock supply based on the judgment of the circuit that performs the error correction. In processing, since the circuit part without the error data is processed, no substantial action is required at this time, so the clock is necessarily connected. Signals and the like are also stopped, which reduces power consumption. This technology does not control the correction processing capability of the error correction circuit, but only dynamically controls the supply of the clock signal according to the processing content. For cases where no error symbol is detected, the processing capability of Bay 1J error correction will not change. In Japanese Patent Application Laid-Open No. 9-1 4 7 4 8, although unnecessary operations are partially suppressed in the same manner, and power consumption is reduced, the processing capacity of the circuit itself remains constant. Regarding both the control of calculation processing power and the control of power consumption, etc., they are not considered. In addition, in W0 9 9/1 4 6 8 5 there is an example of error correction using an S I M D-type processor. The technology described here is to allow the control unit to give control information for calculation operations to a plurality of data processing units, and to make these SI MD processors that perform parallel operations have a data processing unit As a result of the calculation, the data processing unit is set to a standby control means in a standby state, and the above-mentioned control unit performs control to return each data processing unit from the standby state to the active state. In the standby state, the clock supply to the calculation circuit of the data processing section is stopped. Therefore, the data processing section that processes data without errors can be set to a standby state when other data processing sections are performing error correction steps. On the other hand, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page). ---- Line | Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 Α7 Β7 V. Description of the Invention (4) (Please read the precautions on the back before filling this page) When all data processing departments can be set to standby In the state, the control unit will eliminate the standby state and let each data processing unit execute the next step. By this, it is easy to suppress the unnecessary (waste) cycle caused by the standby state of the data processing unit to a minimum. , And can improve the performance of parallel calculus processing according to the s IMD form. If this technology is based on the viewpoint of low power consumption, like the conventional technology, it does not control the correction processing capability of the error correction circuit, but it can only dynamically control the clock signal according to the processing content. Supply situation. When no errors are detected, the error correction capability will not change. An object of the present invention is to provide a data processing device capable of controlling the data processing capacity and power consumption of a parallel data processing unit according to external conditions. Another object of the present invention is to provide a data processing device that can easily control the data processing capacity and power consumption of the parallel data processing units. The above and other objects and new features of the present invention will become apparent from the following description of the present specification and the attached drawings. Disclosure of inventions printed by employees' cooperatives in the Intellectual Property Bureau of the Ministry of Economic Affairs [1] The first aspect of the data processing device of the present invention is provided with a control register that can maintain control data in accordance with instructions from the outside. The degree control unit determines the degree of parallel operation of the parallel operations of the plurality of data processing units based on the control data held by the control register. In this way, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 476883 A7 _ B7 V. Description of the invention (5) 'By controlling the parallelism of the data processing department according to external conditions, it is easy to The status controls the processing capacity and power consumption of the data processing device. The above-mentioned parallelism can be controlled by controlling the supply and stop of clock signals to the data processing unit. That is, the above-mentioned multiple data processing units operate synchronously with the clock signal output from the clock generating circuit. Please read the note on the back first. The Ministry of Economic Affairs, Intellectual Property Bureau, Employee Consumption Cooperative printed the above-mentioned parallelism control unit. The selection gate of the above-mentioned data processing section is used to determine whether to output a clock signal. [$] The data processing device of the present invention can be operated in synchronization with the clock signal. Instructions, and the register, and the speed section that can determine the frequency of the clock signal according to the temporary storage by the control will be based on the divided frequency specified by the control data. In this way, it is easy to control data and power consumption according to external conditions to control according to external conditions. [3] The data processing device unit of the present invention controls the parallelism and movement of the data processing unit, and includes a parallel processing unit that can synchronize with a clock signal, and maintains a control register according to an instruction from the outside. The instruction clock signals are supplied to the selection gates respectively, and according to the control of the second processing section holding controller, the control section of the data processing unit determines the processing point of the data processing unit, and controls the data processing in the data processing system. For example, the third aspect of the processing of the speed of the timing pulse processing unit has a multi-processing device to control temporary data, and the frequency control speed of the degree control number. From the external point of view, the speed can be both. That is, the data place of the plurality of actions of the series has the first of the first control data, and the second control data item is kept
f 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -8 - 476883 A7 — ______ _____ B7 五、發明說明(6 ) 的第2控制暫存器、根據上述第1控制暫存器所保有的上 述第1控制資料,來決定根據上述多個的資料處理部之並 列動作的並列度的並列度控制部、以及根據上述第2控制 暫存器所保有的第2控制資料,來決定上述時脈信號之頻 率的速度控制部所構成。資料處理部之並列度的變更,適 於事先先於一連串的處理之前來控制。而此是因爲當在並 列演算處理的途中變更並列度時,則往往容易發生當初所 要處理之預定資料無法被處理之故。相較於此,對於時脈 頻率的變更,由於沒有變更程式的必要,因此,即使是在 一連串的處理途中,也可以進行。因此,藉著根據外部條 件來控制資料處理部的並列度與動作速度兩者,可以從外 部更精確地控制資料處理裝置的處理能力以及電力消耗。 〔4〕基於上述各觀點的資料處理裝置,可以更具體 地採用以下的構成。 當要處理預測被此要經過相同之資料處理步驟的多個 資料方塊時,則最好資料處理裝置採用S I M D形態。亦 即,更具有可對命令進行解讀,且輸出控制資訊之命令控 制部,而上述命令控制部,則呈並列地將用於演算動作的 控制資訊供給到上述多個的資料處理部。在將不同的處理 予以並列化時,上述資料處理裝置可以採用Μ I M D形式 〇 當採用S I MD形式時,則在資料處理裝置設置一已 儲存了進行錯誤訂正之錯誤訂正格式的程式記憶體,而上 述控制部,則從上述程式記憶體:得命令,而利用上述資 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閲讀背面之注意事項再填寫本頁) • mm— I mmt ----訂---------線| 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 476883 Α7 - Β7 五、發明說明(7 ) 料處理部來進行錯誤訂正處理。例如在上述資料處理部包 含可進行伽羅瓦體(Galois )之乘法與加法之伽羅瓦體演 算電路’上述控制部則控制上述伽羅瓦體演算電路,而讓 資料處理部進行錯誤訂正處理。 又,上述SIMD型的資料處理裝置,上述控制部可 以採用一當將被儲存在資料記憶體之未處理資料轉送到上 述資料處理部,而將在資料處理部中經演算處理完畢的資 料轉送到上述資料記憶體時,會監視根據上述資料處理部 之上述演算處理之狀況的監視電路。上述監視電路,會根 據對上述資料記憶體的存取位址,輸出一將殘留在上述資 料記憶體之未處理資料量超過一定量的狀態通知到外部的 信號。根據對外部的狀態通知功能,很容易從S I M D型 資料處理裝置的外部來判斷從外部所設定之上述並列度等 之處理能力的妥當性。換言之,除了資料處理裝置的外部 狀況外,也能夠考慮到資料處理裝置的內部狀態,來控制 資料處理部的並列度與動作速度。 〔5〕在基於上述各觀點的資料處理裝置,再加上以 下的構成,可以達到半導體積體電路化。 例如更加上從外部輸入資料的輸入電路、儲存從上述 輸入電路所輸入的資料,將所儲存的資料供給到上述資料 處理部,而將在資料處理部所演算的資料再度加以儲存的 資料記憶體、以及將被儲存在上述資料記憶體的資料輸出 到外部的輸出電路。 例如上述輸入電路也可以包含對輸入信號實施解調的 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 11^ — — — — — — — — — ·1111111 ·11111111 · (請先閱讀背面之注意事項再填寫本頁) -10- 476883 A7 B7______ 五、發明說明(8 ) 解調手段、以及將經解調的資料轉送到上述資料記憶體的 資料轉送控制手段。 更者,也可以附加系統介面手段。系統介面手段,則 可以利用在針對上述資料轉送控制手段設定轉送控制條件 、或是對上述控制暫.存器設定控制資料。 實施發明之最佳形態 《資料處理裝置的槪要》 第1圖係表本發明之資料處理裝置之一例。同圖所示 的資料處理裝置1 A,雖然未特別限制,但是是一被定位 作周邊控制器的半導體積體電路,而被形成在如單晶矽般 的1個半導體晶片。該資料處理裝置1 A,雖然未特別限 制’但是包含錯誤訂正電路2、系統介面電路3、記憶體 介面電路4、輸入電路5以及輸出電路6。該些電路則共 用區域資料匯流排L D B、區域位址匯流排L A B以及區 域控制匯流排L C B。 在上述系統介面電路3則連接有未圖示之微電腦等的 系統控制器,而在記憶體介面電路4則連接有可被利用在 資料緩衝器等的資料記憶體7。輸入電路5則對例如受信 資料或是來自碟片之讀取資料實施解調,且將其儲存在資 料Ϊ5憶體7內。錯誤訂正電路2則讀入被儲存在資料記憶 體7的資料而進行錯誤檢查,針對有錯誤的資料實施錯誤 訂IE ’而將訂正資料回寫到資料記憶體內。輸出電路6, 則從資料記憶體7讀入經過錯誤檢查以及錯誤訂正的資料 本紙張尺度適用中國國家標準(CNS)A4規格(21〇><297公釐) ' ' -11 - (請先閲讀背面之注意事項再填寫本頁) |裝--------訂---------線秦 經濟部智慧財產局員工消費合作社印製 476883 Α7 Β7 五、發明說明(9 ) (請先閱讀背面之注意事項再填寫本頁) ’進行必要的處理,且將其輸出到外部。在外部與半導體 積體電路之間則設有未圖示的端子,且經由該外部端子, 資料處理裝置1 A則在與外部之間進行資料(信號)的授 受。 經濟部智慧財產局員工消費合作社印製 上述錯誤訂正電路2,雖然未圖示,但是在S I MD 形態下進行資料處理。亦即,具有彼此具有相同之電路構 成的多個資料處理部20 - 1〜20 - η、以及爲各資料 處理部2 0 — 1〜2 0 — η所共用的命令控制部2 1。各 資料處理部2 0 - 1〜2 0 — η,則具有演算電路2 2、 緩衝記憶體2 3以及待機劈制電路2 6。命令控制部2 1 ’則根據被儲存在程式記憶體2 4的動作程式,來進行資 料記憶體7與各緩衝記億體2 3之間的資料轉送控制、以 及各資料處理部2 0 - 1〜2 0 — η的演算控制。例如當 輸入電路5將一定量的資料儲存在資料記憶體7時,則對 命令控制部2 1要求錯誤訂正處理。而接受到命令的命令 控制部2 1,則對從程式記憶體2 4所取來(fetch )的命 令實施解讀,而針對資料記憶體的資料反覆地實施資料載 入處理、演算處理、資料儲存處理的動作。在資料載入處 理中,則利用演算電路2 2,針對有錯誤的資料實施錯誤 訂正的演算處理。在資料儲存處理中,則進行從緩衝記憶 體2 3,將經過錯誤訂正的資料回寫到資料記憶體7的處 理。上述演算處理,則根據共同被提供給各資料處理部 2 0 - 1〜2 0 - η的演算控制信號2 5而呈並列地執行 。根據該並列的演算處理而提高演算處理能力。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) •12- 476883 Α7 _ Β7 五、發明說明(ίο) 《資料處理部之動作速度可變控制》 (請先閱讀背面之注意事項再填寫本頁) 以下針對上述錯誤訂正電路2中之演算速度的可變控 制來加以說明。 錯誤訂正電路2乃同步於時脈信號C L K而動作。時 脈信號C L K的頻率,則是根據在時脈分頻電路(速度控 制部)3 0所選擇的分頻比所決定。亦即,時脈分頻電路 3 0則是針對在時脈脈衝產生器(CPG) 3 1所產生之 基本時脈信號0實施分頻,而根據動作速度暫存器(第2 控制暫存器)3 2的値,來控制時脈信號C L K的頻率。 在動作速度暫存器3 2,則經由系統介面電路3以及外部 端子(未圖示),從外部設定速度控制資料(第2控制資 料)。例如如第2圖所示,分頻器3 0 A則對基本時脈信 號0實施分頻,而產生分頻信號0/2、 0/4、 0/8 經濟部智慧財產局員工消費合作社印製 ,而由選擇器3 0 B,根據動作速度暫存器3 2的設定値 來選擇其中之一者,且將所選出的分頻信號當作上述時脈 信號C L K來輸出。時脈信號C L K,則經由之後詳述的 及閘(AND GATE) 43 - 1〜43 — η,而被供 給到各資料處理部2 0 - 1〜2 0 - η。 《各資料處理部的待機控制》 上述待機控制電路2 6,則根據演算部2 2根據由命 令控制部2 1所供給之上述控制信號2 5的演算結果,來 判斷是否將資料處理部2 0 - 1 _〜2 0 - η個別地控制在 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -13- 476883 A7 B7 五、發明說明(11) 待機狀態,當設成待機狀態時,則將對應的待機控制信號 27 - i (i = l〜η)設成邏輯値。待機控制信 號2 7 - i則被輸入到上述及閘4 3 - i ,而成爲用來決 定時脈信號C L K之輸出的閘控制信號。因此,當待機控 制信號2 7 — i被設爲邏輯値$ 0 "時,則停止將時脈信 號C L K供給到與該待機控制信號2 7 _ i對應之資料處 理部20 — i ,中止該資料處理部20 - i的動作,而被 設成待機狀態。要解除被設成待機狀態之資料處理部2 0 - i的待機狀態,則是根據命令控制部2 1藉著控制信號 2 5將待機控制電路2 6重置(reset )而進行。當待機控 制電路2 6被重置時,則待機控制信號2 7 - i被設成邏 輯値> 1 〃 ,而再度開始將時脈信號C L K供給到該資料 處理部2 0 - i。 例如,資料處理部2 0 - i開始錯誤訂正處理,而調 查是否有錯誤,對於處理沒有錯誤之資料系列的資料處理 部2 0 - i ,則藉由待機控制電路2 6判斷其狀態,而能 夠自己遷移到待機狀態。藉此能夠減少無謂的電力消耗。 又,當全部的資料處理部2 0 — 1〜2 0 - η —起成爲待 機狀態時,藉著命令控制部2 1檢測出該狀態,命令控制 部2 1會消除全部之資料處理部2 0 - 1〜2 0 — η的待 機狀態,而省略無謂的待機週期,提高演算處理效率。 《資料處理部的並列度控制》 將並列度暫存器的設定値供給到上述及閘4 2 - 1〜 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) -裝! !|訂|! 線- 經濟部智慧財產局員工消費合作社印製 476883 A7 B7_ 五、發明說明(12 ) (請先閱讀背面之注意事項再填寫本頁) 42 - η,藉此,上述及閘42 — 1〜42 - η與及閘 43— 1〜43 - η則構成資料處理部20 - 1〜20 -η的並列度控制部4 〇。上述並列度暫存器4 1,則經由 系統介面電路3以及外部端子(未圖示),而從外部來設 定並列度控制資料(第1控制資料)。並列度控制資料, 則具有與上述資料處理部2 0 — 1〜2 0 — η呈1對1地 對應的多個位元,各位元則被設成2輸入及閘4 2 - 1〜 4 2 - η之其中一個輸入。該並列度控制資料,則根據邏 輯値〜1 〃來指示動作。因此,資料處理部2 0 - i ,則 以並列度控制資料的對應位元爲邏輯値> 1 〃爲必要條件 而動作。 在被設定在並列度暫存器4 1之控制資料的對應位元 被設成邏輯値a 1 〃的資料處理部,則被供給有時脈信號 C L K,而所供給之時脈信號.C L K的頻率,則是根據被 設定在動作速度暫存器3 2的控制資料所決定。藉此,可 以從外部來決定在資料處理部2 0 - 1〜2 0 - η中之並 列動作的並列度與時脈信號C L Κ的頻率。 ‘ 經濟部智慧財產局員工消費合作社印製 上述並列度的變更必須要考慮到在錯誤訂正電路2中 的演算處理時序(timing )。資料處理部20-1〜20 -η之並列度的變更適合於事先在進行一連串的處理之前 來控制的情形。而此是因爲在並列演算處理之途中,若是 變更並列度時,則往往容易發生無法處理當初所處理之預 定資料的情形之故。例如當將演算資料儲存在全部之資料 處理部2 0 - 1〜2 0 - η之緩衝記憶體2 3後,在判定 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ~ 476883 A7 B7 五、發明說明(13) (請先閱讀背面之注意事項再填寫本頁) 有無錯誤後,則在實施錯誤訂正步驟之途中,若是變更並 列度時,則會有應該要執行錯誤訂正步驟之一部分的資料 被摒除於演算對象之外的顧慮。系統控制器則最好是設成 不會因爲並列演算處理的進展狀態,而在途中變更並列度 。如此一來,即使是變更並列度,也完全不需要改變資料 處理部2 0 - 1〜2 0 - η的演算控制程式。 另一方面,時脈頻率的變更,即使是在一連串之處理 途中,也可以獨立於並列度的變更而進行。 根據外部條件來控制資料處理部的並列度與動作速度 等兩者,如第3圖所示,基於並列度與動作速度的2個觀 點,可以從外部更精確地來控制資料處理裝置1 Α的資料 處理能力以及電力消耗。 《處理能力的監視》 經濟部智慧財產局員工消費合作社印製 在第1圖中,5 0爲監視電路。該監視電路5 0,則 根據對於上述資料記憶體7的存取位址,而輸出將殘留在 上述資料記憶體7之未處理資料量超過一定量的狀態通知 到外部的信號(外部待機狀態)5 5。如第1圖所示,監 視電路5 0具有輸入資料指標器(指標値P i ) 5 1、處 理中資料指標器(指標値P e ) 5 2、輸出資料指標器( 指標値Po) 53、以及比較器54。上述輸入指標器5 1 ,則經由區域位址匯流排L A B,依序儲存了在上述輸f This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -8-476883 A7 — ______ _____ B7 5. The second control register of the invention description (6), according to the first control register above The above-mentioned first control data held in the register determines the parallel degree control unit based on the parallel degree of the parallel operation of the plurality of data processing units, and the second control data held by the second control register, The speed control unit determines the frequency of the clock signal. The change of the parallel degree of the data processing department is suitable for controlling in advance of a series of processing. This is because when the degree of parallelism is changed in the course of parallel calculation processing, it often happens that the scheduled data to be processed cannot be processed. In contrast, the change of the clock frequency is not necessary to change the program, so it can be performed even during a series of processing. Therefore, by controlling both the juxtaposition and the operation speed of the data processing unit according to external conditions, the processing capacity and power consumption of the data processing device can be controlled more accurately from the outside. [4] The data processing device based on the above-mentioned viewpoints can more specifically adopt the following configuration. When processing multiple data blocks that are predicted to go through the same data processing step, it is best that the data processing device adopts the SI M D form. That is, it further has a command control unit that can interpret commands and output control information, and the command control unit supplies control information for calculation operations to the plurality of data processing units in parallel. When different processes are parallelized, the above data processing device may adopt the M IMD format. When the SI MD format is used, a program memory having an error correction format for error correction is stored in the data processing device, and The above control department obtains the order from the above-mentioned program memory: and uses the above-mentioned capital paper size to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) • mm— I mmt ---- Order --------- Line | Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed 476883 Α7-Β7 V. Description of the Invention (7 ) The material processing section performs error correction processing. For example, the data processing unit includes a Galois body calculation circuit that can perform multiplication and addition of Galois bodies. The control unit controls the Galois body calculation circuits and allows the data processing unit to perform error correction processing. In the SIMD-type data processing device, the control unit may transfer the unprocessed data stored in the data memory to the data processing unit, and transfer the data processed by the calculation in the data processing unit to the data processing unit. In the case of the above-mentioned data memory, a monitoring circuit that monitors the status of the above-mentioned arithmetic processing by the data processing unit. The monitoring circuit outputs an external signal to notify the status of the amount of unprocessed data remaining in the data memory exceeding a certain amount based on the access address to the data memory. According to the external status notification function, it is easy to judge the validity of the above-mentioned parallelism and other processing capabilities set from the outside of the SI D type data processing device. In other words, in addition to the external conditions of the data processing device, the internal state of the data processing device can also be taken into consideration to control the degree of parallelism and operation speed of the data processing unit. [5] A data processing device based on each of the above points can be integrated into a semiconductor integrated circuit by adding the following configuration. For example, an input circuit for inputting data from the outside, storing data input from the input circuit, supplying the stored data to the data processing section, and storing data calculated by the data processing section again. And output data stored in the data memory to an external output circuit. For example, the above input circuit may also include the paper size that is used to demodulate the input signal. The Chinese national standard (CNS) A4 specification (210 X 297 mm) is applicable. 11 ^ — — — — — — — — — — 1111111 · 11111111 · ( (Please read the precautions on the back before filling this page) -10- 476883 A7 B7______ 5. Description of the invention (8) Demodulation means and data transfer control means to transfer demodulated data to the above data memory. Furthermore, system interface means can also be added. The system interface means can be used to set transfer control conditions for the above-mentioned data transfer control means, or to set control data to the above-mentioned control register. Best Mode for Implementing the Invention "Summary of Data Processing Device" Fig. 1 shows an example of the data processing device of the present invention. The data processing device 1 A shown in the figure, although not particularly limited, is a semiconductor integrated circuit that is positioned as a peripheral controller, and is formed on a single semiconductor wafer like single crystal silicon. This data processing device 1 A includes an error correction circuit 2, a system interface circuit 3, a memory interface circuit 4, an input circuit 5, and an output circuit 6, although not particularly limited. These circuits share the regional data bus L D B, the regional address bus L A B, and the regional control bus L C B. A system controller such as a microcomputer (not shown) is connected to the system interface circuit 3, and a data memory 7 that can be used for a data buffer or the like is connected to the memory interface circuit 4. The input circuit 5 demodulates, for example, the trusted data or the read data from the disc, and stores it in the data memory 5 memory 7. The error correction circuit 2 reads the data stored in the data memory 7 and performs error checking, and performs error correction IE 'on the data having errors, and writes the correction data back to the data memory. The output circuit 6 reads the error-checked and error-corrected data from the data memory 7. The paper size applies the Chinese National Standard (CNS) A4 specification (21〇 > < 297mm) '' -11-(Please Read the precautions on the back before filling this page) | -------- Order --------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 Α7 Β7 V. Description of the invention (9) (Please read the precautions on the back before filling out this page) 'Perform necessary processing and output it to the outside. A terminal (not shown) is provided between the external and the semiconductor integrated circuit, and the data processing device 1 A transmits and receives data (signal) between the external and the semiconductor integrated circuit. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The above error correction circuit 2 is not shown, but the data is processed in the form of SIMD. That is, there are a plurality of data processing sections 20-1 to 20-η having the same circuit configuration as each other, and a command control section 21 common to each of the data processing sections 20-1 to 2 0-η. Each data processing unit 20-1 to 2 0-η includes an arithmetic circuit 2 2, a buffer memory 23, and a standby split circuit 26. The command control unit 2 1 ′ performs data transfer control between the data memory 7 and each of the buffer memory banks 23 according to the action programs stored in the program memory 24 and the data processing units 20-1 ~ 2 0 — calculus control of η. For example, when the input circuit 5 stores a certain amount of data in the data memory 7, the command control unit 21 requests an error correction process. The command control unit 21, which has received the command, interprets the commands fetched from the program memory 24, and repeatedly executes data loading processing, calculation processing, and data storage for the data in the data memory. Processing action. In the data loading processing, the calculation circuit 22 is used to perform error correction calculation processing on the data having errors. In the data storage processing, processing from the buffer memory 2 3 to write back the error-corrected data to the data memory 7 is performed. The above-mentioned calculation processing is executed in parallel based on the calculation control signals 25 provided to the data processing units 20-1 to 2 0-η in common. Based on the parallel calculation processing, the calculation processing capacity is improved. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) • 12- 476883 Α7 _ Β7 V. Description of the invention (ίο) "Variable speed control of data processing department" (Please read the back of the first (Please fill in this page again for precautions) The following explains the variable control of the calculation speed in the above error correction circuit 2. The error correction circuit 2 operates in synchronization with the clock signal C L K. The frequency of the clock signal C L K is determined by the frequency division ratio selected by the clock frequency division circuit (speed control section) 30. That is, the clock frequency dividing circuit 3 0 is to divide the frequency of the basic clock signal 0 generated by the clock pulse generator (CPG) 31, and according to the operating speed register (the second control register) ) 3 2 値, to control the frequency of the clock signal CLK. In the operating speed register 32, the speed control data (second control data) is externally set via the system interface circuit 3 and an external terminal (not shown). For example, as shown in Figure 2, the frequency divider 3 A performs frequency division on the basic clock signal 0, and generates frequency division signals 0/2, 0/4, and 0/8. The selector 3 0 B selects one of them according to the setting 値 of the operation speed register 32, and outputs the selected frequency division signal as the above-mentioned clock signal CLK. The clock signal C L K is supplied to each data processing unit 2 0-1 to 2 0-η through AND gates 43-1 to 43-η described in detail later. << Standby Control of Each Data Processing Unit >> The above-mentioned standby control circuit 26 determines whether the data processing unit 20 will be determined based on the calculation result of the control signal 25 provided by the command control unit 21 according to the calculation unit 22. -1 _ ~ 2 0-η Individually controlled at this paper size Applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) -13- 476883 A7 B7 V. Description of the invention (11) Standby status, when set to In the standby state, the corresponding standby control signal 27-i (i = l ~ η) is set to logic 値. The standby control signal 2 7-i is input to the above and the gate 4 3-i and becomes a gate control signal for determining the output of the clock signal C L K. Therefore, when the standby control signal 2 7 — i is set to a logic “$ 0 ", the clock signal CLK is stopped from being supplied to the data processing unit 20 — i corresponding to the standby control signal 2 7 — i, and the processing is suspended. The operation of the data processing unit 20-i is set to a standby state. To release the standby state of the data processing units 20-i set to the standby state, it is performed in accordance with the command control unit 21 to reset the standby control circuit 26 by the control signal 25. When the standby control circuit 26 is reset, the standby control signal 2 7-i is set to logic 値 > 1 ,, and the clock signal C L K is again supplied to the data processing section 2 0-i. For example, the data processing unit 2 0-i starts error correction processing, and investigates whether there is an error. For the data processing unit 2 0-i that processes the data series without error, the standby control circuit 26 can determine its status, and can Migrate to standby by yourself. This can reduce wasteful power consumption. In addition, when all the data processing units 2 0 — 1 to 2 0-η — are in a standby state, the command control unit 21 detects this state, and the command control unit 21 eliminates all the data processing units 20. -1 ~ 2 0 — η standby state, and omission of unnecessary standby cycles improves the efficiency of calculation processing. "Parallel Degree Control of Data Processing Department" Supply the setting of the parallel register to the above and gate 4 2-1 ~ This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (please first Read the notes on the back and fill out this page)-Install! !! | Order |! Line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 A7 B7_ V. Description of the Invention (12) (Please read the precautions on the back before filling this page) 42-η, so that the above and the gate 42 — 1 to 42-η and AND gate 43-1 to 43-η constitute the parallelism control unit 4 of the data processing unit 20-1 to 20-η. The parallel degree register 41 is used to set the parallel degree control data (the first control data) from the outside via the system interface circuit 3 and an external terminal (not shown). The parallel degree control data has a plurality of bits corresponding to the data processing section 2 0 — 1 to 2 0 — η in a one-to-one manner, and each bit is set to 2 inputs and gates 4 2-1 to 4 2 -One of η inputs. The parallel degree control data instructs operations based on logics 値 1 値. Therefore, the data processing unit 20-i operates with the corresponding bit of the parallelism control data as logic 値 > 1 〃 as a necessary condition. In the data processing section where the corresponding bit of the control data set in the parallel register 4 1 is set to logic 値 a 1 ,, the clock signal CLK is supplied, and the clock signal .CLK is supplied. The frequency is determined based on the control data set in the operating speed register 32. This makes it possible to determine the degree of juxtaposition of the parallel operation in the data processing unit 20-1 to 2 0-η and the frequency of the clock signal C L K from the outside. ‘Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The above-mentioned changes in the degree of parallelism must take into account the calculation processing timing in the error correction circuit 2. The change of the degree of parallelism of the data processing units 20-1 to 20-η is suitable for the case where it is controlled in advance before a series of processing is performed. This is because if the degree of parallelism is changed during the parallel calculation process, it often happens that it is impossible to process the scheduled data that was originally processed. For example, when the calculation data is stored in the buffer memory 2 3 of all data processing departments 20-1 to 2 0-η, it is determined that this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ~ 476883 A7 B7 V. Description of the invention (13) (Please read the precautions on the back before filling in this page) If there are any errors, in the process of implementing the error correction steps, if the parallelism is changed, there will be errors that should be executed. The information in one part of the correction step is excluded from the concerns of the calculation object. The system controller should preferably be set so as not to change the parallel degree on the way because of the progress status of the parallel calculation process. In this way, even if the degree of parallelism is changed, there is no need to change the calculation control program of the data processing unit 20-1 to 2 0-η. On the other hand, the clock frequency can be changed independently of the degree of parallelism even during a series of processing. Controlling both the juxtaposition and operating speed of the data processing unit according to external conditions. As shown in Figure 3, based on the two viewpoints of juxtaposition and operating speed, the data processing device 1 Α can be controlled more accurately from the outside. Data processing capabilities and power consumption. "Monitoring of processing capacity" Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs In the first figure, 50 is a monitoring circuit. The monitoring circuit 50 outputs an external signal (external standby state) to notify the state that the amount of unprocessed data remaining in the data memory 7 exceeds a certain amount based on the access address to the data memory 7. 5 5. As shown in Figure 1, the monitoring circuit 50 has an input data indicator (indicator 値 P i) 5 1. a data indicator in processing (indicator 値 P e) 5 2. an output data indicator (indicator 値 Po) 53, And the comparator 54. The above-mentioned input indicator 5 1 is stored in the above-mentioned input in order through the regional address bus L A B.
入電路5依序將資料儲存在資料記憶體7時的記憶體位址 。處理中資料指標器5 2,則經由區域位址匯流排L A B 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -16 - 476883 A7 _______ B7 五、發明說明(14) ,依序儲存了在命令控制部2 1,根據上述載入(load ) 處理,依序從資料記憶體將資料儲存在緩衝記憶體時的記 憶體位址。輸出資料指標器5 3,則經由區域位址匯流排 LAB,依序儲存了上述輸出電路5在從資料記憶體7依 序輸出資料時的記慎體位址。上述資料記憶體7的存取, 則是針對連續地記憶體位址依序進行。在對資料記憶體7 之末尾的位址進行存取後,即回到先頭位址進行存取。換 言之,資料記憶體7當作循環緩衝器(ring-buffer )來利 用。上述比較器5 4,則檢測輸出資料指標値P 〇即將追 過輸入資料指標値P i的狀態。換言之,檢查是否P i = Ρο + α,而α爲一定的常數。當檢查出Pi=p〇 + a 時,則將外部待機信號5 5指定作邏輯値> 1 〃 。該狀態 是一殘留在具有有限記憶容量之資料記憶體7的未處理資 料量超過一定量,而當再輸入資料時,則根據循環緩衝器 的性質,最新被輸入之未處理資料會將已經處理完畢的資 料蓋過(overwrite )的狀態。換言之,則意味著資料處理 部2 0 - 1〜2 0 — η的資料處理能力太低。 第4圖係表分開表示上述指標器的狀態。當資料記憶 體7當作循環緩衝器來利用時,針對處理對象的輸入速度 ,若是資料處理部2 0 — 1〜2 0 — η中的處理能力適當 時,則如第4圖的(1 )、 ( 2 )、 ( 3 )所示,會一邊 維持Po<Pi ,而指標値Po、 Pe、 Pi會變遷。然 而當資料處理能力不足時,則如(4 )所示成爲 P 〇 = P i ,而如(5 )所示,P 〇會追過P i而成爲 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) ----訂---------線. 經濟部智慧財產局員工消費合作社印製 -17- 476883 A7 B7 五、發明說明(15 ) P〇>Pi 。而此狀態則意味著處理完成,應該要讀取的 資料會被所讀入的資料所破壞。 上述外部待機信號5 5,在即將成爲第4圖的(5 ) 的狀態之前,會被指定爲邏輯値> 1 〃 。外部待機信號 5 5則被供給到系統控制器。當系統控制器檢測到外部待 機信號5 5的指定(assert )狀態時,則根據一定的時間變 更並列度暫存器4 1的値,增加資料處理部的並列度,而 提高錯誤訂正電路2的處理能力。更者,立刻變更動作速 度暫存器3 2的値,而加快錯誤訂正電路2的動作速度。 或是將對輸入電路5進行輸入動作而未圖示的外部電路設 成待機狀態。藉此能夠避免整個系統的錯誤。 根據對外部的狀態通知功能,可以容易從S I M D型 的資料記憶裝置1 Α的外部判斷出從外部所設定之上述並 列度等之處理能力的妥當性。換言之,除了資料處理裝置 1 A之外部的狀況外,也考慮到資料處理裝置1 A的內部 狀態,而控制資料處理部2 0 - 1〜2 0 - η之並列度以 及動作速度。 ' 在第1圖的構成中,上述指標器51、 52、 53, 經濟部智慧財產局員工消費合作社印製 可以從外部,經由系統介面電路3而直接讀取。因此,系 統控制器會利用區域匯流排L D Β、LAB、L C B之空 白週期,直接參照上述指標値5 1、52、5 3的値,根 之並列度 請 先. 閱 讀 背· 面' 之 注 意 事 項 再A !裝 頁I w I I I I I I 訂 據此,可以控制資料處理部2 0 - 1〜2 0 的增減以及時脈頻率之高低。例如當已經處理完畢,但仍 未輸出的資料多時,則降低並列度,可以減少消耗電力。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -18- 476883 A7 ______ B7 五、發明說明(16) 如此,若是設成可以從外部來參照指標器51、 52、 5 3,則可以有別於外部待機信號5 5,根據所希望的觀 點來判定演算處理能力,且根據此,可以控制並列度或是 時脈頻率。 在實際的錯誤訂正中,由於所發生的錯誤幾乎都較由 其錯誤訂正碼所推測之最大的錯誤爲少,因此,錯誤訂正 處理能力不一定經常要最大。在第1圖的資料處理裝置 1 A中,通常是降低錯誤訂正電路2的演算處理能力,而 根據指標器51、 52、 53的內容、或是外部待機信號 5 5的値,當未處理的資料變多時,則提高處理能力。又 當已經處理完畢的資料變多時,則可以降低處理能力。藉 此,根據資料的內容,換言之,根據必要的處理能力,可 以減低平均的消耗電力。 《錯誤訂正處理的例子》 以下則說明在上述錯誤訂正電路2中之R S碼的錯誤 訂正處理的例子。上述命令控制部乃指定R I S C ( Reduced Instruction Set Computer )命令。在 S I M D 型的 錯誤訂正電路2中的各資料處理部20 - 1〜20 — η, 則在演算電路2 2具有伽羅瓦體的乘法器與加法器。 在錯誤訂正時,首先則進行調查有無錯誤之癥候( syndrome)運算,只有在有錯誤時,才進行亞基米得( Euvlid )互除、鏈搜尋(chain search )、錯誤數値計算等 之一連串的錯誤訂正。在此,若是將調查有無錯誤的時間 -__ —— 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閲讀背面之注意事項再填寫本頁) 擎裝-----訂--- 經濟部智慧財產局員工消費合作社印製 •19· 476883 A7 _ B7 五、發明說明(17) (請先閱讀背面之注意事項再填寫本頁) 設爲τ 1、將進行錯誤訂正的時間設爲τ 2時,則當沒有 錯誤時的處理時間成爲Τη=T1 ,而當有錯誤時的處理 時間則成爲T y = Τ 1 + T 2。因此,在沒有錯誤時,則 如使Τ n = T y般地減少並列度、或是放慢動作速度,而 降低處理能力。由於藉由降低處理能力,能夠減少消耗電 力,因此,錯誤愈少,則愈可以減低消耗電力。 第5圖係表R S碼之錯誤訂正之代表性的處理流程。 在同一圖中,以長橢圓形圈起來的部分表示處理的內容, 而以長方形圈起來的部分表示輸出資料。錯誤訂正的處理 流程係由資料轉送1 0 1、癥候計算1 〇 〇 2、錯誤的有 無判定1003、亞基米得互除法1004、鏈搜尋 1 0 0 5、錯誤數値計算1 0 0 6、以及訂正1 0 0 7的 各處理所構成。 經濟部智慧財產局員工消費合作社印製 資料轉送1 0 0 1 ,係一以適合於s I M D型的並列 處理的形式,換言之,根據所指定的並列度,將處理對象 資料從資料記憶體7配列到緩衝記憶體2 3的處理。癥候 計算1002,則是將一連串的受信編碼(從r〇到 ^ r 255) 2001當作輸入,而算出癥候多項式的係數 2002。在此可知當癥候多項式的係數2002全部是 零時,則表示在受信編碼沒有錯誤。當知道沒有錯誤時’ 則省略以後的處理而結束,而當知道有錯誤時,則開始訂 正處理。最初則根據亞基米得互除法1 0 0 4,從癥候多 項式2 0 0 2而算出錯誤位置多項式2 0 0 3與錯誤數値 多項式2004。藉著根據鏈搜-尋1 0 〇 5而求取錯誤位 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -20- 476883 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明(18 ) 置多項式2003的根,可以求取錯誤的位置2005。 此時,當得到錯誤的位置2 0 0 5爲一實際上不會發生的 値時,則知已經發生了超出編碼訂正能力的錯誤。此時, 則輸出不能夠訂正之訊息,而省略以後的處理即結束。當 錯誤的位置求得爲適當時,則根據此而計算錯誤的數値 ^ 2006,進行訂正1007後即結束。 例如針對來自記錄媒體之讀取資料所進行的錯誤訂正 處理,則以在將作爲處理單位之多個扇區的資料當作一群 的編碼系列來處理時極有效率。因此,連受信編碼的錯誤 訂正處理,也最好是針對每個備有伽羅瓦體演算器的資料 處理部進行上述一群之編碼系列的錯誤訂正。例如當使用 全部的η個資料處理部2 0 - 1〜2 0 — η時,則可以同 時處理η個受信編碼系列。藉著改變資料處理部的數目, 可以在不改變基本的處理流程的情形下來改變處理能力。 第6圖係表錯誤訂正處理中之資料處理部的自立的待 機控制的第1動作例。在第6圖中,表示利用4個資料處 理部20—1、 20-2、 20-3以及20-4,而同 時並行地處理4個受信編碼系列2 0 0 1時的處理流程。 在第 6 圖中,GPE0 (20 — 1)〜GPE3 (20 — 4 )則表示被並列的4個資料處理部,縱方向則表示隨著 時間的經過,在各資料處理部2 0 - 1〜2 0 — 4中所執 行的處理。 第6圖係表在4個被輸入的受信編碼系列2 0 0 1中 ,即使檢測出1個錯誤,也會將未檢測出錯誤的資料處理 (請先閱讀背面之注意事項再填寫本頁) 裝 ·1 a·· MM a·· MM MM MB I MB MB 瞻 上0 ♦ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -21 - 經濟部智慧財產局員工消費合作社印製 476883 A7 ______ B7 五、發明說明(19 ) 部設成待機狀態,而執行在訂正以前之處理的流程。係一 在被輸入到資料處理部GPEO (20 - 1)的受信編碼 系列2 0 0 1產生在可訂正範圍內的錯誤,在被輸入到資 料處理部GPE、1 (20 - 2)的受信編碼系列200 1 產生超出可訂正範圍的錯誤,而在被輸入到資料處理部 GPE2 (20 — 3)以及 GPE3 (20 - 4)的受信 編碼系統2 0 0 1未發生錯誤時的處理流程。資料轉送 1001、癥候計算2002、錯誤有無之判定1003 ,則在所有的資料處理部20 — 1、20 - 2、2 0-3 、20-4中會無條件地執行該處理。在該例中,對於已 經知道有錯誤的資料處理部GPE0 (20 - 1)與資料 處理部G P E 1 ( 2 0 - 2 ),則進行後續的錯誤訂正處 理。另一方面,資料處理部GPE2 (20-3)與資料 處理部GPE3 (20-4)未檢測出錯誤,因此資料處 理部GPE2 (20 — 3)與資料處理部GPE3 (20 - 4 ),在此一期間內成爲待機狀態。而經過亞基米得互 除法1 0 0 4、錯誤數値計算處理1 0 0 6的結果,已經 知道發生了超出編碼之訂正能力的資料處理部G P E 1 ( 2 0-2),則在以後的錯誤數値計算1 0 0 6、訂正 1 0 0 7之期間成爲待機狀態,而等待的資料處理部 GPE0 (20 — 1)的處理結束。 此時,若全部的資料處理部2 0 - 1、2 0 - 2、 2 0 — 3、2 (Γ - 4未檢測出錯誤時,由於在不進行錯誤 訂正處理的情形下,可以移到下一次一連串的受信編碼 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) — — — — — — — — — ·1111111 ^ ·11111111 (請先閱讀背i之注意事項再填寫本頁) -22- 476883 A7 ___B7_ 五、發明說明(20 ) 2 0 0 1的處理,因此,可以避免不必要的處理步驟。但 是,在4個資料處理部20 - 1、20 — 2、20 - 3、 (請先閱讀背面之注意事項再填寫本頁) 2 0 — 4同時被處理的4個受信編碼系列2 0 0 1中,即 使是有1個錯誤,則在實際進行錯誤訂正的1個資料處理 部以外的3個資料處理部,則將在亞基米得互除法 1 0 0 4以後的所有的處理設成待機狀態,而等待錯誤訂 正處理結束。在此不能說是有效地利用並設之資料處理部 20— 1、20 — 2、2 0 — 3、20 — 4。隨著資料處 理部的數目增加,則在全部之資料處理部未能檢測出錯誤 的機率降低,而導致處理的效率降低。 經濟部智慧財產局員工消費合作社印製 爲了要避免此一情形,第7圖之處理流程所示的方法 乃有效。此時,最初進行將4個受信編碼系列2 0 0 1讀 入4個資料處理部20_1〜20 — 4的處理100 1, 而在進行癥候計算1 0 0 2與錯誤有無之判定1 0 0 3之 前,則與第6圖所示的處理流程相同。將在已經知道有錯 誤的資料處理部G P E 0 ( 2 0 - 1 )與資料處理部 GPE1 (20 — 2)中所算出的癥候2002儲存在資 料記憶體7,此時,已經知道沒有錯誤的資料處理部 GPE2 (20-3)與資料處理部GPE3 (20-4 )則成爲待機狀態,而等待該處理結束。處理流程則回到 先頭的資料傳送,進行將下一次4個受信編碼系列 2 0 0 1讀入到4個資料處理部2 0 - 1〜2 0 — 4的處 理1 0 0 1,更者,則進行癥候計算1 0 0 2與錯誤有無 的判定1 0 0 3,同樣地進行只將已經檢測出錯誤的受信 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -23- 經濟部智慧財產局員工消費合作社印製 476883 A7 B7 五、發明說明(21 ) 編碼系列2 0 0 1之癥候2 0 0 2儲存在記憶體7內的處 理 1 0 0 8。 在對數目累積到某種程度的受信編碼系列2 0 〇 行完後,只進行針對已經檢測出錯誤的受信編碼系列 2001寫入所儲存之癥候2002的處理1009 ’進 行以後的錯誤訂正。此時,當錯誤的數目超出編碼的訂正 能力時,由於不能夠訂正,因此不進行錯誤數値計算 1006,而成爲待機狀態。在第7圖所示的例子中’進 行暫時將已經檢測出錯誤之受信編碼系列2 0 0 1的癥候 2 0 0 2儲存在記憶體7內的處理1 0 0 8,而再度讀取 的處理1 0 0 9,相較於第6圖所示的例子,則變得必要 。一般而言,當發生錯誤的頻库高時,則以第7圖所示的 處理流程最有效率,而當發生錯誤的頻率低時,則以第6 圖所示的處理流程最有效率。根據對於將對訂正錯誤所需 要的處理步驟數與癥候暫時儲存在記憶體所需要的處理步 驟的數目的關係,能夠判斷那個處理流程更有效率。 特別是在進行實用的錯誤訂正時,發生錯誤之頻率的 平均値會遠較所推測之發生最多錯誤的頻率爲低。當受信 編碼爲2 5 6個位元組,而要訂正在其中之8個以下的錯 誤時,則癥候(syndrome )必須要有1 6個位元組。發生 錯誤的機率,由於典型的例子爲1 0 0 0分之1 ,因此, 平均4個編碼會發生1個錯誤。當要對1 0 0個受信編碼 語=2 5,6 0 0個位元組進行訂正時,若是假設訂正處 理需要10,000個步驟完成-,因此,若是根據第6圖 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) I u I ---- -裝·!!!訂·! 1!線 (請先閲讀背面之注意事項再填寫本頁) 476883 A7 B7 五、發明說明(22) (請先閲讀背面之注意事項再填寫本頁) 所示的處理流程,則成爲10,〇〇〇xl〇〇 + 4 = 250,000個步驟。另一方面,當根據第7圖所示的 處理流程來進行錯誤訂正時,則合計成爲9 0,6 4 0個 步驟。可知在第6圖所示之處理流程時的一半以下即完成 處理。當錯誤的發生率低時、或是資料處理部的數目增加 ,而導致並列度增加時,則採用第7圖所示之處理流程的 處理步驟減低效果會變得更加的顯著。 癥候計算對於全部的輸入系列有必要進行,而經常需 要一定的資料處理量。另一方面,以後的錯誤訂正,若是 錯誤少時,則處理量也可以少。因此,更可以將第7圖的 流程變更成第8圖,而可以針對癥候計算提高並列度,針 對錯誤處理降低並列度。 該些的處理流程,則可以考慮實際的錯誤頻率或資料 的輸入速度以及癥候的計算速度等來決定。 《資料處理部的一例》 經濟部智慧財產局員工消費合作社印製 第9圖係表適於錯誤訂正處理之資料處理部的詳細的 一例。如圖所示之資料處理部2 0 - i係由2個伽羅瓦體 乘法器110、 1個伽羅瓦體加法器11 2、64字元組 的伽羅瓦緩衝器1 5 0、4字元組的伽羅瓦暫存器1 6 0 、3個指標器(PS1,PS2,PD)121、 122 、123、 8字元組的整數暫存器170、 1個整數加減 法器1 8 0、以及其他判斷演算結果’而將資料處理部設 成待機狀態的電路所構成。 -25- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 476883 A7 __m_ 五、發明說明(23 ) 伽羅瓦緩衝器150、伽羅瓦暫存器160、 2個伽 (請先閲讀背面之注意事項再填寫本頁) 羅瓦乘法器、1個伽羅瓦加法器11 2,係藉由6條內部 匯流排被連接,對被儲存在伽羅瓦緩衝器1 5 0、伽羅瓦 暫存器1 6 0之資料進行演算,且將其結果再度儲存在伽 羅瓦緩衝器1 5 0、伽羅瓦暫存器1 6 0。在演算器 111、1 1 2的輸入設有^擇器1 1 4 ’而能夠選擇輸 出演算中所使用之資料的內部匯流排。演算器1 1 1、 1 1 2的輸出,則經由內部匯流排,被儲存在伽羅瓦緩衝 器1 5 0或伽羅瓦暫存器1 6 0。 伽羅瓦緩衝器1 5 0,則將由指標器(P S 1 ) 121、 (PS2)122所指定之位址的2個字元輸出 到內部匯流排,且同時從內部匯流排,將資料寫入到由指 標器(P D ) 1 2 3所指定的位址。指標器1 2 1、 122、 123的値,則可在與伽羅瓦體演算相同的週期 (cycle )內進行增減(+ 1 / - 1 )。指標器的値,則是 針對整數暫存器1 7 0進行寫入與讀取。在整數暫存器 1 7 0則儲存了對於演算對控制指標器1 2 1、122、 經濟部智慧財產局員工消費合作社印製 1 2 3爲必要的値的必要的資料,且利用被連接的整數加 減法器1 8 0進行演算。 對於一邊增減指標器1 2 1、1 2 2、1 2 3的値, 而一邊反覆地進行伽羅瓦體演算的處理而言,則有當指標 器121、 122、 123的値成爲一定的値時,反覆動 作仍未停止的情形。事先將一定的値儲存在暫存器( P E N D ) 1 3 1,而根據控制信號SELPEND來指定應該 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -26- 經濟部智慧財產局員工消費合作社印製 476883 A7 B7 五、發明說明(24) 要監視的指標器,藉由比較器(c Μ P ) 1 3 3來判斷所 監視之指標器的値是否與事先設在暫存器(P E ND ) 1 3 3的値爲一致。當該判斷結果爲一致時,則根據信號 PRTEND而建立旗標暫存器1 4 0的PRTEND旗標,更者, 則設定待機暫存器1 4 1。在未進行指標器1 2 1、 1 2 2、1 2 3的監視時,則使用控制信號SELPEND,設 定成不對指標器121、122、123的値與暫存器( PEND)131的値進行比較。 在個別設在資料處理部2 0 — i的旗標暫存器1 4 0 ,則除了上述的RPTEND旗標外,也設有表示伽羅瓦體加 法器1 2 1的結果成爲零的GE旗標,表示整數演算器 1 8 0的結果成爲零的I ZERO旗標、與表示成爲負的 I N E G旗標。 旗標暫存器1 4 0的內容,則在附設遮罩(mask )之 比較器1 4 1中,將信號CNDXMASK當作遮罩,而與信號 NOPCNDX進行比較,當爲一致時,貝U設定待機暫存器 1 4 2。待機暫存器1 4 2,則例如在1位元的暫存器中 ,除了藉由上述的2個方法,而根據在資料處理部2 0 -i內的演算結果來設定外,也可以從外部,根據信號 PENOPIN直接寫入値加以重置、或是直接當作信號 PENOPEA ,直接讀取到外部。當待機暫存器1 4 2的値被 設定時,則被輸入到資料處理部2 0 - i的控制信號,除 了控制從電路1 4 3對於待機暫存器1 4 2的存取外,則 控制全部成爲無效。由減少消耗麗力的觀點來看,在處於The input circuit 5 sequentially stores data in the memory address of the data memory 7. The data indicator 5 2 in process, via the regional address bus LAB This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -16-476883 A7 _______ B7 V. Description of the invention (14), A memory address when the command control unit 21 is sequentially stored in the buffer memory from the data memory according to the load processing described above is sequentially stored. The output data indicator 5 3 sequentially stores the cautious body addresses of the output circuit 5 when sequentially outputting data from the data memory 7 via the regional address bus LAB. The access to the data memory 7 is performed sequentially for successive memory addresses. After accessing the address at the end of data memory 7, it returns to the previous address for access. In other words, the data memory 7 is used as a ring-buffer. The comparator 54 above detects the state where the output data index 値 P0 is about to pass the input data index 値 Pi. In other words, it is checked whether P i = Po + α, and α is a certain constant. When it is checked that Pi = p〇 + a, the external standby signal 5 5 is designated as logic 値 > 1 〃. This state is that the amount of unprocessed data remaining in the data memory 7 with limited memory capacity exceeds a certain amount, and when data is re-entered, according to the nature of the circular buffer, the newly input unprocessed data will be processed The completed data is overwritten. In other words, it means that the data processing capacity of the data processing unit 2 0-1 to 2 0-η is too low. Fig. 4 is a table showing the states of the above indicators separately. When the data memory 7 is used as a circular buffer, the processing speed of the data processing unit 2 0 — 1 to 2 0 — η is appropriate for the input speed of the processing target, as shown in (1) of FIG. 4 , (2), (3), while maintaining Po < Pi, the indicators , Po, Pe, Pi will change. However, when the data processing capacity is insufficient, it becomes P 〇 = P i as shown in (4), and as shown in (5), P 〇 will follow P i and become the Chinese paper standard (CNS) A4. Specifications (210 X 297 mm) (Please read the notes on the back before filling out this page) ---- Order --------- Line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-17- 476883 A7 B7 V. Description of the invention (15) P0> Pi. This state means that the processing is completed, and the data that should be read will be destroyed by the imported data. The external standby signal 5 5 is designated as logic 値 > 1 在 immediately before the state of (5) in FIG. 4 is reached. The external standby signal 5 5 is supplied to the system controller. When the system controller detects the assert state of the external standby signal 55, it changes the juxtaposition register 41 according to a certain time, increases the juxtaposition of the data processing section, and improves the error correction circuit Processing power. In addition, the operation speed register 3 2 is immediately changed to accelerate the operation speed of the error correction circuit 2. Alternatively, an external circuit (not shown) that performs an input operation on the input circuit 5 is set to a standby state. This can avoid errors in the entire system. Based on the external status notification function, it is easy to determine the validity of the processing capabilities such as the parallelism set from the outside from the outside of the data storage device 1 Α of the SI M D type. In other words, in addition to the external conditions of the data processing device 1 A, the internal state of the data processing device 1 A is also taken into consideration, and the degree of parallelism of the data processing units 20-1 to 2 0-η and the operation speed are controlled. 'In the structure of FIG. 1, the above-mentioned indicators 51, 52, 53, printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs can be read directly from the outside through the system interface circuit 3. Therefore, the system controller will use the blank periods of the regional buses LD Β, LAB, and LCB to directly refer to the above indicators 値 5 1, 52, 5 3, and the degree of juxtaposition, please first. Read the note on the back Then A! Loading page I w IIIIII order, you can control the increase and decrease of the data processing section 20-1 ~ 2 0 and the level of the clock frequency. For example, when there is a lot of data that has been processed but not yet output, the parallelism can be reduced to reduce power consumption. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -18- 476883 A7 ______ B7 V. Description of the invention (16) So, if it is set to be able to refer to the indicators 51, 52, 5 from the outside 3, it can be different from the external standby signal 5 5 to determine the calculation processing capacity according to the desired viewpoint, and according to this, the degree of juxtaposition or clock frequency can be controlled. In actual error correction, since almost all of the errors occurred are less than the largest error inferred from its error correction code, the error correction processing capacity may not always be the largest. In the data processing device 1 A of FIG. 1, the calculation processing capacity of the error correction circuit 2 is generally reduced, and according to the contents of the indicators 51, 52, 53 or the external standby signal 5 5, when the unprocessed As more data becomes available, processing power is increased. When more data has been processed, the processing capacity can be reduced. Therefore, depending on the content of the data, in other words, the necessary processing power, the average power consumption can be reduced. "Example of Error Correction Processing" An example of error correction processing of the RS code in the above error correction circuit 2 will be described below. The above-mentioned command control unit specifies a R IS (Reduce Instruction Set Computer) command. Each of the data processing units 20-1 to 20-η in the S I M D type error correction circuit 2 has a multiplier and adder of a Galois body in the calculation circuit 22. When correcting errors, first investigate whether there is an error in the syndrome operation. Only when there is an error, perform a series of Euclid mutual division, chain search, and calculation of error numbers. Error correction. Here, if it is time to investigate whether there is an error-_ —— This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) --- Order --- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs • 19 · 476883 A7 _ B7 V. Description of Invention (17) (Please read the precautions on the back before filling this page) Set to τ 1. When the time for performing error correction is set to τ 2, the processing time when there is no error becomes Tn = T1, and the processing time when there is an error becomes Ty = T1 + T2. Therefore, when there is no error, the parallelism degree is reduced like Tn = Ty, or the slow-down speed is reduced, and the processing capacity is reduced. Since power consumption can be reduced by reducing processing power, the fewer errors, the more power consumption can be reduced. Fig. 5 is a representative processing flow of error correction of the RS code in the table. In the same figure, a circled part indicates the processing content, and a rectangled part indicates output data. The error correction processing flow is from data transfer 1 0, symptom calculation 1 002, error judgment 1003, Yakimide cross division method 1004, chain search 1 0 0 5, error number calculation 1 0 0 6, And each process of revision 1 0 7 constitutes. The printed data transferred by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is transmitted in the form of parallel processing suitable for s IMD. In other words, according to the specified parallelism, the processing target data is arranged from the data memory 7 Processing to buffer memory 2 3. Symptom Calculation 1002 takes a series of trusted codes (from r0 to ^ r 255) 2001 as input, and calculates the coefficient of the syndrome polynomial 2002. It can be seen here that when all the coefficients 2002 of the symptom polynomial are zero, it means that there is no error in the trusted coding. When it is known that there is no error, the subsequent processing is omitted, and when it is known that there is an error, the correction processing is started. Initially, the error position polynomial 2 0 3 and the error number 値 polynomial 2004 were calculated from the symptom polynomial 2 0 2 based on the cross division of Yakimite 1 0 4. By calculating the error bit according to the chain search-finding 10 005, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -20- 476883 Α7 Β7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Fifth, the description of the invention (18) By setting the root of the polynomial 2003, the error position 2005 can be obtained. At this time, when the obtained error position 2 0 5 is a 値 that does not actually occur, it is known that an error exceeding the encoding correction capability has occurred. At this time, a message that cannot be corrected is output, and the subsequent processing is omitted. When the position of the error is determined to be appropriate, the number of errors 此 2006 is calculated based on this, and the correction is completed after 1007, and the process ends. For example, the error correction processing for the read data from the recording medium is extremely efficient when processing the data of multiple sectors as a processing unit as a group of code series. Therefore, even the error correction processing of the trusted encoding is preferably to correct the above-mentioned group of encoding series errors for each data processing unit equipped with a Galois body calculator. For example, when all η data processing units 2 0-1 to 2 0-η are used, η trusted coding series can be processed at the same time. By changing the number of data processing sections, the processing capacity can be changed without changing the basic processing flow. Fig. 6 shows the first operation example of the stand-alone standby control of the data processing section during error correction processing. Fig. 6 shows a processing flow when four data processing units 20-1, 20-2, 20-3, and 20-4 are used to simultaneously process four trusted coding series 20001. In Figure 6, GPE0 (20 — 1) to GPE3 (20 — 4) indicate the four data processing units that are juxtaposed, and the vertical direction indicates that over time, each data processing unit 2 0-1 to Processes performed in 2 0 — 4. Figure 6 is a table of 4 input trusted coding series 2 0 0 1, even if 1 error is detected, the data will be processed without errors (please read the precautions on the back before filling this page) Installation · 1 a ·· MM a ·· MM MM MB I MB MB Seeing 0 ♦ This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -21-Employee Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Printed 476883 A7 ______ B7 5. The description of the invention (19) is set to the standby state, and the processing flow before the correction is executed. The first error occurred in the correction code series 2 0 0 1 that was input to the data processing unit GPEO (20-1). The error occurred in the trusted code that was input to the data processing unit GPE, 1 (20-2). The series 200 1 generates an error that is out of the correctable range, and is processed when no errors occur in the trusted coding system 2 0 0 1 that is input to the data processing units GPE2 (20 — 3) and GPE3 (20-4). Data transfer 1001, symptom calculation 2002, and error judgment 1003 will be executed unconditionally in all data processing sections 20 — 1, 20-2, 2 0-3, and 20-4. In this example, the data processing unit GPE0 (20-1) and the data processing unit G P E 1 (2 0-2), which have been known to have errors, perform subsequent error correction processing. On the other hand, the data processing unit GPE2 (20-3) and the data processing unit GPE3 (20-4) did not detect an error, so the data processing unit GPE2 (20-3) and the data processing unit GPE3 (20-4), in During this period, it becomes standby. As a result of Yakimide's cross division method 1 0 0 4 and the calculation of the error number 1 0 6, it has been known that the data processing department GPE 1 (2 0-2) that exceeds the correction capacity of the code has occurred. The calculation of the number of errors is 1 0 0 6 and the period of correction 1 0 7 becomes standby, and the processing of the waiting data processing unit GPE0 (20 — 1) ends. At this time, if all the data processing sections 2 0-1, 2 0-2, 2 0 — 3, 2 (Γ-4 do not detect an error, because the error correction process is not performed, you can move to the next A series of trusted codes at a time. The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). — — — — — — — — · 1111111 ^ · 11111111 (Please read the precautions on the back before filling in this (Page) -22- 476883 A7 ___B7_ V. Processing of the invention (20) 2 0 0 1 Therefore, unnecessary processing steps can be avoided. However, in the 4 data processing sections 20-1, 20-2, 20- 3. (Please read the notes on the back before filling this page) 2 0 — 4 Of the 4 trusted coding series 2 0 0 1 that are processed at the same time, even if there is 1 error, the actual error correction is 1 The three data processing departments other than the data processing department set all the processing after Yakimide's mutual division method 1 04 to the standby state and wait for the error correction processing to end. It cannot be said that it is effectively used and Data Processing Department 20— 1, 20 — 2, 2 0 — 3, 20 4. As the number of data processing departments increases, the probability of failure to detect errors in all data processing departments decreases, resulting in reduced processing efficiency. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to avoid this situation The method shown in the processing flow of Fig. 7 is effective. At this time, the process of reading the 4 trusted coding series 2 0 0 1 into the 4 data processing units 20_1 to 20-4 100 1 is performed, and the symptoms are being performed. Calculate 1 0 0 2 and determine whether there is an error. Before 1 0 0 3, the processing flow is the same as that shown in Figure 6. The data processing unit GPE 0 (2 0-1) and the data processing unit that have been known to have errors will be processed. The symptoms 2002 calculated in GPE1 (20-2) are stored in data memory 7. At this time, the data processing unit GPE2 (20-3) and the data processing unit GPE3 (20-4), which have been known to have no errors, are in standby. , And wait for the processing to end. The processing flow returns to the first data transmission, and reads the next 4 trusted coding series 2 0 0 1 into the 4 data processing sections 2 0-1 ~ 2 0-4 processing 1 0 0 1, moreover, symptom calculation is performed 1 0 0 2 and the judgment of the presence or absence of errors 1 0 0 3, the same applies to only the paper size of the letter of trust that has been detected as an error. The Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied. Printed by the Employee Consumption Cooperative 476883 A7 B7 V. Description of the Invention (21) Coding Series 2 0 1 1 Symptom 2 0 0 2 Processing stored in memory 7 1 0 0 8 After the number of trusted code series 200 which has accumulated to a certain degree is completed, only the error correction process for the trusted code series 2001 in which the error has been detected is written into the stored symptom 2002 1009 'is performed. At this time, when the number of errors exceeds the correction capability of the code, the correction cannot be performed. Therefore, the calculation of the number of errors is not performed 1006, and the system enters a standby state. In the example shown in FIG. 7, the process of temporarily storing the syndrome 2 0 0 1 of which the error has been detected 2 0 0 2 is stored in the memory 7, and the process is read again. 1 0 0 9 becomes necessary compared to the example shown in FIG. 6. In general, when the frequency of the error database is high, the processing flow shown in FIG. 7 is the most efficient, and when the frequency of the error is low, the processing flow shown in FIG. 6 is the most efficient. Based on the relationship between the number of processing steps required to correct the error and the number of processing steps required to temporarily store the symptoms in memory, it can be judged which processing flow is more efficient. In particular, when performing practical error correction, the average frequency of errors will be much lower than the frequency of most errors. When the trusted code is 256 bytes, and errors less than 8 of them are to be corrected, the syndrome must have 16 bytes. The probability of an error. Since the typical example is 1 in 100, there is an error of 4 codes on average. When it is necessary to correct 100 trusted code words = 2,600 bytes, if it is assumed that the correction process needs 10,000 steps to complete-, therefore, if the paper size is based on Figure 6, this paper applies to China National Standard (CNS) A4 Specification (210 X 297 mm) I u I ---- -Equipped ·! !! !! Order! 1! Line (please read the notes on the back before filling this page) 476883 A7 B7 V. Description of the invention (22) (please read the notes on the back before filling this page) The processing flow shown in the figure becomes 10. 〇 × 100 + 4 = 250,000 steps. On the other hand, when error correction is performed according to the processing flow shown in Fig. 7, the total number of steps is 90,640. It can be seen that the processing is completed in less than half of the processing flow shown in FIG. When the incidence of errors is low, or the number of data processing units increases, resulting in an increase in the degree of parallelism, the reduction of the processing steps using the processing flow shown in Figure 7 will become more significant. Symptom calculation is necessary for all input series, and often requires a certain amount of data processing. On the other hand, in the case of subsequent error correction, if the number of errors is small, the amount of processing can be reduced. Therefore, the flow in Fig. 7 can be changed to Fig. 8 to increase the parallelism for symptom calculation and reduce the parallelism for error processing. These processing flows can be determined in consideration of the actual error frequency, the speed of inputting data, and the speed of calculating symptoms. "An example of the data processing department" Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 9 is a detailed example of the data processing department suitable for error correction processing. The data processing unit 20-i shown in the figure is composed of two Galois body multipliers 110, one Galois body adder 11 2, 64-byte Galois buffer 1, 50, 4-byte Galois register 1 6 0, 3 pointers (PS1, PS2, PD) 121, 122, 123, 8-byte integer register 170, 1 integer adder-subtractor 1 8 0, and others A circuit that judges the calculation result and sets the data processing unit to a standby state. -25- This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm) 476883 A7 __m_ V. Description of the invention (23) Galois buffer 150, Galois register 160, 2 Gal (Please (Please read the notes on the back before filling in this page.) The Lova multiplier and 1 Galois adder 11 2 are connected through 6 internal buses. The pairs stored in the Galois buffer 1 50, Galois The data in the register 160 is calculated, and the results are stored again in the Galois buffer 150 and the Galois register 160. An internal bus is provided at the inputs of the calculators 111, 1 and 12 to select the data used in the calculations. The outputs of the calculators 1 1 1 and 1 1 2 are stored in the Galois buffer 150 or the Galois register 160 through the internal bus. The Galois buffer 1 50 will output 2 characters of the address specified by the indicators (PS 1) 121 and (PS2) 122 to the internal bus, and simultaneously write data from the internal bus to Address specified by the pointer (PD) 1 2 3 The 値 of the indicators 1 2 1, 122, and 123 can be increased or decreased (+1 /-1) in the same cycle as the Galois body calculation. The pointer of the indicator is written and read for the integer register 170. The integer register 170 stores the necessary data necessary for the calculation of the control indicator 1 2 1, 122, and the printing of 1 2 3 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, and uses the connected data. The integer adder-subtractor 180 performs calculations. For the 値 of the indicator 1 2 1, 1, 2 2, 1 2 3, and the process of performing Galois body calculations repeatedly, there is a case where the 値 of the indicators 121, 122, and 123 become a certain 値When repeated actions have not stopped. Store a certain amount of plutonium in advance in the register (PEND) 1 3 1 and specify according to the control signal SELPEND that the Chinese paper standard (CNS) A4 specification (210 X 297 mm) should be applied to this paper size. -26- Ministry of Economic Affairs Wisdom Printed by the Consumer Cooperative of the Property Bureau 476883 A7 B7 V. Description of the invention (24) The indicator to be monitored, the comparator (c MP) 1 3 3 is used to determine whether the 指标 of the monitored indicator is set in advance with the temporary setting. Registers (PE ND) 1 3 3 are consistent. When the judgment result is consistent, the PRTEND flag of the flag register 1 4 0 is established according to the signal PRTEND, and furthermore, the standby register 1 41 is set. When the indicators 1 2 1, 1, 2 2, 1 2 3 are not monitored, the control signal SELPEND is used to set the 不 of the indicators 121, 122, 123 and 値 of the register (PEND) 131 not to be compared. . In the flag register 1 40 which is individually set in the data processing section 20 — i, in addition to the above-mentioned RPTEND flag, a GE flag indicating that the result of the Galois body adder 1 2 1 becomes zero is also provided. , The I ZERO flag indicating that the result of the integer calculus 180 is zero, and the INEG flag indicating that it is negative. The content of the flag register 1 4 0, in the comparator 1 4 1 with a mask (mask), the signal CNDXMASK is used as a mask, and compared with the signal NOPCNDX. Standby register 1 4 2. The standby register 1 4 2 can be set from, for example, a 1-bit register according to the calculation results in the data processing unit 2 0 -i by using the above two methods. Externally, it can be directly written and reset according to the signal PENOPIN, or it can be directly read to the external as the signal PENOPEA. When 値 of the standby register 1 4 2 is set, the control signals input to the data processing section 2 0-i, in addition to controlling the access of the slave circuit 1 4 3 to the standby register 1 42, All controls become invalid. From the viewpoint of reducing the consumption of Lili,
• — S 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) IU---------•裝--------訂---------線· (請先閱讀背面之注意事項再填寫本頁) -27- 476883 經濟部智慧財產局員工消費合作社印製 A7 ___B7 _ 五、發明說明(25 ) 待機狀態時,最好是停止時脈的供給。又,當將可將其信 號設成無效的閘極(Gate )插入到所有的控制信號時,由 於控制信號的數目成爲數百條的情形也不少,因此,不能 夠忽視電路的規模會因爲所插入的閘極而增加的情形。而 當在停止供給時脈時’由於只需要相對於時脈將閘極插入 ,因此,由電路規模的觀點來看很好。 《D V D驅動系統》 第10圖係表備有作爲上述資料處理裝置之更詳細的 一例的DVD控制器的DVD驅動系統的方塊圖。 同圖所示的D V D控制器1 B,係由:將類比資料予 以2値化的2値化電路(Data·Strobe ) 2 0 0、解調電路 (DVD-Demod ) 2 0 1、調變電路(DVD-Mod ) 2 0 2、 錯誤訂正電路(D V D - E C C ) 2 0 3、記憶體介面電 路(DRAM— C〇NT) 204、音頻介面電路(Audio Processor ) 2 0 5、作爲與個人電腦等之主電腦的介面的 ATAP I介面電路206、系統介面電路(MI C〇N IF) 207、伺服電路(SERVO) 208、以及 時脈振盪器(C P G ) 2 〇 9等的模組所構成,而藉由周 知的半導體製造技術而被形成在1個半導體基板上。又, DVD控制器1B,除了 DVD外,也能夠對CD — ROM、音樂用的CD — DA進行再生。而具有CD用的 解調電路(CD· — DA) 210、對來自CD — ROM的 讀取資訊進行解碼的解碼器2 1 _.5、以及對C D — R〇Μ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) — -ΑΙ 丨! _||丨| 裝 i!訂 ί 丨!!線 (請先閱讀背面之注意事項再填寫本頁) -28- 476883 A7 __B7__ 五、發明說明(26 ) 格式的資料實施解碼的ROM解碼器(ROMDEC ) 2 1 1 〇 上述CPG2 0 9,則根據經由以〇所表示之外部端 子被連接的石英振盪器或外部時脈,而進行遞倍或是分頻 ,產生基準時脈,旦將其供給到各功能方塊。D V D控制 器1 B則同步於該基準時脈而動作。 上述錯誤訂正電路203具有與上述處理能力可改變 之上述錯誤訂正電路2同樣的構成。上述記億體介面電路 (DRAM — CO NT) 204,除了對 DRAM等的資 料記憶體2 1 2進行輸出入要求的調停外,也對記憶體匯 流排2 1 8進行匯流排控制。上述記憶體介面電路2 0 4 、資料記憶體2 1 2,則相當於第1圖的記憶體介面電路 4、資料記憶體7。 上述ATAP I介面電路2 0 6則是第1圖的輸出電 路6的一例。上述系統介面電路2 0 7,則被連接到作爲 系統控制器的微電腦2 2 0。微電腦2 2 0,則經由內部 匯流排(LAB、LDB、LCB) 221,而初期設定 解調電路2 0 1或錯誤訂正電路2 0 3等的各電路,又讀 取錯誤訂正電路2 0 3等的內部匯流排,而進行系統控制 。系統介面電路2 0 7則相當於第1圖的系統介面電路3 〇 上述2値化電路2 0 0、調變電路2 0 2、以及伺服 電路208等,則被連接到前處理LS I 224。前處理 L S I 2 2 4,則將從D V D碟_片’由光學讀寫頭225 (請先閲讀背面之注意事項再填寫本頁) --------訂---------線』 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -29- 476883 A7 ------ B7 五、發明說明(27 ) (請先閲讀背面之注意事項再填寫本頁) 所讀取的記錄資訊加以放大,而將使記錄資訊再生的資訊 信號送到2値化電路2 0 0。又,根據資訊信號的包跡( envelope )等.,而產生聚焦誤差、搜軌誤差的各信號,且將 其供給到伺服電路2 0 8。伺服電路2 0 8,則根據該些 資訊來控制光學讀寫頭2 2 5的搜軌與聚焦。又,抽出搜 軌控制的低頻成分,根據D / A轉換輸出,來控制光學讀 取頭2 2 5之螺進馬達(thread motor ) 2 2 7。又,根據 脈衝檢測來檢測碟片的回轉速度,而進行伺服處理,且根 據D/ A轉換輸出來控制心軸馬達(Spindle motor ) 2 2 8。上述讀取頭的聚焦以及搜軌、乃至於螺進馬達以 及心軸馬達的驅動,則是由驅動I C 2 2 6來進行。 以下則說明第1 0圖所示之D V D驅動系統中之記錄 資訊再生的動作。 從電腦2 2 0則監視來自輸出入電路的指令輸入以及 輸出入璋的按鍵輸入情形,當有輸入時,則解讀所輸入之 指令或是按鍵的內容,而根據此開始動作。 經濟部智慧財產局員工消費合作社印製. 微電腦2 2 0,則經由微電腦介面2 0 7,來對伺服 電路2 0 8的動作設定暫存器進行初始設定,而讓聚焦、 搜軌伺服控制作動,當聚焦被鎖定時,則藉由心軸馬達 2 2 8讓碟片回轉,更者,則讓光學讀取頭2 2 5移動到 一定的位置。 在再生時’由光學讀取頭2 2 5所讀取的資料,則在 前處理L S I 2 2 4中被轉換成數位信號,且將其輸入到 上述D V D控制器1 B。所輸入的資料,首先被輸入到解 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -30- 476883 經濟部智慧財產局員工消費合作社印製 A7 ______Β7__ 五、發明說明(28 ) 調電路201 ,當爲DVD時,則依序進行8 一16方式 之解調、解交錯、同步檢測等。當一定量的資料被解調時 ,則將輸入要求輸出到記憶體介面電路2 〇 4。記億體介 面電路204,則在一定的時間,會接受輸入要求,而將 經解調的資料從解調電路2 0 1轉送到資料記憶體( D R A Μ ) 2 1 2。 當一定量的資料(當爲DVD時,則爲1區段: 1 8 2 X 2 0 8個位兀組)被儲存在資料記憶體2 1 2時 ,則從記憶體介面電路2 0 4產生中斷要求,而當錯誤訂 正電路2 0 3辨識到中斷要求時,即開始進行錯誤訂正處 理(解碼)。 當進行一定之資料的錯誤訂正處理時,錯誤訂正電路 2 0 3會對一定的暫存器等進行設定,而指示資料輸出。 根據此,ATAP I介面電路2 0 6,會對記憶體介面電 路2 0 4發出輸出要求。記憶體介面2 0 4,則在一定的 時間接受輸出要求,且從資料記憶體2 1 2,將資料輸出 到ATAP I介面電路2 0 6,而ATAP I介面電路· 2 〇 6,則將資料輸出到如個人電腦般之主機裝置的介面 電路。 又,錯誤訂正電路2 0 3會根據指令或按鍵的內容, 來設定通用介面電路(通用I F) 2 3 0的一定的暫存器 等’而指示資料輸出。當來自通用I F 2 3 〇的資料爲影 像資料時,則被供給到未圖示的Μ P E G電路,而解除壓 縮’且將其顯示在例如L C D等的顯示裝置。 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) -------------------訂--------·線 (請先閱讀背面之注意事項再填寫本頁) -31 - 經濟部智慧財產局員工消費合作社印製 476883 A7 __ B7 五、發明說明(29) 在結束指令或按鍵的指示、或是在下一個指令或按鍵 被輸入之前,則繼續上述之動作。 以下則說明在第1 0圖所示之D V D驅動系統中之資 訊記錄動作。與上述同樣地,微電腦2 2 0會監視來自輸 出入電路的指令輸入或是輸出入ί阜之按鍵輸入情形,而當 有輸入時,則會解讀所輸入之指令或按鍵的內容,且根據 此開始動作。 微電腦2 2 0,則經由微電腦介面電路2 0 7,對伺 服電路2 0 8進行初始設定,而讓聚焦、搜軌伺服控制作 動,更者,則讓光學讀取頭2 2 5移動到一定的位置。 ΑΤΑ Ρ I介面電路2 0 6,則對主機裝置輸出資料 要求’而輸入資料。當輸入一定量的資料時,貝!J ΑΤΑΡΙ介面電路206,會對記憶體介面電路204 送出輸入要求。記憶體介面電路2 0 4,則在一定的時間 接受輸入要求,且將從ΑΤΑΡ I介面電路2 0 6所輸入 的資料轉送到資料記憶體2 1 2。 當一定量的資料(當爲DVD時,則爲1個區段)被 儲存在資料記憶體2 1 2時,則從記憶體介面電路2 0 4 ,對錯誤訂正電路2 0 3送出中斷要求,藉此,錯誤訂正 電路2 0 3,會對由資料記憶體2 1 2所保有的資料進行 同位(parity )附加處理(編碼)。 錯誤訂正電路2 0 3,當對資料記憶體2 1 2之一定 的資料完成同位附加處理時,則會將同位附加處理已完成 之訊息送到調變電路2 0 2,接茇此,調變電路202, 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) i"** 丨! _丨!丨I!訂·!1 丨—線▲ (請先閲讀背^之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 476883 A7 B7 五、發明說明(30) 會起動一可從資料記憶體,將已經完成同位附加處理的資 料轉送到調變電路2 0 2的資料轉送控制,而經由記憶體 介面電路2 0 4,將資料從資料記憶體2 1 2轉送到調變 電路2 0 2。當爲DVD時,則調變電路2 0 2會依序進 行交錯、同步的插入、8 — 1 6方式之調變等,而輸出資 料。所輸出的資料,則在前處理LSI224中被放大, 且經由光學讀寫頭2 2 5被寫入到光碟上。 第1 1圖係表上述DVD驅動系統的整體。第1 〇圖 之光學讀寫頭2 2 5係由聚焦及搜軌用的致動器2 2 5 B 與由雷射二極體所形成之讀寫頭2 2 5A而構成。第1 〇 圖的馬達驅動I C226包含有致動器225B的驅動器 2 2 6 A、螺進馬達2 2 8的驅動器2 2 6 B、以及心軸 馬達2 2 7的驅動器2 2 6 C。在此,則以讀取頻道(• — S This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) IU --------- • Installation -------- Order ------- --Line · (Please read the precautions on the back before filling this page) -27- 476883 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ___B7 _ V. Description of the invention (25) When in standby, it is best to stop Pulse supply. In addition, when the gate (Gate) whose signal can be set to be invalid is inserted into all the control signals, there are many cases where the number of control signals becomes hundreds. Therefore, the scale of the circuit cannot be ignored because Increased number of gates inserted. On the other hand, when the supply of the clock is stopped ', since the gate only needs to be inserted with respect to the clock, it is good from the viewpoint of circuit scale. << D V D Drive System >> Fig. 10 is a block diagram of a DVD drive system including a DVD controller as a more detailed example of the data processing device. The DVD controller 1 B shown in the figure is composed of: a 2 × 2 analog circuit (Data · Strobe) 2 0 0, a demodulation circuit (DVD-Demod) 2 0 1, a modulation circuit (DVD-Mod) 2 0 2, Error Correction Circuit (DVD-ECC) 2 0 3, Memory Interface Circuit (DRAM—CONT) 204, Audio Interface Circuit (Audio Processor) 2 0 5. As a personal computer The host computer's interface is composed of ATAP I interface circuit 206, system interface circuit (MI CON IF) 207, servo circuit (SERVO) 208, and clock oscillator (CPG) 2 09 and other modules, It is formed on a single semiconductor substrate by a well-known semiconductor manufacturing technology. In addition, the DVD controller 1B can reproduce a CD-ROM and a CD-DA for music in addition to a DVD. CD demodulation circuit (CD · —DA) 210, decoder 2 1 _.5, which decodes the read information from CD-ROM, and CD-ROM This paper standard applies Chinese national standard (CNS) A4 size (210 X 297 mm) — -ΑΙ 丨! _ || 丨 | Install i! Order ί 丨! !! (Please read the precautions on the back before filling in this page) -28- 476883 A7 __B7__ V. ROM description decoder (ROMDEC) 2 1 1 〇 The above-mentioned CPG2 0 9 will be decoded according to the invention (26) format. Through a quartz oscillator or an external clock connected to an external terminal indicated by 0, multiplication or division is performed to generate a reference clock, which is supplied to each functional block. D V D controller 1 B operates in synchronization with this reference clock. The error correction circuit 203 has the same configuration as the error correction circuit 2 whose processing capacity can be changed. The memory interface circuit (DRAM-CO NT) 204 mentioned above not only mediates the input and output requirements of the DRAM and other data memory 2 1 2, but also controls the memory bus 2 1 8. The memory interface circuit 2 0 4 and the data memory 2 12 are equivalent to the memory interface circuit 4 and the data memory 7 in FIG. 1. The above-mentioned ATAP I interface circuit 206 is an example of the output circuit 6 in Fig. 1. The above-mentioned system interface circuit 207 is connected to a microcomputer 2 270 as a system controller. Microcomputer 2 2 0, through the internal bus (LAB, LDB, LCB) 221, and initially set the demodulation circuit 2 0 1 or the error correction circuit 2 0 3 and other circuits, and read the error correction circuit 2 3 3, etc. System's internal bus. The system interface circuit 2 7 is equivalent to the system interface circuit 3 in the first figure. 〇 The above 2 circuit 2 0 0, the modulation circuit 2 0 2 and the servo circuit 208 are connected to the pre-processing LS I 224. . Pre-processing LSI 2 2 4 will be from the DVD disc _ from the optical read-write head 225 (Please read the precautions on the back before filling this page) -------- Order ------- --Line ”Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economy The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -29- 476883 A7 ------ B7 V. Description of the invention ( 27) (Please read the precautions on the back before filling in this page) The recorded information read will be enlarged, and the information signal that reproduces the recorded information will be sent to the 2D circuit 2 0 0. In addition, each signal of the focus error and the tracking error is generated based on the envelope and the like of the information signal, and is supplied to the servo circuit 208. The servo circuit 208 controls the tracking and focusing of the optical head 2 2 5 based on the information. In addition, the low-frequency component of the track control is extracted and the D / A conversion output is used to control the thread motor 2 2 7 of the optical pickup 2 2 5. In addition, the rotation speed of the disc is detected based on the pulse detection, and servo processing is performed, and the spindle motor (Spindle motor) 2 2 8 is controlled according to the D / A conversion output. The focusing of the above-mentioned read head and the track search, as well as the driving of the screw-in motor and the spindle motor are performed by driving the IC 2 2 6. The following describes the operation of recording information reproduction in the D V D drive system shown in FIG. 10. The computer 2 2 monitors the command input from the input / output circuit and the key input of the input / output switch. When there is an input, it interprets the content of the input command or key and starts to act accordingly. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Microcomputer 2 2 0, through the micro computer interface 2 7 to initialize the setting register of the servo circuit 2 0 8 and let the focus and tracking servo control act When the focus is locked, the disc is rotated by the spindle motor 2 2 8, and moreover, the optical pickup 2 2 5 is moved to a certain position. At the time of reproduction ', the data read by the optical pickup 2 2 5 is converted into a digital signal in the pre-processing L S I 2 2 4 and input to the above-mentioned D V D controller 1 B. The information entered is first entered into the solution. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -30- 476883 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ______ Β7__ 5. Description of the invention ( 28) The tuning circuit 201, when it is a DVD, sequentially performs demodulation, deinterleaving, synchronization detection, etc. of 8-16 mode. When a certain amount of data is demodulated, the input request is output to the memory interface circuit 204. The memory-battery interface circuit 204 will accept the input request at a certain time, and transfer the demodulated data from the demodulation circuit 201 to the data memory (DR A M) 2 1 2. When a certain amount of data (when it is a DVD, it is 1 sector: 1 8 2 X 2 0 8 bits) is stored in the data memory 2 1 2, it is generated from the memory interface circuit 2 0 4 Interrupt request, and when the error correction circuit 203 recognizes the interrupt request, it starts error correction processing (decoding). When the error correction processing of a certain data is performed, the error correction circuit 203 will set a certain register, etc., and instruct the data output. Based on this, the ATAP I interface circuit 206 will issue an output request to the memory interface circuit 204. Memory interface 2 0 4 will accept the output request at a certain time, and output data from data memory 2 1 2 to the ATAP I interface circuit 2 06, and the ATAP I interface circuit 2 0 6 will send the data Interface circuit output to a host device such as a personal computer. In addition, the error correction circuit 203 sets a certain register of the general-purpose interface circuit (general-purpose I F) 2 3 0 according to the content of the instruction or the key, and instructs data output. When the data from the general-purpose I F 230 is an image data, it is supplied to an MPG circuit (not shown) to decompress the image and display it on a display device such as LCD. This paper size applies to China National Standard (CNS) A4 specification (210 x 297 mm) ------------------- Order -------- · Line ( Please read the precautions on the back before filling out this page) -31-Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 A7 __ B7 V. Description of the invention (29) Instructions at the end of instructions or keys, or at the next instruction or Until the keys are entered, the above actions continue. The following describes the information recording operation in the D V D drive system shown in Figure 10. In the same way as above, the microcomputer 2 2 0 will monitor the instruction input from the input / output circuit or the key input of the input / output, and when there is input, it will interpret the content of the input instruction or key, and according to this Began to move. If the microcomputer 2 2 0, the microcomputer interface circuit 2 0 7 is used to initialize the servo circuit 2 0 8 and the focus and tracking servo control are activated. Furthermore, the optical pickup 2 2 5 is moved to a certain position. position. ΑΑΑΡ I interface circuit 206 outputs data request 'to the host device and inputs data. When a certain amount of data is input, the J ATAPI interface circuit 206 sends an input request to the memory interface circuit 204. The memory interface circuit 2 0 4 accepts input requests at a certain time, and transfers the data input from the ATPO I interface circuit 2 0 6 to the data memory 2 1 2. When a certain amount of data (in the case of a DVD, it is 1 sector) is stored in the data memory 2 1 2, an interrupt request is sent from the memory interface circuit 2 0 4 to the error correction circuit 2 0 3, With this, the error correction circuit 2 03 performs parity processing (encoding) on the data held by the data memory 2 1 2. The error correction circuit 2 0 3, when the parity additional processing is completed for certain data in the data memory 2 1 2, a message that the parity additional processing has been completed is sent to the modulation circuit 2 0 2, and then, the adjustment Transformer circuit 202, this paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) i " ** 丨! _ 丨!丨 I! Order! 1 丨 —line ▲ (Please read the precautions on the back ^ before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 476883 A7 B7 V. Description of the invention (30) will be activated The data that has completed the co-location additional processing is transferred to the data transfer control of the modulation circuit 202, and the data is transferred from the data memory 2 12 to the modulation circuit 202 through the memory interface circuit 204. When it is a DVD, the modulation circuit 202 will sequentially perform interleaving, synchronous insertion, 8-16 modulation, etc., and output data. The output data is amplified in the pre-processing LSI 224 and written on the optical disc via the optical read-write head 2 2 5. Figure 11 shows the entire DVD drive system. The optical head 2 2 5 in FIG. 10 is composed of an actuator 2 2 5 B for focusing and tracking, and a head 2 2 5A formed by a laser diode. The motor drive IC 226 in FIG. 10 includes a driver 2 2 6 A of an actuator 225B, a driver 2 2 6 B of a screw-in motor 2 2 8, and a driver 2 2 6 C of a spindle motor 2 2 7. Here, read the channel (
Read channel )來總稱前處理LS I 224。讀取頻道包含 了讀取資訊的前置放大器(preamplifer )等。 DVD控制器1B則被使用在對CD及DVD般之碟 片2 3 0進行資訊之記錄•再生、以及對於上述碟片 * 2 3 0的伺服控制上。亦即,D V D控制器1 B,則從讀 取頻道2 2 4取得搜軌誤差信號T E以及聚焦誤差信號 F E等,而如達成讀寫頭2 2 5 A之搜軌以及聚焦等般地 ,將伺服控制信號S V D A 〇、S V D A 1送到驅動器 2 2 6 A,將伺服控制信號S V D A 2送到驅動器 2 2 6 B,而將伺服控制信號S V D A 3送到驅動器 2 26C。更者,DVD控制器1B,則輸入從碟片 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -33· -l,r — — — — — — — — — ^--------^illln! . (請^閲讀背之注意事項再填寫本頁) 476883 A7 _ B7 五、發明說明(31 ) 2 3 〇被讀取,且在讀取頻道2 2 4中被放大之信號 D 1 N而加以解調,又對應該要寫入到碟片2 3 0的資料 實施調變。作爲主介面的上述A T A P I介面電路,則經 由增強(enhanced ) I D E匯流排等的匯流排,而與個人 電腦等的主機裝置連接,而輸入指令等,進行狀態等的表 示與資料的輸出等。 光碟2 3 0的記錄資訊,則被讀寫頭2 2 5A所讀取 。讀寫頭2 2 5A,則藉由發光元件(雷射二極體)輸出 雷射光,而由受光元件(光二極體)檢測來自光碟2 3 0 的反射光。讀寫頭2 3 0的位置,則被致動器2 2 5 B與 螺進馬達2 2 8所控制。 由讀寫頭2 2 5 A所輸出的信號,則在讀取頻道 2 2 4中被放大而被數位化。微電腦2 2 0,則利用 S C I以及I /〇埠,對讀取頻道進行控制。 微電腦2 2 0的I /〇埠,將常開型開關、常閉型開 關的控制信號送到碟片2 3 0之未圖示的托盤(tray ), 且將彈出開關(inject switch )信號當作要求中斷信號力口 以輸入,而將托盤(裝載loading )馬達,根據微電腦 2 2 0之PWM計時器的輸出加以驅動。 第1 1圖所示之DVD驅動系統,除了 DVD之外, 也可以對CD — ROM進行記錄再生、或是對CD - DA 進行再生。基本的再生處理等則大約與DVD相同。亦即 ,與DVD同樣地,由讀寫頭225A,從CD — ROM 或CD — DA的碟片所讀取的信_號,當在讀取頻道2 2 4 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) --------訂------丨!線* 經濟部智慧財產局員工消費合作社印製 -34- 476883 A7 B7 五、發明說明(32) 的前置放大器被放大後,則藉由波形整形電路被整形成數 位波形。C D - R Ο Μ的資料,則在D V D控制器1 B之 上述解調電路2 0 1中被數位解調,而與上述同樣地,經 由錯誤訂正電路2 0 3進行誤差訂正,且藉由解碼器( descrambler )被解碼。經解碼處理後的資料,則在R Ο Μ 解碼器2 1 1中,從CD — ROM格式被解碼成主機裝置 的資料形式,而經由主介面電路2 0 6被送到主機裝置。 C D - DA的資料則在解調電路2 1 0中被解碼,在被儲 存在資料記憶體2 1 2而進行完錯誤訂正後,則經由主介 面電路2 0 6,被輸出到主機裝置。 微電腦2 2 0在載入碟片2 3 0時,則會讀取在光碟 上的T〇C ( Table Of Contents )資訊等,且將其儲存在 緩衝記憶體內。當爲C D時,導入(lead-in )部的T 0 C 資訊最多爲1 〇 〇曲,由於分別是9位元組等的資料’因 此,藉著儲存在記憶密度高的緩衝記億體,除了提高利用 效率外,由於藉著微電腦2 2 0可以隨時讀取,因此,在 搜尋時可以算出移動量、或是根據來自主介面的指令等而 立即使用。 又,微電腦2 2 0對於DVD — ROM碟片隨時讀取 資料的I D或是防止複製資料。 更者,微電腦2 2 0則對DVD — RAM碟片讀取缺 陷資訊,且將其儲存在緩衝記憶體’微電腦2 2 0 ’則將 由主介面2 0 6所指不的邏輯位址轉換成實體位址。 第1 2圖係表第1 1圖之D -V D驅動系統之系統動作 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) (請先閲讀背面之注意事項再填寫本頁) ----1---訂---------線* 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 476883 A7 B7 五、發明說明(33) 圖。在第1 2圖中,將上述資料處理部2 0 — 1〜2 0 — η的並列度設爲P、並列度初始値設爲P i、動作速度設 爲S、動作速度初始値設爲S i。 在重置電源爲Ο N後,則打開托盤,當確認裝塡好碟 片230時(SI、S2、S3),則初期設定爲P=1 、S = 1 ,而開始對碟片進行預掃描(S4)。根據由預 掃掃所讀取的資訊來調查碟片的種類以及誤差率(error rate )等(S5〜S8)。而根據其結果,將並列度Pi設 定成1〜4 (S9〜S 12)。而此則是根據碟片狀況來 設定能力。 接著則輸入指令(S 1 3 )。當所輸入的指令爲> PLAY 〃時(S14),則設定成 S = Si、P = P i (S 1 5)。而當輸入指令爲’JUMP、、 "STOP "時(S 1 7、S 1 8 ),則設定爲 F = 1、S = 1 ,而 導致處理能力降低(S 1 9、S 2 0 )。而此是根據指令 來設定能力。 在此,上述指令,在主介面的規格,則也可以使用當 作vendor unique來使用的指令。 接著則說明在P L A Y模式(m 〇 d e = 1 )下的動 作。第1 2圖,則在P LAY模式中不改變資料處理部的 並列度。而此是因爲在動作中,當要改變資料處理部的並 列度時,則必須要有能夠掌握住在資料處理部中之處理狀 態的構成或是控制,若是不採用該構成或是控制時,則不 容易變更之故。因此,在第1 2麗I的例中,在PLAY模 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --:------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) - 36· 476883 經濟部智慧財產局員工消費合作社印製 A7 __B7____ 五、發明說明(34) 式下之動作能力的變更則只限定在動作速度的變更。 在P LAY模式下,通常是根據步驟s 1 6的設定內 容,而以S=Si、 P=Pi的能力來動作。當誤差增加 ,而處理無法跟上時,則錯誤訂正電路2 0 3會送出( assert )上述外部待機信號5 5。當微電腦2 2 0檢測到上 述外部待機信號之等待(w a i t )指示時,則判斷是否S = 4 ( S 2 2 ),若是3 = 4,則微電腦2 2 0會對解調電 路201等發出暫時停止動作的指示(S23)。若不是 S二4時,則設成S = S + 1,而提高錯誤訂正電路 203的動作速度(S24)。而此則是一藉由控制錯誤 訂正電路2 0 3的速度來改變處理能力的例子。 又,當消耗電流增加,而超過任意的設定値時( 5 2 5 ),微電腦220會以S=1作爲下限,而設定變 更成S = S - 1,降低動作速度,而減少消耗電力( S 2 6、S 2 7 )。而此則是一藉由外部條件來改變處理 能力的例子。 當在上述步驟S 2 5的判定中,消耗電流未增加時, 則在一定期間內監視等待(wah )指示與消耗電力( S 2 8 ),當沒有變化時,也可以回到S = S i ( S 2 9 )° 其他雖然未表示在第1 2圖中,但是也可以判斷主機 裝置的系統構成,當主機裝置爲個人電腦時,則判斷是筆 記型或是桌上型,而來設定並列度。例如筆記型時的並列 度會較爲桌上型時減少。又,當爲DVD - RAM等的系 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱1 ΖΙΓ --2------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 476883 A7 _ ____ B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(35) 統時,則必須要有錯誤訂正(資料解碼)與資料編碼的處 理。資料編碼的處理的內容則較資料的解碼爲少。又,碟 片的寫入速度也會較讀取速度爲慢。考慮此一情形,在寫 入時’也可以降低在錯誤訂正電路2 0 3中之資料處理部 的並列度來使用。 《資料處理裝置之其他的形態》 上述資料處理裝置1 A、 1 B雖然是S I M D形態, 但是資料處理裝置也可以是Μ I M D形態。 第1 3圖係表Μ I MD型的資料處理裝置之一例。而 與第1圖的不同點即是資料處理部2 0 C — 1〜2 0 C — η是分別讀取命令,而且個別地進行演算處理。因此,各 資料處理部2 0 C - 1〜2 0 C — η具有命令控制部與演 算部。資料處理部2 0 C - 1〜2 0 C - η則例如是 CPU單元、浮點運算單元、數位信號處理單元般的電路 。在該Μ I MD型的資料處理裝置,則與第1圖同樣地, 可以根據針對動作速度暫存器3 2之來自外部的設定値, 而來控制動作速度。更者,可以根據針對並列度暫存器 4 1之來自外部的設定値,而來控制資料處理部2 0 C — 1〜20C — η的並列度。 第1 4圖係表其他之資料處理裝置的例子。同圖所示 路路 電電 出面 輸介 、體 D 憶 5 記 路 、 電 D 入 7 輸體 由憶資 係記 g , 料勖 D 資作 1的i 置料並 裝資作 理存個 處儲 η 料於以 資用可 的、 ' 路 ί ιρτ m: 理 處 料Read channel) to collectively pre-process LS I 224. The read channel includes a preamplifer for reading information. The DVD controller 1B is used for recording and reproduction of information on CD and DVD-like discs 230 and servo control of the above-mentioned discs * 230. That is, the DVD controller 1 B obtains the tracking error signal TE, the focus error signal FE, and the like from the read channel 2 2 4, and if it achieves the tracking and focus of the read head 2 2 5 A, it will Servo control signals SVDA 0 and SVDA 1 are sent to drive 2 2 6 A, servo control signals SVDA 2 are sent to drive 2 2 6 B, and servo control signals SVDA 3 are sent to drive 2 26C. Furthermore, for DVD controller 1B, the paper size from the disc is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -33 · -l, r — — — — — — — — — ^- ------- ^ illln!. (please ^ read the notes on the back and fill in this page again) 476883 A7 _ B7 V. Description of the invention (31) 2 3 〇 is read, and on the read channel 2 2 4 The amplified signal D 1 N is demodulated, and the data to be written to the disc 230 is modulated. The A T A P I interface circuit as the main interface is connected to a host device such as a personal computer via an enhanced I D E bus and the like, and inputs instructions, etc., and performs status indication and data output. The recorded information of the disc 2 3 0 is read by the head 2 2 5A. The read / write head 2 2 5A outputs laser light through a light emitting element (laser diode), and the reflected light from the optical disc 2 3 0 is detected by a light receiving element (light diode). The position of the head 2 3 0 is controlled by the actuator 2 2 5 B and the screw-in motor 2 2 8. The signal output from the head 2 2 5 A is amplified and digitized in the read channel 2 2 4. The microcomputer 2 2 0 uses the S C I and I / 〇 ports to control the read channel. The microcomputer 2 I / 0 port sends control signals of normally open switches and normally closed switches to a tray (not shown) of the disc 2 30, and the eject switch signal is used as The operation requires the interruption of the signal to be input, and the tray (loading) motor is driven according to the output of the PWM timer of the microcomputer 2 2 0. The DVD drive system shown in Fig. 11 can record and reproduce CD-ROM or CD-DA in addition to DVD. The basic playback process is about the same as DVD. That is, like the DVD, the signal __ read by the head 225A from the CD-ROM or CD-DA disc, when reading the channel 2 2 4 This paper standard applies the Chinese National Standard (CNS ) A4 size (210 X 297 mm) (Please read the notes on the back before filling this page) -------- Order ------ 丨! Line * Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -34- 476883 A7 B7 V. After the preamplifier of (32) is amplified, it is shaped into a digital waveform by a waveform shaping circuit. The CD-R OM data is digitally demodulated in the demodulation circuit 2 01 of the DVD controller 1 B, and the error correction is performed by the error correction circuit 2 0 3 in the same way as above, and the data is decoded by decoding. The decoder (descrambler) is decoded. The decoded data is decoded from the CD-ROM format into the data format of the host device in the ROM decoder 2 1 1 and sent to the host device via the main interface circuit 206. The CD-DA data is decoded in the demodulation circuit 210, and after the error correction is stored in the data memory 21, it is output to the host device via the main interface circuit 206. When the microcomputer 2 2 0 loads the disc 2 3 0, it will read the TOC (Table Of Contents) information on the disc and store it in the buffer memory. When it is a CD, the T 0 C information of the lead-in part is up to 100 songs. Since it is 9-byte data, etc., therefore, it is stored in a high-density buffer memory. In addition to improving the use efficiency, since it can be read at any time by the microcomputer 2 2 0, it can calculate the amount of movement during the search, or use it immediately according to instructions from the main interface. In addition, the microcomputer 2 2 can read the ID of data at any time for DVD-ROM discs or prevent copying of data. Furthermore, the microcomputer 2 2 reads the defect information from the DVD-RAM disc and stores it in the buffer memory. The 'microcomputer 2 2 0' converts the logical address indicated by the main interface 2 06 into an entity. Address. Figure 12 is the system operation of the D-VD drive system in Figure 11 of this table. The paper size is applicable to China National Standard (CNS) A4 (210 X 297). (Please read the precautions on the back before filling this page. ) ---- 1 --- Order --------- line * Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employee Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 476883 A7 B7 V. Invention Description (33 ) Figure. In FIG. 12, the degree of parallelism of the data processing unit 2 0 — 1 to 2 0 — η is set to P, the initial degree of parallelism is set to P i, the operating speed is set to S, and the initial operating speed is set to S. i. After resetting the power to 0 N, open the tray. When it is confirmed that the disc 230 is installed (SI, S2, S3), the initial settings are P = 1 and S = 1, and the disc is pre-scanned. (S4). Based on the information read by the pre-scan, the type of disc and error rate (S5 ~ S8) are investigated. Based on the results, the degree of parallelism Pi is set to 1 to 4 (S9 to S 12). The ability is set according to the condition of the disc. Then enter the instruction (S 1 3). When the input command is> PLAY ((S14), it is set to S = Si and P = P i (S 1 5). When the input command is' JUMP ,, " STOP " (S 1 7, S 1 8), it is set to F = 1, S = 1 and the processing capacity is reduced (S 1 9, S 2 0) . And this is to set the capability according to the instruction. Here, the above-mentioned commands can also be used as vendor unique commands in the specifications of the main interface. Next, the operation in the P L A Y mode (m o d e = 1) will be described. Figure 12 shows that the parallelism of the data processing unit is not changed in the P LAY mode. This is because in the operation, when the degree of parallelism of the data processing department is to be changed, it is necessary to have a structure or control capable of grasping the processing status living in the data processing department. If the structure or control is not adopted, It is not easy to change. Therefore, in the case of the 12th Li I, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied to the paper size of the PLAY template-: ------------- ----- Order --------- line (please read the precautions on the back before filling this page)-36 · 476883 Printed by A7 __B7____, Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 34) The change of movement ability under the formula is limited to the change of movement speed. In the P LAY mode, it usually operates with the capabilities of S = Si and P = Pi according to the settings in step s 1 6. When the error increases and the processing cannot keep up, the error correction circuit 2 0 3 will assert (assert) the external standby signal 5 5 described above. When the microcomputer 2 2 0 detects the wait instruction of the external standby signal, it determines whether S = 4 (S 2 2). If 3 = 4, the micro computer 2 2 0 temporarily issues a demodulation circuit 201 and the like. Instruction to stop the operation (S23). If it is not S = 4, S = S + 1 is set, and the operation speed of the error correction circuit 203 is increased (S24). This is an example of changing the processing capacity by controlling the speed of the error correction circuit 203. In addition, when the consumption current increases and exceeds an arbitrary setting (5 2 5), the microcomputer 220 sets S = 1 as the lower limit and changes the setting to S = S-1 to reduce the operating speed and reduce power consumption (S 2 6, S 2 7). This is an example of changing the processing power by external conditions. When the current consumption does not increase in the determination in step S 2 5 above, the waiting (wah) indication and power consumption (S 2 8) are monitored for a certain period of time. When there is no change, it can also return to S = S i (S 2 9) ° Although it is not shown in Figure 12 above, the system configuration of the host device can also be determined. When the host device is a personal computer, it can be determined as a notebook or desktop type to set the parallel. degree. For example, the degree of juxtaposition in the notebook type will be less than that in the desktop type. In addition, when it is a DVD-RAM or other paper size, the Chinese National Standard (CNS) A4 specification (210 X 297 public love 1 ZOI-2--------) -Order --------- line (please read the notes on the back before filling out this page) 476883 A7 _ ____ B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs You must have error correction (data decoding) and data encoding processing. Data encoding processing content is less than data decoding. Also, the write speed of the disc will be slower than the read speed. Consider this one In some cases, it is also possible to reduce the juxtaposition of the data processing unit in the error correction circuit 203 at the time of writing. "Other forms of data processing device" Although the above-mentioned data processing devices 1 A and 1 B are in SIMD form However, the data processing device may also be in the form of M IMD. Fig. 13 is an example of the data processing device of the M I MD type. The difference from Fig. 1 is the data processing unit 2 0 C — 1 ~ 2 0 C — η is a separate read command, and calculation processing is performed individually. Therefore, each data processing unit 2 0 C-1 to 2 0 C — η has a command control unit and a calculation unit. The data processing unit 2 0 C-1 to 2 0 C-η is a circuit such as a CPU unit, a floating-point arithmetic unit, and a digital signal processing unit. In this MI MD type data processing device, as in the first figure, the operation speed can be controlled based on the external setting of the operation speed register 32, and the operation speed can be controlled according to the parallel operation. The external register of the degree register 41 is used to control the parallel degree of the data processing unit 20 C — 1 to 20 C — η. Figure 14 shows an example of other data processing devices. It is shown in the same figure. The road and the electricity come out of the media, the body D remembers the 5 records, the electricity D enters the 7 records, the memory is recorded by the memory resource department g, and the material D is used as the i for the 1 material, and it is stored as a storage place. Available, 'Road ί ιρτ m: Dispose of materials
DD
IX (請先閲讀背面之注意事項再填寫本頁)IX (Please read the notes on the back before filling this page)
D D 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 476883 Α7 -----Β7 五、發明說明(36) (請先閱讀背面之注意事項再填寫本頁) 2 〇 D - η、將資料呈並列地供給到資料處理電路的解多 工器4 0 2、根據並列的處理結果,而進行資料輸出的多 工器4 0 1、.並列度暫存器4 1、以及並列度控制電路 4 〇 〇所構成。 在上述並列度暫存器4 1,則經由未圖示的外部端子 ’而從外部設定並列度控制資料。上述並列度控制電路 4 0 0,則根據被設定在並列度暫存器4 1的並列度控制 資料,而來控制上述解多工器4 0 2、資料處理電路 2 0 D — 1〜2 0 D — η、以及多工器4 0 1。 上述輸入電路5 D,則因應必要,對從DVD等的記 錄媒體所讀取的資料實施解調等的前處理,且將其轉送到 資料記憶體7 D。此時,由於很多的情形資料所輸入的順 序並不適於處理的順序,因此,在暫時儲存在資料記億體 7 D後,則轉換成適於處理的順序,且通過解多工器 4 0 2,並列地被供給到資料處理電路2 0 D — 1〜 經濟部智慧財產局員工消費合作社印製 2 0D- η。雖然處理的結果,不一定限於輸出,但是在 第1 4圖中,則以輸出來說明。雖然不限於完全同時;但 是並列而得到的處理結果,則經由上述多工器4 0 1,被 儲存在資料記憶體7 D。輸出電路6 D,則根據適當的順 序、轉送速度來輸出被儲存在資料記憶體7 D的處理結果 。記憶體介面電路4 D,則針對來自輸入電路5 D、輸出 電路6D、以及資料處理電路20D - 1〜20D - η之 記憶體存取要求,來調停其競爭狀態。 由於資料處理電路2 0 D - 〜2 0 D — η的並列化 "— 二 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -39- 476883 A7 _ B7 五、發明說明(37) 對於提高整體之處理能力極爲有效,因此常被採用。對於 想要採用資料處理裝置1 D的資料處理系統,由於由使用 環境等的所要求之最大處理能力高,因此,當採用並列處 理時,可以有效地滿足最大處理性能的規格。爲了要滿足 最大處理能力的規格,對於並列地設有η個資料處理電路 2 0D— 1〜2 0D — η,然在一般的使用狀態下只需要 m個者而言,則是從外部,將並列度m (m< η )設定在 並列度暫存器41,而控制解多工器4 Ο 2、多工器 40 1、資料處理電路20D— 1〜20D - η,根據並 列度m而動作。此時,藉著並列度控制電路4 0 0控制不 將時脈信號供給到不動作的處理電路,可以將整個資料處 理電路的消耗電力控制成m / η,雖然整體必須要加上其 他電路消耗電力的固定値,但由於大多數的情形,資料處 理電路占整體之消耗電力的比例高,因此,整體之消耗電 力減低效果也大。 《根據速度控制、並列度控制的效果》 由於可以從外部來控制以符號2 0 - 1〜2 0 — η爲 代表之資料處理部的並列度,因此,至少可以根據外部的 狀況,來控制資料處理裝置(1 A、1 B )的處理能力與 電力消耗。又,由於可以從外部來改變動作速度’因此’ 同樣地,可以根據外部的狀況來控制資料處理裝置的處理 能力與電力消耗;特別是由於速度控制可以是在與資料處 理步驟的進展狀況無關,而完全不會對處理順序造成影響 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) <請先閲讀背面之注意事項再填寫本頁) ••裝--------訂---------線* 經濟部智慧財產局員工消費合作社印製 476883 A7 B7 五、發明說明(38) 的情況下進行,因此,即使是在一連串的處理途中,也能 夠自由地進行速度控制。 (請先閱讀背面之注意事項再填寫本頁) 因此,藉著可以同時改變並列度與動作速度,可以更 精確地進行處理能力與消耗電力的控制。 根據對於資料記憶體7的資料的儲存狀況來監視資料 處理狀況,而根據外部待機信號5 5,將其狀況通知外部 ,藉此,更容易從外部來控制處理能力。更者,或是設成 可以直接從外部來參照爲了監視而設的指標器5 1〜5 3 ,則可以使得從外部更容易來控制處理能力。 雖然SIMD型的資料處理裝置大多被利用在圖像或 是聲音處理等的處理中,而試圖提升其資料·處理能力,但 是也會有因爲演算處理內容或是演算對象資料,而只能夠 利用1 0 %之本來的演算處理能力的情形。此時,如上所 述,若是能夠從外部彈性地進行速度控制或是並列度控制 ,則可以將提高資料處理效率與削減浪費之電力消耗的效 果發揮到最大極限。例如當要將經壓縮的資料予以解壓縮 時,由於所必須的處理會根據資料而改變,因此,若是根 經濟部智慧財產局員工消費合作社印製 據資料來改變處理能力時,則可以減低不希望的消耗電力 〇 又,當利用在錯誤訂正電路2 0 3時,則錯誤訂正處 理,由於若是沒有錯誤,則不需要執行,因此,若是根據 其處理狀況來改變並列度時,則可以將提高資料處理效率 與削減浪費的電力消耗的效果發揮到最大的限度。又,通 常當處理能力降低,而根據指標_器5 1〜5 3的內容或是 ㈣41 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 476883 A7 一 B7 五、發明說明(39) (請先閱讀背面之注意事項再填寫本頁) 外部待機信號5 5的狀態,導致未處理的資料變多時,則 也可以提高處理能力。又,當已經處理完畢的資料變多時 ,則可以降低處理能力。藉此,可以根據資料的內容,換 言之,必要的處理能力,來減低平均的消耗電力。 當利用在DVD等的碟片驅動裝置時,藉著根據外部 的狀況或是碟片的狀況來調節處理能力,而能夠減低消耗 電力。對於DVD - RAM等的系統而言,必須要有錯誤 訂正(資料解碼)與資料編碼的處理。資料編碼的處理內 容會較資料的解碼爲少。又,由於碟片的寫入速度較讀取 速度爲慢,因此,在寫入時,則降低並列度,可以減少消 耗電力。 由於可以根據資料處理裝置被利用之系統,例如筆記 型的個人電腦/桌上型的個人電腦來切換消耗電力,因此 ,對於系統的開發效率以及提高生產性極有貢獻。 對於可改變處理能力的錯誤訂正電路而言,對共同使 用在編碼/解碼的處理,而只有癥候(syndrome )的演算 處理必須要編碼時,可以降低並列度,或是提高時脈的分 頻比,根據所要求的處理能力,來減少消耗電力。 經濟部智慧財產局員工消費合作社印製 即使是將處理速度或是並列度設成可變化,然而卻不 需要變更基本的程式,因此不會阻礙到程式的開發效率。 時脈信號的分頻比,由於在動作中容易變更,因此能夠隨 時進行最佳的控制。 根據來自內藏有主介面電路之例如主電腦的指令’可 以變更消耗電力。上述指令,藉著使用主介面電路中所準 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -42· 476883 A7 B7 五、發明說明(40) 備的使用者定義指令,則在驅動系統上不需要新的硬體等 〇 以上雖然是根據實施例來具體地說明本發明人所提出 的發明,但是本發明並不限於此,在不脫離其主旨的範圍 內,可進行各種的變更。 例如也可以只利用速度控制與並列度控制的其中一者 來構成資料處理裝置。又,也可以不針對各資料處理部採 用待機控制。又,資料記億體也可以內藏在資料處理裝置 。相反地,用於命令控制部的程式記億體也可以是外加。 被設在資料處理裝置的各種電路,不限於第1圖中所 述的電路,也可以適當地變化。又,根據資料處理部的演 算處理並不限於錯誤訂正,也可以是解壓縮•壓縮、調變 •解調等的處理。因此,資料處理裝置,並不限於應用在 碟片控制器用的L S I的情形,也可以廣泛地應用在通信 用的L S I等上。 又,在第1圖中的上述的上述處理能力變更用的控制 暫存器32、 41以及指標器51、 52、 53,雖然是 設在資料處理裝置之中,但是也可以配置在微電腦2 0 0 等的系統控制器。 產業上的可利用性 本發明可以廣泛地被利用在DVD或CD—ROM等 之光碟驅動裝置、通信用的介面控制器、乃至於如數位照 相機或數位攝影機等之進行圖像_資料之壓縮•解壓縮的信 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閲讀背面之注意事項再填寫本頁)DD The size of this paper applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 476883 Α7 ----- Β7 V. Description of the invention (36) (Please read the precautions on the back before filling this page) 2 〇 D-η, a demultiplexer 4 0 that supplies data to the data processing circuit in parallel, and a multiplexer 4 0 that outputs data according to the results of the parallel processing 4 1. a parallel degree register 4 1, And a parallel degree control circuit 400. In the parallel degree register 41, the parallel degree control data is externally set via an external terminal (not shown). The parallel degree control circuit 4 0 0 controls the demultiplexer 4 0 2 according to the parallel degree control data set in the parallel degree register 41 1. The data processing circuit 2 0 D — 1 ~ 2 0 D — η, and multiplexer 4 0 1. The input circuit 5D performs preprocessing such as demodulation on data read from a recording medium such as a DVD as necessary, and transfers the data to the data memory 7D. At this time, because the order in which data is input is not suitable for processing in many cases, after being temporarily stored in the data record 7D, it is converted into a suitable order for processing, and the demultiplexer 4 0 2. It is supplied in parallel to the data processing circuit 2 0 D — 1 ~ printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 0D- η. Although the result of the processing is not necessarily limited to the output, in Fig. 14, the output is used for illustration. Although it is not limited to being completely simultaneous; processing results obtained in parallel are stored in the data memory 7D through the multiplexer 401 above. The output circuit 6 D outputs the processing result stored in the data memory 7 D according to an appropriate sequence and transfer speed. The memory interface circuit 4 D mediates its competition status with respect to the memory access requirements from the input circuit 5 D, the output circuit 6D, and the data processing circuits 20D-1 to 20D-η. As the data processing circuit 2 0 D-~ 2 0 D — parallelization of η " — two paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) -39- 476883 A7 _ B7 V. Invention Note (37) is very effective in improving the overall processing capacity, so it is often used. For a data processing system that wants to use the data processing device 1D, the maximum processing capacity required by the use environment and the like is high. Therefore, when parallel processing is used, the specifications for maximum processing performance can be effectively met. In order to meet the specifications of the maximum processing capacity, n data processing circuits 2 0D— 1 to 2 0D — η are provided in parallel. However, only m need to be used in a normal use state. The parallel degree m (m < η) is set in the parallel degree register 41 and controls the demultiplexer 4 〇 2, the multiplexer 40 1. The data processing circuit 20D— 1 ~ 20D-η, operates according to the parallel degree m . At this time, by controlling the parallelism control circuit 400 to not supply the clock signal to the non-operation processing circuit, the power consumption of the entire data processing circuit can be controlled to m / η, although the overall consumption of other circuits must be added The power is fixed, but in most cases, the data processing circuit accounts for a high proportion of the overall power consumption, so the overall power consumption reduction effect is also large. "Effects of speed control and juxtaposition control" Since the juxtaposition of the data processing section represented by the symbols 2 0-1 to 2 0-η can be controlled from the outside, at least the data can be controlled according to external conditions Processing capacity and power consumption of the processing devices (1 A, 1 B). In addition, since the operating speed can be changed from the outside, the processing capacity and power consumption of the data processing device can also be controlled according to external conditions. In particular, the speed control can be independent of the progress of the data processing step. And it will not affect the processing order at all. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) < Please read the precautions on the back before filling this page) •• Installation ----- --- Order --------- line * Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 A7 B7 V. The invention description (38) is carried out. Therefore, even in the middle of a series of processing, Speed control can also be performed freely. (Please read the precautions on the back before filling out this page.) Therefore, by changing the juxtaposition and operating speed at the same time, you can control the processing power and power consumption more accurately. The data processing status is monitored based on the storage status of the data in the data memory 7, and the status is notified to the outside based on the external standby signal 55, thereby making it easier to control the processing capacity from the outside. Furthermore, if it is set to be able to directly refer to the indicators 5 1 to 5 3 provided for monitoring from the outside, it is possible to make it easier to control the processing capacity from the outside. Although SIMD-type data processing devices are mostly used in image or sound processing to try to improve their data and processing capabilities, there may also be only 1 due to the content of calculation processing or calculation target data. 0% of the original calculation processing capacity. At this time, as described above, if speed control or juxtaposition control can be flexibly performed from the outside, the effects of improving data processing efficiency and reducing wasteful power consumption can be maximized. For example, when the compressed data is to be decompressed, the necessary processing will be changed according to the data. Therefore, if the processing capacity is changed by printing data according to the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, it can reduce Desired power consumption. When used in the error correction circuit 203, error correction processing is performed. If there is no error, it is not necessary to execute. Therefore, if the degree of parallelism is changed according to the processing status, it can be improved. Data processing efficiency and the effect of reducing wasteful power consumption are maximized. In addition, usually when the processing capacity is reduced, according to the content of the index device 5 1 ~ 5 3 or ㈣41-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 476883 A7 One B7 V. Invention Note (39) (Please read the precautions on the back before filling in this page) When the status of the external standby signal 5 5 causes more unprocessed data, the processing capacity can also be improved. In addition, when more data has been processed, the processing capacity can be reduced. This can reduce the average power consumption based on the content of the data, in other words, the necessary processing power. When a disc drive device such as a DVD is used, the power consumption can be reduced by adjusting the processing capacity according to the external conditions or the condition of the disc. For systems such as DVD-RAM, error correction (data decoding) and data encoding must be processed. The processing of data encoding will be less than the decoding of data. In addition, since the writing speed of the disc is slower than the reading speed, the parallelism can be reduced during writing, and power consumption can be reduced. Since the power consumption can be switched according to the system in which the data processing device is used, such as a notebook personal computer / desktop personal computer, it greatly contributes to the development efficiency and productivity of the system. For the error correction circuit that can change the processing capacity, when the encoding / decoding process is used in common, and only the syndrome calculation process must be encoded, the degree of parallelism can be reduced, or the clock frequency division ratio can be increased , According to the required processing power, to reduce power consumption. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Even if the processing speed or parallelism is set to be variable, there is no need to change the basic program, so it will not hinder the efficiency of program development. Since the frequency division ratio of the clock signal is easily changed during operation, it can be optimally controlled at any time. The power consumption can be changed according to a command from a host computer with a built-in main circuit, for example. The above instructions, by using the paper size approved in the main interface circuit, are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -42 · 476883 A7 B7 V. Description of the invention (40) User-defined instructions prepared No new hardware or the like is required on the drive system. Although the above describes the invention proposed by the present inventors specifically based on the embodiments, the present invention is not limited to this. Make various changes. For example, the data processing device may be configured using only one of speed control and parallelism control. The standby control may not be applied to each data processing unit. In addition, the data recorder can also be built into the data processing device. Conversely, the program memory used for the command control unit can be added. The various circuits provided in the data processing device are not limited to those described in the first figure, and may be appropriately changed. In addition, the calculation processing performed by the data processing unit is not limited to error correction, but may be processing such as decompression, compression, modulation, and demodulation. Therefore, the data processing device is not limited to the case where it is applied to the L S I for the disc controller, and can be widely applied to the L S I for communication and the like. The control registers 32 and 41 and the indicators 51, 52, and 53 for changing the processing capability described above in FIG. 1 are provided in the data processing device, but may be disposed in the microcomputer 20. 0 and other system controllers. Industrial Applicability The present invention can be widely used in optical disc drive devices such as DVDs, CD-ROMs, communication interface controllers, and even image_data compression such as digital cameras or digital video cameras. The size of the decompressed letter paper is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling in this page)
---1----訂---------線 I 經濟部智慧財產局員工消費合作社印製 -43- 476883 A7 __ B7 _ 五、發明說明(4υ 號處理裝置等。 圖面之簡單說明: ^ /第1圖係表本發明之資料處理裝置之一例的方塊圖。 、/第2圖係表時脈分頻電路之一例子的方塊圖。 ^第3圖係以模型來表示並列度與對應於動作速度之設 定狀況的處理能力的說明圖。 ν第4圖係表在監視電路中之記憶體指標的動作說明圖 〇 ν第5圖係表R S碼之錯誤訂正處理之代表的處理順序 的流程圖。 \第6圖係表在錯誤訂正處理中之資料處理部之自立的 待機控制之第1動作例的時序圖。 >第7圖係表在錯誤訂正處理中之資料處理部之自立的 待機控制之第2動作例的時序圖。 \第8圖係表在變更在錯誤訂正處理中之資料處理部之 並列度時之動作例的時序圖。 ‘ —:-----------------訂---------線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 的 細 詳 之 部 311 理 處 料 資 之 311 理 處 正 訂 誤 錯 於 適 表。 係圖 圖塊 9 方 第的 ) 例--- 1 ---- Order --------- Line I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-43- 476883 A7 __ B7 _ V. Description of the Invention (Processing device No. 4υ, etc. Figure The brief explanation is as follows: ^ / Figure 1 is a block diagram showing an example of the data processing device of the present invention. // Figure 2 is a block diagram showing an example of a clock frequency dividing circuit. ^ Figure 3 is a model An explanatory diagram showing the degree of parallelism and the processing capability corresponding to the setting status of the operating speed. Ν Figure 4 shows the operation of the memory index in the monitoring circuit. Figure 5 shows the RS code error correction processing. The flow chart of the representative processing sequence. Figure 6 is a timing chart of the first operation example of the stand-by standby control of the data processing section in the error correction processing. ≫ Figure 7 is the error correction processing in the table Timing chart of the second operation example of the independent standby control of the data processing section. \ Figure 8 is a timing chart of the operation example when the parallelism of the data processing section in the error correction process is changed. '—:- ---------------- Order --------- line (Please read the notes on the back before filling in this Page) The Ministry of Economic Affairs, Intellectual Property Bureau, Employees' Cooperatives printed detailed department 311 Department of Materials 311 Department is correcting the error in the appropriate table. (Picture 9)
的 例 一 之 細 詳 更 之 置 裝 m: 理 處 料 資 爲 有 備 表 係之 圖器 ο 制 1控 第 D V DThe details of the first example of the installation are more detailed: m: The material is handled as a plotter with a prepared watch system. Ο Control 1 D V D
圖 塊 方 的 統 系 titan 驅 D V D insrv 驅 D V D 示 表 地 體1 整第 係係 圖圖 12 1 1 ο 第Λ第圖 ,7 ' 程 流 統 系 驅 D V D 之 圖 的 作 。 動 圖統 塊系 π之 的 統 系 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -44- 經濟部智慧財產局員工消費合作社印製 476883 A7 B7 五、發明說明(42) ^第1 3圖係表Μ I MD型之資料處理裝置之一例的方 塊圖。 ν/第1 4圖係表其他之資料處理裝置的方塊圖。 主要元件對照表 1 Α 資料處理裝置 2 錯誤訂正電路 3 系統介面電路 4 記憶體介面電路 5 輸入電路 6 輸出電路 7 資料記憶體 20— 1〜20 — η 資料處理部 2 1 命令控制部 22 演算電路 23 緩衝記憶體 2 4 程式記憶體 ^ 25 控制信號 26 待機控制電路 2 7 - i 待機控制電路 30 時脈分頻電路 3 0 A 分頻器 3 0 B 選擇器 31 時脈脈衝產生器 _ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) IL----------0M--------訂---------線_ (請先閱讀背面之注意事項再填寫本頁) -45- 476883 A7 B7 五、發明說明(43) 經濟部智慧財產局員工消費合作社印製 3 2 動 作 速 度 暫 存 器 4 2 1〜 4 2 — η 及 4 3 1〜 4 3 — η 及 5 0 監 視 電 路 5 1 輸 入 資 料指 標 器 5 2 處 理 中 資 料 指 標 器 5 3 輸 出 資 料指 標 器 5 4 比 較 器 5 5 外 部 待 機 信 號 1 1 0 伽 維 瓦 體 乘 法 器 1 1 2 伽 羅 瓦 體 加 法 器 1 2 1 指 標 器 1 2 2 指 標 器 1 2 3 指 標 器 1 4 2 待 機 暫 存 器 1 4 3 電 路 1 5 0 伽 羅 瓦 緩 衝 器 1 6 〇 伽 羅 瓦 暫 存 器 1 7 〇 整 數 暫 存 器 1 8 〇 整 數 加 減 法 器 2 0 0 2 値 化 電 路 2 0 1 解 調 電 路 2 0 2 調 變 電 路 2 〇 3 錯 誤 訂 正 電 路 —:------1----------訂---------線 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -46- 476883 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(44) 204 記憶體介面電路 205 音頻介面電路 2 0 6 ATAPI介面電路 207 系統介面電路 2 0 8 伺服電路. 209 時脈振盪器 210 CD用的解調電路 2 11 R〇Μ解碼器 212 資料記憶體 220 微電腦 221 內部匯流排The block system of the titan drive D V D insrv drive D V D shows the structure of the whole body 1 Figure 12 1 1 ο Figure Λ, 7 'The process of the system drive D V D The system of the moving picture system is π. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -44- Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 A7 B7 V. Description of the invention ( 42) ^ Fig. 13 is a block diagram of an example of a data processing device of the table MD type. ν / Figure 14 is a block diagram of other data processing devices. Comparison table of main components 1 Α Data processing device 2 Error correction circuit 3 System interface circuit 4 Memory interface circuit 5 Input circuit 6 Output circuit 7 Data memory 20— 1 ~ 20 — η Data processing section 2 1 Command control section 22 Calculation circuit 23 Buffer memory 2 4 Program memory ^ 25 Control signal 26 Standby control circuit 2 7-i Standby control circuit 30 Clock frequency division circuit 3 0 A Frequency divider 3 0 B Selector 31 Clock pulse generator_ This paper Standards apply to China National Standard (CNS) A4 (210 X 297 mm) IL ---------- 0M -------- Order --------- Line_ ( (Please read the precautions on the back before filling this page) -45- 476883 A7 B7 V. Description of the invention (43) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 3 2 Motion speed register 4 2 1 ~ 4 2 — η And 4 3 1 to 4 3 — η and 5 0 monitoring circuit 5 1 input data indicator 5 2 data indicator 5 in process 5 output data indicator 5 4 comparator 5 5 external standby signal 1 1 0 Galiva body multiplication Device 1 1 2 Galois body adder 1 2 1 Indicator 1 2 2 Indicator 1 2 3 Indicator 1 4 2 Standby register 1 4 3 Circuit 1 5 0 Galois buffer 1 6 〇 Galois register 1 7 〇 Integer Register 1 8 〇 Integer adder and subtracter 2 0 0 2 Alternate circuit 2 0 1 Demodulation circuit 2 0 2 Modulation circuit 2 〇 3 Error correction circuit —: ------ 1 ----- ----- Order --------- Line (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -46 -476883 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (44) 204 Memory Interface Circuit 205 Audio Interface Circuit 2 0 6 ATAPI Interface Circuit 207 System Interface Circuit 2 0 8 Servo Circuit. 209 Clock Oscillation 210 Demodulation circuit for CD 2 11 ROM decoder 212 Data memory 220 Microcomputer 221 Internal bus
224 前處理LSI 225 光學讀寫頭 2 2 5 A 讀寫頭 2 2 5 B 致動器224 Pre-processing LSI 225 Optical head 2 2 5 A Head 2 2 5 B Actuator
2 2 6 馬達驅動I C 2 2 6 A 驅動器 2 2 6 B 驅動器 2 2 6 C 驅動器 227 螺進馬達 2 2 8 心軸馬達 230 汎用介面電路 2 3 0 碟片 1D 資料處理裝置 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -------------------訂---------線 (請先閲讀背面之注意事項再填寫本頁) -47- 476883 A7 B7 五、發明說明(45) 經濟部智慧財產局員工消費合作社印製 4 D 記 憶 體 介 面 電 路 5 D 輸 入 電 路 6 D 輸 出 電 路 7 D 資 料 記 憶 體 4 1 並 列 度 暫 存 器 4 0 0 並 列 度 控 制 電路 4 0 1 多 工 器 4 0 2 解 多 工 器 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -48-2 2 6 Motor driver IC 2 2 6 A driver 2 2 6 B driver 2 2 6 C driver 227 Screw-in motor 2 2 8 spindle motor 230 universal interface circuit 2 3 0 disc 1D data processing device This paper size is applicable to China Standard (CNS) A4 specification (210 X 297 mm) ------------------- Order --------- line (Please read the note on the back first Please fill in this page again for details) -47- 476883 A7 B7 V. Description of Invention (45) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 D Memory Interface Circuit 5 D Input Circuit 6 D Output Circuit 7 D Data Memory 4 1 Parallel degree register 4 0 0 Parallel degree control circuit 4 0 1 Multiplexer 4 0 2 Demultiplexer (please read the precautions on the back before filling this page) This paper standard applies to China National Standard (CNS) A4 (210 X 297 mm) -48-
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PCT/JP1999/003279 WO2000079405A1 (en) | 1999-06-21 | 1999-06-21 | Data processor |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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TWI449926B (en) * | 2012-04-09 | 2014-08-21 | Wistron Corp | Transmitting interface and method for determining transmitting signals |
US10175990B2 (en) | 2009-12-22 | 2019-01-08 | Intel Corporation | Gathering and scattering multiple data elements |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002236527A (en) * | 2001-02-08 | 2002-08-23 | Hitachi Ltd | Multiprocessor system and processor control method |
JP4549652B2 (en) * | 2003-10-27 | 2010-09-22 | パナソニック株式会社 | Processor system |
JP4209377B2 (en) * | 2004-10-20 | 2009-01-14 | 株式会社ルネサステクノロジ | Semiconductor device |
WO2006045798A1 (en) * | 2004-10-25 | 2006-05-04 | Robert Bosch Gmbh | Method and device for distributing data from at least one data source in a multiprocessor system |
US7836284B2 (en) * | 2005-06-09 | 2010-11-16 | Qualcomm Incorporated | Microprocessor with automatic selection of processing parallelism mode based on width data of instructions |
US7694114B2 (en) | 2005-06-09 | 2010-04-06 | Qualcomm Incorporated | Software selectable adjustment of SIMD parallelism |
KR101433620B1 (en) * | 2007-08-17 | 2014-08-25 | 삼성전자주식회사 | Decoder for increasing throughput using double buffering structure and pipelining technique and decoding method thereof |
KR101466694B1 (en) * | 2007-08-28 | 2014-11-28 | 삼성전자주식회사 | ECC circuit, and storage device having the same, and method there-of |
JP4740291B2 (en) * | 2008-07-02 | 2011-08-03 | 富士通セミコンダクター株式会社 | Integrated circuit device |
JP2013161271A (en) * | 2012-02-06 | 2013-08-19 | Ricoh Co Ltd | Simd (single instruction-stream multiple data-stream) type microprocessor |
JP5735610B2 (en) * | 2013-10-31 | 2015-06-17 | 日本電信電話株式会社 | Encoding device and decoding device |
GB2545458A (en) * | 2015-12-17 | 2017-06-21 | Minima Processor Oy | A system and a method for controlling operating voltage |
WO2018021036A1 (en) * | 2016-07-26 | 2018-02-01 | ソニーセミコンダクタソリューションズ株式会社 | Reception device, reception method, and program |
Family Cites Families (5)
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JPH086681A (en) * | 1994-04-18 | 1996-01-12 | Hitachi Ltd | Power saving control system |
JPH08153086A (en) * | 1994-11-30 | 1996-06-11 | Canon Inc | Processor |
JPH09138716A (en) * | 1995-11-14 | 1997-05-27 | Toshiba Corp | Electronic computer |
JPH09282305A (en) * | 1996-04-17 | 1997-10-31 | Ricoh Co Ltd | Digital data processor |
JPH10321645A (en) * | 1997-05-15 | 1998-12-04 | Fujitsu Ltd | Semiconductor device and its manufacture |
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Cited By (2)
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US10175990B2 (en) | 2009-12-22 | 2019-01-08 | Intel Corporation | Gathering and scattering multiple data elements |
TWI449926B (en) * | 2012-04-09 | 2014-08-21 | Wistron Corp | Transmitting interface and method for determining transmitting signals |
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