TW476883B - Data processing device - Google Patents

Abstract

A control resister (41) holds control data according to an instruction given externally. A parallelism control unit (40) determines the parallelism of the parallel operation of data processing sections (20-1 to 20-n) according to the control data held by the control resister. Furthermore, another control resister (32) controls the frequency of the operating clock signal (CLK) for the data processing sections according to the preset control data. Since the parallelism and operating speed of the data processing sections are thus controlled according to external conditions, the processing capacity and power consumption of the data processing sections are also readily controlled according to external state. Changing the parallelism of the data processing sections is suitable for the control prior to a series of processing. It is possible to change the clock frequency even during a series of processing.

Description

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 A7 B7 V. Description of the Invention (1) Technical Field The present invention relates to a data processing device capable of processing data in parallel, and in particular, to a data processing device suitable for, for example, error correction. SIMD (Single Instruction stream Multiple Data stream) type data processing device. 2. Description of the Related Art A data recording device for processing a recording medium such as a hard disk, a CD-ROM (Compact Disc-Read Only Memory), a DVD (Digital Video Disc), or a magneto-optical disk, etc., is produced by using a data recording device The wrong code for recording / praising. Coding terms are defined based on, for example, a collection of special numbers called Galois fields and special calculations defined with them. The set of Galoisian numbers has multiple definitions based on the set of numbers called primitive polynomials as definitions. At the same time, calculations also have different definitions based on primitive polynomials. The most commonly used code is the Reed Solomon code, especially used as an error correction code in a storage system or communication system where errors are easily concentrated in a part of the data. There is no error δ positive processing 'includes the step of calculating the Syndrome from the input code words, the step of calculating the error position polynomial and the error number polynomial from the symptoms, and the error position polynomial to obtain the error position. Steps, a step of obtaining the error number from the error position polynomial and the error number polynomial, and a step of correcting the error with a friend. Since it is from the storage system or the recording medium of the system or the communication system, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) iw — — — — —! · Pack 1! — 1 Order—— ί! -Line Win (Please read the precautions on the back side and fill in this page) -4- 476883 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs 2) The transmission path continuously receives the code word for processing. Therefore, the time allowed for the data processing including the error correction is determined according to the reading speed and the receiving speed of the data. Therefore, a certain degree of data processing capability is required for the circuits for error correction. From this point of view, error correction can be performed using an S IMD type processor or the like. However, in recent years, it is well known that not only notebook personal computers but also desktop personal computers using AC power are also expected to reduce power consumption. In the future, for circuits that perform error correction using the SI MD type, it will inevitably require a reduction in power consumption. The present inventors have discovered in the nature of calculus processing that even if parallel calculus processing has to be used to improve processing power, in some aspects of data processing, there may be cases in which all the data processing capabilities that they have may not be fully utilized. For example, when the above error correction processing capability frequently makes errors, it must be dealt with, but on the contrary, when fewer errors occur, the above error correction step may be almost unnecessary. A technique for reducing power consumption based on this viewpoint is described in Japanese Patent Application Laid-Open No. 9-18 5 5 89. Here, it is described that task allocation is performed on a data processing device having a parallel processing processor and a power supply controller of the Μ I MD (Multi Instruction stream Multiple Data stream) type, while maintaining the required processing power, and at the same time resting. The state of the processor stops supplying power, thereby achieving power saving. However, the power control set here must have 0S (〇 p er a t i n g S y s t e m), which makes the control very complicated. Japanese Patent Application Laid-Open No. 9-7 3 7 0 9 states that the paper used in the wrong version of the paper has a Chinese standard (CNS) A4 (210 X 297 mm). (Please read the precautions on the back before filling in this Page) ▼ Install ----— Order II ------ |! Wire Age-5- 476883 A7 B7 V. Description of the Invention (3) Positive circuit. For the data that does not check the error symbol, then No subsequent calculation processing is performed, and no control signal or clock is supplied to the data block. This control partly stops the clock supply based on the judgment of the circuit that performs the error correction. In processing, since the circuit part without the error data is processed, no substantial action is required at this time, so the clock is necessarily connected. Signals and the like are also stopped, which reduces power consumption. This technology does not control the correction processing capability of the error correction circuit, but only dynamically controls the supply of the clock signal according to the processing content. For cases where no error symbol is detected, the processing capability of Bay 1J error correction will not change. In Japanese Patent Application Laid-Open No. 9-1 4 7 4 8, although unnecessary operations are partially suppressed in the same manner, and power consumption is reduced, the processing capacity of the circuit itself remains constant. Regarding both the control of calculation processing power and the control of power consumption, etc., they are not considered. In addition, in W0 9 9/1 4 6 8 5 there is an example of error correction using an S I M D-type processor. The technology described here is to allow the control unit to give control information for calculation operations to a plurality of data processing units, and to make these SI MD processors that perform parallel operations have a data processing unit As a result of the calculation, the data processing unit is set to a standby control means in a standby state, and the above-mentioned control unit performs control to return each data processing unit from the standby state to the active state. In the standby state, the clock supply to the calculation circuit of the data processing section is stopped. Therefore, the data processing section that processes data without errors can be set to a standby state when other data processing sections are performing error correction steps. On the other hand, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page). ---- Line | Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 Α7 Β7 V. Description of the Invention (4) (Please read the precautions on the back before filling this page) When all data processing departments can be set to standby In the state, the control unit will eliminate the standby state and let each data processing unit execute the next step. By this, it is easy to suppress the unnecessary (waste) cycle caused by the standby state of the data processing unit to a minimum. , And can improve the performance of parallel calculus processing according to the s IMD form. If this technology is based on the viewpoint of low power consumption, like the conventional technology, it does not control the correction processing capability of the error correction circuit, but it can only dynamically control the clock signal according to the processing content. Supply situation. When no errors are detected, the error correction capability will not change. An object of the present invention is to provide a data processing device capable of controlling the data processing capacity and power consumption of a parallel data processing unit according to external conditions. Another object of the present invention is to provide a data processing device that can easily control the data processing capacity and power consumption of the parallel data processing units. The above and other objects and new features of the present invention will become apparent from the following description of the present specification and the attached drawings. Disclosure of inventions printed by employees' cooperatives in the Intellectual Property Bureau of the Ministry of Economic Affairs [1] The first aspect of the data processing device of the present invention is provided with a control register that can maintain control data in accordance with instructions from the outside. The degree control unit determines the degree of parallel operation of the parallel operations of the plurality of data processing units based on the control data held by the control register. In this way, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 476883 A7 _ B7 V. Description of the invention (5) 'By controlling the parallelism of the data processing department according to external conditions, it is easy to The status controls the processing capacity and power consumption of the data processing device. The above-mentioned parallelism can be controlled by controlling the supply and stop of clock signals to the data processing unit. That is, the above-mentioned multiple data processing units operate synchronously with the clock signal output from the clock generating circuit. Please read the note on the back first. The Ministry of Economic Affairs, Intellectual Property Bureau, Employee Consumption Cooperative printed the above-mentioned parallelism control unit. The selection gate of the above-mentioned data processing section is used to determine whether to output a clock signal. [$] The data processing device of the present invention can be operated in synchronization with the clock signal. Instructions, and the register, and the speed section that can determine the frequency of the clock signal according to the temporary storage by the control will be based on the divided frequency specified by the control data. In this way, it is easy to control data and power consumption according to external conditions to control according to external conditions. [3] The data processing device unit of the present invention controls the parallelism and movement of the data processing unit, and includes a parallel processing unit that can synchronize with a clock signal, and maintains a control register according to an instruction from the outside. The instruction clock signals are supplied to the selection gates respectively, and according to the control of the second processing section holding controller, the control section of the data processing unit determines the processing point of the data processing unit, and controls the data processing in the data processing system. For example, the third aspect of the processing of the speed of the timing pulse processing unit has a multi-processing device to control temporary data, and the frequency control speed of the degree control number. From the external point of view, the speed can be both. That is, the data place of the plurality of actions of the series has the first of the first control data, and the second control data item is kept

f This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -8-476883 A7 — ______ _____ B7 5. The second control register of the invention description (6), according to the first control register above The above-mentioned first control data held in the register determines the parallel degree control unit based on the parallel degree of the parallel operation of the plurality of data processing units, and the second control data held by the second control register, The speed control unit determines the frequency of the clock signal. The change of the parallel degree of the data processing department is suitable for controlling in advance of a series of processing. This is because when the degree of parallelism is changed in the course of parallel calculation processing, it often happens that the scheduled data to be processed cannot be processed. In contrast, the change of the clock frequency is not necessary to change the program, so it can be performed even during a series of processing. Therefore, by controlling both the juxtaposition and the operation speed of the data processing unit according to external conditions, the processing capacity and power consumption of the data processing device can be controlled more accurately from the outside. [4] The data processing device based on the above-mentioned viewpoints can more specifically adopt the following configuration. When processing multiple data blocks that are predicted to go through the same data processing step, it is best that the data processing device adopts the SI M D form. That is, it further has a command control unit that can interpret commands and output control information, and the command control unit supplies control information for calculation operations to the plurality of data processing units in parallel. When different processes are parallelized, the above data processing device may adopt the M IMD format. When the SI MD format is used, a program memory having an error correction format for error correction is stored in the data processing device, and The above control department obtains the order from the above-mentioned program memory: and uses the above-mentioned capital paper size to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) • mm— I mmt ---- Order --------- Line | Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed 476883 Α7-Β7 V. Description of the Invention (7 ) The material processing section performs error correction processing. For example, the data processing unit includes a Galois body calculation circuit that can perform multiplication and addition of Galois bodies. The control unit controls the Galois body calculation circuits and allows the data processing unit to perform error correction processing. In the SIMD-type data processing device, the control unit may transfer the unprocessed data stored in the data memory to the data processing unit, and transfer the data processed by the calculation in the data processing unit to the data processing unit. In the case of the above-mentioned data memory, a monitoring circuit that monitors the status of the above-mentioned arithmetic processing by the data processing unit. The monitoring circuit outputs an external signal to notify the status of the amount of unprocessed data remaining in the data memory exceeding a certain amount based on the access address to the data memory. According to the external status notification function, it is easy to judge the validity of the above-mentioned parallelism and other processing capabilities set from the outside of the SI D type data processing device. In other words, in addition to the external conditions of the data processing device, the internal state of the data processing device can also be taken into consideration to control the degree of parallelism and operation speed of the data processing unit. [5] A data processing device based on each of the above points can be integrated into a semiconductor integrated circuit by adding the following configuration. For example, an input circuit for inputting data from the outside, storing data input from the input circuit, supplying the stored data to the data processing section, and storing data calculated by the data processing section again. And output data stored in the data memory to an external output circuit. For example, the above input circuit may also include the paper size that is used to demodulate the input signal. The Chinese national standard (CNS) A4 specification (210 X 297 mm) is applicable. 11 ^ — — — — — — — — — — 1111111 · 11111111 · ( (Please read the precautions on the back before filling this page) -10- 476883 A7 B7______ 5. Description of the invention (8) Demodulation means and data transfer control means to transfer demodulated data to the above data memory. Furthermore, system interface means can also be added. The system interface means can be used to set transfer control conditions for the above-mentioned data transfer control means, or to set control data to the above-mentioned control register. Best Mode for Implementing the Invention "Summary of Data Processing Device" Fig. 1 shows an example of the data processing device of the present invention. The data processing device 1 A shown in the figure, although not particularly limited, is a semiconductor integrated circuit that is positioned as a peripheral controller, and is formed on a single semiconductor wafer like single crystal silicon. This data processing device 1 A includes an error correction circuit 2, a system interface circuit 3, a memory interface circuit 4, an input circuit 5, and an output circuit 6, although not particularly limited. These circuits share the regional data bus L D B, the regional address bus L A B, and the regional control bus L C B. A system controller such as a microcomputer (not shown) is connected to the system interface circuit 3, and a data memory 7 that can be used for a data buffer or the like is connected to the memory interface circuit 4. The input circuit 5 demodulates, for example, the trusted data or the read data from the disc, and stores it in the data memory 5 memory 7. The error correction circuit 2 reads the data stored in the data memory 7 and performs error checking, and performs error correction IE 'on the data having errors, and writes the correction data back to the data memory. The output circuit 6 reads the error-checked and error-corrected data from the data memory 7. The paper size applies the Chinese National Standard (CNS) A4 specification (21〇 &gt; &lt; 297mm) '' -11-(Please Read the precautions on the back before filling this page) | -------- Order --------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 Α7 Β7 V. Description of the invention (9) (Please read the precautions on the back before filling out this page) 'Perform necessary processing and output it to the outside. A terminal (not shown) is provided between the external and the semiconductor integrated circuit, and the data processing device 1 A transmits and receives data (signal) between the external and the semiconductor integrated circuit. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The above error correction circuit 2 is not shown, but the data is processed in the form of SIMD. That is, there are a plurality of data processing sections 20-1 to 20-η having the same circuit configuration as each other, and a command control section 21 common to each of the data processing sections 20-1 to 2 0-η. Each data processing unit 20-1 to 2 0-η includes an arithmetic circuit 2 2, a buffer memory 23, and a standby split circuit 26. The command control unit 2 1 ′ performs data transfer control between the data memory 7 and each of the buffer memory banks 23 according to the action programs stored in the program memory 24 and the data processing units 20-1 ~ 2 0 — calculus control of η. For example, when the input circuit 5 stores a certain amount of data in the data memory 7, the command control unit 21 requests an error correction process. The command control unit 21, which has received the command, interprets the commands fetched from the program memory 24, and repeatedly executes data loading processing, calculation processing, and data storage for the data in the data memory. Processing action. In the data loading processing, the calculation circuit 22 is used to perform error correction calculation processing on the data having errors. In the data storage processing, processing from the buffer memory 2 3 to write back the error-corrected data to the data memory 7 is performed. The above-mentioned calculation processing is executed in parallel based on the calculation control signals 25 provided to the data processing units 20-1 to 2 0-η in common. Based on the parallel calculation processing, the calculation processing capacity is improved. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) • 12- 476883 Α7 _ Β7 V. Description of the invention (ίο) "Variable speed control of data processing department" (Please read the back of the first (Please fill in this page again for precautions) The following explains the variable control of the calculation speed in the above error correction circuit 2. The error correction circuit 2 operates in synchronization with the clock signal C L K. The frequency of the clock signal C L K is determined by the frequency division ratio selected by the clock frequency division circuit (speed control section) 30. That is, the clock frequency dividing circuit 3 0 is to divide the frequency of the basic clock signal 0 generated by the clock pulse generator (CPG) 31, and according to the operating speed register (the second control register) ) 3 2 値, to control the frequency of the clock signal CLK. In the operating speed register 32, the speed control data (second control data) is externally set via the system interface circuit 3 and an external terminal (not shown). For example, as shown in Figure 2, the frequency divider 3 A performs frequency division on the basic clock signal 0, and generates frequency division signals 0/2, 0/4, and 0/8. The selector 3 0 B selects one of them according to the setting 値 of the operation speed register 32, and outputs the selected frequency division signal as the above-mentioned clock signal CLK. The clock signal C L K is supplied to each data processing unit 2 0-1 to 2 0-η through AND gates 43-1 to 43-η described in detail later. << Standby Control of Each Data Processing Unit >> The above-mentioned standby control circuit 26 determines whether the data processing unit 20 will be determined based on the calculation result of the control signal 25 provided by the command control unit 21 according to the calculation unit 22. -1 _ ~ 2 0-η Individually controlled at this paper size Applies Chinese National Standard (CNS) A4 specifications (210 X 297 mm) -13- 476883 A7 B7 V. Description of the invention (11) Standby status, when set to In the standby state, the corresponding standby control signal 27-i (i = l ~ η) is set to logic 値. The standby control signal 2 7-i is input to the above and the gate 4 3-i and becomes a gate control signal for determining the output of the clock signal C L K. Therefore, when the standby control signal 2 7 — i is set to a logic “$ 0 &quot;, the clock signal CLK is stopped from being supplied to the data processing unit 20 — i corresponding to the standby control signal 2 7 — i, and the processing is suspended. The operation of the data processing unit 20-i is set to a standby state. To release the standby state of the data processing units 20-i set to the standby state, it is performed in accordance with the command control unit 21 to reset the standby control circuit 26 by the control signal 25. When the standby control circuit 26 is reset, the standby control signal 2 7-i is set to logic 値 &gt; 1 ，, and the clock signal C L K is again supplied to the data processing section 2 0-i. For example, the data processing unit 2 0-i starts error correction processing, and investigates whether there is an error. For the data processing unit 2 0-i that processes the data series without error, the standby control circuit 26 can determine its status, and can Migrate to standby by yourself. This can reduce wasteful power consumption. In addition, when all the data processing units 2 0 — 1 to 2 0-η — are in a standby state, the command control unit 21 detects this state, and the command control unit 21 eliminates all the data processing units 20. -1 ~ 2 0 — η standby state, and omission of unnecessary standby cycles improves the efficiency of calculation processing. "Parallel Degree Control of Data Processing Department" Supply the setting of the parallel register to the above and gate 4 2-1 ~ This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (please first Read the notes on the back and fill out this page)-Install! !! | Order |! Line-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 A7 B7_ V. Description of the Invention (12) (Please read the precautions on the back before filling this page) 42-η, so that the above and the gate 42 — 1 to 42-η and AND gate 43-1 to 43-η constitute the parallelism control unit 4 of the data processing unit 20-1 to 20-η. The parallel degree register 41 is used to set the parallel degree control data (the first control data) from the outside via the system interface circuit 3 and an external terminal (not shown). The parallel degree control data has a plurality of bits corresponding to the data processing section 2 0 — 1 to 2 0 — η in a one-to-one manner, and each bit is set to 2 inputs and gates 4 2-1 to 4 2 -One of η inputs. The parallel degree control data instructs operations based on logics 値 1 値. Therefore, the data processing unit 20-i operates with the corresponding bit of the parallelism control data as logic 値 &gt; 1 〃 as a necessary condition. In the data processing section where the corresponding bit of the control data set in the parallel register 4 1 is set to logic 値 a 1 ，, the clock signal CLK is supplied, and the clock signal .CLK is supplied. The frequency is determined based on the control data set in the operating speed register 32. This makes it possible to determine the degree of juxtaposition of the parallel operation in the data processing unit 20-1 to 2 0-η and the frequency of the clock signal C L K from the outside. ‘Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The above-mentioned changes in the degree of parallelism must take into account the calculation processing timing in the error correction circuit 2. The change of the degree of parallelism of the data processing units 20-1 to 20-η is suitable for the case where it is controlled in advance before a series of processing is performed. This is because if the degree of parallelism is changed during the parallel calculation process, it often happens that it is impossible to process the scheduled data that was originally processed. For example, when the calculation data is stored in the buffer memory 2 3 of all data processing departments 20-1 to 2 0-η, it is determined that this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ~ 476883 A7 B7 V. Description of the invention (13) (Please read the precautions on the back before filling in this page) If there are any errors, in the process of implementing the error correction steps, if the parallelism is changed, there will be errors that should be executed. The information in one part of the correction step is excluded from the concerns of the calculation object. The system controller should preferably be set so as not to change the parallel degree on the way because of the progress status of the parallel calculation process. In this way, even if the degree of parallelism is changed, there is no need to change the calculation control program of the data processing unit 20-1 to 2 0-η. On the other hand, the clock frequency can be changed independently of the degree of parallelism even during a series of processing. Controlling both the juxtaposition and operating speed of the data processing unit according to external conditions. As shown in Figure 3, based on the two viewpoints of juxtaposition and operating speed, the data processing device 1 Α can be controlled more accurately from the outside. Data processing capabilities and power consumption. "Monitoring of processing capacity" Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs In the first figure, 50 is a monitoring circuit. The monitoring circuit 50 outputs an external signal (external standby state) to notify the state that the amount of unprocessed data remaining in the data memory 7 exceeds a certain amount based on the access address to the data memory 7. 5 5. As shown in Figure 1, the monitoring circuit 50 has an input data indicator (indicator 値 P i) 5 1. a data indicator in processing (indicator 値 P e) 5 2. an output data indicator (indicator 値 Po) 53, And the comparator 54. The above-mentioned input indicator 5 1 is stored in the above-mentioned input in order through the regional address bus L A B.

The input circuit 5 sequentially stores data in the memory address of the data memory 7. The data indicator 5 2 in process, via the regional address bus LAB This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -16-476883 A7 _______ B7 V. Description of the invention (14), A memory address when the command control unit 21 is sequentially stored in the buffer memory from the data memory according to the load processing described above is sequentially stored. The output data indicator 5 3 sequentially stores the cautious body addresses of the output circuit 5 when sequentially outputting data from the data memory 7 via the regional address bus LAB. The access to the data memory 7 is performed sequentially for successive memory addresses. After accessing the address at the end of data memory 7, it returns to the previous address for access. In other words, the data memory 7 is used as a ring-buffer. The comparator 54 above detects the state where the output data index 値 P0 is about to pass the input data index 値 Pi. In other words, it is checked whether P i = Po + α, and α is a certain constant. When it is checked that Pi = p〇 + a, the external standby signal 5 5 is designated as logic 値 &gt; 1 〃. This state is that the amount of unprocessed data remaining in the data memory 7 with limited memory capacity exceeds a certain amount, and when data is re-entered, according to the nature of the circular buffer, the newly input unprocessed data will be processed The completed data is overwritten. In other words, it means that the data processing capacity of the data processing unit 2 0-1 to 2 0-η is too low. Fig. 4 is a table showing the states of the above indicators separately. When the data memory 7 is used as a circular buffer, the processing speed of the data processing unit 2 0 — 1 to 2 0 — η is appropriate for the input speed of the processing target, as shown in (1) of FIG. 4 , (2), (3), while maintaining Po &lt; Pi, the indicators ， Po, Pe, Pi will change. However, when the data processing capacity is insufficient, it becomes P 〇 = P i as shown in (4), and as shown in (5), P 〇 will follow P i and become the Chinese paper standard (CNS) A4. Specifications (210 X 297 mm) (Please read the notes on the back before filling out this page) ---- Order --------- Line. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-17- 476883 A7 B7 V. Description of the invention (15) P0> Pi. This state means that the processing is completed, and the data that should be read will be destroyed by the imported data. The external standby signal 5 5 is designated as logic 値 &gt; 1 在 immediately before the state of (5) in FIG. 4 is reached. The external standby signal 5 5 is supplied to the system controller. When the system controller detects the assert state of the external standby signal 55, it changes the juxtaposition register 41 according to a certain time, increases the juxtaposition of the data processing section, and improves the error correction circuit Processing power. In addition, the operation speed register 3 2 is immediately changed to accelerate the operation speed of the error correction circuit 2. Alternatively, an external circuit (not shown) that performs an input operation on the input circuit 5 is set to a standby state. This can avoid errors in the entire system. Based on the external status notification function, it is easy to determine the validity of the processing capabilities such as the parallelism set from the outside from the outside of the data storage device 1 Α of the SI M D type. In other words, in addition to the external conditions of the data processing device 1 A, the internal state of the data processing device 1 A is also taken into consideration, and the degree of parallelism of the data processing units 20-1 to 2 0-η and the operation speed are controlled. 'In the structure of FIG. 1, the above-mentioned indicators 51, 52, 53, printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs can be read directly from the outside through the system interface circuit 3. Therefore, the system controller will use the blank periods of the regional buses LD Β, LAB, and LCB to directly refer to the above indicators 値 5 1, 52, 5 3, and the degree of juxtaposition, please first. Read the note on the back Then A! Loading page I w IIIIII order, you can control the increase and decrease of the data processing section 20-1 ~ 2 0 and the level of the clock frequency. For example, when there is a lot of data that has been processed but not yet output, the parallelism can be reduced to reduce power consumption. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -18- 476883 A7 ______ B7 V. Description of the invention (16) So, if it is set to be able to refer to the indicators 51, 52, 5 from the outside 3, it can be different from the external standby signal 5 5 to determine the calculation processing capacity according to the desired viewpoint, and according to this, the degree of juxtaposition or clock frequency can be controlled. In actual error correction, since almost all of the errors occurred are less than the largest error inferred from its error correction code, the error correction processing capacity may not always be the largest. In the data processing device 1 A of FIG. 1, the calculation processing capacity of the error correction circuit 2 is generally reduced, and according to the contents of the indicators 51, 52, 53 or the external standby signal 5 5, when the unprocessed As more data becomes available, processing power is increased. When more data has been processed, the processing capacity can be reduced. Therefore, depending on the content of the data, in other words, the necessary processing power, the average power consumption can be reduced. "Example of Error Correction Processing" An example of error correction processing of the RS code in the above error correction circuit 2 will be described below. The above-mentioned command control unit specifies a R IS (Reduce Instruction Set Computer) command. Each of the data processing units 20-1 to 20-η in the S I M D type error correction circuit 2 has a multiplier and adder of a Galois body in the calculation circuit 22. When correcting errors, first investigate whether there is an error in the syndrome operation. Only when there is an error, perform a series of Euclid mutual division, chain search, and calculation of error numbers. Error correction. Here, if it is time to investigate whether there is an error-_ —— This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) --- Order --- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs • 19 · 476883 A7 _ B7 V. Description of Invention (17) (Please read the precautions on the back before filling this page) Set to τ 1. When the time for performing error correction is set to τ 2, the processing time when there is no error becomes Tn = T1, and the processing time when there is an error becomes Ty = T1 + T2. Therefore, when there is no error, the parallelism degree is reduced like Tn = Ty, or the slow-down speed is reduced, and the processing capacity is reduced. Since power consumption can be reduced by reducing processing power, the fewer errors, the more power consumption can be reduced. Fig. 5 is a representative processing flow of error correction of the RS code in the table. In the same figure, a circled part indicates the processing content, and a rectangled part indicates output data. The error correction processing flow is from data transfer 1 0, symptom calculation 1 002, error judgment 1003, Yakimide cross division method 1004, chain search 1 0 0 5, error number calculation 1 0 0 6, And each process of revision 1 0 7 constitutes. The printed data transferred by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is transmitted in the form of parallel processing suitable for s IMD. In other words, according to the specified parallelism, the processing target data is arranged from the data memory 7 Processing to buffer memory 2 3. Symptom Calculation 1002 takes a series of trusted codes (from r0 to ^ r 255) 2001 as input, and calculates the coefficient of the syndrome polynomial 2002. It can be seen here that when all the coefficients 2002 of the symptom polynomial are zero, it means that there is no error in the trusted coding. When it is known that there is no error, the subsequent processing is omitted, and when it is known that there is an error, the correction processing is started. Initially, the error position polynomial 2 0 3 and the error number 値 polynomial 2004 were calculated from the symptom polynomial 2 0 2 based on the cross division of Yakimite 1 0 4. By calculating the error bit according to the chain search-finding 10 005, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -20- 476883 Α7 Β7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Fifth, the description of the invention (18) By setting the root of the polynomial 2003, the error position 2005 can be obtained. At this time, when the obtained error position 2 0 5 is a 値 that does not actually occur, it is known that an error exceeding the encoding correction capability has occurred. At this time, a message that cannot be corrected is output, and the subsequent processing is omitted. When the position of the error is determined to be appropriate, the number of errors 此 2006 is calculated based on this, and the correction is completed after 1007, and the process ends. For example, the error correction processing for the read data from the recording medium is extremely efficient when processing the data of multiple sectors as a processing unit as a group of code series. Therefore, even the error correction processing of the trusted encoding is preferably to correct the above-mentioned group of encoding series errors for each data processing unit equipped with a Galois body calculator. For example, when all η data processing units 2 0-1 to 2 0-η are used, η trusted coding series can be processed at the same time. By changing the number of data processing sections, the processing capacity can be changed without changing the basic processing flow. Fig. 6 shows the first operation example of the stand-alone standby control of the data processing section during error correction processing. Fig. 6 shows a processing flow when four data processing units 20-1, 20-2, 20-3, and 20-4 are used to simultaneously process four trusted coding series 20001. In Figure 6, GPE0 (20 — 1) to GPE3 (20 — 4) indicate the four data processing units that are juxtaposed, and the vertical direction indicates that over time, each data processing unit 2 0-1 to Processes performed in 2 0 — 4. Figure 6 is a table of 4 input trusted coding series 2 0 0 1, even if 1 error is detected, the data will be processed without errors (please read the precautions on the back before filling this page) Installation · 1 a ·· MM a ·· MM MM MB I MB MB Seeing 0 ♦ This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -21-Employee Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Printed 476883 A7 ______ B7 5. The description of the invention (19) is set to the standby state, and the processing flow before the correction is executed. The first error occurred in the correction code series 2 0 0 1 that was input to the data processing unit GPEO (20-1). The error occurred in the trusted code that was input to the data processing unit GPE, 1 (20-2). The series 200 1 generates an error that is out of the correctable range, and is processed when no errors occur in the trusted coding system 2 0 0 1 that is input to the data processing units GPE2 (20 — 3) and GPE3 (20-4). Data transfer 1001, symptom calculation 2002, and error judgment 1003 will be executed unconditionally in all data processing sections 20 — 1, 20-2, 2 0-3, and 20-4. In this example, the data processing unit GPE0 (20-1) and the data processing unit G P E 1 (2 0-2), which have been known to have errors, perform subsequent error correction processing. On the other hand, the data processing unit GPE2 (20-3) and the data processing unit GPE3 (20-4) did not detect an error, so the data processing unit GPE2 (20-3) and the data processing unit GPE3 (20-4), in During this period, it becomes standby. As a result of Yakimide's cross division method 1 0 0 4 and the calculation of the error number 1 0 6, it has been known that the data processing department GPE 1 (2 0-2) that exceeds the correction capacity of the code has occurred. The calculation of the number of errors is 1 0 0 6 and the period of correction 1 0 7 becomes standby, and the processing of the waiting data processing unit GPE0 (20 — 1) ends. At this time, if all the data processing sections 2 0-1, 2 0-2, 2 0 — 3, 2 (Γ-4 do not detect an error, because the error correction process is not performed, you can move to the next A series of trusted codes at a time. The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). — — — — — — — — · 1111111 ^ · 11111111 (Please read the precautions on the back before filling in this (Page) -22- 476883 A7 ___B7_ V. Processing of the invention (20) 2 0 0 1 Therefore, unnecessary processing steps can be avoided. However, in the 4 data processing sections 20-1, 20-2, 20- 3. (Please read the notes on the back before filling this page) 2 0 — 4 Of the 4 trusted coding series 2 0 0 1 that are processed at the same time, even if there is 1 error, the actual error correction is 1 The three data processing departments other than the data processing department set all the processing after Yakimide's mutual division method 1 04 to the standby state and wait for the error correction processing to end. It cannot be said that it is effectively used and Data Processing Department 20— 1, 20 — 2, 2 0 — 3, 20 4. As the number of data processing departments increases, the probability of failure to detect errors in all data processing departments decreases, resulting in reduced processing efficiency. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to avoid this situation The method shown in the processing flow of Fig. 7 is effective. At this time, the process of reading the 4 trusted coding series 2 0 0 1 into the 4 data processing units 20_1 to 20-4 100 1 is performed, and the symptoms are being performed. Calculate 1 0 0 2 and determine whether there is an error. Before 1 0 0 3, the processing flow is the same as that shown in Figure 6. The data processing unit GPE 0 (2 0-1) and the data processing unit that have been known to have errors will be processed. The symptoms 2002 calculated in GPE1 (20-2) are stored in data memory 7. At this time, the data processing unit GPE2 (20-3) and the data processing unit GPE3 (20-4), which have been known to have no errors, are in standby. , And wait for the processing to end. The processing flow returns to the first data transmission, and reads the next 4 trusted coding series 2 0 0 1 into the 4 data processing sections 2 0-1 ~ 2 0-4 processing 1 0 0 1, moreover, symptom calculation is performed 1 0 0 2 and the judgment of the presence or absence of errors 1 0 0 3, the same applies to only the paper size of the letter of trust that has been detected as an error. The Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied. Printed by the Employee Consumption Cooperative 476883 A7 B7 V. Description of the Invention (21) Coding Series 2 0 1 1 Symptom 2 0 0 2 Processing stored in memory 7 1 0 0 8 After the number of trusted code series 200 which has accumulated to a certain degree is completed, only the error correction process for the trusted code series 2001 in which the error has been detected is written into the stored symptom 2002 1009 'is performed. At this time, when the number of errors exceeds the correction capability of the code, the correction cannot be performed. Therefore, the calculation of the number of errors is not performed 1006, and the system enters a standby state. In the example shown in FIG. 7, the process of temporarily storing the syndrome 2 0 0 1 of which the error has been detected 2 0 0 2 is stored in the memory 7, and the process is read again. 1 0 0 9 becomes necessary compared to the example shown in FIG. 6. In general, when the frequency of the error database is high, the processing flow shown in FIG. 7 is the most efficient, and when the frequency of the error is low, the processing flow shown in FIG. 6 is the most efficient. Based on the relationship between the number of processing steps required to correct the error and the number of processing steps required to temporarily store the symptoms in memory, it can be judged which processing flow is more efficient. In particular, when performing practical error correction, the average frequency of errors will be much lower than the frequency of most errors. When the trusted code is 256 bytes, and errors less than 8 of them are to be corrected, the syndrome must have 16 bytes. The probability of an error. Since the typical example is 1 in 100, there is an error of 4 codes on average. When it is necessary to correct 100 trusted code words = 2,600 bytes, if it is assumed that the correction process needs 10,000 steps to complete-, therefore, if the paper size is based on Figure 6, this paper applies to China National Standard (CNS) A4 Specification (210 X 297 mm) I u I ---- -Equipped ·! !! !! Order! 1! Line (please read the notes on the back before filling this page) 476883 A7 B7 V. Description of the invention (22) (please read the notes on the back before filling this page) The processing flow shown in the figure becomes 10. 〇 × 100 ＋ 4 = 250,000 steps. On the other hand, when error correction is performed according to the processing flow shown in Fig. 7, the total number of steps is 90,640. It can be seen that the processing is completed in less than half of the processing flow shown in FIG. When the incidence of errors is low, or the number of data processing units increases, resulting in an increase in the degree of parallelism, the reduction of the processing steps using the processing flow shown in Figure 7 will become more significant. Symptom calculation is necessary for all input series, and often requires a certain amount of data processing. On the other hand, in the case of subsequent error correction, if the number of errors is small, the amount of processing can be reduced. Therefore, the flow in Fig. 7 can be changed to Fig. 8 to increase the parallelism for symptom calculation and reduce the parallelism for error processing. These processing flows can be determined in consideration of the actual error frequency, the speed of inputting data, and the speed of calculating symptoms. "An example of the data processing department" Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 9 is a detailed example of the data processing department suitable for error correction processing. The data processing unit 20-i shown in the figure is composed of two Galois body multipliers 110, one Galois body adder 11 2, 64-byte Galois buffer 1, 50, 4-byte Galois register 1 6 0, 3 pointers (PS1, PS2, PD) 121, 122, 123, 8-byte integer register 170, 1 integer adder-subtractor 1 8 0, and others A circuit that judges the calculation result and sets the data processing unit to a standby state. -25- This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm) 476883 A7 __m_ V. Description of the invention (23) Galois buffer 150, Galois register 160, 2 Gal (Please (Please read the notes on the back before filling in this page.) The Lova multiplier and 1 Galois adder 11 2 are connected through 6 internal buses. The pairs stored in the Galois buffer 1 50, Galois The data in the register 160 is calculated, and the results are stored again in the Galois buffer 150 and the Galois register 160. An internal bus is provided at the inputs of the calculators 111, 1 and 12 to select the data used in the calculations. The outputs of the calculators 1 1 1 and 1 1 2 are stored in the Galois buffer 150 or the Galois register 160 through the internal bus. The Galois buffer 1 50 will output 2 characters of the address specified by the indicators (PS 1) 121 and (PS2) 122 to the internal bus, and simultaneously write data from the internal bus to Address specified by the pointer (PD) 1 2 3 The 値 of the indicators 1 2 1, 122, and 123 can be increased or decreased (+1 /-1) in the same cycle as the Galois body calculation. The pointer of the indicator is written and read for the integer register 170. The integer register 170 stores the necessary data necessary for the calculation of the control indicator 1 2 1, 122, and the printing of 1 2 3 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, and uses the connected data. The integer adder-subtractor 180 performs calculations. For the 値 of the indicator 1 2 1, 1, 2 2, 1 2 3, and the process of performing Galois body calculations repeatedly, there is a case where the 値 of the indicators 121, 122, and 123 become a certain 値When repeated actions have not stopped. Store a certain amount of plutonium in advance in the register (PEND) 1 3 1 and specify according to the control signal SELPEND that the Chinese paper standard (CNS) A4 specification (210 X 297 mm) should be applied to this paper size. -26- Ministry of Economic Affairs Wisdom Printed by the Consumer Cooperative of the Property Bureau 476883 A7 B7 V. Description of the invention (24) The indicator to be monitored, the comparator (c MP) 1 3 3 is used to determine whether the 指标 of the monitored indicator is set in advance with the temporary setting. Registers (PE ND) 1 3 3 are consistent. When the judgment result is consistent, the PRTEND flag of the flag register 1 4 0 is established according to the signal PRTEND, and furthermore, the standby register 1 41 is set. When the indicators 1 2 1, 1, 2 2, 1 2 3 are not monitored, the control signal SELPEND is used to set the 不 of the indicators 121, 122, 123 and 値 of the register (PEND) 131 not to be compared. . In the flag register 1 40 which is individually set in the data processing section 20 — i, in addition to the above-mentioned RPTEND flag, a GE flag indicating that the result of the Galois body adder 1 2 1 becomes zero is also provided. , The I ZERO flag indicating that the result of the integer calculus 180 is zero, and the INEG flag indicating that it is negative. The content of the flag register 1 4 0, in the comparator 1 4 1 with a mask (mask), the signal CNDXMASK is used as a mask, and compared with the signal NOPCNDX. Standby register 1 4 2. The standby register 1 4 2 can be set from, for example, a 1-bit register according to the calculation results in the data processing unit 2 0 -i by using the above two methods. Externally, it can be directly written and reset according to the signal PENOPIN, or it can be directly read to the external as the signal PENOPEA. When 値 of the standby register 1 4 2 is set, the control signals input to the data processing section 2 0-i, in addition to controlling the access of the slave circuit 1 4 3 to the standby register 1 42, All controls become invalid. From the viewpoint of reducing the consumption of Lili,

• — S This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) IU --------- • Installation -------- Order ------- --Line · (Please read the precautions on the back before filling this page) -27- 476883 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ___B7 _ V. Description of the invention (25) When in standby, it is best to stop Pulse supply. In addition, when the gate (Gate) whose signal can be set to be invalid is inserted into all the control signals, there are many cases where the number of control signals becomes hundreds. Therefore, the scale of the circuit cannot be ignored because Increased number of gates inserted. On the other hand, when the supply of the clock is stopped ', since the gate only needs to be inserted with respect to the clock, it is good from the viewpoint of circuit scale. << D V D Drive System >> Fig. 10 is a block diagram of a DVD drive system including a DVD controller as a more detailed example of the data processing device. The DVD controller 1 B shown in the figure is composed of: a 2 × 2 analog circuit (Data · Strobe) 2 0 0, a demodulation circuit (DVD-Demod) 2 0 1, a modulation circuit (DVD-Mod) 2 0 2, Error Correction Circuit (DVD-ECC) 2 0 3, Memory Interface Circuit (DRAM—CONT) 204, Audio Interface Circuit (Audio Processor) 2 0 5. As a personal computer The host computer's interface is composed of ATAP I interface circuit 206, system interface circuit (MI CON IF) 207, servo circuit (SERVO) 208, and clock oscillator (CPG) 2 09 and other modules, It is formed on a single semiconductor substrate by a well-known semiconductor manufacturing technology. In addition, the DVD controller 1B can reproduce a CD-ROM and a CD-DA for music in addition to a DVD. CD demodulation circuit (CD · —DA) 210, decoder 2 1 _.5, which decodes the read information from CD-ROM, and CD-ROM This paper standard applies Chinese national standard (CNS) A4 size (210 X 297 mm) — -ΑΙ 丨! _ || 丨 | Install i! Order ί 丨! !! (Please read the precautions on the back before filling in this page) -28- 476883 A7 __B7__ V. ROM description decoder (ROMDEC) 2 1 1 〇 The above-mentioned CPG2 0 9 will be decoded according to the invention (26) format. Through a quartz oscillator or an external clock connected to an external terminal indicated by 0, multiplication or division is performed to generate a reference clock, which is supplied to each functional block. D V D controller 1 B operates in synchronization with this reference clock. The error correction circuit 203 has the same configuration as the error correction circuit 2 whose processing capacity can be changed. The memory interface circuit (DRAM-CO NT) 204 mentioned above not only mediates the input and output requirements of the DRAM and other data memory 2 1 2, but also controls the memory bus 2 1 8. The memory interface circuit 2 0 4 and the data memory 2 12 are equivalent to the memory interface circuit 4 and the data memory 7 in FIG. 1. The above-mentioned ATAP I interface circuit 206 is an example of the output circuit 6 in Fig. 1. The above-mentioned system interface circuit 207 is connected to a microcomputer 2 270 as a system controller. Microcomputer 2 2 0, through the internal bus (LAB, LDB, LCB) 221, and initially set the demodulation circuit 2 0 1 or the error correction circuit 2 0 3 and other circuits, and read the error correction circuit 2 3 3, etc. System's internal bus. The system interface circuit 2 7 is equivalent to the system interface circuit 3 in the first figure. 〇 The above 2 circuit 2 0 0, the modulation circuit 2 0 2 and the servo circuit 208 are connected to the pre-processing LS I 224. . Pre-processing LSI 2 2 4 will be from the DVD disc _ from the optical read-write head 225 (Please read the precautions on the back before filling this page) -------- Order ------- --Line ”Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economy The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -29- 476883 A7 ------ B7 V. Description of the invention ( 27) (Please read the precautions on the back before filling in this page) The recorded information read will be enlarged, and the information signal that reproduces the recorded information will be sent to the 2D circuit 2 0 0. In addition, each signal of the focus error and the tracking error is generated based on the envelope and the like of the information signal, and is supplied to the servo circuit 208. The servo circuit 208 controls the tracking and focusing of the optical head 2 2 5 based on the information. In addition, the low-frequency component of the track control is extracted and the D / A conversion output is used to control the thread motor 2 2 7 of the optical pickup 2 2 5. In addition, the rotation speed of the disc is detected based on the pulse detection, and servo processing is performed, and the spindle motor (Spindle motor) 2 2 8 is controlled according to the D / A conversion output. The focusing of the above-mentioned read head and the track search, as well as the driving of the screw-in motor and the spindle motor are performed by driving the IC 2 2 6. The following describes the operation of recording information reproduction in the D V D drive system shown in FIG. 10. The computer 2 2 monitors the command input from the input / output circuit and the key input of the input / output switch. When there is an input, it interprets the content of the input command or key and starts to act accordingly. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Microcomputer 2 2 0, through the micro computer interface 2 7 to initialize the setting register of the servo circuit 2 0 8 and let the focus and tracking servo control act When the focus is locked, the disc is rotated by the spindle motor 2 2 8, and moreover, the optical pickup 2 2 5 is moved to a certain position. At the time of reproduction ', the data read by the optical pickup 2 2 5 is converted into a digital signal in the pre-processing L S I 2 2 4 and input to the above-mentioned D V D controller 1 B. The information entered is first entered into the solution. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -30- 476883 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ______ Β7__ 5. Description of the invention ( 28) The tuning circuit 201, when it is a DVD, sequentially performs demodulation, deinterleaving, synchronization detection, etc. of 8-16 mode. When a certain amount of data is demodulated, the input request is output to the memory interface circuit 204. The memory-battery interface circuit 204 will accept the input request at a certain time, and transfer the demodulated data from the demodulation circuit 201 to the data memory (DR A M) 2 1 2. When a certain amount of data (when it is a DVD, it is 1 sector: 1 8 2 X 2 0 8 bits) is stored in the data memory 2 1 2, it is generated from the memory interface circuit 2 0 4 Interrupt request, and when the error correction circuit 203 recognizes the interrupt request, it starts error correction processing (decoding). When the error correction processing of a certain data is performed, the error correction circuit 203 will set a certain register, etc., and instruct the data output. Based on this, the ATAP I interface circuit 206 will issue an output request to the memory interface circuit 204. Memory interface 2 0 4 will accept the output request at a certain time, and output data from data memory 2 1 2 to the ATAP I interface circuit 2 06, and the ATAP I interface circuit 2 0 6 will send the data Interface circuit output to a host device such as a personal computer. In addition, the error correction circuit 203 sets a certain register of the general-purpose interface circuit (general-purpose I F) 2 3 0 according to the content of the instruction or the key, and instructs data output. When the data from the general-purpose I F 230 is an image data, it is supplied to an MPG circuit (not shown) to decompress the image and display it on a display device such as LCD. This paper size applies to China National Standard (CNS) A4 specification (210 x 297 mm) ------------------- Order -------- · Line ( Please read the precautions on the back before filling out this page) -31-Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 A7 __ B7 V. Description of the invention (29) Instructions at the end of instructions or keys, or at the next instruction or Until the keys are entered, the above actions continue. The following describes the information recording operation in the D V D drive system shown in Figure 10. In the same way as above, the microcomputer 2 2 0 will monitor the instruction input from the input / output circuit or the key input of the input / output, and when there is input, it will interpret the content of the input instruction or key, and according to this Began to move. If the microcomputer 2 2 0, the microcomputer interface circuit 2 0 7 is used to initialize the servo circuit 2 0 8 and the focus and tracking servo control are activated. Furthermore, the optical pickup 2 2 5 is moved to a certain position. position. ΑΑΑΡ I interface circuit 206 outputs data request 'to the host device and inputs data. When a certain amount of data is input, the J ATAPI interface circuit 206 sends an input request to the memory interface circuit 204. The memory interface circuit 2 0 4 accepts input requests at a certain time, and transfers the data input from the ATPO I interface circuit 2 0 6 to the data memory 2 1 2. When a certain amount of data (in the case of a DVD, it is 1 sector) is stored in the data memory 2 1 2, an interrupt request is sent from the memory interface circuit 2 0 4 to the error correction circuit 2 0 3, With this, the error correction circuit 2 03 performs parity processing (encoding) on the data held by the data memory 2 1 2. The error correction circuit 2 0 3, when the parity additional processing is completed for certain data in the data memory 2 1 2, a message that the parity additional processing has been completed is sent to the modulation circuit 2 0 2, and then, the adjustment Transformer circuit 202, this paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) i &quot; ** 丨! _ 丨!丨 I! Order! 1 丨 —line ▲ (Please read the precautions on the back ^ before filling out this page) Printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 476883 A7 B7 V. Description of the invention (30) will be activated The data that has completed the co-location additional processing is transferred to the data transfer control of the modulation circuit 202, and the data is transferred from the data memory 2 12 to the modulation circuit 202 through the memory interface circuit 204. When it is a DVD, the modulation circuit 202 will sequentially perform interleaving, synchronous insertion, 8-16 modulation, etc., and output data. The output data is amplified in the pre-processing LSI 224 and written on the optical disc via the optical read-write head 2 2 5. Figure 11 shows the entire DVD drive system. The optical head 2 2 5 in FIG. 10 is composed of an actuator 2 2 5 B for focusing and tracking, and a head 2 2 5A formed by a laser diode. The motor drive IC 226 in FIG. 10 includes a driver 2 2 6 A of an actuator 225B, a driver 2 2 6 B of a screw-in motor 2 2 8, and a driver 2 2 6 C of a spindle motor 2 2 7. Here, read the channel (

Read channel) to collectively pre-process LS I 224. The read channel includes a preamplifer for reading information. The DVD controller 1B is used for recording and reproduction of information on CD and DVD-like discs 230 and servo control of the above-mentioned discs * 230. That is, the DVD controller 1 B obtains the tracking error signal TE, the focus error signal FE, and the like from the read channel 2 2 4, and if it achieves the tracking and focus of the read head 2 2 5 A, it will Servo control signals SVDA 0 and SVDA 1 are sent to drive 2 2 6 A, servo control signals SVDA 2 are sent to drive 2 2 6 B, and servo control signals SVDA 3 are sent to drive 2 26C. Furthermore, for DVD controller 1B, the paper size from the disc is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -33 · -l, r — — — — — — — — — ^- ------- ^ illln!. (please ^ read the notes on the back and fill in this page again) 476883 A7 _ B7 V. Description of the invention (31) 2 3 〇 is read, and on the read channel 2 2 4 The amplified signal D 1 N is demodulated, and the data to be written to the disc 230 is modulated. The A T A P I interface circuit as the main interface is connected to a host device such as a personal computer via an enhanced I D E bus and the like, and inputs instructions, etc., and performs status indication and data output. The recorded information of the disc 2 3 0 is read by the head 2 2 5A. The read / write head 2 2 5A outputs laser light through a light emitting element (laser diode), and the reflected light from the optical disc 2 3 0 is detected by a light receiving element (light diode). The position of the head 2 3 0 is controlled by the actuator 2 2 5 B and the screw-in motor 2 2 8. The signal output from the head 2 2 5 A is amplified and digitized in the read channel 2 2 4. The microcomputer 2 2 0 uses the S C I and I / 〇 ports to control the read channel. The microcomputer 2 I / 0 port sends control signals of normally open switches and normally closed switches to a tray (not shown) of the disc 2 30, and the eject switch signal is used as The operation requires the interruption of the signal to be input, and the tray (loading) motor is driven according to the output of the PWM timer of the microcomputer 2 2 0. The DVD drive system shown in Fig. 11 can record and reproduce CD-ROM or CD-DA in addition to DVD. The basic playback process is about the same as DVD. That is, like the DVD, the signal __ read by the head 225A from the CD-ROM or CD-DA disc, when reading the channel 2 2 4 This paper standard applies the Chinese National Standard (CNS ) A4 size (210 X 297 mm) (Please read the notes on the back before filling this page) -------- Order ------ 丨! Line * Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -34- 476883 A7 B7 V. After the preamplifier of (32) is amplified, it is shaped into a digital waveform by a waveform shaping circuit. The CD-R OM data is digitally demodulated in the demodulation circuit 2 01 of the DVD controller 1 B, and the error correction is performed by the error correction circuit 2 0 3 in the same way as above, and the data is decoded by decoding. The decoder (descrambler) is decoded. The decoded data is decoded from the CD-ROM format into the data format of the host device in the ROM decoder 2 1 1 and sent to the host device via the main interface circuit 206. The CD-DA data is decoded in the demodulation circuit 210, and after the error correction is stored in the data memory 21, it is output to the host device via the main interface circuit 206. When the microcomputer 2 2 0 loads the disc 2 3 0, it will read the TOC (Table Of Contents) information on the disc and store it in the buffer memory. When it is a CD, the T 0 C information of the lead-in part is up to 100 songs. Since it is 9-byte data, etc., therefore, it is stored in a high-density buffer memory. In addition to improving the use efficiency, since it can be read at any time by the microcomputer 2 2 0, it can calculate the amount of movement during the search, or use it immediately according to instructions from the main interface. In addition, the microcomputer 2 2 can read the ID of data at any time for DVD-ROM discs or prevent copying of data. Furthermore, the microcomputer 2 2 reads the defect information from the DVD-RAM disc and stores it in the buffer memory. The 'microcomputer 2 2 0' converts the logical address indicated by the main interface 2 06 into an entity. Address. Figure 12 is the system operation of the D-VD drive system in Figure 11 of this table. The paper size is applicable to China National Standard (CNS) A4 (210 X 297). (Please read the precautions on the back before filling this page. ) ---- 1 --- Order --------- line * Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employee Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by 476883 A7 B7 V. Invention Description (33 ) Figure. In FIG. 12, the degree of parallelism of the data processing unit 2 0 — 1 to 2 0 — η is set to P, the initial degree of parallelism is set to P i, the operating speed is set to S, and the initial operating speed is set to S. i. After resetting the power to 0 N, open the tray. When it is confirmed that the disc 230 is installed (SI, S2, S3), the initial settings are P = 1 and S = 1, and the disc is pre-scanned. (S4). Based on the information read by the pre-scan, the type of disc and error rate (S5 ~ S8) are investigated. Based on the results, the degree of parallelism Pi is set to 1 to 4 (S9 to S 12). The ability is set according to the condition of the disc. Then enter the instruction (S 1 3). When the input command is> PLAY （(S14), it is set to S = Si and P = P i (S 1 5). When the input command is' JUMP ,, &quot; STOP &quot; (S 1 7, S 1 8), it is set to F = 1, S = 1 and the processing capacity is reduced (S 1 9, S 2 0) . And this is to set the capability according to the instruction. Here, the above-mentioned commands can also be used as vendor unique commands in the specifications of the main interface. Next, the operation in the P L A Y mode (m o d e = 1) will be described. Figure 12 shows that the parallelism of the data processing unit is not changed in the P LAY mode. This is because in the operation, when the degree of parallelism of the data processing department is to be changed, it is necessary to have a structure or control capable of grasping the processing status living in the data processing department. If the structure or control is not adopted, It is not easy to change. Therefore, in the case of the 12th Li I, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied to the paper size of the PLAY template-: ------------- ----- Order --------- line (please read the precautions on the back before filling this page)-36 · 476883 Printed by A7 __B7____, Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 34) The change of movement ability under the formula is limited to the change of movement speed. In the P LAY mode, it usually operates with the capabilities of S = Si and P = Pi according to the settings in step s 1 6. When the error increases and the processing cannot keep up, the error correction circuit 2 0 3 will assert (assert) the external standby signal 5 5 described above. When the microcomputer 2 2 0 detects the wait instruction of the external standby signal, it determines whether S = 4 (S 2 2). If 3 = 4, the micro computer 2 2 0 temporarily issues a demodulation circuit 201 and the like. Instruction to stop the operation (S23). If it is not S = 4, S = S + 1 is set, and the operation speed of the error correction circuit 203 is increased (S24). This is an example of changing the processing capacity by controlling the speed of the error correction circuit 203. In addition, when the consumption current increases and exceeds an arbitrary setting (5 2 5), the microcomputer 220 sets S = 1 as the lower limit and changes the setting to S = S-1 to reduce the operating speed and reduce power consumption (S 2 6, S 2 7). This is an example of changing the processing power by external conditions. When the current consumption does not increase in the determination in step S 2 5 above, the waiting (wah) indication and power consumption (S 2 8) are monitored for a certain period of time. When there is no change, it can also return to S = S i (S 2 9) ° Although it is not shown in Figure 12 above, the system configuration of the host device can also be determined. When the host device is a personal computer, it can be determined as a notebook or desktop type to set the parallel. degree. For example, the degree of juxtaposition in the notebook type will be less than that in the desktop type. In addition, when it is a DVD-RAM or other paper size, the Chinese National Standard (CNS) A4 specification (210 X 297 public love 1 ZOI-2--------) -Order --------- line (please read the notes on the back before filling out this page) 476883 A7 _ ____ B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs You must have error correction (data decoding) and data encoding processing. Data encoding processing content is less than data decoding. Also, the write speed of the disc will be slower than the read speed. Consider this one In some cases, it is also possible to reduce the juxtaposition of the data processing unit in the error correction circuit 203 at the time of writing. "Other forms of data processing device" Although the above-mentioned data processing devices 1 A and 1 B are in SIMD form However, the data processing device may also be in the form of M IMD. Fig. 13 is an example of the data processing device of the M I MD type. The difference from Fig. 1 is the data processing unit 2 0 C — 1 ~ 2 0 C — η is a separate read command, and calculation processing is performed individually. Therefore, each data processing unit 2 0 C-1 to 2 0 C — η has a command control unit and a calculation unit. The data processing unit 2 0 C-1 to 2 0 C-η is a circuit such as a CPU unit, a floating-point arithmetic unit, and a digital signal processing unit. In this MI MD type data processing device, as in the first figure, the operation speed can be controlled based on the external setting of the operation speed register 32, and the operation speed can be controlled according to the parallel operation. The external register of the degree register 41 is used to control the parallel degree of the data processing unit 20 C — 1 to 20 C — η. Figure 14 shows an example of other data processing devices. It is shown in the same figure. The road and the electricity come out of the media, the body D remembers the 5 records, the electricity D enters the 7 records, the memory is recorded by the memory resource department g, and the material D is used as the i for the 1 material, and it is stored as a storage place. Available, 'Road ί ιρτ m: Dispose of materials

D

IX (Please read the notes on the back before filling this page)

DD The size of this paper applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 476883 Α7 ----- Β7 V. Description of the invention (36) (Please read the precautions on the back before filling this page) 2 〇 D-η, a demultiplexer 4 0 that supplies data to the data processing circuit in parallel, and a multiplexer 4 0 that outputs data according to the results of the parallel processing 4 1. a parallel degree register 4 1, And a parallel degree control circuit 400. In the parallel degree register 41, the parallel degree control data is externally set via an external terminal (not shown). The parallel degree control circuit 4 0 0 controls the demultiplexer 4 0 2 according to the parallel degree control data set in the parallel degree register 41 1. The data processing circuit 2 0 D — 1 ~ 2 0 D — η, and multiplexer 4 0 1. The input circuit 5D performs preprocessing such as demodulation on data read from a recording medium such as a DVD as necessary, and transfers the data to the data memory 7D. At this time, because the order in which data is input is not suitable for processing in many cases, after being temporarily stored in the data record 7D, it is converted into a suitable order for processing, and the demultiplexer 4 0 2. It is supplied in parallel to the data processing circuit 2 0 D — 1 ~ printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 0D- η. Although the result of the processing is not necessarily limited to the output, in Fig. 14, the output is used for illustration. Although it is not limited to being completely simultaneous; processing results obtained in parallel are stored in the data memory 7D through the multiplexer 401 above. The output circuit 6 D outputs the processing result stored in the data memory 7 D according to an appropriate sequence and transfer speed. The memory interface circuit 4 D mediates its competition status with respect to the memory access requirements from the input circuit 5 D, the output circuit 6D, and the data processing circuits 20D-1 to 20D-η. As the data processing circuit 2 0 D-～ 2 0 D — parallelization of η &quot; — two paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) -39- 476883 A7 _ B7 V. Invention Note (37) is very effective in improving the overall processing capacity, so it is often used. For a data processing system that wants to use the data processing device 1D, the maximum processing capacity required by the use environment and the like is high. Therefore, when parallel processing is used, the specifications for maximum processing performance can be effectively met. In order to meet the specifications of the maximum processing capacity, n data processing circuits 2 0D— 1 to 2 0D — η are provided in parallel. However, only m need to be used in a normal use state. The parallel degree m (m &lt; η) is set in the parallel degree register 41 and controls the demultiplexer 4 〇 2, the multiplexer 40 1. The data processing circuit 20D— 1 ~ 20D-η, operates according to the parallel degree m . At this time, by controlling the parallelism control circuit 400 to not supply the clock signal to the non-operation processing circuit, the power consumption of the entire data processing circuit can be controlled to m / η, although the overall consumption of other circuits must be added The power is fixed, but in most cases, the data processing circuit accounts for a high proportion of the overall power consumption, so the overall power consumption reduction effect is also large. "Effects of speed control and juxtaposition control" Since the juxtaposition of the data processing section represented by the symbols 2 0-1 to 2 0-η can be controlled from the outside, at least the data can be controlled according to external conditions Processing capacity and power consumption of the processing devices (1 A, 1 B). In addition, since the operating speed can be changed from the outside, the processing capacity and power consumption of the data processing device can also be controlled according to external conditions. In particular, the speed control can be independent of the progress of the data processing step. And it will not affect the processing order at all. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) &lt; Please read the precautions on the back before filling this page) •• Installation ----- --- Order --------- line * Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 A7 B7 V. The invention description (38) is carried out. Therefore, even in the middle of a series of processing, Speed control can also be performed freely. (Please read the precautions on the back before filling out this page.) Therefore, by changing the juxtaposition and operating speed at the same time, you can control the processing power and power consumption more accurately. The data processing status is monitored based on the storage status of the data in the data memory 7, and the status is notified to the outside based on the external standby signal 55, thereby making it easier to control the processing capacity from the outside. Furthermore, if it is set to be able to directly refer to the indicators 5 1 to 5 3 provided for monitoring from the outside, it is possible to make it easier to control the processing capacity from the outside. Although SIMD-type data processing devices are mostly used in image or sound processing to try to improve their data and processing capabilities, there may also be only 1 due to the content of calculation processing or calculation target data. 0% of the original calculation processing capacity. At this time, as described above, if speed control or juxtaposition control can be flexibly performed from the outside, the effects of improving data processing efficiency and reducing wasteful power consumption can be maximized. For example, when the compressed data is to be decompressed, the necessary processing will be changed according to the data. Therefore, if the processing capacity is changed by printing data according to the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, it can reduce Desired power consumption. When used in the error correction circuit 203, error correction processing is performed. If there is no error, it is not necessary to execute. Therefore, if the degree of parallelism is changed according to the processing status, it can be improved. Data processing efficiency and the effect of reducing wasteful power consumption are maximized. In addition, usually when the processing capacity is reduced, according to the content of the index device 5 1 ~ 5 3 or ㈣41-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 476883 A7 One B7 V. Invention Note (39) (Please read the precautions on the back before filling in this page) When the status of the external standby signal 5 5 causes more unprocessed data, the processing capacity can also be improved. In addition, when more data has been processed, the processing capacity can be reduced. This can reduce the average power consumption based on the content of the data, in other words, the necessary processing power. When a disc drive device such as a DVD is used, the power consumption can be reduced by adjusting the processing capacity according to the external conditions or the condition of the disc. For systems such as DVD-RAM, error correction (data decoding) and data encoding must be processed. The processing of data encoding will be less than the decoding of data. In addition, since the writing speed of the disc is slower than the reading speed, the parallelism can be reduced during writing, and power consumption can be reduced. Since the power consumption can be switched according to the system in which the data processing device is used, such as a notebook personal computer / desktop personal computer, it greatly contributes to the development efficiency and productivity of the system. For the error correction circuit that can change the processing capacity, when the encoding / decoding process is used in common, and only the syndrome calculation process must be encoded, the degree of parallelism can be reduced, or the clock frequency division ratio can be increased , According to the required processing power, to reduce power consumption. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Even if the processing speed or parallelism is set to be variable, there is no need to change the basic program, so it will not hinder the efficiency of program development. Since the frequency division ratio of the clock signal is easily changed during operation, it can be optimally controlled at any time. The power consumption can be changed according to a command from a host computer with a built-in main circuit, for example. The above instructions, by using the paper size approved in the main interface circuit, are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -42 · 476883 A7 B7 V. Description of the invention (40) User-defined instructions prepared No new hardware or the like is required on the drive system. Although the above describes the invention proposed by the present inventors specifically based on the embodiments, the present invention is not limited to this. Make various changes. For example, the data processing device may be configured using only one of speed control and parallelism control. The standby control may not be applied to each data processing unit. In addition, the data recorder can also be built into the data processing device. Conversely, the program memory used for the command control unit can be added. The various circuits provided in the data processing device are not limited to those described in the first figure, and may be appropriately changed. In addition, the calculation processing performed by the data processing unit is not limited to error correction, but may be processing such as decompression, compression, modulation, and demodulation. Therefore, the data processing device is not limited to the case where it is applied to the L S I for the disc controller, and can be widely applied to the L S I for communication and the like. The control registers 32 and 41 and the indicators 51, 52, and 53 for changing the processing capability described above in FIG. 1 are provided in the data processing device, but may be disposed in the microcomputer 20. 0 and other system controllers. Industrial Applicability The present invention can be widely used in optical disc drive devices such as DVDs, CD-ROMs, communication interface controllers, and even image_data compression such as digital cameras or digital video cameras. The size of the decompressed letter paper is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling in this page)

--- 1 ---- Order --------- Line I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-43- 476883 A7 __ B7 _ V. Description of the Invention (Processing device No. 4υ, etc. Figure The brief explanation is as follows: ^ / Figure 1 is a block diagram showing an example of the data processing device of the present invention. // Figure 2 is a block diagram showing an example of a clock frequency dividing circuit. ^ Figure 3 is a model An explanatory diagram showing the degree of parallelism and the processing capability corresponding to the setting status of the operating speed. Ν Figure 4 shows the operation of the memory index in the monitoring circuit. Figure 5 shows the RS code error correction processing. The flow chart of the representative processing sequence. Figure 6 is a timing chart of the first operation example of the stand-by standby control of the data processing section in the error correction processing. &Gt; Figure 7 is the error correction processing in the table Timing chart of the second operation example of the independent standby control of the data processing section. \ Figure 8 is a timing chart of the operation example when the parallelism of the data processing section in the error correction process is changed. '—:- ---------------- Order --------- line (Please read the notes on the back before filling in this Page) The Ministry of Economic Affairs, Intellectual Property Bureau, Employees' Cooperatives printed detailed department 311 Department of Materials 311 Department is correcting the error in the appropriate table. (Picture 9)

The details of the first example of the installation are more detailed: m: The material is handled as a plotter with a prepared watch system. Ο Control 1 D V D

The block system of the titan drive D V D insrv drive D V D shows the structure of the whole body 1 Figure 12 1 1 ο Figure Λ, 7 'The process of the system drive D V D The system of the moving picture system is π. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -44- Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 476883 A7 B7 V. Description of the invention ( 42) ^ Fig. 13 is a block diagram of an example of a data processing device of the table MD type. ν / Figure 14 is a block diagram of other data processing devices. Comparison table of main components 1 Α Data processing device 2 Error correction circuit 3 System interface circuit 4 Memory interface circuit 5 Input circuit 6 Output circuit 7 Data memory 20— 1 ～ 20 — η Data processing section 2 1 Command control section 22 Calculation circuit 23 Buffer memory 2 4 Program memory ^ 25 Control signal 26 Standby control circuit 2 7-i Standby control circuit 30 Clock frequency division circuit 3 0 A Frequency divider 3 0 B Selector 31 Clock pulse generator_ This paper Standards apply to China National Standard (CNS) A4 (210 X 297 mm) IL ---------- 0M -------- Order --------- Line_ ( (Please read the precautions on the back before filling this page) -45- 476883 A7 B7 V. Description of the invention (43) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 3 2 Motion speed register 4 2 1 ~ 4 2 — η And 4 3 1 to 4 3 — η and 5 0 monitoring circuit 5 1 input data indicator 5 2 data indicator 5 in process 5 output data indicator 5 4 comparator 5 5 external standby signal 1 1 0 Galiva body multiplication Device 1 1 2 Galois body adder 1 2 1 Indicator 1 2 2 Indicator 1 2 3 Indicator 1 4 2 Standby register 1 4 3 Circuit 1 5 0 Galois buffer 1 6 〇 Galois register 1 7 〇 Integer Register 1 8 〇 Integer adder and subtracter 2 0 0 2 Alternate circuit 2 0 1 Demodulation circuit 2 0 2 Modulation circuit 2 〇 3 Error correction circuit —: ------ 1 ----- ----- Order --------- Line (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -46 -476883 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (44) 204 Memory Interface Circuit 205 Audio Interface Circuit 2 0 6 ATAPI Interface Circuit 207 System Interface Circuit 2 0 8 Servo Circuit. 209 Clock Oscillation 210 Demodulation circuit for CD 2 11 ROM decoder 212 Data memory 220 Microcomputer 221 Internal bus

224 Pre-processing LSI 225 Optical head 2 2 5 A Head 2 2 5 B Actuator

2 2 6 Motor driver IC 2 2 6 A driver 2 2 6 B driver 2 2 6 C driver 227 Screw-in motor 2 2 8 spindle motor 230 universal interface circuit 2 3 0 disc 1D data processing device This paper size is applicable to China Standard (CNS) A4 specification (210 X 297 mm) ------------------- Order --------- line (Please read the note on the back first Please fill in this page again for details) -47- 476883 A7 B7 V. Description of Invention (45) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 D Memory Interface Circuit 5 D Input Circuit 6 D Output Circuit 7 D Data Memory 4 1 Parallel degree register 4 0 0 Parallel degree control circuit 4 0 1 Multiplexer 4 0 2 Demultiplexer (please read the precautions on the back before filling this page) This paper standard applies to China National Standard (CNS) A4 (210 X 297 mm) -48-

Claims (1)

476883 Α8 Β8 C8 D8 VI. Patent application scope: jL · Supplement No. 88 1 1 3540 Chinese Patent Application Amendment (please read the precautions on the back before filling out this page) Amendment in March 1990 1 · A data processing device, comprising: a plurality of data processing units capable of performing parallel operations; a control register holding control data in accordance with an instruction from the outside; and a control data held in the control register, The operation of the data processing unit is stopped, and the juxtaposition control unit that determines the juxtaposition of the parallel operation is formed on one semiconductor wafer. 2 · If the data processing device of the first patent application range, wherein the plurality of data processing units operate in synchronization with a clock signal output from a clock generating circuit, the parallel degree control unit has The signals are respectively supplied to the selection gates of the data processing section, and the selection gates determine whether to output a clock signal based on the control data. Printed by the Ministry of Economic Affairs, Intellectual Property. 4 Printed by the Consumer Cooperative of the 3rd Bureau. For example, the data processing device in the second scope of the patent application. Frequency of. 4 · If the scope of the patent application, the data processing device of item 1 has a command control unit that can interpret the newly acquired command and output control information. The above command control unit can be used in parallel for calculation operations. The control information is supplied to the plurality of data processing sections, and data processing is performed in a SIMD format. This paper size applies to China National Standard (CNS) A4 specification (210x 297 mm) 476883 A8 B8 C8 D8 | Sixth, the scope of patent application 5. If the data processing device of the fourth scope of the patent application, there is more Error Correction Program memory of the error correction program (please read the precautions on the back before filling this page). The above-mentioned command control unit obtains commands from the above-mentioned program memory and uses the above-mentioned data processing unit to perform error correction processing. 6. The data processing device according to item 5 of the scope of patent application, wherein the data processing unit includes a Galois body calculation circuit capable of performing multiplication and addition of the Galois body, and the command control unit controls the Galois body calculation circuit. , And instruct the data processing department to correct the error. 7. If the data processing device of the scope of the patent application is item 4, the above-mentioned command control section can transfer the unprocessed data stored in the data memory to the above data processing section, and the data that has been calculated in the data processing section Transfer to the above data memory; also has a monitoring circuit for monitoring the calculation processing status of the above data processing unit; the above monitoring circuit outputs one that will remain in the above data memory according to the access address to the above data memory The status of the unprocessed data exceeding a certain amount is notified to the external signal. The Ministry of Economic Affairs ’Smart Money is a printed data processing device of the Bureau ’s Consumer Cooperatives, which is characterized by: It contains multiple solid-materials that can be synchronized with clock signals to perform side-by-side operations. According to external sources, Instructions, and the control register holding the control data, and the speed control unit that determines the frequency of the clock signal according to the control data held by the control register, are formed in the 丨 _ $ _ body chip on. 9 · If the data processing device in the scope of patent application No. 8 is used, the paper size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm). 476883 A8 B8 C8 D8 6. The scope of the patent application has a command control section that can interpret the command taken and output control information. The above command control section can supply the control information for calculation operations to the multiple The data processing department uses s IMD to process data. 10. If the data processing device of the 9th patent application scope has a program memory that has stored an error correction program for error correction, the above-mentioned command control unit obtains an order from the above-mentioned program memory and uses the above-mentioned data processing To correct errors. 1 1 · If the data processing device of the scope of patent application No. 10, the data processing unit includes a Galois body calculation circuit that can perform multiplication and addition of the Galois body, and the command control unit controls the Galois body Calculate the circuit and make the data processing department perform error correction processing. 1 2 · If the data processing device in the scope of patent application item 8, the above-mentioned command control section can transfer the unprocessed data stored in the data memory to the above-mentioned data processing section, and the data processing section which has been calculated in the data processing section The data is transferred to the above-mentioned data memory; it also has a monitoring circuit for monitoring the calculation processing status of the above-mentioned data processing unit; and the above-mentioned monitoring circuit outputs a residue on the data memory according to the access address to the data memory. The signal that the unprocessed data in the data memory exceeds a certain amount is notified to the outside. 1 3 · A data processing device, comprising: a plurality of data processing units capable of performing a parallel operation in synchronization with a clock signal; and according to an instruction from the outside, the ^ th paper size that holds the first control data is applicable China National Standard (CNS) Α4 specification (210 × 297 mm) (Please read the precautions on the back before filling in this page} -3- 476883 Α8 Β8 C8 D8: rc, patent control patent 1 control register, 2nd control register that holds 2nd control data according to external instructions, 1st control register The parallel control unit that determines the parallel degree of the parallel operation of the plurality of data processing units held by the first control data held, and determines the clock based on the second control data held by the second control register. The speed control section of the signal frequency is formed on a single semiconductor wafer. 14. If the data processing device of item 13 in the scope of patent application has a command control unit that can interpret the command received and output control information, the above command control unit can be used in parallel for calculation actions The control information is supplied to the above-mentioned multiple data processing sections, and data processing is performed in the form of SIMD. 1 5 · If a data processing device that applies for a patent and the scope of item 14 has a program memory in which an error correction program for error correction has been stored, the control unit obtains a command from the program memory and uses the above The data processing department performs error correction processing. 16 · If the data processing device of item 15 of the scope of patent application, the data processing unit includes a Galois body calculation circuit that can perform multiplication and addition of the Galois body, and the command control unit controls the Galois body Calculate the circuit and make the data processing department perform error correction processing. 1 7 · If you apply for a data processing device with the scope of item 14 in the patent application, the above-mentioned control section can transfer the unprocessed data stored in the data memory to the above-mentioned data processing section, and the calculation will be performed in the data processing section. The completed data is transferred to the above-mentioned data memory; another monitoring paper size for monitoring the calculation processing status of the above-mentioned data processing department is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) '' -4- (please first Read the notes on the back and fill in this page) Order __ Printed by the Employees ’Cooperatives of the 4th Bureau of Wisdom and Finance of the Ministry of Economy 476883 A8 B8 C8 D8 Printed by the Consumers’ Cooperatives of the Intellectual Property Bureau of the Ministry of Economy X 1 _Please see the scope of the patent circuit> The monitoring circuit outputs a signal to notify the external state of the unprocessed data remaining in the above-mentioned data memory based on the access address to the above-mentioned data memory. 1 1 8 Scope of patents item 1-item 3 The data processing device of any one of item 13 further includes an input circuit for inputting data from the outside to store data inputted from the input circuit, and provides the stored data to the data processing unit J, and The data memory stored in the data processing department is again stored in the data memory, and the data stored in the above data memory is output to an external output circuit to be formed on a semiconductor base; the person on the side is 109 The data processing device No. 18 of the scope of patent application, wherein the input circuit further includes demodulation means for demodulating the input signal and data transfer means for transferring the demodulated data to the above data memory. 0 2 0 • If the data processing device of claim 19 of the three main delta patents includes a system interface means, Feeding said transfer resource control means of the feed by the means of the above system and a surface system via the transfer control condition is set by Shu. 2 1 • For example, the data processing device of the third main δ 円 patent scope of item 20, in which the above-mentioned control register y can be accessed directly from the outside through the above-mentioned system interface means j 2 2 • A kind of information The j processing device is characterized in that it includes a majority of data processing units that can perform the same processing in parallel, and determines the degree of parallelism of the majority of the data processing units according to instructions (please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 specification (210X 297 mm) 476883 Α8 Β8 C8 D8 6. Parallel control department for patent application scope. (Please read the precautions on the back before filling out this page) 2 3 · If the data processing device of the 22nd patent application scope has a control register set with control data indicating the above instructions, the above-mentioned parallel degree is determined according to The control data held by the control register is determined. 24. The data processing device according to item 23 of the scope of patent application, wherein most of the data processing units described above operate synchronously with the clock signal output by the clock generating circuit; the parallelism control unit has a function of processing the data separately. The part provides the selection gate of the clock signal; the selection gate is to determine whether to output the clock signal according to the control data. 25. If the data processing device according to item 24 of the scope of patent application, wherein the clock generating circuit is based on another control material of the control register, the frequency of the clock signal is set to be selectable. The Ministry of Economics ’Smart Money is printed by the Bureau ’s Consumer Cooperatives. For example, the data processing device in the 23rd scope of the patent application, which has a command control unit that can interpret the order received and output control information, The command control unit may supply control information for calculation operations to the plurality of data processing units in parallel, and perform data processing in a SIMD format. 2 7 · If the data processing device in the scope of patent application No. 26 has a program memory in which an error correction program for error correction has been stored, the above-mentioned command control section obtains an order from the above-mentioned program memory, and this paper The standard applies to China National Standard (CNS) A4 specification (210 × 297 mm) -6-476883 Printed by Employee Consumer Cooperatives of the 4th Bureau of Wisdom and Finance of the Ministry of Economic Affairs A8 B8 C8 D8 6. Application scope of patent Use the above-mentioned data processing department for error correction processing. 2 8 · If the data processing device according to item 27 of the scope of patent application, the data processing unit includes a Galois body calculation circuit that can perform multiplication and addition of the Galois body, and the command control unit controls the Galois body Calculate the circuit and make the data processing department perform error correction processing. 2 9 · If the data processing device in the scope of application for patent No. 26, the above-mentioned command control section can transfer the unprocessed data stored in the data memory to the above-mentioned data processing section, and the calculation will be completed in the data processing section The data is transferred to the above-mentioned data memory; it also has a monitoring circuit for monitoring the calculation processing status of the above-mentioned data processing unit; and the above-mentioned monitoring circuit outputs one which will remain in the above according to the access address to the above-mentioned data memory. The status of the unprocessed data in the data memory exceeds a certain amount to notify the external signal. 3 0 · A data processing device, comprising: a majority of data processing units that are synchronized with a clock signal and can perform the same processing in parallel; and a speed control unit that determines the frequency of the clock signal according to instructions. 3 1 · If the data processing device in the 30th scope of the patent application, including a control register set with control data indicating the above instructions, the degree of parallelism is determined according to the control data held by the control register. 3 2 · If you apply for the data processing device in item 31 of the scope of patent application, the paper size of this paper applies the Chinese national standard IcNS) A4 specification (21〇 × 297mmΊ) &quot; (Please read the precautions on the back before filling this page ) 476883 8 8 8 8 ABCD 6. In the scope of patent application, there is a command control unit that can interpret the command taken and output control information. The above command control unit can supply control information for calculation operations in parallel. To the above-mentioned multiple data processing sections, the data processing is performed in the form of s 1 MD. 3 3. If the data processing device of the scope of patent application No. 32 'has a stored error correction program, Program memory, the command control unit obtains commands from the program memory, and uses the data processing unit to perform error correction processing. 3 4. The data processing device such as the item 33 of the scope of patent application, wherein the data processing unit Contains Galois body calculation circuit that can perform multiplication and addition of Galois body, and the above command control unit controls the Galois body calculation And the data processing department to make error correction processing. 3 5. If the data processing device of the 31st scope of the patent application, the above command control unit can transfer the unprocessed data stored in the data memory to the above data processing And transfers the data that has been calculated in the data processing section to the data memory; it also has a monitoring circuit for monitoring the calculation processing status of the data processing section; the monitoring circuit is based on the data memory Accessing the address, and outputting a signal that notifies the external state of the unprocessed data in the data memory exceeding a certain amount to an external signal. 3 6. A kind of data processing device, characterized by: including: synchronizing with the time Pulse signal, most data processing departments that can perform the same processing in parallel, and determine the majority of the above data according to the first instruction. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm). Please read the notes on the back first. (Fill in this page again), 1T Printed by Employee Consumer Cooperatives, 1st Bureau of Smart Finance, Ministry of Economic Affairs-8- 476883 A8 B8 C8 D8 6. Scope of patent application Juxtaposition control unit for juxtaposition of parallel operation of the processing department and speed control unit that determines the frequency of the above-mentioned clock signal according to the second instruction. 37. The data processing device according to item 36 of the scope of the patent application, which includes a first control register set with the first control data indicating the first instruction, and a second control set with the second instruction. The second control register of data; the parallel degree is determined according to the second control data held by the first control register, and the frequency is determined according to the second control data held by the second control register. 3 8 · If the data processing device in the scope of patent application No. 37, there is a command control unit that can interpret the fetched command and output control information. The above command control unit can be used in parallel for calculation operations The control information is supplied to the above-mentioned multiple data processing sections, and data processing is performed in the form of SIMD. 39. If the data processing device of the 38th scope of the patent application has a program memory in which an error correction program for error correction has been stored, the command control unit obtains a command from the program memory and uses the above The data processing department performs error correction processing. 4 〇 · If the data processing device of the 39th scope of the patent application, the data processing unit includes a Galois body calculation circuit that can perform multiplication and addition of the Galois body, and the command control unit controls the Galois The system calculates the circuit, and causes the data processing department to perform error correction processing. 4 • If the data processing device of the 38th scope of the patent application, the above-mentioned command control unit can store the unprocessed data stored in the data memory. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ( Please read the notes on the back before filling in this page.) Order tfi. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-9- 476883 A8 B8 C8 D8 6. The scope of patent application will be transferred to the above data processing department and will be processed in the data processing The calculated data in the ministry is transferred to the above-mentioned data memory; it also has a monitoring circuit for monitoring the calculation processing status of the above-mentioned data processing unit; and the above-mentioned monitoring circuit is output according to the access address to the above-mentioned data memory. A signal to notify an external state that the amount of unprocessed data remaining in the data memory exceeds a certain amount. 4 2 · The data processing device according to any one of the items 23, 31, or 37 in the scope of patent application, which further includes an input circuit for inputting data from the outside, and stores the input from the above input circuit. Data, and the stored data is provided to the above-mentioned data processing section, and the data calculated in the data processing section is stored again as a data memory, and the data stored in the above-mentioned data memory is output to an external The output circuit is formed on a single semiconductor substrate. 4 3 · The data processing device according to item 42 of the scope of patent application, wherein the input circuit further includes demodulation means for demodulating the input signal, and data for transferring the demodulated data to the above-mentioned data memory. Means of transfer. 4 4 · If the data processing device in item 43 of the scope of patent application includes a system interface means, and the above-mentioned data transfer control means, the transfer control conditions are set via the above-mentioned system interface means. 4 5 · If the data processing device according to item 44 of the scope of patent application, the above-mentioned control register can be accessed directly from the outside through the above-mentioned system interface means. This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling out this page) Order Wisdom Finance Department of the Ministry of Economic Affairs is printed by the staff consumer cooperatives -10-