JP5735610B2 - Encoding device and decoding device - Google Patents

Description

  The present invention relates to an error correction coding apparatus and decoding apparatus, and in particular, receives data or communication packet data as a transmission source from the outside of the apparatus, and provides redundant data (repair data) or restored data to the outside of the apparatus. It relates to a device for giving.

  At present, error correction technology is widely used in various communication systems such as sanitary digital broadcasting, communication on the Internet, and communication on mobile terminals. In particular, with the development of broadband environments in recent years, video distribution services using the Internet are expected, and error correction technology for the Internet network has become important. The following is an example of the Internet network.

  When the communication path is viewed from the service provider side using the Internet, the Internet network can be regarded as an erasure communication path (PEC: Packet Erasure Channel). This is a case where binary erasure channels are grouped as packet units, and the channel output is either output with correct information or output as unknown due to some failure in the line. It is a communication channel. In general IP-based services, the TCP / IP protocol is used, and the decoder side only uses error detection, and when an error occurs, a method of correcting the error by retransmission control or the like is used (ARQ (Automatic Repeat request method). However, when a large-scale service such as multicast distribution is assumed, it is required to correct errors based on data received on the receiving side, and a method that can correct errors only on the receiving side without requiring a feedback channel Is used (FEC (Forward Error Correction) method). Since this FEC method does not perform retransmission control or the like, the FEC method is also used in a video conference system in which real-time performance is important with little delay. The following will discuss the FEC method.

  As the FEC method, Reed-Solomon code (RS code) is widely used in digital broadcasting and the like. In Japanese digital broadcasting, it is defined as a code length of 204 bytes, and by adding approximately 10% redundant data to the original data of 188 bytes, tolerance is given to errors. However, it is generally known that performance is improved if a code having a long code length is used as an error correction code. However, there is a known disadvantage that decoding becomes complicated and the amount of calculation becomes enormous as the code length increases. ing. Therefore, in the RS code, it is common to handle the code length as 256 bytes or less. In addition, when the RS code is applied to a packet called IP-based packet level FEC, the size of one code block is limited to 256 packets for the above reason.

  In contrast, a decoding method based on a belief propagation algorithm is known to have excellent decoding characteristics with a practical amount of computation when the code length is long, and is defined by a sparse graph A low density parity check code (LDPC code (for example, see Non-Patent Document 1)), which is a linear code, has been attracting attention as a practical error correction method that approaches the channel capacity defined by Shannon. Yes. Further, as an erasure correction code based on a sparse graph, Digital Fountain's LT code (for example, see Non-Patent Document 2) and Raptor code (for example, Non-Patent Document 3) are known, and the coding efficiency is known. It is known to achieve a code characteristic that can be decoded only by receiving arbitrary code data without greatly degrading the code with a practical amount of computation.

  In general, these error correction technologies are incorporated into a device that transmits and receives video information to and from a communication path when connected to an external video device, and also incorporated into a video transmission / reception program and an information transmission program that operate on a computer. . Often, the error correction processing unit is implemented as an external library of the program. In this case, the program and the library exchange original data and redundant data via an API (Application Programming Interface). As such a library, for example, there is OpenFEC (for example, see Non-Patent Document 4).

R. G. Gallager, “Low density parity check codes”, in Research Monograph series. Cambridge, MIT Press, 1963. M.M. Luby, “LT Codes”, The 43rd Annual IEEE Symposium on Foundations of Computer Science, 2002. Shorollahi, A, “Raptor codes”, Information Theory, IEEE Transactions on Volume 52, Issue 6, 2006 http: // openfec. org

  As described above, since the error correction processing unit generally operates separately from the video processing unit and the communication unit, it is necessary to exchange original data and redundant data with them. At this time, if the error correction processing unit and other processing units are operating on physically different devices, it is necessary to transfer data between the error correction processing unit and the other processing units. When operating as a program on a computer, the error correction processing unit and other processing units share a common memory area so that the error correction processing unit can directly perform processing without transferring data. is there. However, if the data format, operation unit, and memory access unit do not match between the error correction processing unit and the other processing units, the shared data cannot be processed as it is.

  For example, in Non-Patent Document 4, the error correction processing unit, that is, the library, and the other processing unit, that is, the library calling side share the address on the memory in which the processing target data is stored, so that data to the library is stored. The library can directly perform processing without performing transfer, that is, memory copy. However, for example, when the library operation unit is a 64-bit unit and the library calling side performs data arrangement on a 32-bit boundary, the library cannot directly process the data on the shared memory.

  The present invention has been made in view of the above points, and provides a function of sharing a memory area that can be accessed in accordance with the operation unit of the error correction processing unit with other processing units, without performing a memory copy. The object is to realize high-speed error correction processing.

  In order to achieve the above object, an encoding apparatus and decoding apparatus, an encoding method, and a decoding method of the present invention include a memory address table for a packet buffer, an error correction encoding / decoding processing unit, By sharing the processing unit, the error correction encoding / decoding processing unit can process the data written by the other processing unit as it is.

Specifically, the encoding device of the present invention is:
A payload memory address table for encoding that manages the memory address of the payload data of each packet included in one code block in the packet transmission buffer memory in which the transmission data is stored. An encoding memory address table generation unit for generating an integer multiple;
An encoding operation unit that reads the payload data of each packet from the packet transmission buffer memory with reference to an address stored in the encoding payload memory address table, and encodes the read payload data;
Is provided.

In the encoding device of the present invention,
A transmission memory address table generation unit for creating a transmission packet memory address table for managing the memory address of the header of each packet in the packet transmission buffer memory based on the information of each packet;
A packet transmission unit that reads and transmits the header and payload data of each packet from the packet transmission buffer memory with reference to addresses stored in the packet memory address table for transmission;
May be further provided.

Specifically, the decoding device of the present invention is:
Decoding memory that generates a payload memory address table for decoding that manages the memory address of the payload data in the packet reception buffer memory in which the received data is stored so that the leading address of the payload data is an integral multiple of the decoding operation unit An address table generation unit;
A decoding operation unit that reads the payload data of each packet from the packet reception buffer memory with reference to the address stored in the decoding payload memory address table, and decodes the read payload data;
Is provided.

In the decoding device of the present invention,
A reception availability table creating unit that creates a reception availability table that manages whether or not each packet is received in the order of reception of each packet;
The decoding memory address table generation unit associates the address of the header of each packet in the packet reception buffer memory with the transmission order based on the information of each packet,
The decoding operation unit may restore lost packets based on whether or not each packet in the reception availability table has been received.

Specifically, the encoding method of the present invention is:
A payload memory address table for encoding that manages the memory address of the payload data of each packet included in one code block in the packet transmission buffer memory in which the transmission data is stored. A procedure for generating a memory address table on the transmission side that is generated to be an integer multiple,
An encoding operation procedure for reading the payload data of each packet from the packet transmission buffer memory with reference to the address stored in the encoding payload memory address table, and encoding the read payload data;
In order.

In the encoding method of the present invention,
In the transmission-side memory address table generation procedure, further, a transmission packet memory address table for managing the memory address of the header of each packet in the packet transmission buffer memory based on the information of each packet is created,
A packet transmission procedure for reading and transmitting the header and payload data of each packet from the packet transmission buffer memory with reference to an address stored in the transmission packet memory address table is further provided after the encoding operation procedure. Also good.

Specifically, the decoding method of the present invention is:
Receiver memory that generates a payload memory address table for decoding that manages the memory address of the payload data in the packet reception buffer memory in which the received data is stored so that the start address of the payload data is an integral multiple of the decoding operation unit Address table generation procedure,
A decoding calculation procedure for reading payload data of each packet from the packet reception buffer memory with reference to an address stored in the decoding payload memory address table, and decoding the read payload data;
In order.

In the decoding method of the present invention,
In the reception-side memory address table generation procedure, a reception availability table for managing the presence / absence of each packet in the order of reception of each packet is created, and the data of each packet included in one code block is stored in the order of reception Associating the header address of each packet in the packet reception buffer memory with the transmission order based on the information of each packet,
In the decoding operation procedure, lost packets may be restored based on whether or not each packet in the reception availability table is received.

  According to the present invention, the function of sharing the memory area that can be accessed in accordance with the operation unit of the error correction processing unit with other processing units is provided, and high-speed error correction processing is realized without performing memory copy. can do.

An example of the encoding apparatus which concerns on Embodiment 1 is shown. An example of the decoding apparatus which concerns on Embodiment 3 is shown. An example of the decoding apparatus which concerns on Embodiment 4 is shown. 10 illustrates an example of a decoding device according to a fifth embodiment. A first example of the relationship between the data arrangement on the memory for one code block and the payload memory address table is shown. A second example of the relationship between the data arrangement on the memory for one code block and the payload memory address table is shown. An outline of operations between payloads in an error correction encoding / decoding operation is shown. The structural example of 1 code block in embodiment of this invention is shown.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to embodiment shown below. These embodiments are merely examples, and the present invention can be implemented in various modifications and improvements based on the knowledge of those skilled in the art. In the present specification and drawings, the same reference numerals denote the same components.

  The data to be transmitted is referred to as source data, the redundant data used for error correction is referred to as repair data, and the payload in packet transmission (actual data portion excluding the header portion in one packet) is part of the source data, the source payload, A thing that is a part of repair data is called a repair payload. The encoding process is performed for each code block, and each code block includes a plurality of source payloads and a plurality of repair payloads. The repair payload is generated by a coding operation from a plurality of source payloads in the code block using a generator matrix in LDPC or a generator polynomial in RS code. FIG. 8 shows the configuration of one code block in the present invention.

  The present invention relates to memory area sharing between an error correction encoding / decoding processing unit (error correction library) and another processing unit (software using an error correction library). In particular, the present invention provides an error correction encoding / decoding processing unit and other processing units for a packet buffer memory address table arranged so that the beginning of a packet payload is an integer multiple of an error correction unit. By sharing the data, the error correction encoding / decoding processing unit can process the data written by the other processing unit as it is.

(Embodiment 1)
FIG. 1 is an overall configuration diagram of an encoding apparatus showing an example of the configuration of the present invention. The encoding device according to the present embodiment functions as an error correction encoding device and includes an error correction encoding processing unit 12. The error correction coding processing unit 12 can be read as an error correction library. The error correction coding apparatus includes a packet transmission processing unit 11. The packet transmission processing unit 11 is arranged outside the error correction coding processing unit 12.

  The packet transmission processing unit 11 includes a packet transmission buffer memory securing request unit 101, a source data reading unit 104, a payload data writing unit 105, an encoding process start request unit 106, and a packet transmission unit 109. The error correction encoding processing unit 12 includes a packet transmission buffer memory securing unit 102, a packet / payload memory address table generation unit 103 that functions as an encoding memory address table generation unit and a transmission memory address table generation unit, and an encoding Payload memory address table input unit 107, encoding operation unit 108, and packet transmission buffer memory 132.

The encoding device according to the present embodiment executes the encoding method according to the present embodiment. The encoding method according to the present embodiment includes a transmission side memory address table generation procedure and an encoding calculation procedure in order.
For the sending memory address table generation procedure, generating encoded payload memory address table T _C which manages the memory address of the payload data of each packet included in one code block in the packet transmitting buffer memory 132 which transmit data is stored To do.
The coding algorithm, by referring to the address stored in the encoded payload memory address table T _C from the packet transmission buffer memory 132 reads out the payload data of each packet, carries out a coding of the read payload data.

In the transmission side memory address table generation procedure may further create a transmission packet memory address table T _S which manages the memory address of the header of each packet in the packet transmitting buffer memory 132 based on the information of each packet. In this case, the packet transmission unit 109 transmits with reference to the address stored in the transmission packet memory address table T _S from the packet transmission buffer memory 132 reads the header and payload data of each packet.

  Step S101: The packet transmission buffer memory securing request unit 101 makes a packet transmission buffer memory securing request to the error correction coding processing unit 12. At this time, the packet transmission buffer memory securing request unit 101 designates information regarding each packet. The information regarding each packet is, for example, the header length, the source payload length, the repair payload length, the number of source payloads in the code block, and the number of repair payloads. Information about each packet includes information for encoding such as a repair payload generation matrix and a generation polynomial. As a result, the packet / payload memory address table generating unit 103 secures a packet transmission buffer memory 132 having a size equal to or larger than one code block.

  Step S102: The packet transmission buffer memory securing unit 102 has a sufficiently large packet transmission buffer memory that can store packet (header + payload) data for one code block in a memory space that can be referred to by the packet transmission processing unit 11. 132 is secured.

Step S103: Packet payload memory address table generating unit 103, the start address of each payload storage area generates a payload memory address table T _C for encoding to be placed on the boundary of the error correction operation unit. Thus, the start address of the payload data is to be an integral multiple of arithmetic encoding unit, generating a payload memory address table T _C for coding. A specific generation method will be described later in a seventh embodiment. Note that memory reservation and address table generation need only be performed once at the start of transmission as long as the code block length (the sum of the number of source payloads and the number of repair payloads), header length, payload length, and the like do not change.

Transmission packet memory address table T _S from the address value of each payload in encoded payload memory address table T _C, is generated by subtracting the address value of the packet header size of. Packet payload memory address table generation unit 103 generates by subtracting the header size from the numerical address of the transmission packet memory address table T _S a collection of head addresses of respective headers. For example, the address value of the payload # 1 to # 4 if 0x0030,0x0620,0x0C10,0x1200, _{T S} stores 0x0008,0x05F8,0x0BE8,0x11D8 as the address of the payload # 1 to # 4.

  Step S <b> 104: The source data reading unit 104 reads the source data to be subjected to packet transmission from the storage or network and passes it to the payload data writing unit 105.

Step S105: payload data writing unit 105 refers to the payload memory address table T _C for coding, by dividing the source data to the source payload writes sequentially in the packet transmitting buffer memory 132. In the example of FIG. 1, source data corresponding to the source payload length is written to address addresses 0x0030, 0x0620, 0x0C10, and 0x1200, respectively. Square in T _C of "0x0030" and the like in FIG. 1 is an example of numerical values of the addresses each payload is placed in a square one cell, the table is composed of a plurality of cells. After the writing of the source payload for one code block is completed, step S106 is executed.

Step S106: The encoding process start request unit 106 makes a start request for the encoding process.
Step S107: encoding process start request unit 106 inputs the payload memory address table T _C for encoding in the encoding payload memory address table input unit 107. Coded payload memory address table input unit 107 is input to the payload memory address table T _C for encoding required for encoding the packet transmission unit 109, and outputs to the encoding operation unit 108.

Step S108: encoding operation unit 108 accesses the source payload to be calculated with reference to the payload memory address table T _C for encoding operation specified by such a generator polynomial in the generator matrix or RS code in LDPC To generate a repair payload. Coding operation unit 108 refers to the payload memory address table T _C for encoding, for example, the first and fourth and seventh source payload in the XOR operation to the processing for generating the first repair payload Read out the operation target and write the operation result.

For example payload # 5 are generated by the operation of the payload # 1 and the payload # 3, but the information that is specified by such a generator matrix and generator polynomial, by reference to the information and encoded payload memory address table T _C The location where memory access is actually performed is determined. In FIG. 1, the areas of payload # 5 and payload # 6, which are repair payloads generated, are the same areas as payload # 5 and payload # 6 in the packet transmission buffer memory 132 at the top of the figure. However, the repair payload generation destination area may be secured in an area other than the packet transmission buffer memory 132. However area of each repair payload needs to be written in the payload memory address table T _C for coding.

Step S109: Finally, the packet transmission unit 109, with reference to the transmission packet memory address table T _S, will send one by one packet. At this time, the packet transmission unit 109, will refer to the transmission packet memory address table T _S from the head, packet transmits the data of the address to the network.

Note that the header area of each packet is not necessarily reserved on the packet transmission buffer memory 132. In that case, the transmission packet memory address table T _S payload memory address table T _C for coding becomes the same content, the packet transmission unit 109 combines the data of the data and payload of the header area secured separately, packet Send it. The header information may be generated at any stage before packet transmission. If it has not been generated before reaching the packet transmission unit 109, the packet transmission unit 109 performs generation.

  In addition to the packet / payload memory address table generation unit 103 in FIG. 1, the packet transmission buffer memory reservation unit 102 in FIG. 1, the payload memory address table input unit 107 for encoding, and the encoding operation unit 108, the software creates a table. For example, instead of a system in which the software operates, an interface for receiving a memory allocation request from software using a library and returning the memory allocation to the software may be further provided.

  The error correction coding apparatus according to the present embodiment may be realized using software that causes a computer to operate as each functional unit. For example, a packet / payload memory address table generating unit 103 and a packet transmission buffer memory securing unit 102, and a packet buffer address table for each packet arranged so that the beginning of the packet payload is an integer multiple of the error correction operation unit The error correction encoding apparatus may be realized by causing the computer to execute software that generates the error and transmits the address to the error correction encoding library, that is, the error correction encoding processing unit 12. The same applies to the following embodiments.

(Embodiment 2)
In the present embodiment, the packet transmission processing unit 11 itself, creates a packet transmission buffer memory 132, the coding payloads memory address table T _C, the transmission packet memory address table T _S. In this case, as the head address of each payload are aligned by the arithmetic unit in the encoding operation unit 108, the payload data write unit 105 generates a payload memory address table T _C for coding. Specific generation method of encoding payload memory address table T _C according to the present embodiment will be described in Embodiment 7 described below.

  In the present embodiment, steps S101 and S102 in the first embodiment are omitted, and processing equivalent to steps S102 and S103 is performed in the packet transmission processing unit 11. The subsequent steps are the same as those in the first embodiment.

  By adopting the configuration of this embodiment, the packet transmission buffer memory securing request unit 101, the packet transmission buffer memory securing unit 102, and the packet / payload memory address table generating unit 103 can be omitted.

(Embodiment 3)
FIG. 2 is an overall configuration diagram of the decoding apparatus according to the present embodiment. The decoding device according to the present embodiment functions as an error correction decoding device and includes an error correction decoding processing unit 22. The error correction decoding apparatus according to the present embodiment includes a packet reception processing unit 21. The packet reception processing unit 21 is disposed outside the error correction decoding processing unit 22.

  The packet reception processing unit 21 includes a packet reception buffer memory securing request unit 201, a packet reception unit 204, a payload data writing unit 205, and a reception availability table / decoding table memory address table update unit that functions as a reception availability table creation unit. 206, a decryption processing start request unit 207, and a source data output unit 210. The error correction decoding processing unit 22 includes a packet reception buffer memory securing unit 202, a packet / payload memory address table generation unit 203 functioning as a decoding memory address table generation unit, a decoding payload memory address table input unit 208, and a decoding A calculation unit 209 and a packet reception buffer memory 232 are provided.

The decoding device according to the present embodiment executes the decoding method according to the present embodiment. The decoding method according to the present embodiment includes a reception-side memory address table generation procedure and a decoding calculation procedure in order.
The receiving memory address table generation procedure to generate a decoded payload memory address table T _D for managing the memory address of the payload data in the packet receiving buffer memory 232 which received data are stored.
The decoding algorithm reads the payload data of each packet from the packet reception buffer memory 232 with reference to the address stored in the decoded payload memory address table T _D, decodes the read payload data.

The receiving memory address table generation procedure stores the presence or absence of the reception of each packet, to create a receivability table T _A1 for managing the transmission order of each packet, the data of each packet included in one code block in the order received The header address of each packet in the packet reception buffer memory 232 may be associated with the transmission order based on the information of each packet. In this case, in the decoding calculation procedure, the decoding calculation unit 209 restores the lost packet based on whether or not each packet is received in the reception availability table T _A1 .

  Step S201: The packet reception buffer memory securing request unit 201 makes a request for securing the packet reception buffer memory to the error correction decoding processing unit 22. At this time, the packet reception buffer memory securing request unit 201 designates information regarding each packet. The information regarding each packet is, for example, the header length, the source payload length, the repair payload length, the number of source payloads in the code block, and the number of repair payloads. The information regarding each packet includes information regarding codes such as an error check matrix and a generator polynomial of the repair payload. As a result, the packet / payload memory address table generating unit 203 secures the packet reception buffer memory 232 having an area larger than one code block.

  Step S202: The packet reception buffer memory securing unit 202 has a sufficiently large packet reception buffer memory that can store packet (header + payload) data for one code block in a memory space that can be referred to by the packet reception processing unit 21. 232 is secured.

Step S203: Packet payload memory address table generating unit 203, the start address of each payload storage area, to generate a decoded payload memory address table T _D to be placed on the boundary of the error correction operation unit. Thus, as the start address of the payload data is an integral multiple of the operational units of the decoding to generate a decoded payload memory address table T _D. A specific generation method will be described later in a seventh embodiment. Note that memory reservation and address table generation need only be performed once at the start of transmission as long as the code block length (the sum of the number of source payloads and the number of repair payloads), header length, payload length, and the like do not change.

Receiving packet memory address table T _R from the address value of each payload in decoding the payload memory address table T _D, it is generated by subtracting the address value of the packet header size of. Packet payload memory address table generating unit 203 generates and adds the header size from the numerical address of the received packet memory address table T _R a collection of head addresses of respective headers. For example, the address value of _{T D} of the payload # 1 to # 4 if 0x0030,0x0620,0x0C10,0x1200, _{T R} stores 0x0008,0x05F8,0x0BE8,0x11D8 as the address of the payload # 1 to # 4.

  Step S204: The packet receiving unit 204 receives a packet from the packet transmission processing unit 11 via the network.

Step S205: The packet receiving unit 204 passes the data to the payload data writing unit 205. Payload data writing unit 205 refers to the reception packet memory address table T _R, and writes the received packets into the sequential packet reception buffer memory 232 in the order received. Here, the area for storing the header of each packet is not necessarily in the packet reception buffer memory 232. In this case, the header is removed by the packet reception unit 204 and only the payload is written. After receiving the packet, step S206 is executed.

Step S206: receiving availability table decoding payload memory address table updating unit 206 corresponds to the payload number of the received packet, to the cells of the decoded payload memory address table T _D, to record the address at which the payload is stored Update process is performed. Similarly, the reception is recorded in the corresponding cell of the reception availability table T _A1 . Steps S204 to S206 are repeated until the packet reception process for one code block is completed.

After reception of one code block has been completed, in step S206, the cell of decoding the payload memory address table T _D corresponding to the not received number, recording data storage destination address for the payload decoding, the corresponding The erasure is recorded in the cell of the reception availability table T _A1 .

Step S207: The decryption process start request unit 207 makes a decryption process start request. In this case, the decoding processing start request unit 207, these two tables _{T D} and _{T A1,} and inputs to the decoding payload memory address table input unit 208.

Step S208: decoding arithmetic unit 209 accesses the payload to be calculated with reference to the decoded payload memory address table T _D, performs a computation designated by like generator polynomial in the error check matrix or the RS code in LDPC , Recover lost payload.

For example, the information that the payload # 3 is restored by the operation of the payload # 1 and the payload # 5 is specified by an error check matrix, a generator polynomial, etc., but it is actually calculated by referring to the information and the payload memory address table. Therefore, the location for memory access is determined. In FIG. 2, the area of the payload # 3 that is the restored payload is the same area as the payload # 3 in the packet reception buffer memory 232. However, the restoration destination area of the payload may be secured in an area other than the packet reception buffer memory 232. However the area of the restored payload needs to be written to the decoding payload memory address table T _D.

Error correction decoding apparatus according to this embodiment, since the error correction decoding processing unit 22 different from the packet reception processing section 21 manages the decryption payload memory address table T _D, it is possible to reduce the load of the packet reception processing section 21 . The soft side to utilize the error correction library manages the decryption payload memory address table T _D, separately soft side, access to a specific payload temporarily transferred to another area of the payload data on account of the soft side However, the address table can be updated accordingly.

(Embodiment 4)
FIG. 3 is an overall configuration diagram of the error correction decoding apparatus according to the present embodiment. The error correction decoding apparatus according to the present embodiment includes a reception availability table update unit 226 instead of the reception availability table / decoding table memory address table update unit 206 in the second embodiment, and the decoding payload memory address table input unit 208 includes Instead, a decoding payload memory address table update / input unit 228 is provided.

In the case of the third embodiment, since the cell number and payload number in the reception availability table T _A1 correspond to each other, TA1 [2] = 1 and TA1 [3] = 0 assuming that 1 indicates reception and 0 indicates erasure. , Payload # 2 is received, Payload # 3 is lost, and the reception availability table is updated. At this time, the suffix of T _A1 in Embodiment 3 indicates the payload number.

In the present embodiment, the reception availability table T _A3 has a format in which the packet reception order can be associated with the received payload number. For example, TA1 [1] = 1, TA1 [2] = 4, TA1 [3] = 5, etc., and the received payload number is input to each cell, and TA1 is updated. Here, the subscript of T _A1 in Embodiment 4 indicates the order of reception. After the packet reception processing section 21 is a packet received, the receiving availability table updating unit 226 updates only the receivability table T _A3, decoding the payload memory address table T _D is not updated.

The decryption processing start request unit 207 inputs the reception availability table T _A3 to the decryption payload memory address table update / input unit 228. Then, the decoding payload memory address table update and input unit 228, and updates the decryption payload memory address table T _D based on the received permission table T _A2.

In the present embodiment, the decoding operation unit 209 updates the reception availability table TA _A3 in a format in which the cell order matches the payload order, as in the third embodiment. For example, the third cell is updated so as to correspond to whether or not the payload # 3 can be received. Alternatively, another reception availability table T _A2 may be created in the same format.

For example, since the first received payload is address 0x0030, the second received payload is address 0x0620, etc., the correspondence between the reception order and the memory address of the storage destination is determined, so TD [1 ] = 0x0030, TD [4] = 0x0620, TD [5] = 0x0C10, it is possible to update the decryption payload memory address table _{T D} in the error correction decoding process section 22 and so on .... However, in the present embodiment, subscript T _D indicates the payload number.

After the decoding process, the packet reception processing unit 21 needs to know which payload could be restored and which could not be done. However, in order to convey the information, the place where the restoration could not be performed is 0 as in T _A2 of the third embodiment. Need to be. Therefore, the error correction decoding processing unit 22 changes the format to T _{A1 in} the third embodiment. The nature of the reception availability table T _A2 for transmitting the restoration result is the same as in the third embodiment.

In the present embodiment, the payload number that could not be received is described at the end of the reception availability table T _{A3 by} the packet reception processing unit 21 and notified to the error correction decoding processing unit 22 together with information indicating how many have been received. . For example, when payloads # 3 and # 6 are lost, the packet reception processing unit 21 notifies the error correction decoding processing unit 22 of information that a total of four received as TA1 [5] = 3 and TA1 [6] = 6. To do.

The decoding calculation unit 209 allocates restoration destinations # 3 and # 6 from an empty area of the buffer. For example, TD [3] = 0x17F0 and TD [6] = 0x1DE0 are updated. Thus, the packet reception processing section 21 can retrieve the data restored by referring to T _D.

The invention according to this embodiment, the soft side and decoding the payload memory address table T _D, it is not necessary to implement the update unit, the effect of those simplify the structure of the soft side.

  In the error correction decoding apparatus according to the present embodiment, as a mechanism in which software requests a library to create a table, for example, in response to a memory allocation request from software that uses a library instead of a system in which the software operates, the memory allocation is performed by software. An interface for returning may be further provided.

(Embodiment 5)
FIG. 4 is an overall configuration diagram of the error correction decoding apparatus according to the present embodiment. The error correction decoding apparatus according to the present embodiment includes a reception availability table update unit 226 instead of the reception availability table / decoding table memory address table update unit 206 in the second embodiment.

In this embodiment, the payload data writing unit 205 analyzes the payload header of the received packet once, not in the order of reception, and obtains the payload number, and then places it in the packet reception buffer memory 232 in the order of the payload number. To go. Address value of each cell in decoding the payload memory address table T _D is not required updates for sufficient if the address of the same payload number and cell numbers are arranged. Therefore, the error correction decoding apparatus according to the present embodiment updates the reception availability table T _A1 by the reception availability table updating unit 226 in the same manner as in Embodiment 3, and thereafter performs the same processing as in Embodiment 3.

(Embodiment 6)
Another embodiment of the embodiment 3, 4, 5, not provided with the packet reception buffer memory securement requesting unit 201, a packet receiving buffer memory 232 within the packet reception processing section 21, receiving the payload memory address table T _R, for decoding a packet memory address table T _D may be created.

In this embodiment, as the head address of each payload are aligned by the arithmetic unit in decoding operation unit 209 to generate a decoded payload memory address table T _D. In this case, steps S201 and S202 are omitted in the third, fourth, and fifth embodiments, and processing equivalent to steps S202 and S203 is performed in the packet reception processing unit 21. The subsequent steps are the same as those in the third, fourth, and fifth embodiments.

(Embodiment 7)
In the present embodiment, it described a specific generation method of decoding the payload memory address table T _D in the payload memory address for coding table T _C and Embodiment 3-5 in the first and second embodiments.

T _C and T _D is generated by subtracting the header size from the numerical start address of each header. For example, when the error correction operation unit is 16 bytes, the buffer memory of the number of packets corresponding to one code block is secured as shown in FIG. 5, and the start address of each payload storage area is calculated so as to be a multiple of 16. To create a payload memory address table. For example, when the payload start address is “0x0030” and the packet header size is 40 bytes, the payload storage area start address is “0x0008”.

  In FIG. 5, an empty area of 12 bytes from the end of each payload is secured so that the end of each payload and the beginning of the next header do not fall within the same 16-byte segment. FIG. 6 shows an example in which the payload storage area is arranged with the empty area from the end of each payload as small as possible. The address obtained by rounding up the value obtained by adding the header size to the address at the end of the payload in units of 16 bytes becomes the next payload start address, and the header start address is calculated backward from there to reduce it to a value that cannot be further reduced in calculation. .

  In the error correction encoding / decoding operation, a plurality of payloads are divided into operation units and exclusive OR is calculated. However, when the arrangement as shown in FIG. 6 is performed, the payload as shown in FIG. XOR of the header area heads that are irrelevant at the end of is calculated. In FIG. 7, XOR operation is performed 16 bytes at a time from the top addresses of two payloads, and the result is sequentially stored in the operation result storage destination. The last part is stored including the unused part, and the software handles the data by ignoring the unused part. However, even in this case, data from the end of the calculation result to the calculation unit boundary can be ignored and handled as a non-use area.

  The example of the memory arrangement of FIG. 5 prevents a part of the header area that is not necessary for the operation from being partially involved in the operation at the end of the payload when performing an XOR (exclusive OR) operation between the payloads. effective. The example of FIG. 6 has the effect of minimizing the empty area between the end of the payload and the next header. For this reason, in FIG. 7, in FIG. 6, the beginning of the next header is partly involved in the XOR operation at the end of the payload, but unnecessary portions are not used. Therefore, FIG. 5 is used when meaningful information is stored in advance in the header area of each packet before the calculation of payloads.

  In order to prevent memory access outside the reserved area, when the arrangement as shown in FIG. 6 is performed, the empty area after the end of the payload at the end of the code block needs to be secured so as to be divided by the operation unit. .

<Effects produced by the invention>
According to the present invention, the cost associated with data sharing between the error correction coding processing unit 12 and the packet transmission processing unit 11 is reduced, and the error correction decoding processing unit 22 and the packet reception processing unit 21 are connected to each other. Costs associated with data sharing can be reduced, and overall throughput can be improved and processing load can be reduced.

When the packet order is changed in the network transmission path, the process of changing the data in the original order on the receiving side requires a memory copy, which causes a load. Error correction decoding processing unit 22 according to the fifth embodiment from the third embodiment manages the decryption payload memory address table T _D, continue to store the packet on a receiving buffer in the order as received. For this reason, the error correction decoding apparatus according to the third to fifth embodiments can reduce the load on the packet reception processing unit 21. Since the error correction decoding processing unit 22 performs an exclusive OR operation for each payload, if the payload storage memory address corresponding to the payload number is known, the decoding operation can be performed even if the payloads are not arranged in the original number order. Can be done. This effect can be said to be particularly effective in the field of error correction processing in which operations are performed in packet units or payload units and the arrival order is not guaranteed.

  In information transmission using error correction processing, a packet, which is a unit of transmission, is generally composed of a payload portion that is subject to protection against errors and a header portion that does not require protection. In the case of a configuration in which only the payload portion is continuously arranged on the memory, a memory copy is generated to form a packet by combining with the header at the time of transmission, and only the payload is stored after storing the packet in a temporary area at the time of reception You need a memory copy to remove When the entire packet is stored in the memory while referring to the transmission / reception packet memory address table as in the present invention, the number of memory copies related to transmission / reception can be reduced. Furthermore, by using the encoding / decoding payload memory address table as in the present invention, it is possible to perform error correction processing while accessing only the data of the payload portion necessary for error correction calculation. .

In the case of the fifth embodiment, since it is necessary to look at the header once to know the payload number, it may be necessary to copy the memory from the socket buffer of the packet receiving unit 204 to another area once. Since the process for searching the memory address corresponding to the payload number from the received packet memory address table T _R is applied, the effect of the present invention as compared to the third and fourth embodiments is weakened. Meanwhile, there is no need for updating decryption payload memory address table T _D, can be easily implemented.

  Further, recent computers have an instruction extension for SIMD (Single Instruction Multiple Data) operation, and by using this, the operation speed of exclusive OR in error correction processing can be greatly improved. For example, an ordinary 32-bit CPU can only execute an exclusive OR operation every 32 bits (4 bytes), but using SIMD instructions enables operations in units of 128 bits (16 bytes). The calculation speed is improved. However, for this purpose, it is necessary to access the data to be calculated in units of 16 bytes. In the error correction calculation, only the payload data is a calculation target. Therefore, the start address of the payload data must be a multiple of 16 bytes so that the calculation can be performed 16 bytes at a time from the start of the payload data. That is, the payload data must be secured in an area aligned with 16 bytes. If the combined packet size of the header and payload is a multiple of 16, even if the header size is not a multiple of 16 bytes, the SIMD operation is not performed exceptionally only from the beginning of the payload to the first 16-byte boundary. Thereafter, SIMD operations can be performed every 16 bytes. However, since it is impossible when the packet size is not a multiple of 16, payload data is stored so that each payload area is aligned with 16 bytes as in the present invention, and an address table of each payload area is used. By performing data sharing with the error correction coding and packet decoding processing unit, it is possible to reduce the cost of data sharing at any packet size and to perform high-speed calculations in the error correction coding and packet decoding processing unit.

  In addition, since the error correction encoding processing unit 12 and the error correction decoding processing unit 22 provide means for securing the buffer memory and generating the address table, the configuration of the information transmitting / receiving device using the same device becomes easy. is there.

  The present invention can be applied to the information communication industry.

11: Packet transmission processing unit 12: Error correction coding processing unit 21: Packet reception processing unit 22: Error correction decoding processing unit 101: Packet transmission buffer memory securing request unit 102: Packet transmission buffer memory securing unit 103: Packet payload memory Address table generation unit 104: Source data reading unit 105: Payload data writing unit 106: Encoding processing start request unit 107: Encoding payload memory address table input unit 108: Encoding operation unit 109: Packet transmission unit 132: Packet transmission Buffer memory 201: Packet reception buffer memory allocation request unit 202: Packet reception buffer memory allocation unit 203: Packet / payload memory address table generation unit 204: Packet reception unit 205: Payload data writing unit 206: Reception Availability table / decoding table memory address table update unit 207: Decoding processing start request unit 208: Decoding payload memory address table input unit 209: Decoding operation unit 210: Source data output unit 226: Receivability table updating unit 228: For decoding Payload memory address table update / input unit 232: packet reception buffer memory

Claims (8)

A payload memory address table for encoding that manages the memory address of the payload data of each packet included in one code block in the packet transmission buffer memory in which the transmission data is stored. An encoding memory address table generation unit for generating an integer multiple;
An encoding operation unit that reads the payload data of each packet from the packet transmission buffer memory with reference to an address stored in the encoding payload memory address table, and encodes the read payload data;
An encoding device comprising: A transmission memory address table generation unit for creating a transmission packet memory address table for managing the memory address of the header of each packet in the packet transmission buffer memory based on the information of each packet;
A packet transmission unit that reads and transmits the header and payload data of each packet from the packet transmission buffer memory with reference to addresses stored in the packet memory address table for transmission;
The encoding device according to claim 1, further comprising: Decoding memory that generates a payload memory address table for decoding that manages the memory address of the payload data in the packet reception buffer memory in which the received data is stored so that the leading address of the payload data is an integral multiple of the decoding operation unit An address table generation unit;
A decoding operation unit that reads the payload data of each packet from the packet reception buffer memory with reference to the address stored in the decoding payload memory address table, and decodes the read payload data;
A decoding device comprising: A reception availability table creating unit that creates a reception availability table that manages whether or not each packet is received in the order of reception of each packet;
The decoding memory address table generation unit associates the address of the header of each packet in the packet reception buffer memory with the transmission order based on the information of each packet,
The decoding apparatus according to claim 3, wherein the decoding calculation unit restores a lost packet based on whether or not each packet in the reception availability table is received. A payload memory address table for encoding that manages the memory address of the payload data of each packet included in one code block in the packet transmission buffer memory in which the transmission data is stored. A procedure for generating a memory address table on the transmission side that is generated to be an integer multiple,
An encoding operation procedure for reading the payload data of each packet from the packet transmission buffer memory with reference to the address stored in the encoding payload memory address table, and encoding the read payload data;
The encoding method which has these in order. In the transmission-side memory address table generation procedure, further, a transmission packet memory address table for managing the memory address of the header of each packet in the packet transmission buffer memory based on the information of each packet is created,
A packet transmission procedure for reading out and transmitting the header and payload data of each packet from the packet transmission buffer memory with reference to an address stored in the packet memory address table for transmission is further provided after the encoding operation procedure. The encoding method according to claim 5, wherein: Receiver memory that generates a payload memory address table for decoding that manages the memory address of the payload data in the packet reception buffer memory in which the received data is stored so that the start address of the payload data is an integral multiple of the decoding operation unit Address table generation procedure,
A decoding calculation procedure for reading payload data of each packet from the packet reception buffer memory with reference to an address stored in the decoding payload memory address table, and decoding the read payload data;
In order. In the reception-side memory address table generation procedure, a reception availability table for managing the presence / absence of each packet in the order of reception of each packet is created, and data of each packet included in one code block is stored in the order of reception Associating the header address of each packet in the packet reception buffer memory with the transmission order based on the information of each packet,
The decoding method according to claim 7, wherein in the decoding calculation procedure, lost packets are restored based on whether or not each packet in the reception availability table is received.

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