TW471036B - Method of forming gate electrode of semiconductor device - Google Patents

Method of forming gate electrode of semiconductor device Download PDF

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Publication number
TW471036B
TW471036B TW088121365A TW88121365A TW471036B TW 471036 B TW471036 B TW 471036B TW 088121365 A TW088121365 A TW 088121365A TW 88121365 A TW88121365 A TW 88121365A TW 471036 B TW471036 B TW 471036B
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Taiwan
Prior art keywords
gate electrode
forming
silicide film
film
titanium silicide
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TW088121365A
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Chinese (zh)
Inventor
Se-Aug Jang
Tae-Kyun Kim
In-Seok Yeo
You-Seok Suh
Dae-Gyu Park
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Hyundai Electronics Ind
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Disclosed is a method of forming a gate electrode of semiconductor device capable of preventing occurrence of voids in a titanium silicide film during formation of the gate electrode including a titanium silicide film. The method comprises steps of: forming a gate oxide on a semiconductor substrate; depositing a polysilicon layer on the gate oxide; depositing a silicide film on the polysilicon layer; densifying the silicide film; crystallizing the silicide film; depositing a hard mask film on the silicide film; and forming a gate electrode by patterning in a selected type the hard mask film, the crystallized silicide film, the polysilicon layer and the gate oxide.

Description

471036471036

五、發日月說明（1) 發明背i 別 方 曰本發明是關於1欣平導體元件之開電 疋一具有多晶矽化物結構的半導體元件 ^ 法。 1卞幻間私極的形成 之描述 隨著半導體元件積體電路的高度隼并外 屬導線，寬變得更小。因為多晶矽閘“的金 :很難高速運作。傳統上，是以沈積金屬矽又：’ 層上的多晶矽化物結構的閘電極為主。 在夕日曰石夕Fifth, the description of the sun and the moon (1) The invention of the invention, i.e. the invention is related to the power of 1 Xinping conductor element, a semiconductor element with a polycrystalline silicide structure method. 1 Description of the formation of private poles between magical cells As the height of a semiconductor device integrated circuit is combined with external wires, the width becomes smaller. Because of the polycrystalline silicon gate "gold: it is difficult to operate at high speed. Traditionally, the gate electrode is mainly deposited with silicon and polycrystalline silicide structure on the layer."

圖到；^傳統多晶機結構的間電極之方法參考第1A ”4= 二;Γϊΐ成ί或沈積法形成閘極氧化物 多晶上沈積選定厚度的摻雜雜質的 之後，如第1Β圖所示，鈦化矽薄膜TiSi ! 4 積於多，石夕層13上…匕石夕薄膜;二物4 =Figure to: ^ The method of the inter electrode of the traditional polycrystalline silicon structure refers to the first 1A "4 = 2; Γ ϊΐ or deposition method to form the gate oxide polycrystal after the deposition of doped impurities of selected thickness, as shown in Figure 1B As shown in the figure, the silicon nitride film TiSi! 4 is accumulated on the stone layer 13 ... the stone layer; the two objects 4 =

•、衣王％為非晶恕。沈積製程時的非晶態鈦化 U• Yi Wang% is amorphous. Amorphous Titanium during deposition process U

TiSlx 14為較鬆散結構。 存除 如第1C圖所示，非晶質的鈦化矽薄膜TiSix 14 =二退火數分鐘而轉變成結晶的鈦化矽薄膜TiSi2 5' 、 =二ϋ是在約7 5 〇 °C左右或更高溫下進行使得結晶的鈦 4膜T i S i2 1 5轉變成較低電阻的[5 4結構。 參考第1D圖所示，硬罩幕膜16沈積在結晶鈦化矽薄膜 1 h 15上。藉由連續蝕刻硬罩幕膜16，結晶的鈦化矽薄TiSlx 14 is a relatively loose structure. As shown in FIG. 1C, the amorphous silicon titanide film TiSix 14 = is annealed for several minutes and is transformed into a crystalline silicon titanide film TiSi2 5 ', = ϋ is at about 750 ° C or At higher temperatures, the crystalline titanium 4 film T i S i 2 1 5 is transformed into a lower resistance [5 4 structure. Referring to FIG. 1D, a hard mask film 16 is deposited on the crystalline silicon titanide film 1 h 15. By continuously etching the hard mask film 16, the crystallized silicon titanate is thin

471036 五、發明說明（2) 膜T 1 s I2 1 5和摻雜雜質的多晶矽層丨3以形成閘電極丨〇。 然而’當非晶質鈦化矽薄膜T i s “丨4轉變成結晶薄膜 時’會在結晶的鈦化矽薄膜T i s ^ 1 5中形成多個約〇 · 1輝或 小於的空洞，其情形如第2 A圖所示。在快速熱退火時，空 洞1 7會因為結晶的鈦化矽薄膜τ丨s丨2 1 5快速收縮而產生。 結果’如第2 B圖所示，即使在形成閘電極1 〇之後，空 洞1 7仍然存在，而造成閘電極1 0有效寬度的減少也會增加 閘電極1 0的片電阻。 第3A圖是結晶的鈦化矽薄膜TiSid5經過快速熱退火 之後的掃描式電子顯微鏡（”SEM”）照片。空洞17會產生 在結晶的鈦化矽薄膜TiSi2l5的某些區域。 曰而且，第3β圖是圖形結晶的鈦化矽薄膜TiSi215和多 晶石夕層1 3以形成閘電極的SEM照片。 I考第3B圖’空洞1 7會產生在結晶欽化石夕薄膜 n b 的兩邊而降低閘電極的有效寬度。 又 因此，本發明的目的是降低閘電極的電阻。 =如明的另一目的是避免閘電極有效寬度的降低。 法且ί:達i上述目的，本發明提出-種形成閘電極的方 巧有:列步·：形成一開電極於半導體基板上，：： :曰“夕：於閘極氧化物± ’沈積—石夕化物薄膜 ： 緻社、化矽化物薄膜，結晶 、二日日^ 幕暝於矽化物薄膜，和形成二：化物“，沈積-硬罩 又皁幕胺、結晶的矽化物薄 夕 弋々八的 勝 夕日日矽層和閘極氧化物。471036 V. Description of the invention (2) The film T 1 s I 2 1 5 and the impurity-doped polycrystalline silicon layer 丨 3 to form a gate electrode 丨 0. However, 'when the amorphous silicon titanated film T is "丨 4 is transformed into a crystalline film', a plurality of cavities of about 0.1 or less are formed in the crystalline silicon titanized film T is ^ 1 5. As shown in Figure 2A. During rapid thermal annealing, voids 17 will be generated due to the rapid shrinkage of the crystalline silicon titanide film τ 丨 s 丨 2 1 5. The result 'as shown in Figure 2B, even in the formation After the gate electrode 10, the void 17 still exists, and the reduction of the effective width of the gate electrode 10 will also increase the sheet resistance of the gate electrode 10. Figure 3A shows the crystalline silicon titanate film TiSid5 after rapid thermal annealing. Scanning electron microscope ("SEM") photograph. Cavities 17 will be created in certain areas of the crystalline silicon titanate film TiSi2115. Also, Figure 3β is a patterned crystalline silicon titanate film TiSi215 and polycrystalline silicon layer 1 3 to form a SEM photograph of the gate electrode. I test Figure 3B 'cavity 17 will generate on both sides of the crystallized fossil film nb to reduce the effective width of the gate electrode. Therefore, the object of the present invention is to reduce the resistance of the gate electrode . = Another purpose of Ruming is to avoid switching The effective width is reduced. In order to achieve the above object, the present invention proposes a method for forming a gate electrode: column step: forming an open electrode on a semiconductor substrate: ::: "Xi: Yu gate" Oxide ± 'Deposition—Silicon film: Zhishe, silicide film, crystal, two days a day ^ 暝 暝 on the silicide film, and the formation of two: compounds ", deposition-hard cover and soap curtain amine, crystalline The silicon layer and gate oxide of siliceous thin yawning day.

^1036^ 1036

471036 五、發明說明C4) 因此，可以獲得較低電阻的閘電極。 圖示的簡單說明 第1 A圖到第1 D圖是形成半導體元件之閘電極之傳統方 法的橫截面圖。 第2A圖表示傳統鈦化矽薄膜傳統結晶時產生空洞。 第2B圖表示傳統形成閘電極時產生空洞。 第3A圖是傳統鈦化矽薄膜傳統結晶時產生空洞的SEM 照片。 第3B圖是傳統閘電極的SEM照片。 第4A圖到第4E圖是根據本發明形成半導體元件之閘電· 極之方法的橫截面圖。 第5圖是本發明之閘電極的S Ε Μ。照片。 第6圖是根據本發明描述片電阻和閘電極線寬的關係 圖。 圖式中元件名稱與符號對照 10 : :閘 電 極 100 :閘電極 11 半 導 體 基 板 12 閘 極 氧 化 物 13 多 晶 矽 層 14 鈦 化 矽 薄 膜 TiSi 15 鈦 化 矽 薄 膜 TiSi 16 硬 罩 幕 膜 17 空 洞471036 V. Description of the invention C4) Therefore, a lower resistance gate electrode can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1D are cross-sectional views of a conventional method of forming a gate electrode of a semiconductor element. FIG. 2A shows a cavity generated during the conventional crystallization of a conventional silicon titanide film. FIG. 2B shows a cavity generated when a gate electrode is conventionally formed. Figure 3A is a SEM photograph of the voids generated during the conventional crystallization of a conventional silicon titanide film. Figure 3B is a SEM photograph of a conventional gate electrode. 4A to 4E are cross-sectional views of a method of forming a gate electrode of a semiconductor element according to the present invention. Fig. 5 shows the SEM of the gate electrode of the present invention. photo. Fig. 6 is a diagram illustrating the relationship between the chip resistance and the gate electrode line width according to the present invention. Comparison of component names and symbols in the drawing

471〇36471〇36

M,MMW^Kayr.vvM, MMW ^ Kayr.vv

Γ-Γ-

第10頁 471036 五、發明說明（6) 空洞的產生。 之後，如第4D圖所示，可以在半導體基板21上的形成 物以75 0〜90 0 °C溫度範圍進行快速熱退火1〇〜6〇秒將緻密 化的非晶態鈦化矽薄膜T i S ix24轉變成具有低電阻穩定態 C54結構的結晶化鈦化矽薄膜TiSi22 5。 其次，參考第4E圖，形成硬罩幕膜26在於鈦化矽薄膜 TiS “25上，而硬罩幕膜26由氧化物或氮化物所構成。此 時，硬罩幕膜26用來避免鈦化矽薄膜TiSi225的抗反射並 以自對位法來形成接觸孔。之後，具有硬罩幕膜26的閘電 極100藉由圖形硬罩幕膜26，鈦化矽薄膜TiSi225，摻雜多 晶矽層23和閘極絕緣層22的選定部份來形成。因為鈦化石夕 薄膜已經緻密化，即使進行結晶化步驟時薄膜的收縮也可 以最小。因此不會產生空洞。 的閘電極1 0 0 如弟5圖’跟據上述製程本較佳實施例中 不會產生空洞1 7。 $ 6圖疋根據本發明描述片電阻和閘電極線寬的關係 圖’ A1表不進行緻密化和結晶化兩個步驟的情形，而八2表 :只進行結晶化步驟的情形。第6圖A1的情形雖然線 寬改變仍可以獲得均勻的片電阻。然而在八2的情形中， 生在鈦化㈣膜中約(^雞或小於的空洞會增加片電阻。 在較佳實施例中，雖然使用鈦化石夕薄膜作為石夕化物薄 :，除了鈦化矽薄膜也可以使用其他過渡金屬的矽化物薄 如上述，根據本發明 其更具有在沈積鈦化矽薄膜和Page 10 471036 V. Description of the invention (6) The generation of holes. After that, as shown in FIG. 4D, the formation on the semiconductor substrate 21 can be subjected to rapid thermal annealing at a temperature range of 75 0 to 90 0 ° C for 10 to 60 seconds to densify the amorphous silicon titanic thin film T i S ix24 is transformed into a crystalline siliconized titanium thin film TiSi22 5 with a low-resistance steady state C54 structure. Next, referring to FIG. 4E, the hard mask film 26 is formed on the silicon titanide film TiS "25, and the hard mask film 26 is composed of an oxide or a nitride. At this time, the hard mask film 26 is used to avoid titanium The siliconized silicon film TiSi225 is anti-reflective and forms contact holes by self-alignment method. After that, the gate electrode 100 having the hard mask film 26 is patterned with a hard mask film 26, a silicon titanium film TiSi225, and a polycrystalline silicon layer 23 And the gate insulating layer 22 are formed. Because the titanium fossil thin film has been densified, even when the crystallization step is performed, the shrinkage of the film can be minimized. Therefore, no void is generated. The gate electrode 1 0 0 Such as 5 Figure 'According to the above process, no void 17 will be generated in this preferred embodiment. $ 6 Figure 描述 Description of the relationship between chip resistance and gate electrode line width according to the present invention' A1 shows two steps of densification and crystallization Table 2 shows a case where only the crystallization step is performed. In the case of FIG. 6 A1, a uniform sheet resistance can be obtained even if the line width is changed. However, in the case of 8 2 the (^ Chicken or smaller holes will increase the sheet resistance. The preferred embodiment, although the titanium fossil Tokyo film as stone Xi compound thin: silicide, in addition to titanium silicon thin film may be used other transition metals thin As described above, according to the present invention, which is more in the deposition of titanium silicon thin film, and

第11頁 471036 五、發明說明（7) 沈積鈦化矽薄膜步驟之間緻密化鈦化矽薄膜的步驟。 結果，在結晶化製程時不會有空洞產生在鈦化矽薄膜 中 。 而且，可以獲得較低電阻的閘電極。 需予陳明者，熟於此技術的人所進行的其他改變，在 不偏離本發明的範圍和精神時，應仍舊在本案之申請專利 範圍之内。Page 11 471036 V. Description of the invention (7) The step of densifying the silicon titanate film between the steps of depositing the silicon titanate film. As a result, no voids are generated in the silicon titanate film during the crystallization process. Moreover, a lower-resistance gate electrode can be obtained. For those who need to know, other changes made by those skilled in this technology should still be within the scope of the patent application in this case without departing from the scope and spirit of the present invention.

第12頁Page 12

Claims (1)

471036 六、申請專利範 MM 88121365 圍 修正 年 < 月V.曰471036 VI. Patent Application MM 88121365 Circumstances Amendment Year < Month V. Day I,種形成閘電極的方法，具有下列步驟： 形成一閘電極於半導體基板上； /尤積—多晶矽層於閘極氧化物上； 沈積一矽化物薄膜於多晶矽層上； 其特徵在於：是種形成閘電極的方法尚包括下牛 驟： 乂 緻您化石夕化物薄膜； 結晶化矽化物薄膜； 沈積一硬罩幕膜於矽化物薄膜；以及 藉由選定形態圖形硬罩幕膜、結晶的石夕化物薄膜、多 晶矽層和閘極氧化物而形成一閘電極。 、 2·如申請專利範圍第1項之形成閘電極的方法，其中 ‘在緻密化的步驟中，矽化物薄膜是在5 0 0〜65〇t溫度範圍 的惰性氣氛的烘箱中進行熱處理30分〜5小時。 又 3·如申請專利範圍第1項之形成閘電極的方法，其中 在緻密化的步驟中，矽化物薄膜是在5 0 0〜6 5 0 °c溫度範圍 的惰性氣氛的快速熱退火設備中進行熱處理1 〇〜1 2 Q秒。 4 ·如申睛專利範圍第1項之形成閘電極的方法，其中 石夕化物薄膜是由物理氣相鍍膜法所形成。 5. 如申請專利範圍第1項之形成閘電極的方法，其中 結晶夺化物薄膜的步驟是在乃〇〜9 〇 〇 C溫度範圍的快速熱 退火設備中進行1 〇〜6 0粆。 6. 如申請專利範圍第1項之形成閘電極的方法，其中 結晶矽化物薄膜的步驟是在750〜9 0 0 t溫度範圍的快速熱I. A method for forming a gate electrode having the following steps: forming a gate electrode on a semiconductor substrate; / especially a polycrystalline silicon layer on a gate oxide; depositing a silicide film on the polycrystalline silicon layer; A method for forming a gate electrode includes the following steps: Initiating a fossil film; crystallizing a silicide film; depositing a hard mask film on the silicide film; and patterning the hard mask film by a selected pattern. A gate electrode is formed by a stone oxide film, a polycrystalline silicon layer, and a gate oxide. 2. The method for forming a gate electrode according to item 1 of the scope of patent application, wherein, in the step of densification, the silicide film is heat-treated in an oven in an inert atmosphere at a temperature range of 500 to 65 ° t for 30 minutes. ~5 hours. 3. The method for forming a gate electrode according to item 1 of the scope of patent application, wherein in the step of densification, the silicide film is in a rapid thermal annealing equipment in an inert atmosphere at a temperature range of 500 to 6 50 ° C. The heat treatment is performed for 10 to 12 seconds. 4 · The method for forming a gate electrode as described in item 1 of the Shenjing patent scope, wherein the lithophyllite film is formed by a physical vapor deposition method. 5. The method for forming a gate electrode according to item 1 of the scope of patent application, wherein the step of crystallizing the compound film is performed in a rapid thermal annealing equipment at a temperature range of 0 ~ 900 ° C for 100 ~ 600 °. 6. The method for forming a gate electrode as described in the first item of the patent application, wherein the step of crystallizing the silicide film is a rapid thermal process in a temperature range of 750 ~ 900 t. 第13頁Page 13 年月日 修正 471036 _案號 88121365 六、申請專利範圍 退火沒備中進行熱處理1 Q〜6 〇秒。 中 7 ·如申請專利範圍第丨項之形成閘電極的方法’其 結晶矽化物薄膜的步驟是在7 5 0〜9 0 0 °C溫度範圍的快u ”、、 退火設備中進行熱處理1 〇〜6 〇秒。 8 · —種形成閘電極的方法，具有下列步驟： 形成一閘電極於半導體基板上； 沈積一多晶石夕層於閘極氧化物上； 沈積一矽化鈦薄膜於多晶矽層上； 其特徵在於：是種形成閘電極的方法，尚包括下列步Year Month Date Amendment 471036 _ Case No. 88121365 VI. Scope of Patent Application: Heat treatment is performed for 1 Q ~ 60 seconds during annealing. Medium 7 · As described in the patent application method of the method of forming a gate electrode, the step of crystallization of the silicide film is performed in a temperature range of 750 to 900 ° C, and heat treatment is performed in an annealing equipment. ~ 60 seconds. 8-A method for forming a gate electrode, comprising the following steps: forming a gate electrode on a semiconductor substrate; depositing a polycrystalline layer on the gate oxide; depositing a titanium silicide film on the polycrystalline silicon layer It is characterized in that it is a method for forming a gate electrode, and further includes the following steps 驟： 敏後化石夕化鈦薄膜·， 結晶化石夕化鈦薄膜； ，積一硬罩幕膜於矽化鈦薄膜；以及 藉由選定形態圖形硬罩幕膜、已結晶的矽化鈦薄膜、 多晶矽層和閘極氧化物而形成一閘電極； ^而在緻密化的步驟中，矽化鈦薄膜是在5 0 0〜6 5 0 °C溫 度範圍的惰性氣氛的烘箱中進行熱處理3 0分〜5小時。Step: Sensitized fossilized titanium thin film ·, Crystallized fossilized titanium thin film; Integrating a hard mask film on a titanium silicide film; and a hard mask film with a selected shape pattern, a crystallized titanium silicide film, and a polycrystalline silicon layer And a gate oxide to form a gate electrode; ^ In the densification step, the titanium silicide film is heat-treated in an oven in an inert atmosphere at a temperature range of 500 to 6 50 ° C for 30 minutes to 5 hours . 9 ·如申請專利範圍第8項之形成閘電極的方法，其中 矽化1鈦薄膜是由物理氣相鍍膜法所形成。 钍曰如申請專利範圍第8項之形成閘電極的方法，其中 =曰曰卜矽化鈦薄膜的步驟是在75〇〜9〇〇 〇c溫度 熱退丨火設備中進行10〜60秒。 種形成閘電極的方法，具有下列步驟： 形成一閘電極於半導體基板上；9. The method for forming a gate electrode according to item 8 of the scope of patent application, wherein the titanium silicide film is formed by a physical vapor deposition method. For example, the method for forming a gate electrode according to item 8 of the scope of the patent application, wherein the step of forming a titanium silicide film is performed in a thermal annealing furnace at a temperature of 75-900 ° C for 10-60 seconds. A method for forming a gate electrode has the following steps: forming a gate electrode on a semiconductor substrate; ^71036 88121365 六、申請專利範圍 曰 修正 沈積一多晶矽層於閘極氧化物上； 沈積—矽化鈦薄膜於多晶矽層上； 驟 /、特徵在於··是種形成閘電極的方法，尚包括下列步 緻密化矽化鈦薄膜； 結晶化矽化鈦薄膜； 沈積一硬罩幕膜於矽化鈦薄膜；和 ^ 藉由選定形態圖形硬罩幕膜、已結晶的矽化鈦薄膜、 多晶石夕層和閘極氧化物而形成一閘電極；^ 71036 88121365 6. Scope of patent application: Correction and deposition of a polycrystalline silicon layer on the gate oxide; Deposition-Titanium silicide film on the polycrystalline silicon layer; Step / 、 Characterized in that it is a method of forming a gate electrode, including the following Densify the titanium silicide film; crystallize the titanium silicide film; deposit a hard mask film on the titanium silicide film; and ^ pattern the hard mask film, the crystallized titanium silicide film, the polycrystalline silicon layer and the gate electrode by a selected shape Oxide to form a gate electrode; 而在緻密化的步驟中，矽化鈦薄膜是在5 0 0〜6 5 0 °C溫 度範圍的惰性氣氛的快速熱退火設備中進行熱處理1 〇〜 1 2 0 秒。 1 2.如申請專利範圍第11項之形成閘電極的方法，其 中矽化鈦薄膜是由物理氣相鍍膜法所形成。 1 3 ·如申請專利範圍第11項之形成閘電極的方法，其 中結晶化矽化鈦薄膜的梦驟是在7 5 0〜9 0 0 °C溫度範圍的快 速熱退火設備中進行丨〇 — 60秒。In the densification step, the titanium silicide film is heat-treated in a rapid thermal annealing apparatus in an inert atmosphere at a temperature range of 500 to 650 ° C for 10 to 120 seconds. 1 2. The method for forming a gate electrode according to item 11 of the application, wherein the titanium silicide film is formed by a physical vapor deposition method. 1 3 · The method for forming a gate electrode according to item 11 of the scope of patent application, wherein the dream step of crystallizing the titanium silicide film is performed in a rapid thermal annealing equipment at a temperature range of 7500 ~ 900 ° C. 〇-60 second. 第15頁Page 15
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