TWI292928B - Manufacturing method of semiconductor device - Google Patents

Description

1292928 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical connection to which Manning belongs The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a self-aligned metal halide. In the prior art, as the semiconductor element accumulating degree (Inte grati ο η ) increases, the pattern and line width in the opposite element are gradually reduced, resulting in an increase in the contact resistance between the gate and the conductor and the line in the element, resulting in a slower resistance. - Capacitance delay (RC De 1 ay ), which in turn affects the operating speed of the component. Since the resistance of the metal telluride is higher than that of the crystal 夕 Ρ Ρ 1 ysi 1 ic ο η , and its thermal stability is higher than that of the general interconnect material (for example, aluminum), in order to reduce the source (Source) / The Sheet Resistance of the Drain region ensures the integrity of the Shallow Junction between the metal and the semiconductor component, and can form a connection interface between the gate and the source/drain and metal wires. Metal sanding to reduce the electrical resistance between the gate and source/no 'pole regions and metal wires. At present, the fabrication of semiconductor components is aligned with the metal germanide process. The self-formation is a metallization that is applied to a high temperature environment on a semiconductor wafer to cover the gate layer, and which is formed in contact with the crucible at a high temperature and in a high temperature environment. Since the wafer is otherwise touched, it is a high-temperature treatment, and it is not necessary to form a metal layer in the formation of the metal lithium compound. The metal is then reacted under the gold and the source/drain regions to produce a metal halide. And = transformation to form a lower resistance value. The metal layer on the bismuth is not connected to the bismuth and does not produce metal bismuth. Due to lithography

1292928 V. INSTRUCTIONS (2) ' -------- The process steps can be formed in a specific bit 2. This metal telluride is called self-aligned metal telluride. The 4 soldiers' self-aligned metallization process makes the metal and the stone and polycrystalline germanium f, and forms a metal telluride, so when the metal telluride is formed, it will be a knife, as in December 1999 in the semiconductor component. In the study of the International Symposium, the ultra-thin insulation layer of the Shixi Huayu channel has the Shi Xizhi nano-p-type gold-oxygen crystal crystal" and the I j published in the International Symposium on Joint Technology. The new 7〇〇, its selective epitaxial growth technology. However, as the component accumulating degree gradually increases, the junction of the source/drain regions becomes shallower, so the metal telluride may extend further down to the junction of the source/drain regions (Juncti〇n It is even possible to pass through the source/drain regions, which may easily cause problems in the source/drain regions of the semiconductor device, thereby affecting the device performance. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of fabricating a semiconductor device in which a ruthenium layer is formed on a substrate prior to performing a self-aligned metal telluride process, thereby performing a self-aligned metal germanide process. The enthalpy of the surface of the source/drain region is not consumed, and the junction leakage current during the ultra-shallow bonding can be avoided. Another object of the present invention is to provide a method of fabricating a self-aligned metalloid compound which can reduce the phase transition temperature of the metal telluride layer by using a germanium germanium layer prior to performing the self-aligned metal germanide process. According to an object of the present invention, a method of fabricating a semiconductor device is provided, the method comprising: forming a gate structure and a source/drain on a substrate

1292928 V. INSTRUCTIONS (3) ! : J! Gate; the structure is constructed by the gate dielectric layer, the conductor layer and the cap layer, and the heat is formed on the upper surface to form an amorphous sand staggered layer. The amorphous germanium layer on the surface of the source/drain region is transformed into a crystalline germanium. After removing the amorphous germanium layer outside the source/drain regions, the cap layer is removed. Then, a self-aligned process of nugned suicide is performed to form a layer of metal 3 on the substrate, followed by a thermal process to cause a deuteration reaction between the metal layer and the surface of the gate structure and the surface of the source electrode. Forming a metal telluride layer on the surface of the gate structure and the source 鹣/= and the surface of the polar region, and then in the form of wet etching: ΐίϊ reaction metal [final rapid thermal tempering process reduces the resistance value of the metal halide layer . The present invention forms a stone-like layer at the source before the self-alignment metal lithium process, so that the surface of the source/drain region is not consumed when self-aligning the metal granules. The junction leakage current can occur when the junction is shallow. OVERVIEW OF THE INVENTION The present invention additionally provides a self-aligned metal germanide fabrication method comprising: forming a gate structure dielectric layer and a conductor layer on a substrate. Then the amorphous layer of the body layer, the source/... surface: the wrong re-/Han=process, so that the guiding slaves recognize the nine ^ 曰曰 / 1 匕 staggered layer into a crystalline bismuth layer. The contact removes the conductor layer from the non-tantal layer outside the source/drain regions. Then, a self-aligned metal germanium compound (se if 7 = l1Cide) process is performed to form a metal layer on the substrate, and J = l is provided for 4 steps to make the metal layer and the gate structure surface and the source/drain region surface. The light of the stone, Xi,,

1292928 V. Inventive description, the gentry reaction, in order to gate the surface of the structure and the source of the genus: η to remove the unreported stagnation of the genus layer by wet etching, and finally perform a fast 埶f,, 7 The value of the inverse two is lowered. The mouth of the fire coat column is the most resistant layer of the bismuth layer. The invention is for self-alignment of the metal bismuth compound 裎 汲 汲 汲 汲 汲 郴 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 昆 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于The junction leakage current occurs when the self-aligned metal slab is joined. To avoid the super-layer and it: ΐ ϊ: The surface structure of the ΐ structure and the source/no-polar region is covered with a tempering tempering step: in the process of aligning the metal lithium compound, the rapid thermal transfer is performed at a lower temperature. The metal halide is phase-transferred to reduce the electrical resistance of the metal halide. The above objects, features and advantages of the present invention can be more clearly understood. Two preferred embodiments are described in detail with reference to the accompanying drawings. Referring to Figure 1A, a substrate 1 is provided. The material of the substrate is, for example, a semiconductor germanium substrate. Forming the element isolation structure 1〇2 in the substrate 1〇〇, the element isolation structure 102 is, for example, a field oxide layer formed by a region oxidation method (LOCOS) or a shallow trench isolation (shallow trench) Is〇iati〇I1, STI) structure. Then, a gate dielectric layer 1〇4, a conductor layer 1〇6, and a cap layer 108 are sequentially formed on the surface of the substrate 100. The material of the gate dielectric layer 104 is, for example, hafnium oxide.

10293twf.ptd Page 8 1292928 V. Description of the invention (5) " Shi Xi's method of forming it, for example, by chemical vapor deposition in the form of on-site doping ions; and the material of the cap layer is, for example, Phosphorus glass, stone-filled glass or a gap formed by a subsequent predetermined gap is a method of forming a top layer, for example, chemical vapor deposition (CVD). A patterned cap layer 108, a conductor layer 106 and a gate dielectric layer 1 〇 4 are formed to form a gate structure 1 1 〇. Next, referring to FIG. 1B, a dopant implantation process is performed to form a lightly doped region 丨丨2 in the substrate 1 两侧 on both sides of the gate structure 110, in this step, the gate structure 110 is The mask has a p-type or N-type light doping on the substrate, and the main germanium is formed to be used as a light doping to prevent the occurrence of a hot carrier effect;;: a lightly doped drain. Next, referring to FIG. 1C, a spacer 114 is formed on the sidewall of the gate structure 1 1 ,. The material of the spacer 114 is different from the material of the cap layer 1 〇 8 , and the spacer Π The material of 4 includes yttrium oxide or chaotic lithium. The method of forming is to deposit yttrium oxide or tantalum nitride on the substrate by chemical vapor deposition, and then perform the spacer 1 1 by anisotropic etching. 4 money engraved 'to form a spacer 114 on the sidewall of the gate structure. Then, the entire gate structure 1 1 含有 containing the spacers 4 is used as a mask to perform a dopant implantation process on the substrate 100, and the substrate 1 on both sides of the gate structure 110 having the spacers 4 A heavily doped region 1 1 6 is formed in 0 0 , and the heavily doped region 1 16 and the lightly doped region 11 2 constitute a source/narrow region 11 8 . Next, please refer to Figure 1D to form an amorphous germanium layer on the substrate.

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Ο, a method for forming an amorphous germanium layer on the substrate 1 is, for example, a chemical vapor deposition method using decane/decane/hydrogen as a reaction gas source, an operating pressure of 3 mtorr and a deposition temperature of 4〇() ^ to 5〇Q. Next, a thermal "process" is performed to convert the amorphous 夕 layer 11 20 on the surface of the source/drain region 1 18 into a crystalline bismuth layer i 22 . The thermal process operating temperature is, for example, between 疋5 0 0 C and 600 ° C. 'Because the material of the source/drain region 1 1 8 is 矽' during the thermal process, the amorphous germanium layer on the surface The 丨2 〇 effect is converted into a crystalline bismuth telluride layer 1 2 2, and the amorphous germanium telluride layer other than the source/drain region 丨丨8 is not converted into a crystalline bismuth telluride layer 丨2 2 . Then, referring to FIG. 1E, the amorphous germanium germanium layer 1 2 0 other than the source/drain region 丨丨8 is removed, and the removal method is, for example, a gasification hydrogen/hydrogen gas as an etching gas source. For example, between 70 ° C and 75 ° C. Next, please refer to Figure 1F to remove the top cover layer 8 by removing the method of HF based etchant. Next, referring to FIG. 1G, a self-aligned si licide process is performed, for example, a physical vapor deposition method is used to form a thickness of about 1 〇〇 to 5 〇〇 on the substrate 100. The metal layer is 1 2 4, and the material of the metal layer 1 24 is, for example, titanium. Then, refer to the 1 , diagram for the thermal process. For example, the thermal process is rapid thermal pr〇cess. The operating temperature of this thermal process is, for example, 600 to 700 °C, so that the metal layer 124 (titanium) and the gate A bismuth reaction occurs between the surface of the polar structure and the surface of the source/drain region to form a first metal telluride layer 丨26 on the surface of the gate structure and the surface of the source/drain region (TiSi2 C49) .

10293twf.ptd Page 10 1292928 V. INSTRUCTIONS (7) In the case of titanium, TiSi2 C49) turns green # + R ^ metal telluride layer 126 (矽化128 (titanium telluride, TiSi?, low brother one to the telluride layer 7 Between 0 0 °C and 900 ° C. The temperature of this thermal tempering process is about the same as in the above embodiment, before the process, on the source " and the aging: self-aligning metal矽 行 自行 自行 = = = = = = = = = = = = = = Therefore, the (MOSFET) 作 之 之 之 之 之 金 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在The top layer 1 08 of the first layer is described as an example only. Of course, the gate electrode 蛀Μη η μ t π , , τ & is formed into the cap layer 106, so that the gate layer is also formed on the pole rail system. It can be invisible. , ka _ ^ a 仃..., 耘, so that the source/drain region 1 1 8 表 夕 化 。 。 。 。 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因 因彳. After the 锗 layer, the conductor layer 1 〇6 and the source/polar region 118 will leave a crystalline 夕 锗 锗 layer. Since the 夕 锗 锗 layer will lower the temperature of the phase transfer, it will follow In the rapid thermal tempering step in the process of self-alignment of the metal compound, the metal phase can be phase-transferred at a lower temperature to reduce the metal resistance. In the embodiment of the invention, the metal is condensed. Explain for the example, of course

L〇293twf.ptd Page 11 1292928 V. INSTRUCTIONS (8) The present invention is also applicable to other Refractory Metal ions, such as 镌, 始, Titanium, Nickel, Face, 纪 or Key. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that the present invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10293twf.ptd Page 12 1292928 Schematic Description of the Drawings FIG. 1A to FIG. 1I are cross-sectional views showing a process of self-aligning metal cerium compound according to an embodiment of the present invention. Schematic description · 100 substrate 102 element isolation structure 104 gate dielectric layer 106 conductor layer 108 cap layer 110 gate structure 112 light doping 114 spacer 116 thick swap region 118 source / > and polar region 120 Amorphous germanium germanium layer 122 crystalline germanium stagger layer 124 metal layer 126 first metal telluride layer 128 second metal telluride layer

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Claims (1)

1292928 VI. Patent Application Range 1. A method for fabricating a semiconductor device: < 10,000, the method includes the following steps: providing a substrate on which the substrate has been formed - a rabbit non-polar region, the gate structure including a pole a dielectric layer, an integral original cap layer and a spacer; θ is formed on the substrate to form a first thermal process, and the source/drain region is transformed into a first thermal process Forming a crystalline germanium layer; < removing the amorphous germanium sound outside the source/drain region for non-tanning; removing the cap layer; θ ' forming a metal layer on the substrate, performing one a second thermal process for causing a bismuth reaction between the metal layer and the surface of the source/drain region of the gate structure surface disk to form a metal on the surface of the gate structure, the surface and the surface of the source/drain region a telluride layer; and removing the metal layer that has not reacted with ruthenium. Method 2. The manufacturer of the semiconductor device as described in the third paragraph of the application of the patent application, wherein the material of the four metal layers includes a refractory metal. Method 3. The method for manufacturing a semiconductor device according to the above-mentioned patent application, wherein the material of the S-metal layer is one selected from the group consisting of tungsten, cobalt, titanium, nickel, platinum, palladium, and molybdenum. The method of manufacturing a semiconductor device according to the above-mentioned patent application, wherein the temperature range of the first thermal process is between 500 t and 6 〇〇〇 c. 5 · as claimed in the third paragraph of the patent application A method of forming a semiconductor device, wherein the method of forming the amorphous germanium layer on the substrate comprises chemistry 10293twf.ptd Page 14 1292928 VI. Patent application scope Vapor deposition method 6 Gan = application of the semiconductor element described in Item 5 of the S, wherein the amorphous germanium layer is formed on the germanium substrate. / decane / hydrogen is the source of the reaction gas. (iii) This includes the method described in § 7 of the scope of the patent application, in which the source/drain region is removed. 叔 6. The unprepared formula uses hydrogen chloride/hydrogen as the source of etching gas. ^Daily 矽 锗 包括 包括 包括 包括 包括 包括 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如< 材贝 has a different method of law. 9. As described in the scope of the patent application, the material of the cap layer is selected from the semiconductor element described in the first paragraph of the invention of the phosphorus n. The second dome layer includes a rice cooker containing a nitrogen acid component; i is manufactured by the manufacturer of the semiconductor component described in the first aspect of the patent application, wherein the step of removing the metal I that has not reacted with Shi Xi is further The rapid thermal tempering process reduces the resistance of the metallurgical layer. 1 2 - A method for fabricating self-aligned metal telluride. The method comprises the steps of: i providing a substrate on which a gate dielectric layer, a gate conductor layer, a spacer, and a source are formed. a drain region is formed on the substrate; and a first thermal process is performed to convert the gate layer and the amorphous germanium layer on the surface of the source/drain region into a crystallized layer Layer L〇293twf.ptd Page 15 1292928 6. The patent application scope removes the gate conductor layer, the amorphous germanium layer outside the source/drain region; forms a metal layer on the substrate; performs a second a thermal process to cause a bismuth reaction between the metal layer and the surface of the gate structure and the surface of the source/drain region to form a first metal telluride on the surface of the gate structure and the surface of the source/drain region a layer; and removing the metal layer that has not reacted with Shi Xi. A method of producing a self-aligned metal telluride according to claim 12, wherein the material of the metal layer comprises a refractory metal. 1 . The method for manufacturing a self-aligned metal halide according to claim 12, wherein the material of the metal layer is one selected from the group consisting of tungsten, cobalt, titanium, nickel, platinum, palladium, and molybdenum. . 1 5. The method of manufacturing a self-aligned metal telluride according to claim 12, wherein the temperature of the first thermal process ranges from 500 ° C to 6 Ο (ΓC. 1 6. The method for producing a self-aligned metal halide according to claim 12, wherein the method for forming the amorphous germanium layer on the substrate comprises a chemical vapor deposition method. The method for producing a self-aligned metal halide according to any of the preceding claims, wherein the method for forming the amorphous germanium germanium layer on the substrate comprises using decane/decane/hydrogen as a reaction gas source. The method for manufacturing self-aligned metal telluride according to item 2, wherein removing the gate conductor layer and the amorphous germanium layer other than the source/drain region comprises using hydrogenated hydrogen gas as an etching gas 10293twf.ptd Page 16 1292928 VI. Application for patent scope Source. 1 . The method of manufacturing a self-aligned metal halide according to claim 12, wherein the step of removing the metal layer not reacted with ruthenium further comprises performing a third thermal process to The first metal telluride layer is transformed into a second metallization layer, and the second metallization layer has a lower resistance than the first metal halide layer. 10293twf.ptd Page 17