TWI284941B - Fabricating process to improve resistance and current leakage phenomenon of deep-micron transistor for semiconductor device - Google Patents

Abstract

This invention reveals a fabricating process to improve the resistance and the current leakage phenomenon of deep-submicron transistor for semiconductor device. It comprises the following procedures: firstly, it sequentially forms an isolated region, a gate structure, a source/drain light-doping region, a gate gap-wall, a promoted source/drain structure, and a source/drain heavy doping region upon semiconductor substrate. Further, after utilizing a two-stage deposition metal layers, it forms a various-thickness or a various-material metal layer upon the gate structure, and the source/draw region. Afterwards, it respectively produces the various self-alignment metallic silicone compounds. This invention utilizes two aforementioned different metallic silicone compounds, and accords with the promoted source/drain structure to achieve the effects of reducing the resistance value of device, and avoiding the current leakage phenomenon of shallow junction.

Description

1284941 V. INSTRUCTION STATEMENT α) FIELD OF THE INVENTION The present invention relates to a semiconductor process technology, and more particularly to a gate structure and source capable of forming a self-aligned si 1 'salicide' salicide / Semiconductor device process in the drain region and which can improve the resistance and leakage of deep submicron transistors. BACKGROUND OF THE INVENTION: According to the semiconductor component process into the deep sub-micron process, and the accumulation of the integrated circuit is getting more and more, the area of the source/no-polar region is also reduced, but it will increase the source/汲 extreme contact. Resistor, but can not maintain the high current drive capability of the component, so in order to reduce the resistance of the component and increase the convenience of the subsequent connection of the wire, the automatic alignment metal halide technology has been widely used in the semiconductor process. However, the miniaturization of components is more limited by the application of shallow metal tantalum junctions, which are more likely to cause leakage with shallow junctions. Therefore, selective germanium epitaxy technology is used to produce elevated source/polarity gold oxides. The semiconductor transistor is controlled by the leakage generated by the application of simultaneously obtaining the shallow junction and the metal-rock junction. The semiconductor process steps for fabricating sources and poles for self-alignment and metal lithium are described in the first (a) to first (c) drawings. First, as shown in the first (a) diagram, a shallow trench isolation (STI) i 2 u-transistor gate structure 14 is formed in a semiconductor substrate 10, which is formed by a gate. The oxide layer 14 2 and a plurality of layers 14 4 are formed; and the gate structure 14 is used as a mask to perform a lower energy #一 ion implantation, forming a source/drain light in the semiconductor substrate 10擦杂#

1284941 V. INSTRUCTIONS (2) Area 1 6; Then, after forming the gate gap wall 丨8 on the sidewall of the gate structure 14 4, a selective epitaxial layer is grown in the ultra-high vacuum chemical vapor deposition system. The source/drain heavily doped region 22 is formed by a second ion implantation of higher energy after the source/drain region is formed to form an elevated source/drain structure. Once the active gates of the transistor gate structure and the raised source/drain structure 22 are completed, the process of self-aligning the metal telluride is performed, at this time: as shown in Fig. 1(b), A titanium metal layer 2 4 'continuously' is deposited on the semiconductor substrate 1 to temper the titanium metal layer 24 to make it with the lower gate, and the structure 14 and the source/drain structure 22 are on the epitaxial layer. The reaction is then converted to titanium = f. Thereafter, a portion of the titanium metal layer 24 that has not been reacted into the spring compound 28 is removed by wet residue etching to form a titanium metal telluride 2 as shown in the first (c) diagram. Man s _ treatment to reduce titanium: = = = object 28 is carried out... fire thick ^ conductor process step, if you want to form a more area of metal seconds, shallow i = gentleman = reduce resistance, then source / no pole H affects component characteristics and reliability.

Therefore, the resistance of the #A sub-micron transistor of the present invention and the above-mentioned problems have been proposed to improve the semiconductor device process for deepening the gate;) 3⁄4 "^" is an electrical phenomenon, so that ί = t, and the resistance of the polar region At the same time, it will not cause, i is missing. Image, and thus effectively solve the existence of the prior art, the purpose and summary of the invention:

Page 6 1284941 V. INSTRUCTIONS (3) The main object of the present invention is to provide a semiconductor device process for improving the resistance and leakage of deep submicron transistors, which is formed by different self-aligned metal telluride at the gate. The structure and source/drain regions are used to reduce the resistance in the gate structure and source/drain regions, while at the same time avoiding leakage of shallow junctions. Another object of the present invention is to provide a semiconductor device process for improving the resistance and leakage of a deep submicron transistor, which is to reduce the resistance of the device and avoid leakage current in the shallow junction. It meets the basic electrical requirements of the component to ensure component characteristics and reliability, thereby improving product yield. To achieve the above object, the present invention is in the form of a semiconductor substrate having an isolation region, a gate structure, a source/drain lightly doped region, a gate spacer, a raised source/drain structure, and a source/drain a heavily doped region or the like; then forming a first metal layer, a barrier layer, and a patterned chemical vapor deposition layer on the semiconductor substrate to expose the barrier layer on the gate structure; After removing the barrier layer and the first metal layer exposed on the gate structure, removing the patterned chemical vapor deposition layer; then depositing a second metal layer on the barrier layer and the gate structure, and bonding the semiconductor The substrate is thermally tempered to convert a portion of the second metal layer in contact with the gate structure and a portion of the first metal layer in contact with the source/drain region into a metal halide; and then removing unreacted The second metal layer, the barrier layer and the first metal layer are most thermally tempered. The details, technical contents, features and achievements of the present invention will be more readily understood by the detailed description of the specific embodiments and the accompanying drawings.

Page 7 • 1284941 V. Description of invention (4) Effect. Description of the drawings: 10 Semiconductor substrate 12 14 Gate structure 142 144 Polysilicon layer 16 18 Gate spacer 20 22 Source/drain heavily doped region (source 24 Titanium layer 28 30 Semiconductor substrate 32 34 Gate structure 342 344 Polysilicon Layer 36 38 Gate Clearance Wall 40 42 Twin Layer 44 46 Barrier Layer 48 50 Second Metal Layer 52 54 Metal Telluride Details • Conventional techniques for forming a resistance on a gate structure j on the source/drain region Juncti on) Extremely easy to leak current The conductor component process uses a gate structure or a metal layer of different materials to improve the value! And avoid leakage current of shallow junction shallow trench isolation region gate oxide source / bungee light doped region chopped layer / > and polar structure) titanium germanium shallow trench isolation region gate oxide source /汲 very lightly doped region read source / drain (heavily doped) region first metal layer chemical vapor deposition layer metal germanide second (a) to second (h) is one of the preferred embodiments of the present invention Example in system

Page 8, 1284941 V. DESCRIPTION OF THE INVENTION (5) A cross-sectional view showing the steps of the steps of the semiconductor device. As shown in the figure, the main manufacturing method of the present invention includes the following steps: as shown in the second (a) diagram, a first The semiconductor substrate 3 is formed with a shallow trench isolation region (ST 1) 32 for isolating the active device and the passive component in the semiconductor substrate 30; and forming a crystal gate on the semiconductor substrate 3 The pole structure 34 includes a gate oxide layer 342 and a polysilicon layer 3 44 thereon; and then the gate structure 34 is used as a mask to perform a low concentration first ion cloth on the semiconductor substrate 30. Implanted to form a source/ > and a lightly doped region 36 in the semiconductor substrate 3; and a gate spacer 3 8 is formed next to the sidewalls of the gate structure 34. composition. Next, after the source/drain lightly doped region 36 is formed, and before the shape/deuterium epitaxial layer, a high temperature activation treatment is performed, which is greater than 8 〇. A rapid thermal anneal (RTA) treatment is carried out in a furnace or a higher temperature (about 1050 ° C) furnace tube to reform the twin lattice of the surface of the semiconductor substrate 30. After thermal tempering, the epitaxial method (6卩^8乂丫) is used to selectively grow in the gate structure 34 and the source/drain region 40 in an epitaxial reactor. The epitaxial layer 4 2 is formed to form a raised source/drain structure. Then, the gate structure 34 and the gate spacer 38 are used as a mask to perform a high concentration second ion implantation on the semiconductor substrate 30 to form source/drain re-doping in the semiconductor substrate 30. The impurity region 40; and then a rapid thermal tempering treatment of about 800 ° Cj furnace tube tempering or higher temperature (900 ° C) to make the surface of the stomach conductor substrate 30 amorphous due to ion implantation The Shi Xi phenomenon tempered into the original crystalline state.

Page S 1284941 V. INSTRUCTIONS (6) After forming the structure of each element as shown in the second (a) diagram, the two-stage metal deposition process can be continued. Referring to FIG. 2(b), a first metal layer 44 is deposited on the semiconductor substrate 30 by metal sputtering or chemical vapor deposition. The material of the first metal layer 44 can be Titanium, ruthenium or platinum metal, or other viable metal materials, preferably titanium. Forming a barrier layer 4 6 on the surface of the first metal layer 44. The barrier layer 46 is formed by implanting nitrogen ions or introducing nitrogen gas onto the surface of the first metal layer 44 to make the surface. A portion of the first metal layer 44 is converted into a metal nitride to serve as the barrier layer 46. Then, a chemical vapor deposition layer 4 is formed on the surface of the barrier layer 46. As shown in the second (c), the chemical vapor deposition layer 48 is generally an oxide layer containing tetraoxoethyl TEOS can also be a nitride layer or any chemical vapor deposition material that can be selectively removed, that is, a material that can be removed by wet etching in subsequent processing steps. Next, referring to the second (d), the surface of the semiconductor substrate is etched and removed by dry etching, so that a portion of the chemical vapor deposited layer 48 above the gate structure 34 is completely removed, and the gate is exposed. The barrier layer 46 on the structure 34; and the chemical vapor deposition layer 48 as a mask, another etching step is performed, and the barrier layer 46 and the first metal layer 44 above the gate structure 34 are all Removed to expose the gate structure 34. At this time, the remaining chemical vapor deposition layer 48 can be removed by using a general wet etching method to remove the semiconductor chemical layer from the semiconductor substrate by a general chemical vapor deposition layer. A structure as shown in the second (e) figure can be obtained. Please refer to the second (f) diagram, using metal sputtering or chemical vapor

• Page 10 Ϊ 284941 " ------- Washing method, ^, layer 46 (篥 = into a second metal layer 50 on the exposed gate structure 34 and the barrier material system - metal layer 44 The barrier layer 46) is a metal of the second metal layer 50, which may be a metal of a metal, a cobalt metal or a platinum metal, or another material which can be a heat tempering material. The semiconductor substrate 30 is subjected to a tempering contact between the metal layer 4 and the source/> and the polar region 4 in a furnace tube of more than 50,000 ° C. The layer 4 2 is free to choose. The portion is converted into a metal halide 5 2, and a portion where the second metal layer 50 is in contact with the tantalum material of the surface of the surface 4 is converted into a metal telluride as shown in the figure (g). After the preparation of the metal lithium 52, 54 is completed, the unreacted metal lithium 5 2 or the first metal layer 44 remaining after the reaction, the barrier layer 46 and the unreacted metal lithium 54 can be completely removed. Or the second metal layer 5〇 remaining after the reverse, as shown in the second (h) diagram, the metal bismuth 5 2, 5 4 is finally thermally tempered to reduce the resistance of the metal halide 5 2, 5 4 value. Wherein, the barrier layer 46 used in the above process is not necessary. If the barrier layer 46 is not designed, the chemical vapor deposition layer 48 is directly formed on the surface of the first metal layer 44, and can be The subsequent steps are performed as follows. The structure and steps of the barrier layer are omitted, and the other detailed processes are the same as those described above, and thus will not be described again. In a preferred embodiment, the metal layer produced by the first metal layer is located on the source/drain region, and the gold/telluride generated by the second metal layer is located on the gate structure. The thickness of the metal layer and the type of metal shell can be scheduled in time according to its characteristics and component requirements. The present invention proposes an improved deep submicron to improve the lack of conventional knowledge.

1284941 V. INSTRUCTIONS (8) The semiconductor device process for resisting and leakage of crystals is formed by two-stage deposition of metal layers to form metal layers of different thicknesses or materials on the gate structure and source/drain regions. To form different self-aligned metal tellurides. The metal telluride on the gate structure is thicker to reduce its resistance value; the metal telluride on the source/drain region can be thinner, and at the same time it is combined with the elevated source/no-polar structure to make the source/no-polar region The internal resistance can be significantly reduced, and the leakage of the shallow junction can be completely improved. Therefore, the present invention can reduce the leakage current in the shallow junction while reducing the resistance value of the component, so as to meet the basic electrical requirements of the component, thereby ensuring component characteristics and reliability, thereby improving Product yield. The embodiments described above are merely illustrative of the technical spirit and the characteristics of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and to implement the present invention. Equivalent changes or modifications made by the spirit of the present invention should still be included in the scope of the present invention.

Page 12 1284941 BRIEF DESCRIPTION OF THE DRAWINGS First (a) to first (c) are cross-sectional views showing the steps of fabricating a semiconductor device in the prior art. The second (a) through second (h) drawings are cross-sectional views showing the steps of the steps of fabricating a semiconductor device of the present invention. 1Ι1·ΙΙΙ第13页

Claims (1)

1284941 VI. Patent Application Range 1 · A semiconductor device process for improving the resistance and leakage of deep submicron transistors, comprising the following steps: (a) providing a semiconductor substrate on which an isolation region and a gate structure are sequentially formed. a source/no-light-light-changing region, a gate spacer, an elevated source/drain structure, and a source/drain heavily doped region; (b) depositing a first metal layer on the semiconductor substrate; c) forming a barrier layer on the surface of the first metal layer; (d) forming a patterned chemical vapor deposition layer on the barrier layer to expose the barrier layer on the gate structure; (e) Removing the barrier layer and the first metal #(f) exposed on the gate structure to remove the patterned chemical vapor deposition layer; (g) depositing a second layer on the barrier layer and the gate structure a metal layer; (h) thermally tempering the semiconductor substrate such that a portion of the second metal layer in contact with the gate structure and a portion of the first metal layer in contact with the source/drain region Turned into metal telluride, (i) removed unreacted into metal And the second metal layer, the barrier layer and the first metal layer; and (j) thermally tempering the metal cerium compound. g 2 · The semiconductor device process of claim 1, wherein the step (a) of forming the components in the semiconductor substrate further comprises the following steps: Page 14 1284941 VI. Patent Application Form a gate structure on the semiconductor substrate, comprising a gate oxide layer and a polysilicon layer thereon; using the gate structure as a mask to perform a low concentration ion implantation Forming a source/drain lightly doped region in the semiconductor substrate; forming a gate spacer on the sidewall of the gate structure; performing a high temperature activation process; growing a gate on the gate structure and the source/> Breaking the stray layer to form an elevated source/drain structure; using the gate structure and the gate spacer as a mask, the semiconductor substrate is subjected to a high concentration ion implantation to form a source/drain heavily doped a region; and performing a thermal tempering treatment on the semiconductor substrate. 3. The semiconductor device process of claim 2, wherein the method of growing the doped layer is performed by a stupid crystal method. 4. The semiconductor device process of claim 1, wherein the first metal layer is made of titanium metal, a starting metal, a platinum metal, or other feasible metal material. 5. The semiconductor device process of claim 1, wherein the step (d) further comprises: forming a chemical vapor deposited layer on the barrier layer; and etching the removed portion of the chemical vapor deposition layer A layer is formed to form a chemical vapor deposited layer of the pattern t to expose the barrier layer on the gate structure. 6 · The semiconductor component process as described in claim 1 of the patent scope, wherein Page 15 1284941 VI. Scope of Application The material of the second metal layer can be titanium metal, base metal, platinum metal, or other feasible metal materials. 7. The semiconductor device process of claim 1, wherein the barrier layer is composed of a metal nitride layer. 8. The semiconductor device process of claim 7, wherein the metal nitride layer is formed by performing a nitrogen ion value on the first metal layer to convert a portion of the first metal layer Form the nitrided metal layer. 9. The semiconductor device process of claim 1, wherein the chemical vapor deposited layer may be an oxide layer comprising a tetraoxyethyl fluorene (TEOS), a tantalum nitride layer, or any optional Sexually removed #Chemical vapor deposition material. The semiconductor device process of claim 1, wherein the heat tempering treatment in the step (h) is tempering in a furnace tube of more than 500 °C. II. The semiconductor device process of claim 1, wherein the thermal tempering treatment in the step (j) is tempering in a furnace tube of about 700 °C. 1 2 · A semiconductor device process for improving the resistance and leakage of deep submicron transistors, comprising the following steps: (a) providing a semiconductor substrate on which is formed an isolation region, a gate structure, a source/no Very lightly doped regions, gate gaps P, raised source/drain structures, and source/drain heavily doped regions; Page 16 1284941 6. Patent Application (b) depositing a first metal layer on the semiconductor substrate; (c) forming a patterned chemical vapor deposited layer on the first metal layer to expose the gate Structurally the first metal layer; (d) removing the first metal layer exposed on the gate structure; (e) removing the patterned chemical vapor deposition layer; (f) on the gate structure Depositing a second metal layer; (g) thermally tempering the semiconductor substrate such that a portion of the second metal layer in contact with the gate structure and a portion in contact with the source/drain region The first metal layer is converted into a metal halide (h) to remove the second metal layer that is not reacted into a metal halide and the metal layer; and (i) to thermally temper the metal alloy. The semiconductor device process of claim 12, wherein the step (a) of forming the components in the semiconductor substrate further comprises the step of: forming a gate structure on the semiconductor substrate. , comprising a gate oxide layer and a polysilicon layer thereon; using the gate structure as a mask, performing a low concentration ion implantation to form a source/drain lightly doped region in the semiconductor substrate; a sidewall spacer is formed on the sidewall of the pole structure; g is subjected to a high temperature activation process; a one second stigma layer is grown on the gate structure and the source and the pole to form an elevated source/drain structure; Page 17 1284941 VI. The scope of application for the patent is based on the gate structure and the gate spacer as a mask, and a high concentration ion implantation is performed on the semiconductor substrate to form a source/drain heavily doped region; The semiconductor substrate is thermally tempered. 1 4 The semiconductor device process of claim 13, wherein the method of growing the broken layer is performed by a stupid method. The semiconductor device process of claim 12, wherein the material of the first metal layer is titanium metal, base metal, platinum metal, or other feasible metal material. The semiconductor device process of claim 12, wherein the step (d) further comprises: forming a chemical vapor deposited layer on the first metal layer; and etching the removed portion A chemical vapor deposited layer is formed to form the patterned chemical vapor deposited layer to expose the first metal layer on the gate structure. 1 7 The semiconductor component process of claim 12, wherein the second metal layer is made of titanium metal, cobalt metal, platinum metal, or other feasible metal material. 1 8 The semiconductor device process of claim 12, wherein the chemical vapor deposited layer may be an oxide layer containing tetraethoxyethyl fluorene (TEOS), a tantalum nitride layer, or any Can be selectively removed j chemical vapor deposition material. Stomach 1 9 · The semiconductor component process as described in claim 12, wherein the thermal tempering in the step (g) is a furnace tube larger than 500 ° C Page 18 1284941 VI. Tempering in the scope of patent application. The semiconductor component process as described in claim 12, wherein the heat tempering in the step (i) is tempered in a furnace tube of about 700 °C. Page 19